Simulation Modelling Practice and Theory: Alexander Viehweider, Georg Lauss, Lehfuss Felix
Simulation Modelling Practice and Theory: Alexander Viehweider, Georg Lauss, Lehfuss Felix
Simulation Modelling Practice and Theory: Alexander Viehweider, Georg Lauss, Lehfuss Felix
a r t i c l e i n f o a b s t r a c t
Article history: Power Hardware-in-the-Loop – as a particular simulation technology that includes real
Received 3 October 2010 hardware with high power rating in the simulation loop – is used more and more in the
Received in revised form 10 March 2011 scientific field. Power Hardware-in-the-Loop simulations may suffer – depending on the
Accepted 4 April 2011
attached power hardware and the simulated subsystem – from the drawback of becoming
unstable without appropriate countermeasures. This contribution introduces and com-
pares three methods to guarantee stability under unfavorable stability conditions. The
Keywords:
three methods behave differently as far as accuracy is concerned. Multi-Rate Partitioning
Hardware-in-the-Loop
Stability
is introduced as a good compromise between effort and performance.
Filtering Ó 2011 Elsevier B.V. All rights reserved.
Multi-rate
1. Introduction
The Hardware-in-the-Loop (HIL) simulation is a recognized simulation method in different engineering areas (e.g. auto-
motive applications). Power Hardware-in-the-Loop (PHIL) simulations as an extension of classical HIL applications is gaining
ground especially in the field of electric energy systems [2,6,7,10,13,14,16,18,19]. The Power Hardware-in-the-Loop simula-
tion allows for system and component test scenarios that would otherwise be impossible to implement. The test of a hard-
ware component (load, generator, inverter . . .) with an extended electrical network (simulated) becomes feasible.
One of the main issues is if the whole PHIL simulation runs stably. This can be considered as a necessary condition within
this context. Additionally stability should come with an acceptable accuracy of the results extracted from the PHIL simula-
tion. Accuracy is a sufficient condition for a successful PHIL simulation.
Stability and accuracy are highly dependent on the way software simulation and hardware under test (HuT) are inter-
faced, the so called interfacing algorithm (IA) [11,15].
A good overview of interfacing algorithms is given in the PhD thesis by Ren [3]. The author concluded that only two algo-
rithms out of five have good accuracy and acceptable stability properties.
Early publications in the field dealt with quite simple hardware under test. For example, Ayasun et al. in [4,5] and Wu
et al. in [21,22] looked at a simple network consisting of a voltage source, two resistors and an inductance. They attached
a series connection of a resistor and an inductance as real hardware to the PHIL simulation.
The trend now moves to more sophisticated applications of this simulation technology (e.g. [2,10,13,18,20]), but stability
still remains an issue.
⇑ Corresponding author. Address: Department of Advanced Energy, The University of Tokyo, Trans-disciplinary Sciences Bldg., 5-1-5, Kashiwanoha,
Kashiwa, Chiba 277-8561, Japan. Fax: +81 4 7136 3873.
E-mail address: [email protected] (A. Viehweider).
1569-190X/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved.
doi:10.1016/j.simpat.2011.04.001
1700 A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708
This article introduces three methods to stabilize Power Hardware-in-the-Loop simulations that use the Ideal Trans-
former Method (ITM) as IA. The method easiest to implement is the Hardware Inductance Addition (HIA) method, but accu-
racy is generally poor. Feedback Current Filtering (FCF) may outperform HIA, but accuracy may still not be sufficient. The
third one, Multi-Rate Partitioning (MRP), is demanding as far as the implementation is concerned since it demands a mul-
ti-rate real time computing system, but leads to interesting stability and accuracy results. The merit of this paper is to sys-
tematically compare and verify the three methods by applying them to an application with photovoltaic generation.
To compare the three methods of stabilization a small low voltage grid attached to a photovoltaic inverter (modeled as a
current source with output filter) is introduced and the analytic results compared.
In Fig. 1 a general overview of a PHIL simulation system for electric energy system simulation is given. A real time sim-
ulation of an electrical network runs on a real time computing system. The real time computing system drives a power
amplifier that is connected to real hardware, the so called Hardware under Test (HuT). The power amplifier exchanges power
(usually in the range of some hundred watts to 1 MW [17] in the field of electric energy system simulation). Depending on
the application the power amplifier must be able to provide power (if an electric load is attached) or absorb power (if a gen-
erator is attached). From the HuT a signal (usually the current through the HuT) is fed back into the real time system in order
to capture the interaction between the HuT and the simulated network. The power amplifier and the way signals are ex-
changed between the software and hardware side (the interface algorithm IA) constitute the so called Power Interface (PI).
It goes without saying that a sophisticated real time computing system is needed for this type of simulation. The minimal
achievable step size TS (computing time) of the real time system heavily influences stability and accuracy of the whole PHIL
simulation.
2.2. Modeling
Modeling of the configuration in Fig. 1 (which as a combination of a continuous and discrete time system is a hybrid sys-
tem) is approached in different ways. Ren [3,15] and Hong et al. [8] use a quasi-continuous approach (analysis in the con-
tinuous time domain) for the whole system description in the Laplace domain approximating the discrete time behavior of
the real time computing system, whereas Ayasun et al. in [4,5] use discrete time models in the z domain.
Within this article the quasi-continuous approach is used where the effect of the discrete time behavior of the real time
computing system is modeled as additional time delay in the continuous time domain.
A lot of problems in the field of PHIL simulation can be reduced to the configuration in Fig. 2 (left), where the voltage
source U0 and the impedance ZA(s) are simulated (computed) in software and the impedance ZB(s) characterizes the HuT that
is attached via the PI to the real time computing system. For the time being it is assumed that the HuT is a passive load. From
the stability point of view it does not change anything if we add a current source or voltage source on the hardware side – in
Fig. 2. Introducing the Power Interface with the interface algorithm into the model of the real system.
order to model power generation – since it is assumed that the whole system is linear. Configuration Fig. 1 (left) is especially
suited to introduce basic issues in PHIL simulation.
The introduction of the PI with its interface algorithm transforms the system into the system in Fig. 2 (right) from a mod-
eling point of view, where A(s) is an appropriate matrix description of the PI with the interface algorithm in the Laplace do-
main (e.g. chain matrix, impedance matrix, . . .).
In the ideal case (the power amplifier and the sensors are ideal and the real time computing system is infinitely fast) the
system model on the right side of Fig. 2 would be completely identical to the left system model, since the chain matrix A(s)
would reduce to the identity matrix.
In the case of a real PHIL experiment non-idealities affect the simulation; the chain matrix A(s = jw) differs from the unity
matrix especially for higher frequencies. This is due to the fact that the power amplifier and the sensors have a limited band-
width and the real time computing system works in a discrete time manner, introducing additional delay within this quasi-
continuous approach.
Besides that, quantization noise and amplifier noise are introduced; these effects are not considered within this
contribution.
The Ideal Transformer Method (ITM) voltage type as shown in Fig. 3 is one of the most straightforward interface models
and often used in practice [3,9,15]. It is characterized by a fictional current controlled current source on the software side and
a voltage controlled voltage source on the hardware side. The software current source is driven by the current i2 measured
through the HUT. The computed voltage u1 over the software current source is the driving signal for the controlled ‘‘real
hardware’’ voltage source (= voltage amplifier).
The signal flow diagram can easily be derived for the ITM IA. It is assumed that the dynamic behavior of the voltage ampli-
fier and the current sensor can be described by the transfer function TVA(s), TC(s) in the Laplace domain. Additionally TD1 and
TD2 are the delays in the forward and feedback path due to the computational time of the model and the A/D, D/A converters.
Therefore, it follows that
esT D1 T VA ðsÞ 0
AðsÞ ¼ : ð2Þ
0 esT D2 T C ðsÞ
The signal flow diagram shown in Fig. 4 results; it clearly shows the closed loop character of the PHIL simulation.
1702 A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708
Fig. 5. Relative error for the PHIL configuration according to Fig. 3 (ZA = 1, ZB = 2, TS = 25 ls, TVA(s) according to Appendix A).
In Fig. 4 the delay of the forward and backward path TD1, TD2 has been combined into the whole time delay TD and the
dynamic behavior of the sensor is assumed to be ideal (TC(s) = 1). Usually the time delay TD can be set to twice the computing
time (step size) of the real time computing system TS. For more information on this topic, confer [12].
In order to show how accuracy of a PHIL simulation with an ITM IA is computed a very simple example is given. It is
assumed that the voltage ratio between the voltage over the HuT ZB (according to Fig. 2) and the internal voltage source
U0 is of interest. According to Kirchhoff’s law this voltage ratio is given in the Laplace domain for the original system by
Z B ðsÞ
T IDEAL ðsÞ ¼ ð3Þ
Z A ðsÞ þ Z B ðsÞ
Since the interface is not ideal, the voltage ratio obtained with PHIL using ITM IA is given by
Z B ðsÞ
T PHIL ðsÞ ¼ T VA ðsÞesTD ð4Þ
Z A ðsÞT VA ðsÞesT D þ Z B ðsÞ
This means that there is a difference between the ideal voltage ratio and the voltage ratio obtained by PHIL simulation
and one can compute a relative error a(w) in dB given by
T REAL ðs ¼ jwÞ T IDEAL ðs ¼ jwÞ
aðwÞ ¼ 20 log
ð5Þ
T IDEAL ðs ¼ jwÞ
This error a(w) takes into account the relative difference between the ideal ratio and the ratio obtained by PHIL simula-
tion. It depends heavily on the frequency. It is typically small for low frequencies and large for high frequencies because of
the delay and the limited bandwidth of the PHIL system.
In Fig. 5 the accuracy is shown under the assumption that the impedances ZA and ZB are real valued (defined as ZA = RA =
1 O and ZB = RB = 2 O), the voltage amplifier described in the Appendix A is used and that the sampling (computing) time TS
(=step size) of the real time computing is 25 ls.
Different methods to improve the stability properties of the ITM interface are introduced. They differ as far as their ease of
implementation and their efficiency is concerned. An efficient stabilization would guarantee both: good stability properties
and high fidelity of the PHIL simulation.
A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708 1703
The simplest way of improving stability is to add in series with the HuT an inductor of a certain inductance LADD as shown
in Fig. 6:
The open loop transfer function of the PHIL constellation amounts now to:
Z A ðsÞ
F O ðsÞ ¼ T VA ðsÞesT D ð6Þ
sLADD þ Z B ðsÞ
It is assumed that ZA(s) and ZB(s) are realizable, strictly passive impedances; both of them have the following structure:
NðsÞ
ZðsÞ ¼ ; ð7Þ
DðsÞ
where the numerator N(s) is a polynomial of degree dN and the denominator D(s) a polynomial of degree dD. From network
theory it follows that the degree of the numerator and the denominator are related in the following way:
dN ¼ dD or dN ¼ dD 1; ð8Þ
Therefore, it follows that there exists a limit value LADD,
so that impedance values LADD > LADD stabilize the system. This is
due to the fact that the amount of the open loop transfer function |FO(jw)| can be made as small as necessary at frequencies
wC where <(FO(jwC)) = 180°. From the accuracy point of view the additional inductance should be as small as possible.
HIA may lead to poor accuracy results. Often in order to guarantee stability the value of the additional inductance has to
be chosen very high, so that results are very inaccurate especially for higher frequencies. Since the value of the inductor is the
only parameter to choose for this method the degree of freedom is equal to 1 and therefore really limited.
The feedback current filtering method has more degrees of freedom has. As the name suggests the measured current
through the HuT is filtered appropriately. The filter order depends on the HuT. The open loop transfer function in this case
is
Z A ðsÞ
F O ðsÞ ¼ T F ðsÞT VA ðsÞesT D ; ð9Þ
Z B ðsÞ
where TF(s) is the transfer function of the feedback current filter.
The filter can be optimized in order to meet the stability and accuracy requirements.
If the voltage amplifier has sufficient behavior and the computational time of the real time computing system is very
short, then in order to guarantee accuracy the TF(s) should be close to 1 in a broad frequency range, guaranteeing at the same
time that the system with the open loop transfer functions according to (9) is stable.
The needed filter order depends on the HuT attached. For example if ZB(s) is a series connection of a resistor and a capac-
itor ZB(s) = R + 1/(sC) and ZA(s) is a pure resistance the filter must be at least of n order n = 2 in order that the PHIL simulation
runs stably.
MRP is a method inspired by the architecture of modern real time computing systems. Modern real time computing sys-
tems allow for subsystems with higher sampling rates (smaller step sizes). Unfortunately the size of the fast sampled sub-
systems is limited – usually the very fast subsystems are computed on a FPGA board. MRP partitions the system to simulate
different subsystems with different sampling rates. Ideally the ratio of the sampling rates of the single subsystem should be
very high in order to obtain good dynamic decoupling.
Fig. 7 shows the main procedure: the system to be simulated is split into a large subsystem with a large step size and a
small subsystem with a very small step size. If the ratio between the step size of the large subsystem and the small subsys-
tem is very high, then stability could checked in a two step procedure:
First, the stability of the PHIL simulation with only the fast subsystem as the simulated part together with the hardware is
determined; it is a necessary condition. Secondly, the stability of the whole system is determined.
The partitioning depends strongly on the topology and the elements of the networks. If carried out appropriately, it can
guarantee certain accuracy together with a reasonable stability margin. Usually, the method is combined with FCF, but the
cut-off frequency of the current feedback filter can be chosen with a high value.
For stability reasons the fast subsystem should be large and comprise a high portion of the original system; this may not
be feasible due to computing limitations of the real time computing hardware. Therefore, as much as possible of the system
should be computing with the fast sampling rate (small step size). For each configuration stability has to be checked
separately.
The introduced methods from chapter 3 (HIA, FCF, MRP) are applied to a real world problem: a photovoltaic inverter is
connected to a low voltage grid via a long transmission line. The low voltage grid should be simulated and the photovoltaic
inverter attached as a real hardware device via the Power Interface to the real time computing system as shown in Fig. 8. The
three approaches for stabilization are applied to this problem and the analytic results shown.
This contribution focuses on theoretical and analytical results, therefore the PHIL experiment is not carried out with real
hardware, but a simulated PHIL simulation is used for the analytical discussion.
A Simulated Power Hardware-in-the-Loop Simulation (SPHIL) is a pure software simulation (model) where the properties
of the Power Interface of the PHIL configuration are included in the simulation and a simulation model for the HuT is avail-
able and used. It means simulating the system as shown in Fig. 2 (right side) with an appropriate matrix A(s) in order to cap-
ture the effects of the non-ideal coupling between hardware and software parts of the PHIL simulation. It is a highly efficient
tool for prediction of the behavior of the PHIL simulation but accurate models of the power amplifier and the sensors and the
hardware under test are necessary.
The low voltage grid consists of an infinite bus (a voltage source) and a long cable that is modeled with some p-sections
(R0 , L0 , C0 ). The photovoltaic inverter is modeled very simply; an AC current source is attached to an output filter. It is true that
Fig. 10. Relative error of the simulated PHIL configuration depending on the stabilization method.
this model cannot reflect the intrinsic complexity of a modern photovoltaic inverter, but as shown in [8] the output filter
influences heavily the stability properties of the PHIL simulation. The output filter consists mainly of capacitors; capacitors
on the hardware side of the voltage type ITM filter drastically reduce the stability margin if sufficient countermeasures are
not taken.
The PHIL simulation of the system shown in Fig. 9 with the parameter values as given in Appendix B would not run stably
without any countermeasure. The three introduced methods are therefore applied and the accuracy properties of the single
methods compared. Additionally very fast sampling of the real time computing system is also considered for reference.
As criteria for the accuracy of the system the amount of the relative error in dB between the voltages over the hardware
under test U2 and the voltage of the infinite bus U0 is used and the phase for U2 for the real system (without PI) and the PHIL
simulation (with PI) compared.
In order to guarantee stability for the HIA method an inductor of 4 mH had to be added, for the FCF method a Butterworth
filter of order 3 with cut-off frequency 4 kHz and for the MRP method a Butterworth filter of order 3 with cut-off frequency
Fig. 11. Phase of U2 for the ideal system and the PHIL configuration for different stabilization methods.
1706 A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708
Table 1
Evaluation summary of the stabilization methods.
7 kHz. The order and cut-off frequency of the Butterworth filter has been chosen by evaluating the Nyquist criteria for the
whole setup (for FCF by using Eq. (9) and for MRP by using a quasi continuous model) The filter order is a compromise
between achieved stability margin and accuracy of the PHIL setup. Therefore filter order and cut-off frequency have been
determined in an iterative way. For the MRP method the transmission has been split into two pieces: two thirds of the long
cable is simulated with large step size and one third with small step size. The reason behind is the dynamic decoupling that is
achieved by doing so. The effective impedance ratio between software part and hardware part changes, allowing for more
stability margin of the setup.
Also for fast sampling FCF a Butterworth filter of order 3 and cut-off frequency 9 kHz was necessary.
In Fig. 10 the outcomes for the different stabilization methods are shown. The frequency bandwidth of accuracy of the
PHIL configuration is defined as the bandwidth, where the relative error is lower than 20 dB (=10% relative error). As ex-
pected, HIA has the smallest accuracy bandwidth up to 380 Hz. FCF with an optimized feedback filter is much better with a
bandwidth up to 620 Hz. It comes as no surprise that faster sampling of the real time computing system (1 ls) leads to the
best results, but it is astonishing how close MRP comes to faster sampling. On the other hand, a multi-rate real time com-
puting system (25 ls, 1 ls) is needed for MRP and part of the system to simulate is computed with the high rate (1 ls).
A similar outcome is obtained by comparing the phases of the voltage U2 for the ideal case and the PHIL configuration
(Fig. 11). For HIA already at low frequency heavy phase inaccuracies occur. FCF is more accurate and MRP leads to the best
results comparable to a very fast real time computing system that computes the whole simulation model at a fast rate. This
may not be possible for large systems, but it may be possible to simulate part of the system at a fast rate and the rest with a
slow rate.
In Table 1 a short evaluation summary of the single stabilization methods is given.
5. Conclusions
This contribution compared three ways of establishing stability for a PHIL simulation with the ITM IA in the case of an
unstable PHIL configuration. They differed as far as their complexity for implementation is concerned: HIA is the simplest
A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708 1707
method bu demands an additional hardware inductance; FCF uses a filter that can be implemented on the software side of
the PHIL simulation and MRP requires a multi-rate capable real time computing system and is therefore the most demanding
as far as the equipment is concerned but the method with best accuracy results.
The stabilization results should be further evaluated for uncertain parameters and nonlinear settings. Nonlinearity in the
general context asks for other methods for stabilization like the Popov criteria [1]. In the case of weak nonlinearities, the
methods discussed in this contribution may suffice to guarantee stability and accuracy depending on the needed fidelity
of the simulation.
The transfer function TVA(s) of the voltage amplifier, whose model is used in chapter 4 has been identified by using the
step function response shown in Fig. 12. The used voltage amplifier is a linear amplifier (as opposed to switched-mode
amplifiers) and has a maximal power rating of 10 kW.
The transfer function obtained by curve fitting is:
1
T VA ðsÞ ¼ esð4 lsÞ
1 þ sð8 lsÞ þ s2 ð2:91e 13 s2 Þ
This transfer function proved to be a good model of the dynamic behavior in the whole power range.
References
[1] S. Sastry, Nonlinear Systems; Analysis, Stability and Control, Springer, 1999.
[2] S. Goyal, Power Network In The Loop: Subsystem Testing Using A Switching Amplifier, Master Thesis, Queensland University of Technology, 2009.
[3] W. Ren, Accuracy Evaluation of Power Hardware-in-the-Loop (PHIL) Simulation, PhD Thesis, The Florida State University, 2007.
[4] S. Ayasun, R. Fischl, T. Chmielewski, S. Vallieu, K. Miu and C. Nwankpa, Evaluation of the Static Performance of a Simulation–Stimulation Interface for
Power Hardware in the Loop, in: Proc. IEEE Bologna Power Tech Conference, 2003.
[5] S. Ayasun, R. Fischl, S. Vallieu, J. Braun, D. Cadirh, Modelling and stability analysis of a simulation–stimulation interface for hardware-in-the-loop
applications, Simulation Modelling Practice and Theory 15 (2007) 734–746.
[6] L. Gauchia, J. Sanz, A per-unit hardware-in the-loop simulation of a fuel cell/battery hybrid energy system in, IEEE Transactions on Industrial
Electronics 57 (2007) 1186–1194.
[7] S. Grubic, B. Amlang, W. Schumacher, A. Wenzel, A high performance electronic hardware-in-the-loop drive-load simulation using a linear inverter
(LinVerter), IEEE Transactions on Industrial Electronics 57 (2010) 1208–1216.
[8] M. Hong, S. Horie, Y. Miura, T. Ise, C. Dufour, A method to stabilize a power hardware-in-the-loop simulation of inductor coupled systems, in: Proc.
International Conference on Power Systems Transients Kyoto Japan, IPST, 2009 (Paper 239).
[9] S. Lentijo, S. D’Arco, A. Monti, Comparing the dynamic performances of power hardware-in-the-loop interfaces, IEEE Transactions on Industrial
Electronics 57 (2010) 1195–1207.
[10] Y. Liu, M. Steurer, P. Ribiero, A novel approach to power quality assessment: real time hardware-in-the-loop test bed, IEEE Transactions on Power
Delivery 20 (2005) 1200–1201.
[11] A. Monti, H. Figueroa, S. Lentijo, X. Wu, R. Dougal, Interface issues in hardware-in-the-loop simulation, in: Proc. IEEE Electric Ship Technologies
Symposium, IEEE, 2005, pp. 39–45.
[12] D. Ocasnu, C. Gombert, S. Bacha, D. Roye, F. Blache, S. Mekhtoub, Real-time hybrid facility for the study of distributed power generation systems, Revue
des Energies Renouverables 11 (2008) 343–356.
[13] D. Ocasnu, Modelisation, Commande et Simulation Temps-Réel Hybride des Systémes de Génération Non Conventionnels, PhD Thesis, Universite
Joseph Fourier, 2008.
[14] M.O. Faruque, V. Dinavahi, Hardware-in-the-loop simulation of power electronic systems using adaptive discretization, IEEE Transactions on Industrial
Electronics 57 (2010) 1146–1158.
[15] W. Ren, M. Steuer, T. Baldwin, Improve the stability and the accuracy of power hardware-in-the-loop simulation by selecting appropriate interface
algorithms, IEEE Transactions on Industry Applications 44 (4) (2008) 1286–1294.
[16] Y. Srinivasa Rao, M.C. Chandorkar, Real-time electrical load emulator using optimal feedback control technique, IEEE Transactions on Industrial
Electronics 57 (2010) 1217–1225.
[17] M. Steurer, C.S. Edrington, M. Sloderbeck, W. Ren, J. Langston, A megawatt-scale power hardware-in-the-loop simulation setup for motor drives, IEEE
Transactions on Industrial Electronics 57 (2010) 1254–1260.
1708 A. Viehweider et al. / Simulation Modelling Practice and Theory 19 (2011) 1699–1708
[18] A. Viehweider, G. Lauss, F. Lehfuss, Stable and accurate MIMO Power Hardware-in-the-Loop-Simulation, in: Proc. Opal RT RealTime 2010 Conference,
Opal RT, Paris, 2010, digitally.
[19] D. Westermann, M. Kratz, A real-time development platform for the next generation of power system control functions, IEEE Transactions on Industrial
Electronics 57 (2010) 1159–1166.
[20] X. Wu, S. Lentijo, A. Deshmuk, A. Monti, F. Ponci, Design and implementation of a power-hardware-in-the-loop interface: a non-linear load case study,
in: Proc., vol. 2, 2005, pp. 1332–1338.
[21] X. Wu, A. Monti, Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations – part I, in: Proc. IECON,
2005.
[22] X. Wu and A. Monti, Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations – part II, in: Proc.
IECON, 2005.