74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

November 1988
Revised February 2005

74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description Features
The AC/ACT74 is a dual D-type flip-flop with Asynchronous ■ ICC reduced by 50%
Clear and Set inputs and complementary (Q, Q) outputs. ■ Output source/sink 24 mA
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at ■ ACT74 has TTL-compatible inputs
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH

Ordering Code:
Package
Order Number Package Description
Number
74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC74SC_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
(Note 1)
74AC74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 2) Wide
74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT74SC_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
(Note 1)
74ACT74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74SJX_NL M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
(Note 2)
74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JECED J-STD-020B.
Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B).
Note 2: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.

FACT¥ is a trademark of Fairchild Semiconductor Corporation.

© 2005 Fairchild Semiconductor Corporation DS009920 www.fairchildsemi.com

74AC74 • 74ACT74
Connection Diagram Pin Descriptions
Pin Names Description
D1 , D2 Data Inputs
CP1, CP2 Clock Pulse Inputs
CD1, CD2 Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q1, Q2, Q2 Outputs

Logic Symbols
IEEE/IEC

Truth Table
(Each Half)
Inputs Outputs

SD CD CP D Q Q

L H X X H L
H L X X L H
L L X X H H
H H  H H L
H H  L L H
H H L X Q0 Q0
H HIGH Voltage Level
L LOW Voltage Level


X Immaterial
LOW-to-HIGH Clock Transition
Q0 (Q0) Previous Q (Q) before LOW-to-HIGH Transition of Clock

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 74AC74 • 74ACT74
Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74AC74 • 74ACT74
Absolute Maximum Ratings(Note 3) Recommended Operating
Supply Voltage (VCC) 0.5V to 7.0V Conditions
DC Input Diode Current (IIK) Supply Voltage (VCC)
VI 0.5V 20 mA AC 2.0V to 6.0V
VI VCC  0.5V 20 mA ACT 4.5V to 5.5V
DC Input Voltage (VI) 0.5V to VCC  0.5V Input Voltage (VI) 0V to VCC
DC Output Diode Current (IOK) Output Voltage (VO) 0V to VCC
VO 0.5V 20 mA Operating Temperature (TA) 40qC to 85qC
VO VCC  0.5V 20 mA Minimum Input Edge Rate ('V/'t)
DC Output Voltage (VO) 0.5V to VCC  0.5V AC Devices
DC Output Source VIN from 30% to 70% of VCC
or Sink Current (IO) r50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
DC VCC or Ground Current Minimum Input Edge Rate ('V/'t)
per Output Pin (ICC or IGND) r50 mA ACT Devices
Storage Temperature (TSTG) 65qC to 150qC VIN from 0.8V to 2.0V
Junction Temperature (TJ) VCC @ 4.5V, 5.5V 125 mV/ns
PDIP 140qC Note 3: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.

DC Electrical Characteristics for AC

VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH 3.0 1.5 2.1 2.1 VOUT 0.1V
Level Input 4.5 2.25 3.15 3.15 V or VCC  0.1V
Voltage 5.5 2.75 3.85 3.85
VIL Maximum LOW 3.0 1.5 0.9 0.9 VOUT 0.1V
Level Input 4.5 2.25 1.35 1.35 V or VCC  0.1V
Voltage 5.5 2.75 1.65 1.65
VOH Minimum HIGH 3.0 2.99 2.9 2.9
Level Output 4.5 4.49 4.4 4.4 V IOUT 50 PA
Voltage 5.5 5.49 5.4 5.4
VIN VIL or VIH
3.0 2.56 2.46 IOH 12 mA
4.5 3.86 3.76 V IOH 24 m
5.5 4.86 4.76 IOH 24 m (Note 4)
VOL Maximum LOW 3.0 0.002 0.1 0.1
Level Output 4.5 0.001 0.1 0.1 V IOUT 50 PA
Voltage 5.5 0.001 0.1 0.1
VIN VIL or VIH
3.0 0.36 0.44 IOL 12 mA
4.5 0.36 0.44 V IOL 24 mA
5.5 0.36 0.44 IOL 24 mA (Note 4)
IIN (Note 6) Maximum Input Leakage Current 5.5 r 0.1 r 1.0 PA VI VCC, GND
IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Maximum
IOHD Output Current (Note 5) 5.5 75 mA VOHD 3.85V Minimum
ICC Maximum Quiescent VIN VCC
5.5 2.0 20.0 PA
(Note 6) Supply Current or GND
Note 4: All outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
Note 6: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

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 74AC74 • 74ACT74
DC Electrical Characteristics for ACT
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VOUT 0.1V
V
Input Voltage 5.5 1.5 2.0 2.0 or VCC  0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VOUT 0.1V
V
Output Voltage 5.5 1.5 0.8 0.8 or VCC  0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 IOUT 50 PA
V
Output Voltage 5.5 5.49 5.4 5.4
VIN VIL or VIH
4.5 3.86 3.76 V IOH 24 mA
5.5 4.86 4.76 IOH 24 mA (Note 7)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1 IOUT 50 PA
V
Output Voltage 5.5 0.001 0.1 0.1
VIN VIL or VIH
4.5 0.36 0.44 V IOL 24 mA
5.5 0.36 0.44 IOL 24 mA (Note 7)
IIN Maximum Input VI VCC, GND
5.5 r0.1 r1.0 PA
Leakage Current
ICCT Maximum VI VCC  2.1V
5.5 0.6 1.5 mA
ICC/Input
IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Maximum
IOHD Output Current (Note 8) 5.5 75 mA VOHD 3.85V Minimum
ICC Maximum Quiescent VIN VCC
5.5 2.0 20.0 PA
Supply Current or GND
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.

AC Electrical Characteristics for AC

VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 9) Min Typ Max Min Max
fMAX Maximum Clock 3.3 100 125 95
MHz
Frequency 5.0 140 160 125
tPLH Propagation Delay 3.3 3.5 8.0 12.0 2.5 13.0
ns
CDn or SDn to Qn or Qn 5.0 2.5 6.0 9.0 2.0 10.0
tPHL Propagation Delay 3.3 4.0 10.5 12.0 3.5 13.5
ns
CDn or SDn to Qn or Qn 5.0 3.0 8.0 9.5 2.5 10.5
tPLH Propagation Delay 3.3 4.5 8.0 13.5 4.0 16.0
ns
CPn to Qn or Qn 5.0 3.5 6.0 10.0 3.0 10.5
tPHL Propagation Delay 3.3 3.5 8.0 14.0 3.5 14.5
ns
CPn to Qn or Qn 5.0 2.5 6.0 10.0 2.5 10.5
Note 9: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V

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74AC74 • 74ACT74
AC Operating Requirements for AC
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 10) Typ Guaranteed Minimum
tS Set-up Time, HIGH or LOW 3.3 1.5 4.0 4.5
ns
Dn to CPn 5.0 1.0 3.0 3.0
tH Hold Time, HIGH or LOW 3.3 2.0 0.5 0.5
ns
Dn to CPn 5.0 1.5 0.5 0.5

tW CPn or CDn or SDn 3.3 3.0 5.5 7.0

ns
Pulse Width 5.0 2.5 4.5 5.0
trec Recovery Time 3.3 2.5 0 0
ns
CDn or SDn to CP 5.0 2.0 0 0
Note 10: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V

AC Electrical Characteristics for ACT

VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 11) Min Typ Max Min Max
fMAX Maximum Clock
5.0 145 210 125 MHz
Frequency
tPLH Propagation Delay
5.0 3.0 5.5 9.5 2.5 10.5 ns
CDn or SDn to Qn or Qn
tPHL Propagation Delay
5.0 3.0 6.0 10.0 3.0 11.5 ns
CDn or SDn to Qn or Qn
tPLH Propagation Delay
5.0 4.0 7.5 11.0 4.0 13.0. ns
CPn to Qn or Qn
tPHL Propagation Delay
5.0 3.5 6.0 10.0 3.0 11.5 ns
CPn to Qn or Qn
Note 11: Voltage Range 5.0 is 5.0V r 0.5V

AC Operating Requirements for ACT

VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 12) Typ Guaranteed Minimum
tS Set-up Time, HIGH or LOW
5.0 1.0 3.0 3.5 ns
Dn to CPn
tH Hold Time, HIGH or LOW
5.0 0.5 1.0 1.0 ns
Dn to CPn

tW CPn or CDn or SDn

5.0 3.0 5.0 6.0 ns
Pulse Width
trec Recovery Time
5.0 2.5 0 0 ns
CDn or SDn to CP
Note 12: Voltage Range 5.0 is 5.0V r 0.5V

Capacitance
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC OPEN
CPD Power Dissipation Capacitance 35.0 pF VCC 5.0V

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 74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

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74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

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 74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14

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74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

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