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Jameco Part Number 1550792

 HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
Available in either an 8-pin DIP or SO-8 package style • +5 V CMOS compatibility
respectively, the HCPL-7710 or HCPL-0710 optocouplers • 8 ns maximum pulse width distortion
utilize the latest CMOS IC technology to achieve outstand-
• 20 ns maximum prop. delay skew
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete • High speed: 12 Mbd
CMOS compatibility. • 40 ns maximum prop. delay
• 10 kV/µs minimum common mode rejection
Basic building blocks of the HCPL-x710 are a CMOS LED
• -40°C to 100°C temperature range
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which • Safety and regulatory approvals
supplies current to the LED. The detector IC incorporates UL Recognized
an integrated photodiode, a high-speed transimped- 3750 V rms for 1 min. per UL 1577
ance amplifier, and a voltage comparator with an output 5000 V rms for 1 min. per UL 1577 (for HCPL-7710
driver. option 020)
CSA Component Acceptance Notice #5
Functional Diagram IEC/EN/DIN EN 60747-5-2
TRUTH –V IORM = 630 Vpeak for HCPL-7710 Option 060
TABLE
**VDD1 1 8 VDD2**
– VIORM
(POSITIVE = 560 Vpeak for HCPL-0710 Option 060
LOGIC)
VI, INPUT LED1 VO, OUTPUT
H OFF H
VI 2 7 NC* Applications
L ON L
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
IO
3 6
• AC plasma display panel level shifting
NC* VO
• Multiplexed data transmission
LED1
• Computer peripheral interface
GND1 4 5 GND2
SHIELD • Microprocessor system interface

* Pin 3 is the anode of the internal LED and must be left

unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
TRUTH TABLE
(POSITIVE LOGIC)
8 VDD2**
VI, INPUT LED1 VO, OUTPUT
H OFF H
7 NC* L ON L

IO
6 VO CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.

5 GND2
Selection Guide
8-Pin DIP Small Outline
(300 Mil) SO-8
HCPL-7710 HCPL-0710

Ordering Information
HCPL-0710 and HCPL-7710 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option UL 5000
Part RoHS Non RoHS Surface Gull Tape Vrms/ 1 IEC/EN/DIN
number Compliant Compliant Package Mount Wing & Reel Minute rating EN 60747-5-2 Quantity
-000E No option 50 per tube
-300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
-020E -020 X 50 per tube
300mil
HCPL-7710 -320E -320 X X X 50 per tube
DIP-8
-520E -520 X X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E #560 X X X X 1000 per reel
-000E No option X 100 per tube
-500E #500 X X 1500 per reel
HCPL-0710 SO-8
-060E #060 X X 100 per tube
-560E #560 X X X 1500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7710-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-0710 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.


Package Outline Drawing
HCPL-7710 8-Pin DIP Package
9.65 ± 0.25 7.62 ± 0.25
(0.380 ± 0.010) (0.300 ± 0.010)

TYPE NUMBER 8 7 6 5 6.35 ± 0.25

(0.250 ± 0.010)
A XXXX DATE CODE

YYWW

1 2 3 4

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076
5° TYP. 0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
1.080 ± 0.320 0.65 (0.025) MAX. "L" = OPTION 020
(0.043 ± 0.013) "V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010) OPTION NUMBERS 300 AND 500 NOT MARKED.

Package Outline Drawing

HCPL-7710 Package with Gull Wing Surface Mount Option 300

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25 1.016 (0.040)
(0.380 ± 0.010) 1.194 (0.047)

8 7 6 5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010) 9.398 (0.370)
9.906 (0.390)

1 2 3 4

0.381 (0.015)
1.194 (0.047) 0.635 (0.025)
1.778 (0.070)

1.780 9.65 ± 0.25

(0.070) (0.380 ± 0.010)
1.19 MAX.
(0.047) 7.62 ± 0.25
MAX. (0.300 ± 0.010)
+ 0.076
0.254 - 0.051
4.19 MAX. + 0.003)
(0.165) (0.010 - 0.002)

1.080 ± 0.320
(0.043 ± 0.013) 0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
2.54 0.635 ± 0.130
(0.100) (0.025 ± 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

Outline (8-pin DIP - Option 300)


Package Outline Drawing
HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION

8 7 6 5
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
3.937 ± 0.127 YWW TYPE NUMBER 7.49 (0.295)
(0.155 ± 0.005) (LAST 3 DIGITS)
DATE CODE

PIN ONE 1 2 3 4
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003) 1.270 BSC
(0.050) 0.64 (0.025)

* 5.080 ± 0.127 7° 0.432

45° X
(0.200 ± 0.005) (0.017)

3.175 ± 0.127
(0.125 ± 0.005) 0 ~ 7° 0.228 ± 0.025
1.524
(0.009 ± 0.001)
(0.060)

0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 0.305 MIN.
5.207 ± 0.254 (0.205 ± 0.010) (0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

Solder Reflow Thermal Profile

300
PREHEATING RATE 3°C + 1°C/- 0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
PEAK
TEMP.
TEMP.
245°C
240°C
PEAK
TEMP.
230°C
200
TEMPERATURE ( °C)

2.5°C ± 0.5°C/SEC.
SOLDERING
30 TIME
160°C 200°C
150°C SEC.
140°C
30
3°C + 1°C/- 0.5°C SEC.

100
PREHEATING TIME
150°C, 90 + 30 SEC. 50 SEC.

TIGHT
ROOM TYPICAL
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)

Note: Non-halide flux should be used.


Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used.

Regulatory Information
The HCPL-x710 have been approved by the following organizations:

UL IEC/EN/DIN EN 60747-5-2
Recognized under UL 1577, component recognition Approved under:
program, File E55361. IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
CSA DIN EN 60747-5-2 (VDE 0884
Approved under CSA Component Acceptance Notice Teil 2):2003-01.
#5, File CA 88324. (Option 060 only)

Insulation and Safety Related Specifications

   Value
Parameter Symbol 7710 0710 Units Conditions
Minimum External Air L(I01) 7.1 4.9 mm Measured from input terminals to output
Gap (Clearance) terminals, shortest distance through air.
Minimum External L(I02) 7.4 4.8 mm Measured from input terminals to output
Tracking (Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic 0.08 0.08 mm Insulation thickness between emitter and
Gap (Internal Clearance) detector; also known as distance through
insulation.
Tracking Resistance CTI ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

All Avago data sheets report the creepage and clearance surface of a printed circuit board between the solder fillets
inherent to the optocoupler component itself. These of the input and output leads must be considered. There
dimen­sions are needed as a starting point for the equip- are recommended techniques such as grooves and ribs
ment designer when determining the circuit insulation which may be used on a printed circuit board to achieve
requirements. However, once mounted on a printed circuit desired creepage and clearances. Creepage and clearance
board, minimum creepage and clearance require­ments distances will also change depending on factors such as
must be met as specified for individual equipment stan- pollution degree and insulation level.
dards. For creepage, the shortest distance path along the


IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
         HCPL-7710 HCPL-0710
Description Symbol Option 060 Option 060 Units
Installation classification per DIN VDE 0110/1.89, Table 1
  for rated mains voltage ≤150 V rms I-IV I-IV
  for rated mains voltage ≤300 V rms I-IV I-III
  for rated mains voltage ≤450 V rms I-III
Climatic Classification 55/100/21 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2 2
Maximum Working Insulation Voltage VIORM 630 560 V peak
Input to Output Test Voltage, Method b† VPR 1181 1050 V peak
  VIORM x 1.875 = VPR, 100% Production
  Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a† VPR 945 840 V peak
  VIORM x 1.5 = VPR, Type and Sample Test,
  tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage† VIOTM 6000 4000 V peak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
  (Maximum values allowed in the event of a failure,
  also see Thermal Derating curve, Figure 11.)
   Case Temperature TS 175 150 °C
   Input Current IS,INPUT 230 150 mA
   Output Power PS,OUTPUT 600 600 mW
Insulation Resistance at TS, V10 = 500 V RIO ≥109 ≥109 Ω

†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations sec-
tion IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be
ensured by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units
Storage Temperature TS –55 125 °C
Ambient Operating Temperature TA –40 +100 °C
Supply Voltages VDD1, VDD2 0 6.0 Volts
Input Voltage VI –0.5 VDD1 +0.5 Volts
Output Voltage VO –0.5 VDD2 +0.5 Volts
Input Current II –10 +10 mA
Average Output Current IO 10 mA
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Ambient Operating Temperature TA –40 +100 °C
Supply Voltages VDD1, VDD2 4.5 5.5 V
Logic High Input Voltage VIH 2.0 VDD1 V
Logic Low Input Voltage VIL 0.0 0.8 V
Input Signal Rise and Fall Times tr, tf 1.0 ms


Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.

DC Specifications
Parameter Symbol Min. Typ. Max. Units Test Conditions
Logic Low Input IDD1L 6.0 10.0 mA VI = 0 V
Supply Current [1]
Logic High Input IDD1H 1.5 3.0 mA VI = VDDI
Supply Current

Input Supply Current IDD1 13.0 mA

Output Supply Current IDD2 5.5 11.0 mA
Input Current II -10 10 µA
Logic High Output VOH 4.4 5.0 V IO = -20 µA, VI = VIH
Voltage 4.0 4.8 IO = -4 mA, VI = VIH
Logic Low Output VOL 0 0.1 V IO = -20 µA, VI = VIL
Voltage 0.5 1.0 IO = -4 mA, VI = VIL

Switching Specifications
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time tPHL 20 40 ns CL = 15 pF
to Logic Low Output [2] CMOS Signal Levels
Propagation Delay Time tPHL 20 40 ns CL = 15 pF
to Logic Low Output [2] CMOS Signal Levels
Propagation Delay Time tPLH 23 40 ns CL = 15 pF
to Logic High Output CMOS Signal Levels
Pulse Width [3] PW 80 ns CL = 15 pF
CMOS Signal Levels
Data Rate [3] 12.5 MBd CL = 15 pF
CMOS Signal Levels
Pulse Width Distortion [4] PWD 3 8 ns CL = 15 pF
|tPHL - tPLH| CMOS Signal Levels
Propagation Delay Skew [5] tPSK 20 ns CL = 15 pF
Output Rise Time tR 9 ns CL = 15 pF
(10 - 90%) CMOS Signal Levels
Output Fall Time tF 8 ns CL = 15 pF
(90 - 10%) CMOS Signal Levels
Common Mode |CMH| 10 20 kV/µs VI = VDD1, VO >
Transient Immunity at 0.8 VDD1,
Logic High Output [6] VCM = 1000 V
Common Mode |CML| 10 20 kV/µs VI = 0 V, VO > 0.8 V,
Transient Immunity at VCM = 1000 V
Logic Low Output [6]
Input Dynamic Power CPD1 60 pF
Dissipation Capacitance [7]
Output Dynamic Power CPD2 10 pF
Dissipation Capacitance [7]


Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary 0710 VISO 3750 Vrms RH = 50%,
Withstand Voltage [8, 9, 10] 7710 3750 t = 1 min.,
TA = 25°C
Option 020 5000
Resistance RI-O 1012 W VI-O = 500 Vdc
(Input-Output) [8]
Capacitance CI-O 0.6 pF f = 1 MHz
(Input-Output) [8]
Input Capacitance [11] CI 3.0
Input IC Junction-to-Case -7710 qjci 145 °C/W Thermocouple
Thermal Resistance -0710 160 located at center
underside of package
Output IC Junction-to-Case -7710 qjco 140
Thermal Resistance -0710 135
Package Power Dissipation PPD 150 mW
Notes:
  1. The LED is ON when VI is low and OFF when VI is high.
  2. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
  3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaran­teed. Maximum Data Rate is
the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent
jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is
30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-x710 performances above 12.5 MBd are not guaranteed by Hewlett-
Packard.
  4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
  5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
  6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
  7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detec-
tion current limit, II-O ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA).
10. The Input-Output Momentary With­stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).

2.2
5 29
0 °C
2.1 25 °C
0 °C 85 °C 27
4 25 °C
85 °C 2.0 25
TPLH, TPHL (ns)

TPLH
VITH (V)

3
VO (V)

23
1.9
21 TPHL
2
1.8
19
1 1.7
17

0 1.6 15
0 1 2 3 4 5 4.5 4.75 5 5.25 5.5 0 10 20 30 40 50 60 70 80
VI (V) VDD1 (V) TA (C)

Figure 1. Typical output voltage vs. input voltage. Figure 2. Typical input voltage switching threshold vs. Figure 3. Typical propagation delays vs. temperature.
input supply voltage.
HCPL-0710 fig 1 HCPL-0710 fig 2 HCPL-0710 fig 3


 4 15 7

6
3
14
5
PWD (ns)

TR (ns)

TF (ns)
2
4
13
1
3

0 12 2
0 20 40 60 80 0 20 40 60 80 0 20 40 60 80
TA (C) TA (C) TA (C)

Figure 4. Typical pulse width distortion vs. tempera- Figure 5. Typical rise time vs. temperature. Figure 6. Typical fall time vs. temperature.
ture.
HCPL-0710 fig 4 HCPL-0710 fig 5 HCPL-0710 fig 6

29 6 25
23
27 5 21
25 19
4
TPLH, TPHL (ns)

TPHL 17
23
PWD (ns)

TR (ns)
3 15
21 13
TPLH 2
19 11
9
17 1
7
15 0 5
15 20 25 30 35 40 45 50 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35
CI (pF) C I (pF) CI (pF)

Figure 7. Typical propagation delays vs. output load Figure 8. Typical pulse width distortion vs. output load Figure 9. Typical rise time vs. load capacitance.
capacitance. capacitance.
HCPL-0710 fig 9

10 STANDARD 8 PIN DIP PRODUCT SURFACE MOUNT SO8 PRODUCT

800 800
OUTPUT POWER - P S , INPUT CURRENT - I S

OUTPUT POWER - P S , INPUT CURRENT - I S

9 P S (mW) P S (mW)
700 700
8 I S (mA) I S (mA)

7 600 600
FALL TIME (ns)

6 500 500
5
400 400
4
300 300
3
(230)
2 200 200
(150)
1 100 100
0 0 0
0 5 10 15 20 25 30 35 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200
CI (pF)
T A - CASE TEMPERATURE - o C T A - CASE TEMPERATURE - o C

Figure 10. Typical fall time vs. load capacitance. Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN
60747-5-2.
HCPL-0710 fig 10


Application Information
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are extremely easy to required for proper operation are two bypass capacitors.
use. No external interface circuitry is required because Capacitor values should be between 0.01 µF and 0.1 µF.
the HCPL-x710 use high-speed CMOS IC technology For each capacitor, the total lead length between both
allowing CMOS logic to be connected directly to the ends of the capacitor and the power-supply pins should
inputs and outputs. not exceed 20 mm. Figure 13 illustrates the recommend-
As shown in Figure 12, the only external components ed printed circuit board layout for the HPCL-x710.

VDD1 1 8 VDD2
C1 C2
VI 2 7 NC
YYWW
710

NC 3 6 VO

GND1 4 5 GND2

C1, C2 = 0.01 µF TO 0.1 µF

Figure 12. Recommended Printed Circuit Board layout.

VDD1 VDD2

VI
YYWW
710

C1 C2
VO

GND1 HCPL-0710 fig 11 GND2

C1, C2 = 0.01 µF TO 0.1 µF

Figure 13. Recommended Printed Circuit Board layout.

Propagation Delay, Pulse-Width Distortion and Propagation Delay

Skew
Propagation Delay is a figure of merit which describes
HCPL-0710 fig 12 from low to high. Similarly, the propagation delay from
how quickly a logic signal propagates through a high to low (tPHL) is the amount of time required for the
system. The propaga­tion delay from low to high (tPLH) input signal to propagate to the output, causing the
is the amount of time required for an input signal to output to change from high to low. See Figure 14.
propagate to the output, causing the output to change

INPUT 5 V CMOS
VI 50%
0V
tPLH tPHL

VOH
OUTPUT 90% 90%
VO 2.5 V CMOS
10% 10%
VOL

Figure 14.

10
HCPL-0710 fig 13
Pulse-width distortion (PWD) is the difference between Propagation delay skew is defined as the differ-
tPHL and tPLH and often determines the maxi­mum data ence between the minimum and maximum propa­
rate capability of a transmission system. PWD can be gation delays, either tPLH or tPHL, for any given group
expressed in percent by dividing the PWD (in ns) by of optocoup­lers which are operating under the same
the minimum pulse width (in ns) being trans­mitted. conditions (i.e., the same drive current, supply volt­age,
Typically, PWD on the order of 20 - 30% of the minimum output load, and operating temperature). As illustrated
pulse width is tolerable. The PWD specification for the in Figure 15,­ if the inputs of a group of optocouplers
HCPL-x710 is 8 ns (10%) maximum across recommend- are switched either ON or OFF at the same time, tPSK is
ed operating condi­tions. 10% maximum is dictated the difference between the shortest propagation delay,
by the most stringent of the three fieldbus standards, either tPLH or tPHL, and the longest propagation delay,
PROFIBUS. either tPLH or tPHL.
Propagation delay skew, tPSK, is an important parameter As mentioned earlier, tPSK can determine the maximum
to con­sider in parallel data applications where synchro- parallel data transmission rate. Figure 16 is the timing
nization of signals on parallel data lines is a concern. If diagram of a typical parallel data application with both
the parallel data is being sent through a group of op- the clock and data lines being sent through the opto-
tocouplers, differences in propagation delays will cause couplers. The figure shows data and clock signals at the
the data to arrive at the outputs of the optocouplers at inputs and outputs of the optocouplers. In this case the
different times. If this difference in propagation delay data is assumed to be clocked off of the rising edge of
is large enough it will determine the maximum rate at the clock.
which parallel data can be sent through the optocou-
plers.

DATA
VI 50%
INPUTS

2.5 V, CLOCK
VO
CMOS
tPSK

VI 50% DATA

OUTPUTS
tPSK
CLOCK
2.5 V,
VO
CMOS tPSK

Figure 15. Propagation delay skew waveform. Figure 16. Parallel data transmission example.

HCPL-0710 fig 14 HCPL-0710 fig 15

Propagation delay skew repre­sents the uncertainty of tocouplers in a parallel application is twice tPSK.
where an edge might be after being sent through an A cautious design should use a slightly longer pulse
optocoupler. Figure 16 shows that there will be uncer- width to ensure that any additional uncertainty in the
tainty in both the data and clock lines. It is important rest of the circuit does not cause a problem.
that these two areas of uncertainty not overlap,
The HCPL-x710 optocouplers offer the advantage of
otherwise the clock signal might arrive before all of
guaranteed specifications for propagation delays, pulse-
the data outputs have settled, or some of the data
width distortion, and propagation delay skew over the
outputs may start to change before the clock signal
recommended temperature and power supply ranges.
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through op-

11
Digital Field Bus Communication Networks
To date, despite its many draw­backs, the 4 - 20 mA Controllers can now receive multiple readings from field
analog current loop has been the most widely accepted devices (sensors, actuators, etc.) in addition to diagnos-
standard for implementing process control systems. tic information.
In today’s manufacturing environment, however,
The physical model for each of these digital field bus
automated systems are expected to help manage
communica­tion networks is very similar as shown in
the process, not merely monitor it. With the advent
Figure 17. Each includes one or more buses, an interface
of digital field bus communication networks such as
unit, optical isolation, transceiver, and sensing and/or
DeviceNet, PROFIBUS, and Smart Distributed Systems
actuating devices.
(SDS), gone are the days of constrained information.

CONTROLLER

BUS
INTERFACE

OPTICAL
ISOLATION

TRANSCEIVER
FIELD BUS

TRANSCEIVER TRANSCEIVER TRANSCEIVER TRANSCEIVER

OPTICAL OPTICAL OPTICAL OPTICAL

ISOLATION ISOLATION ISOLATION ISOLATION

BUS BUS BUS BUS

INTERFACE INTERFACE INTERFACE INTERFACE

XXXXXX SENSOR

YYY

DEVICE
CONFIGURATION MOTOR
MOTOR CONTROLLER
STARTER

Figure 17. Typical field bus communication physical model.

HCPL-0710 fig 16

Optical Isolation for Field Bus Networks

To recognize the full benefits of these networks, each These components could include such things as devices
recom­mends providing galvanic isolation using Avago with serial ports, parallel ports, RS232 and RS485 type
optocouplers. Since network communication is bi-direc- ports. As shown in Figure 18, power from the network is
tional (involving receiving data from and transmitting used only for the transceiver and input (network) side of
data onto the network), two Avago optocouplers are the optocouplers.
needed. By providing galvanic isolation, data integrity is
Isolation of nodes connected to any of the three types of
retained via noise reduction and the elimination of false
digital field bus networks is best achieved by using the
signals. In addition, the network receives maximum pro-
HCPL-x710 optocouplers. For each network, the HCPL-
tection from power system faults and ground loops.
x710 satisify the critical propagation delay and pulse
Within an isolated node, such as the DeviceNet Node width distortion require­ments over the temperature
shown in Figure 18, some of the node’s components are range of 0°C to +85°C, and power supply voltage range
referenced to a ground other than V- of the network. of 4.5 V to 5.5 V.

12
 AC LINE

NODE/APP SPECIFIC LOCAL

NODE
uP/CAN SUPPLY

GALVANIC
HCPL HCPL
ISOLATION
x710 x710 BOUNDARY

5 V REG.
TRANSCEIVER

DRAIN/SHIELD
V+ (SIGNAL)
SIGNAL
V– (SIGNAL)
V+ (POWER)
POWER
V– (POWER)

NETWORK
POWER
SUPPLY

Figure 18. Typical DeviceNet node.

Implementing DeviceNet and SDS withHCPL-0710

the HCPL‑x710
fig 17
Isolated Node Powered by the Network
With transmission rates up to 1 Mbit/s, both DeviceNet This type of node is very flexible and as can be seen in
and SDS are based upon the same broadcast-oriented, Figure 19, is regarded as “isolated” because not all of its
communica­tions protocol — the Controller Area components have the same ground reference. Yet, all
Network (CAN). Three types of isolated nodes are rec- compo­nents are still powered by the network. This node
ommended for use on these networks: Isolated Node contains two regulators: one is isolated and powers the
Powered by the Network (Figure 19), Isolated Node CAN controller, node-specific application and isolated
with Transceiver Powered by the Network (Figure 20), (node) side of the two optocoup­lers while the other is
and Isolated Node Providing Power to the Network non-isolated. The non-isolated regulator supplies the
(Figure 21). transceiver and the non-isolated (network) half of the
two optocouplers.

NODE/APP SPECIFIC

uP/CAN

ISOLATED
GALVANIC
HCPL HCPL SWITCHING
ISOLATION
x710 x710 POWER
BOUNDARY
SUPPLY
REG.
TRANSCEIVER

DRAIN/SHIELD
V+ (SIGNAL)
SIGNAL
V– (SIGNAL)
V+ (POWER)
POWER
V– (POWER)

NETWORK
POWER
SUPPLY

Figure 19. Isolated node powered by the network.

HCPL-0710 fig 18
13
Isolated Node with Transceiver Powered by the Network *Bus V+ Sensing
Figure 20 shows a node powered by both the network It is suggested that the Bus V+ sense block shown in
and another source. In this case, the trans­ceiver and Figure 20 be implemented. A locally powered node with
isolated (network) side of the two optocouplers are an un-powered isolated Physical Layer will accumulate
powered by the network. The rest of the node is errors and become bus-off if it attempts to transmit. The
powered by the AC line which is very beneficial when Bus V+ sense signal would be used to change the BOI
an application requires a significant amount of power. attribute of the DeviceNet Object to the “auto-reset”
This method is also desirable as it does not heavily load (01) value. Refer to Volume 1, Section 5.5.3. This would
the network. cause the node to continually reset until bus power was
detected. Once power was detected, the BOI attribute
More importantly, the unique “dual-inverting” design would be returned to the “hold in bus-off” (00) value.
of the HCPL-x710 ensure the network will not “lock-up” The BOI attribute should not be left in the “auto-reset”
if either AC line power to the node is lost or the node (01) value since this defeats the jabber protection ca-
powered-off. Specifically, when input power (VDD1) to pability of the CAN error confinement. Any inexpensive
the HCPL-x710 located in the transmit path is eliminat- low frequency optical isolator can be used to implement
ed, a RECESSIVE bus state is ensured as the HCPL‑x710 this feature.
output voltage (VO) go HIGH.

AC LINE

NON ISO
NODE/APP SPECIFIC 5V

uP/CAN

GALVANIC
HCPL HCPL HCPL
ISOLATION
0710 0710 0710
BOUNDARY

REG.
TRANSCEIVER

DRAIN/SHIELD
V+ (SIGNAL)
SIGNAL
V– (SIGNAL)
V+ (POWER)
POWER
V– (POWER)

NETWORK * OPTIONAL FOR BUS V + SENSE

POWER
SUPPLY

Figure 20. Isolated node with transceiver powered by the network.

HCPL-0710 fig 19

14
Isolated Node Providing Power to the Network
Figure 21 shows a node providing power to the More importantly, the unique “dual-inverting” design
network. The AC line powers a regulator which provides of the HCPL-x710 ensure the network will not “lock-up”
five (5) volts locally. The AC line also powers a 24 volt if either AC line power to the node is lost or the node
isolated supply, which powers the network, and another powered-off. Specifically, when input power (VDD1) to
five-volt regulator, which, in turn, powers the transceiv- the HCPL-x710 located in the transmit path is eliminat-
er and isolated (network) side of the two optocouplers. ed, a RECESSIVE bus state is ensured as the HCPL‑x710
This method is recommended when there are a limited output voltage (VO) go HIGH.
number of devices on the network that don’t require
much power, thus eliminating the need for separate
power supplies.

AC LINE

DEVICENET NODE

NODE/APP SPECIFIC 5 V REG.

uP/CAN

ISOLATED
GALVANIC
HCPL HCPL SWITCHING
ISOLATION
0710 0710 POWER
BOUNDARY
SUPPLY
5 V REG.
TRANSCEIVER

DRAIN/SHIELD
V+ (SIGNAL)
SIGNAL
V– (SIGNAL)
V+ (POWER)
POWER
V– (POWER)

Figure 21. Isolated node providing power to the network.

HCPL-0710 fig 20

15
Power Supplies and Bypassing
The recommended DeviceNet application circuit is the input and output power-supply pins of the HCPL-
shown in Figure 22. Since the HCPL-x710 are fully com- x710. For each capacitor, the total lead length between
patible with CMOS logic level signals, the optocoup­ler is both ends of the capacitor and the power supply pins
connected directly to the CAN transceiver. Two bypass should not exceed 20 mm. The bypass capac­itors are
capacitors (with values between 0.01 and 0.1 µF) are required because of the high-speed digital nature of the
required and should be located as close as possible to signals inside the optocoupler.

GALVANIC
ISOLATION
ISO 5 V BOUNDARY
5V
LINEAR OR
1 VDD1 VDD2 8 SWITCHING
REGULATOR
TX0 0.01 + +
2 VIN 7 µF
HCPL-0710 VCC
5 V+
0.01 µF 3 VO 6 TxD
CANH 4 CAN+

4 GND1 GND2 5 + 82C250 3 SHIELD

C4
0.01 µF CANL 2 CAN–
GND 1 V–
Rs REF
VREF
RXD
5 GND2 GND1 4 GND
C1
RX0 0.01 D1 0.01 µF R1
6 VO 3 µF 30 V 1M
500 V
HCPL-0710
0.01 µF 7 VIN 2

8 VDD2 VDD1 1

ISO 5 V 5V

Figure 22. Recommended DeviceNet application circuit.

HCPL-0710 fig 21

Implementing PROFIBUS with the HCPL-x710 PROFIBUS USER:

CONTROL STATION
An acronym for Process Fieldbus, PROFIBUS is essen- (CENTRAL PROCESSING)
OR FIELD DEVICE
tially a twisted-pair serial link very similar to RS-485
capable of achieving high-speed communi­cation up to
12 MBd. As shown in Figure 23, a PROFIBUS Control­ler USER INTERFACE
(PBC) establishes the connec­tion of a field automation FDL/APP
PROCESSOR
unit (control or central processing station) or a field
device to the transmission medium. The PBC consists UART
of the line transceiver, optical isolation, frame character PBC
transmitter/receiver (UART), and the FDL/APP processor
OPTICAL ISOLATION
with the interface to the PROFIBUS user.

TRANSCEIVER

MEDIUM

Figure 23. PROFIBUS Controller (PBC).

16

HCPL-0710 fig 22
Power Supplies and Bypassing
The recommended PROFIBUS application circuit is Being very similar to multi-station RS485 systems, the
shown in Figure 24. Since the HCPL-x710 are fully com- HCPL-061N optocoupler provides a transmit disable
patible with CMOS logic level signals, the optocoup ­ function which is necessary to make the bus free after
ler is connected directly to the transceiver. Two bypass each master/slave transmission cycle. Specifically, the
capacitors (with values between 0.01 and 0.1 µF) are HCPL-061N disables the transmitter of the line driver
required and should be located as close as possible to by putting it into a high state mode. In addition, the
the input and output power-supply pins of the HCPL- HCPL-061N switches the RX/TX driver IC into the listen
x710. For each capacitor, the total lead length between mode. The HCPL-061N offers HCMOS compatibility and
both ends of the capacitor and the power supply pins the high CMR performance (1 kV/µs at VCM = 1000 V)
should not exceed 20 mm. The bypass capac­itors are essential in industrial communication interfaces.
required because of the high-speed digital nature of the
signals inside the optocoupler.

GALVANIC
ISOLATION
BOUNDARY
5V ISO 5 V

8 VDD2 VDD1 1 ISO 5 V

0.01 µF 7 VIN 2
8
HCPL-x710 VCC
0.01 1
Rx 6 VO 3 R
µF 6
A +
0.01
µF RT SHIELD
5 GND2 GND1 4 SN75176B
4 7
D B –
3
DE
5V ISO 5 V
2 RE
1 VDD1 VDD2 8 GND
5
0.01 0.01 µF 1M
Tx 2 VIN 7 µF
HCPL-x710
0.01 µF 3 VO 6

4 GND1 GND2 5

ISO 5 V

1 VCC 8
5V
2 ANODE VE 7 680 Ω
0.01
1, 0 kΩ µF
Tx ENABLE 3 CATHODE VO 6

4 GND 5

HCPL-061N

HCPL-0710 fig 23

Figure 24. Recommended PROFIBUS application circuit.

17
For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0564EN
AV02-0641EN - January 4, 2008