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Unit V

This document contains 1 mark and 10 mark questions related to parallel processing and multiprocessor systems. Some key topics covered include: 1. Definitions of pipelining, parallel processing in SISD systems, and calculating pipeline speedup. 2. Difficulties that can cause instruction pipelines to deviate from normal operation and how RISC processors handle data conflicts and branch penalties. 3. Types of array processors, Flynn's classifications of computers, and structures of SISD, SIMD, and multiprocessor systems. 4. Improving system performance through multiprocessor organization and minimizing resource and data dependency conflicts in instruction pipelines.

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38 views2 pages

Unit V

This document contains 1 mark and 10 mark questions related to parallel processing and multiprocessor systems. Some key topics covered include: 1. Definitions of pipelining, parallel processing in SISD systems, and calculating pipeline speedup. 2. Difficulties that can cause instruction pipelines to deviate from normal operation and how RISC processors handle data conflicts and branch penalties. 3. Types of array processors, Flynn's classifications of computers, and structures of SISD, SIMD, and multiprocessor systems. 4. Improving system performance through multiprocessor organization and minimizing resource and data dependency conflicts in instruction pipelines.

Uploaded by

Bunny Rider
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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UNIT V

1 Marks Questions
1. What is pipelining?

2. How parallel processing may be achieved in SISD case?

3. To complete n tasks using K-segment pipeline requires how many clock cycles?

4. Give the expression for speedup of a pipeline processing over an equivalent non pipeline
processing.

5. What are the three major difficulties that the cause the instruction pipeline to deviate
from its normal operation

6. How the RISC processors handle the difficulties associated with data conflicts and branch
penalties?

7. What are the different types of array processors?

8. “All processors receive the same instruction from the control unit but operate on
different items of data.” This statement is referred to which of the Flynn’s classification
of computers?

9. Draw the structure of SISD?

10. What are super computers?

11. How the multiprocessors are classified on memory organization base?

12. What is parallel processing?

13. What is a multiprocessor system?

14. How system performance can be improved from a multiprocessor organisation?

15. How resource conflict problem can be minimized in instruction pipeline?

16. How data dependency conflict problem can be minimized in instruction pipeline?

17. What are the various interconnection structures, mention?

18. Write the various ways to avoid branch difficulties in instruction pipeline.

19 What is a dynamic priority algorithm?

20. How many processors are interconnected in an n-dimensional binary cube?

21. What is difference between SIMD and MIMD?

22. Draw the structure of SIMD?


23. Draw the block diagram of Crossbar switch.

24. What is a Hypercube system?

25. What is delayed branching?

26. Define control hazards.

27. Define structural hazard.

28. What is loosely coupled multiprocessor?

29. Mention different dynamic Arbitration Algorithms.

30. What is tightly coupled multiprocessor?

10 Marks Questions
1. a) A non-pipeline system takes 50 ns to process a task. The same task can be processed
in a six-segment pipeline with a clock cycle of 10 ns. Determine the speed-up ratio of
the pipeline for 100 tasks. What is the maximum speed-up that can be achieved?
[4M]
b) Write about Multi-stage switching network and draw 8 x 8 omega switching network.
[6M]

2. a) Discuss the Cache coherence problem and the resolving methods. [5M]
b) Explain Multi-port memory interconnection structure and give its advantages and
disadvantages. [5M]

3. Explain various schemes of Interconnection Structures with Suitable diagrams. [10M]

4. a) Formulate a four segment instruction pipeline for a computer. Specify the operations
to be performed in each segment. [4M]
b) Discuss the bottlenecks in instruction pipeline and explain how to resolve them.
[6M]
5. Write short notes on
a) Explain arithmetic pipeline. [5M]
b) RISC Pipeline [5M]

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