XILINX PROGRAMS FOR DIFFERENT IMPLEMENTATIONS OF 4X1 MULTIPLEXER

PROGRAM FOR DATAFLOW MODEL OF 4x1 MULTIPLEXER:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_dataflow is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

i2 : in STD_LOGIC;

i3 : in STD_LOGIC;

s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

y : out STD_LOGIC);

end mux_dataflow;

architecture Dataflow of mux_dataflow is

begin

y<=((not s1) and (not s0) and i0) or ((not s1) and s0 and i1) or (s1 and (not s0) and i2) or (s1 and s0 and i3);

end Dataflow;

PROGRAM FOR BEHAVIORAL MODEL OF 4x1 MULTIPLEXER:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_behavioral is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

i2 : in STD_LOGIC;

i3 : in STD_LOGIC;

s1 : in STD_LOGIC;
 s0 : in STD_LOGIC;

y : out STD_LOGIC);

end mux_behavioral;

architecture Behavioral of mux_behavioral is

begin

process(i0,i1,i2,i3,s1,s0)

begin

if( s1='0' and s0='0')then

y<=i0 ;

elsif( s1='0' and s0='1')then

y<=i1;

elsif( s1='1' and s0='0')then

y<=i2;

else

y<=i3;

end if;

end process;

end Behavioral;

PROGRAM FOR STRUCTURAL MODEL OF 4x1 MULTIPLEXER:

Program for component “2x1 MULTIPLEXER”

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2x1 is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

s : in STD_LOGIC;

e : in STD_LOGIC;
 y : out STD_LOGIC);

end mux2x1;

architecture Behavioral of mux2x1 is

begin

process(i0,i1,s,e)

begin

if( e='1')then

y<=((not s) and i0) or (s and i1);

else

y<=e;

end if;

end process;

end Behavioral;

Program for component “OR”

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or22 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end or22;

architecture Dataflow of or22 is

begin

c<=a or b;

end Dataflow;
Package File Template

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package mux_testpack is

component mux2x1 is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

s : in STD_LOGIC;

e : in STD_LOGIC;

y : out STD_LOGIC);

end component mux2x1;

component or22 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end component or22;

end mux_testpack;

Program for structural declaration

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.mux_testpack.all;

entity mux_structural is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

i2 : in STD_LOGIC;

i3 : in STD_LOGIC;
 s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

y : out STD_LOGIC);

end mux_structural;

architecture Structural of mux_structural is

signal t1,t2:STD_LOGIC;

begin

u0: mux2x1 port map(i0,i1,s0,(not s1),t1);

u1: mux2x1 port map(i2,i3,s0,s1,t2);

u2: or22 port map(t1,t2,y);

end Structural;

XILINX PROGRAMS FOR DIFFERENT IMPLEMENTATIONS OF 1X4 DEMULTIPLEXER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux_dataflow is

Port ( i : in STD_LOGIC;

s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

y0 : out STD_LOGIC;

y1 : out STD_LOGIC;

y2 : out STD_LOGIC;

y3 : out STD_LOGIC);
end demux_dataflow;

architecture Dataflow of demux_dataflow is

begin

y0<=(not s1) and (not s0) and i;

y1<=(not s1) and s0 and i;

y2<=s1 and (not s0) and i;

y3<=s1 and s0 and i;

end Dataflow;

PROGRAM FOR BEHAVIORAL MODEL OF 1x4 DEMULTIPLEXER:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux_behavioral is

Port ( i : in STD_LOGIC;

s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

y0 : out STD_LOGIC;

y1 : out STD_LOGIC;

y2 : out STD_LOGIC;

y3 : out STD_LOGIC);

end demux_behavioral;

architecture Behavioral of demux_behavioral is

begin

process(i,s1,s0)

begin

y0<='0';

y1<='0';
y2<='0';

y3<='0';

if(s1='0' and s0='0')then

y0<=i;

elsif(s1='0' and s0='1')then

y1<=i;

elsif(s1='1' and s0='0')then

y2<=i;

else

y3<=i;

end if;

end process;

end Behavioral;

PROGRAM FOR STRUCTURAL MODEL OF 1x4 DEMULTIPLEXER:

Program for component “1x2 DEMULTIPLEXER”

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux1x2 is

Port ( i : in STD_LOGIC;

e : in STD_LOGIC;

s : in STD_LOGIC;

y0 : out STD_LOGIC;

y1 : out STD_LOGIC);

end demux1x2;

architecture Behavioral of demux1x2 is

begin
process(i,e,s)

begin

if( e='1')then

y0<=(not s) and i;

y1<=s and i;

else

y0<=e;

y1<=e;

end if;

end process;

end Behavioral;

Package File Template

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package demux_testpack is

component demux1x2 is

Port ( i : in STD_LOGIC;

e : in STD_LOGIC;

s : in STD_LOGIC;

y0 : out STD_LOGIC;

y1 : out STD_LOGIC);

end component demux1x2;

end demux_testpack;

Program for structural declaration

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.demux_testpack.all;

entity demux_structural is

Port ( i : in STD_LOGIC;

s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

y0 : out STD_LOGIC;

y1 : out STD_LOGIC;

y2 : out STD_LOGIC;

y3 : out STD_LOGIC);

end demux_structural;

architecture Structural of demux_structural is

begin

u0: demux1x2 port map(i,(not s1),s0,y0,y1);

u1: demux1x2 port map(i,s1,s0,y2,y3);

end Structural;