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Tutorial

The document contains 10 questions related to sequential circuits and digital logic design. Question 1 asks to draw a Moore state graph for a sequential circuit with one input and output where the output becomes 1 after two 0s and two 1s have occurred at the input. Question 2 asks to draw a Mealy state graph and table for a circuit where the output is the input from two periods ago. Question 3 asks to design an asynchronous counter to divide a clock by 10.

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193 views

Tutorial

The document contains 10 questions related to sequential circuits and digital logic design. Question 1 asks to draw a Moore state graph for a sequential circuit with one input and output where the output becomes 1 after two 0s and two 1s have occurred at the input. Question 2 asks to draw a Mealy state graph and table for a circuit where the output is the input from two periods ago. Question 3 asks to design an asynchronous counter to divide a clock by 10.

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Beat Boy Rkay
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Tutorial Sheet-II

Q1. A sequential circuit has one input and one output. The output becomes 1 and remains 1
thereafter when at least two 0’s and at least two 1’s have occurred as inputs, regardless of the
order of occurrence. Draw a state graph (Moore type).

Q2. A sequential circuit has an input (X) and an output (Z). The output is the same as the input
was two clock periods previously. For example,
X=0101101011010001
Z=0001011010110100
The first two values of Z are 0. Find a Mealy state graph and table for the circuit.

Q3. Design an asynchronous counter which will divide the clock frequency by 10 i.e. f/10.

Q4. For the circuit shown in figure 1:


a) Construct a transition table and state graph for the circuit shown.
b) Construct a timing chart for the input sequence X = 10101. (Assume that initially Q1 = Q2 = 0
and that X changes midway between the rising and falling clock edges.) Indicate the times Z has
the correct value.
(c) List the output values produced by the input sequence.

Figure 1
Q5. An arbitrary flip flop has two inputs as YZ. The truth table is given as:

Y Z Qn+1
0 0 0
0 1 Qn
1 0 Qn’
1 1 1

Design a Mod-6 synchronous counter using YZ flip flop.

Q6. Design a four‐bit shift register with parallel load using D flip‐flops. There are two control
inputs: shift and load. When shift = 1, the content of the register is shifted by one position. New
data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal
to 0, the content of the register does not change.

Q7. Design F (A, B, C, D) = ∑ (0, 1, 2, 4, 5, 7, 11, 15) using PLA.

Q8. Design F (A, B, C, D) = π (1, 2, 3, 4, 5, 11, 12, 15) using PAL.

Q9. A 6-bit DAC has a step size of 100mV. Determine the full-scale output voltage and the
percentage resolution.
Q10. Find the output voltage for the given DAC.

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