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Micro II and Embedded

Systems

Introduction to PIC
Microcontroller

Revised based on slides from WPI ECE2801

Moving Towards Embedded
Hardware
Typical components of a PC:
 x86 family microprocessor
 Megabytes or more of main (volatile) memory
 Gigabytes or more of magnetic memory (disk)
 Operating System (w/ user interface)
 Serial I/O
 Parallel I/O
 Real-time clock
 Keyboard
 Video Display
 Sound card
 Mouse
 NIC (Network Interface Card)
 etc.

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 The PIC 16F87x Series
Microcontroller
Some of the characteristics of the PIC 16F87x series
 High performance, low cost, for embedded applications
 Only 35 instructions
 Each instruction is exactly one word long and is executed in 1
cycle (except branches which take two cycles )
 4K words (14bit) flash program memory
 192 bytes data memory (RAM) + 128 bytes EEPROM data
memory
 Eight level deep hardware stack
 Internal A/D converter, serial port, digital I/O ports, timers, and
more!

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What these changes mean when
programming?
 Since there is no DOS or BIOS, you’ll have to
write I/O functions yourself. Everything is done
directly in assembly language.
 Code design, test, and debug will have to be
done in parallel and then integrated after the
hardware is debugged.
 Space matters! Limitations on memory may
mean being very clever about algorithms and
code design.

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 PIC16F87X

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Harvard Architecture
Program memory and Data memory are separated memories
and they are accessed from separated buses.

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Instruction Pipelining
 It takes one cycle to fetch the instruction and another cycle to
decode and execute the instruction
 Each instruction effectively executes in one cycle
 An instruction that causes the PC to change requires two
cycles.

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 Program Memory
Organization
 13-bit program counter (PC)
⇒ addresses for 213 = 8K
locations
 Each location is 14 bits (All
the instructions are 14 bits
long)
 PIC16F874 has only 4K (x14
bit) program memory - the
upper bit is simply ignored
during fetches from program
memory
 Paging: 2K / page

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 Two Special addresses
 Reset Vector Address (0000h)
• When the CPU starts up from its reset state, its PC is automatically cleared
to zero.
• Assign goto Mainline instruction
Mainline
callInitial ;Initialize everything
MainLoop
call Task1 ;Deal with task1
callTask2 ;Deal with task2
…
call LoopTime ;Force looptime to a fixed value
goto MainLoop ;repeat
 Interrupt Vector Address (0004h)
• 0004h is automatically loaded into the program counter when an interrupt
occurs.
• Assign goto IntService instruction there: cause the CPU to jump to the
beginning of the interrupt service routine, located elsewhere in the memory
space.

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 PCL and PCLATH registers
 PC: Program
Counter, 13 bits
 PCL (02h): 8 bits,
the lower 8 bits of
PC
 PCLATH (0Ah): PC
Latch, provides the
upper 5 (or 2) bits
of PC when PCL is
written to

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 Stack
 8 level deep x 13 bit
wide hardware stack
 The stack operates as a
circular buffer. After the
stack has been pushed
eight times, the ninth push
will overwrite the value that was stored from the first push.
There are no status bits to indicate stack overflow or stack
underflow conditions.
 No PUSH or POP instructions. The PC is pushed onto the
stack when a CALL instruction is executed, or an interrupt
causes a branch. The stack is popped when a RETURN,
RETLW, or a RETFIE instruction is executed.
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Introduction to PIC Microcontroller:
Data Memory Organization
Review
 Harvard architecture
• Separated Program memory and Data memory, separated
access
• Instruction pipelining: while the first instruction is executed
(which might involves data memory access), the second
one is fetched from the program memory
 Program memory
• Up to 8K words (13 bit PC, 213=8K)
• Each word is 14 bits
• Each instruction is exactly 1 word long.
• General program structure – two special addresses: Reset
vector address (0000h) and Interrupt vector address
(0004h)
• 8 level deep hardware stack

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 Data Memory Organization
 Data memory is made up of
• Special Function Registers (SFR) area
• General Purpose Registers (GPR) area
 SFRs control the operation of the device, e.g.
• I/O ports and associated control registers used to establish each bit of a
port as wither an input or an output
• Registers that provide the data input and data output to the variety of
resources on the chip, such as the timers, the serial ports, and the analog-
to-digital converter.
• Registers that contain control bits for selecting the mode of operation of a
chip resource as well as enabling or disabling its operation
• Registers that contain status bits which denote the state of one of these
chip resources
 GPRs are the other name for the microcontroller’s RAM, are the
general area for data storage and scratch pad operations
 Register File is a PIC terminology, denote memory locations that an
instruction can access via an address.

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 Banking
 Data memory is partitioned into banks
 Each bank extends up to 7Fh (128) bytes
• 4 banks : 4*128 bytes = 512 bytes
• 2 banks : 2*128 bytes = 256 bytes
 Lower locations of each bank are reserved for SFRs. Above the SFRs
are GPRs.
 Implemented as Static RAM
 Some “high use” SFRs from bank0 are mirrored in the other banks
(e.g., INDF, PCL, STATUS, FSR, PCLATH, INTCON)
 RP0 and RP1 bits in the STATUS register selects the bank when
using direct addressing mode.

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 Direct Addressing
 Use only 7 bits of instruction to
identify a register file address
 The other two bits of register
address come from RP0 and
RP1 bits in the STATUS register
Example: Bank switching
CLRF STATUS ; Clear STATUS register (Bank0)
:;
BSF STATUS, RP0 ; Bank1
:;
BCF STATUS, RP0 ; Bank0
:;
MOVLW 0x60 ; Set RP0 and RP1 in STATUS register, other
XORWF STATUS, F ; bits unchanged (Bank3)
:;
BCF STATUS, RP0 ; Bank2
:;
BCF STATUS, RP1 ; Bank0

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Direct/Indirect Addressing

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Indirect Addressing
 The INDF register is not a physical register. Addressing the
INDF register will cause indirect addressing.
 Any instruction using the INDF register actually access the
register pointed to by the File Select Register (FSR).
 The effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit in STATUS register.
Example
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done? (to 0x2F)
GOTO NEXT ;no clear next
CONTINUE
: ;yes continue

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Special Function Registers (1)
 W, the working register
• To move values from one register to another register, the
value must pass through the W register.
 FSR (04h,84h,104h,184h), File Select Register
• Indirect data memory addressing pointer
 INDF (00h,80h,100h,180h)
• accessing INDF accesses the location pointed by IRP+FSR
 PC, the Program Counter, PCL (02h, 82h, 102h, 182h) and
PCLATH (0Ah, 8Ah, 10Ah, 18Ah)

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 Special Function Registers (2)
 STATUS (03h, 83h, 103h, 183h)

• IRP: Register bank select bit (indirect addressing)

• RP1:RP0 – Register bank select bits (direct addressing)
• NOT_TO: Time Out bit, reset status bit
• NOT_PD: Powel-Down bit, reset status bit
• Z: Zero bit ~ ZF in x86
• DC: Digital Carry bit ~ AF in x86
• C: Carry bit ~ CF in x86 (note: for subtraction, borrow is opposite)

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 I/O Ports
 General I/O pins are the simplest of peripherals used to monitor and
control other devices.
 For most ports, the I/O pin’s direction (input or output) is controlled by the
data direction register TRISx (x=A,B,C,D,E): a ‘1’ in the TRIS bit
corresponds to that pin being an input, while a ‘0’ corresponds to that pin
being an output
 The PORTx register is the latch for the data to be output. Reading PORTx
register read the status of the pins, whereas writing to it will write to the
port latch.
 Example: Initializing PORTD (PORTD is an 8-bit port. Each pin is
individually configurable as an input or output).
bcf STATUS, RP0 ; bank0
bcf STATUS, RP1
clrf PORTD ; initializing PORTD by clearing output data latches
bsf STATUS, RP0 ; select bank1
movlw 0xCF ; value used to initialize data direction
movwf TRISD ; PORTD<7:6>=inputs, PORTD<5:4>=outputs,
; PORTD<3:0>=inputs
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