CMP325

Operating Systems
Lecture 20-22
Non-Contiguous Memory Allocation

Spring 2019
Note: Arif Butt (PUCIT)
Some slides and/or pictures are adapted from course text book and Lecture slides of
• Dr Syed Mansoor Sarwar
• Dr Kubiatowicz
• Dr P. Bhat
• Dr Hank Levy
• Dr Indranil Gupta

For practical implementation of operating system concepts discussed in these slides,

students are advised to watch and practice video lectures on the subject of OS with
Linux by Arif Butt available on the following link:
http://www.arifbutt.me/category/os-with-linux/ 1
 Today’s Agenda
• Review of Previous Lecture
• Introduction to Paging
– Address Translation in Paging
– Implementation of Page Table
• In CPU Registers
• In Associative Memory
• In main memory
– Structure of Page Table
• Hierarchical
• Inverted
• Hashed
• Introduction to Segmentation
• Introduction to Paged Segmentation
• Intel 80386 Address Translation
2
 LOGICAL/VIRTUAL ADDRESS
• A Logical address is the address generated by the
process/CPU OR is the address used by the process to
access its own address space
– Logical Address Actual Physical RAM Address
– When a process access a logical address, MMU hardware translates the
Logical Address to Physical Address
– Operating System determines the mapping from Logical Address to Physical
address

• Benefits
– Isolation
– Illusion of larger memory space
– Relocation (A program does not need to know which physical
addresses it will use when it is run. Can even change physical location
when it is running)

3
 INTRODUCTION TO PAGING
• Paging is like reading a book. At any time we do not need all pages except ones
we are reading. The analogy suggest that pages we are reading are in the main
memory and the rest can be in the secondary memory
• Logical/Virtual address space is the set of addresses that programs use for
load and store operations on disk. Logical address space is divided into pages
• Physical address space is the set of addresses used to reference locations in
the main memory. Physical address space is divided into frames
• Pages and frames must be of same size
• Typical page sizes range from 1KB to 64 KB. (different for different
architectures)
• Pages that have been loaded into the main memory form disk are said to have
been mapped into the main memory
• A program / process is loaded by loading its pages into available not necessarily
contiguous frames
• To run a program having n pages, find n free frames and load the pages into
these frames. These frames need not to be contiguous. For example a program
comprising of 10 pages need 10 free frames in main memory, which need not to
be contiguous. For this to work, we need to store the mapping information of
which page is loaded in which frame, in some data structure called “Page Table”
• No external fragmentation. Internal Fragmentation in paging is half a page per
process
4
 PAGE TABLES
• Page Tables are used to keep track of
how logical addresses map to physical Frame No

addresses. Page table entries generally

000
contain the frame number where the
particular page is loaded. In addition a
PTE may also contain a modify bit,
resident bit, valid bit and protection
bits
• Page table size depends on the
maximum number of pages of a process
that a CPU support. E.g. if a system
support a process of maximum 8 pages
then the page table will contain 8 rows 111
(length is debatable). So the address
of page table will consist of 3 bits
5
USE OF PAGE TABLES

Frame # of memory
Page # of a process where this page is
loaded.

6
 LOGICAL & PHYSICAL ADDRESS FORMAT IN PAGING
Logical Address format (p, d)

• Address generated by CPU is divided into:

– Page number (p) – used as an index into a page table which contains
base address of each page in physical memory.
– Page offset (d) – combined with base address of frame to define
the physical memory address that is sent to the memory unit.

Physical Address format (f, d)

• Physical address translated from the L.A is divided into:

– Frame number (f) – kept in the page table against the page number.
– Frame offset (d) – is the same as the page offset

7
 ADDRESS TRANSLATION ARCHITECTURE IN PAGING
• Address translation means conversion of logical address into the
equivalent physical address.

Index to the page table

Displacement within
the page

PTBR +

Contains the base address

of Page Table

8
 PAGING EXAMPLE

• Page size = 4 bytes No of bits for page no = 2

No of bits for frame no = 3
• Process address space = 4pages Page#
Frame#
0111
• Physical address space = 8frames
(p,d)
• Logical address: (1,3) = 0111
(f,d)
• Physical address: (6,3) = 11011

11011

9
 SAMPLE PROBLEMS
Problem 6
• Consider a logical address space of 16 pages each of 1024 words (each word of 2
Bytes) mapped into a physical memory of 32 frames
• Give the Logical and Physical address format
• Also give the total Logical and Physical address space
• Compute the required page table size for this situation
Problem 7
• A system has 48 bit L.A & a main memory of 64 GBs. Page size is 4096 bytes.
Compute the number of pages and frames that exist in the system. Also give L.A &
P.A format.
Problem 8
• Consider a system with
– L.A = 32 bits ; Page Size = 4 K ; Main memory = 512 MB.
• Compute the total process address space and maximum number of pages in a process
address space. Also give the logical and physical address format. Also give the page
table size for this situation.
Problem 9
• Consider a LA space of 8 pages of 1024 words mapped into memory of 32 frames.
– How many bits are there in the LA?
– How many bits are there in PA?

10
 SAMPLE PROBLEMS
Problem 10
• In a system with a logical address space of 64 pages, each of 512 bytes
mapped into physical memory of 1024 frames. Compute lengths (in bits)
of p, d, f, logical and physical address format.
Problem 11
• A system has 48 bit logical address, physical address space is 32 bits
and page size is 4 KB. Determine the lengths of p, d, f, logical and
physical address formats, maximum number of pages per process and
maximum number of frames in the system, page table entry size (PTES)
and the size of the page table.
Problem 12
• Consider a system that allows maximum 2 Mega pages per process with 2
KB page size. Determine the length of the logical address only.
Problem 13
• Consider a system with 24 bits physical address space that supports a
frame size of 512 Bytes. Calculate the page table entry size (PTES) and
the length of physical address.
11
 SAMPLE PROBLEMS
Problem 14
• For each of the following logical addresses (given in decimal), compute the
page number and offset within the page; if the page size is 4 KB
– 20000
– 32768
– 60000
• Repeat for an 8 KB page
Problem 15
• A machine has a 32 bit address space and an 8 KB page. The page table is
entirely in hardware, with one 32 bit word per entry. When a process
starts, the page table is copied to the hardware from memory, at one
word every 100 nsec. If each process runs for 100 msec (including the
time to load the page table), what fraction of the CPU time is devoted to
loading the page tables?

Problem 16

• A machine has a 48 bit virtual addresses and 32 bit physical addresses.

Page size is 8 KB. How many entries are needed for the page table?

12
 SAMPLE PROBLEMS
Problem 17
• Let 14000 is a logical address, in which page does it exist if the page
size is 1 KB?

Problem 18
• In a system with 34 bits logical address and 32 bits physical address
and a 16 KB page size. How many entries will be there in the page table?

Problem 19
• Consider a virtual address 40808. Compute the virtual page number and
offset for a 4 KB page

13
IMPLEMENTATION OF
PAGE TABLE

14
 IMPLEMENTATION OF PAGE TABLES
IN CPU REGISTERS
• Design CPU in such a way that page table can be kept / maintained within the
CPU, using its registers. (costly affair)
• Feasible for small process address space with less number of pages which may
be of large size
• Effective Memory Access Time (time to convert L.A to P.A) is almost the same
as the Physical memory access time
• Example is PDP-11, which has eight pages each of size 8 KB

IN MAIN MEMORY
• Page table is kept in main memory
• Page-table base register (PTBR) points to the starting address of page table
• Page-table length register (PRLR) indicates size of the page table
• In this scheme every data/instruction access requires two memory accesses.
One for the page table (that resides inside the main memory) and one for the
data / instruction.
TEFFECTIVE = 2 TMEM

15
 IMPLEMENTATION OF PAGE TABLES (cont…)
IN ASSOCIATIVE CACHE / TLB
• Use a Cache / Translation Look Aside Buffer (TLB)
• Place references of some of the recently used pages in TLB, i.e. a
portion of page table resides in TLB and the rest in main memory
• On a context switch, the TLB is flushed and loaded with values for the
scheduled processes. (Normally TLB contains the page numbers of the
currently running process)
• If mapping is found page hit else page fault

16
 IMPLEMENTATION OF PAGE TABLE (cont…)
PAGING HARDWARE

LA

CPU P d
Page # Frame #
TLB
f Hit

PA
+ f d
PTBR

Contains the base TLB TLB (Cache in MMU)

address of Page Table Miss
f
Physical Memory

PT (In main memory)

17
 IMPLEMENTATION OF PAGE TABLE (cont…)

Performance In Paging

Effective Memory Access Time (Page hit) = Time to access TLB + Time to access memory

Effective memory Access Time (Page Fault) = Time to access TLB + 2 x Time to access memory

• If HR is the hit ratio and MR is the miss ratio then

TEFFECTIVE = HR (TTLB + TMEM ) + MR ( TTLB + 2 TMEM )

18
 IMPLEMENTATION OF PAGE TABLE (cont…)
Problem 20
• Consider a system with memory access time of 100 nsec. Page table is
implemented using associative memory. The TLB access time is 20 ns.
Hit ratio is 80%. Calculate the Effective memory access time. Calculate
the Effective memory access time if there is no TLB, i.e. the entire
page table is kept in memory.
Problem 21
• Repeat above example with a hit ratio of 95% and compare
Problem 22
Consider a paging system with the page table stored in memory.
a. If a memory reference takes 200 nanoseconds, how long does a paged
memory reference take?
b. If we add associative registers, and 75 percent of all page-table
references are found in the associative registers, what is the effective
memory reference time? (Assume that finding a page-table entry in the
associative registers takes zero time, if the entry is there.)

19
 IMPLEMENTATION OF PAGE TABLE (cont…)
Problem 23
• If the hit ratio to a TLB is 80%, and it takes 15 nanoseconds to search
the TLB and 150 nanoseconds to access the main memory, then what
must be the effective memory access time in nanoseconds?
Problem 24
• If the hit ratio to register is 30% and hit ratio to TLB is 50%, and it
takes 1 and 10 nanoseconds to search the register and the TLB
respectively and 150 nanoseconds to access the main memory, then what
must be the Effective Memory Access Time in nanoseconds?
Problem 25
• Consider a system with 80% hit ratio, 50 nsec time to search the
associative registers, 750 nsec time to access main memory. Find the
time to access a page:
a. When the page number is found in associative memory
b. When the page number is not found in associative memory
c. Find the effective memory access time

20
STRUCTURE OF
PAGE TABLE

21
 QUESTION 2: PAGE TABLE SIZE
• Isn’t the page table huge? How can it be stored in RAM?
• Yes, it would be…, so real real page tables aren’t simple
arrays

• For example, consider a logical address space of 64 bits and

page size of 4 KB. Also consider the 8 byte PTE. How big
the page table need to be?

22
 STRUCTURE OF PAGE TABLE
• L.A space increases day by day due to the large size of
processes, thus increasing the size of the Page Table
• Thus there is a dire need to structure Page Table in a
better way especially in situation where the Page Table
becomes larger in size than a single page size, i.e. a page
table cannot be contained by a single page
• We can use following techniques for the structure of our
page tables:
a. Multi level / Hierarchical Page Table
b.Hashed Page Table
c. Inverted Page Table
23
 Multi level / Hierarchical Page Tables
• Consider a system with a logical address of 32 bits, and page size of 4K
and each page entry of 4 Bytes
• Maximum pages in a process address space = 1M
• Page Table size = 4 M (because each entry in page table is of 4 Bytes).
Since total no of pages are 220 i.e. 1MB, so there will be 220 rows/
tupples /entries, each tupple of 4 Bytes. So page table size will be 4MB
• Since the system has a page size of 4K, therefore, the page table of 4M
can’t be accommodated in a single page of 4K. Thus we have to make
pages of the page table
• We keep two page tables:
– Outer page table / page directory (which keep track of the pages
of the inner page table)
– Inner Page Table which actually maps the frames
• No of pages in the outer page table = 4M / 4K = 1K
• So size of outer page table = 1K entries of 4 bytes each = 4KB
• This outer page table will now fit in one page

24
 Multi level / Hierarchical Page Tables (cont…)
• A logical address (on 32-bit machine with 4K page size) is divided into:
– a page number consisting of 20 bits.
– a page offset consisting of 12 bits.
• Since the page table is paged, the page number is further divided into:
page number page offset
– a 10-bit page number
p1 p2 d
– a 10-bit page offset
10 10 12
• Thus, a logical address is as follows: where p1 is an index into the outer page
table, and p2 is the displacement within
the page of the outer page table.

25
 Two-Level Page Table Scheme
Outer page table is used to get hold of various
pages inside the inner page table.

P1 is used to index the outer page table whose

entry will give us the base address of one of the 1 K pages each of size 4 KB
pages inside the inner page tables.

P2 is then used to index the particular inner page

table to get the Frame Number.

Note:
Only the outer most / top level page table is required
To be kept in memory at all times. Other pages of the
inner page tables can be copied to and from the hard
disk as needed.
26
 Two-Level Page Table Scheme (cont…)
Address-translation scheme for a two-level 32-bit paging architecture

Since address translation works from the outer page table inwards, this
scheme is also known as forward mapped page table. Pentium II uses this
architecture

27
 Multi level / Hierarchical Page Tables (cont…)
• Some other examples are:
– 32 bit Sun SPARC support 3 Level Paging
– 32 bit Motorola 68030 support 4 Level Paging
– 64 bit Sun Ultra SPARC support 7 Level Paging
• Since each level is stored as a separate table in memory,
converting a logical address to a physical one may take more
than three memory accesses
• As the no of levels increases, too many memory references
needed for address translation
• But at times this is required to support large process
address space, so that larger processes can be executed in
larger applications

28
 Inverted Page Tables
• A Page Table has one entry for each Page in the Logical Address space of
process
• An Inverted Page Table has one entry for each Frame in the Physical Address
space (Physical Memory)
• Entries of a Page Table contains Frame numbers
• Entries of a Inverted Page Table contains Page numbers and pid (information
about the process that owns that page)
• Page Table is indexed with page number, p
• Inverted Page Table is indexed with Frame number, f
• Inverted Page Tables are used to reduce the size of page table
• Only one page table is required in the system. (All processes will have / share a
single Inverted Page Table)
• Page table size is limited by the number of frames (i.e. the physical / main
memory) and not Process Address Space
• Each entry in the Page Table contains pid and p#. There is a possibility that
there are two processes executing at a time and each process has a page no 3.
So to avoid this confusion we have to keep pid as well
• 64 bit Ultra SPARC and IBM Power PC uses this technique

29
 Inverted Page Tables (cont…)
This scheme decreases the amount of memory needed to store each page table
but increases the time needed to search the table. It is because inverted page
table is sorted by Physical address, but looks up occur on Virtual address. So
the whole table might need to be searched for a match.

F# 0

Inverted Page Table is indexed with Frame # i,

and not with page # , hence is named as
(pid,p) pair is searched in the
inverted page table
Inverted Page Table. If a match
is found say at entry i, then Inverted Page Table has entries equal to
that is the Frame # where that the number of frames in Main memory. Each
page is loaded in main memory. entry contain the pid and its page number.

30
 Hashed Page Tables
• Another common approach to handle address spaces larger than 32 bits

is Hashed Page Table

• Hashing. A key is given, you pass it through a function that returns an

integer value known as hash value, which is used to index a table / array

(hash value must be within that array) where the required record will be

lying or may contain a pointer to the record (link list)

• Hash Function. A function used to manipulate the key of an element in a

list to identify its location in the list

31
 Hashed Page Tables (cont…)

Each entry in the L.L has three

fields: page number, frame number
for the page and pointer to the
next node- (p, f, next)

Search the L.L (page no and corresponding frame no)

looking for a node whose page no corresponds to the page no in the
Logical Address.

Contains one entry (Link List) for pages of one process. So here
we don’t have to look for pid.

• Hashing can be combined with Inverted Page Tables, to overcome its

limitation of complex / time consuming search.
• For 64 bit address space Clustered Page Tables are used.

32
 SAMPLE PROBLEMS
Problem 26
• A computer with a 32 bit address uses a two level page table. Virtual
addresses are split into a 9 bit top level page table field, an 11 bit
second level page table field and an offset. How large are the pages and
how many are there in the address space?
Problem 27
• Suppose that a 32 bit virtual address is broken up into four fields: a, b,
c and d. The first three are used for a three level page table system.
The fourth field, d, is the offset. Does the number of pages depend on
the sizes of all four fields? If not, which ones matter and which ones do
not?
Problem 28
• A computer has 32 bit logical addresses and 4 KB pages. How many
entries are needed in the page table if traditional (one level) paging is
used?
• How many page table entries are needed for two level paging, with 10
bits in each part?

33
 SAMPLE PROBLEMS
Problem 29
• Consider a system with 20 bit logical address and a page size of8 KB and
a single level page table. Let the page table base register (PTBR)
contains 14000 and PTES is 4 bytes. What will be the starting address
of the last entry of the page table? Also determine the maximum
number of pages per process supported by the system. What will be the
format of the logical address? Can you calculate the number of frames
with the provided information?
Problem 30
• Repeat above problem if logical address is of 32 bit and a two level
page table is used.
Problem 31
• Consider a system with 36 bits logical address that supports 4 KB page
size. Available physical memory is 64 MB. Calculate p, d, f, PTES,
minimum number of levels of the page table per process, format of
logical and physical addresses.

34
 SAMPLE PROBLEMS
Problem 32
• Consider a system with 36 bits logical address space that supports 4 KB page size.
Available physical memory is 64 GB. OS running on this system supports 32 bits
PIDs. Calculate p, d, f, PTES in an inverted page table, size of the inverted page
table, and the format of logical and physical addresses.
Problem 33
• In a system with 2048 MB RAM and a 4 KB page size, how many entries will be there
in an inverted page table?
Problem 34
• In a 64 bit machine, with 256 MB RAM and a 4 KB page size, how many entries will
there be in the page table if it is inverted?
Problem 35
• Consider a system that has a Process ID of 32 bits and uses inverted page table for
address translation. The 34 bits logical address is viewed as a 22 bits page identifier
(p) and 12 bits offset (d). Size of physical address is 32 bits. Compute page size,
PTES, number of pages, and size of inverted page table.

35
 SHARED PAGES
Shared Code
– One copy of read-only (reentrant) code shared among processes e.g.
text editors

– Shared code must appear in same location in the logical address

space of all processes

– Multiple invocations of vi editor or gcc; when multiple users invoke

vim the code part can be shared by multiple processes, while data
can be private for each process

Private Code and Data

– Each process keeps a separate copy of the code and data

– The pages for the private code and data can appear anywhere in the
logical address space
36
 Shared Pages Example

Consider three processes P1, P2, P3, each correspond to an editor, e.g. vim
P# F# Code of the editor is shared
0 by all the three processes,
loaded in frames 3, 4 and 6,
1 which corresponds to page# 0,
1, 2 respectively.
2
3

P# F#
0

Each process page table has four 1

pages, three for the editor code 2
and one for the buffer / data.
3

P# F#

2
3 Thus all processes are accessing the same
physical memory frames for the code of
editor. This way we have avoided to load the
code of the editor at three different
locations.

37
INTRODUCTION TO
SEGMENTATION

38
 INTRODUCTION TO SEGMENTATION
• A segment is a set of logically related instructions or data elements associated
with a given name
• A segment is a logical unit such as: Main program, procedure, function, local &
global variables, stack, symbol table, arrays
• A program is a collection of segments. Each program is divided into a number of
segments which can be of different lengths, however, there is a maximum
segment length
• A program is loaded by loading all of its segments into dynamic partitions that
need not to be contiguous
• Memory-management scheme that supports programmer’s view of memory
• Private Code and Data
– Each process keeps a separate copy of the code and data
– The pages for the private code and data can appear anywhere in the logical
address space

The user does not think of memory as a

Subroutine Stack linear array of words. Rather the user
prefers to view memory as a collection of
Symbol variable sized segments, with no
SQRT Main Table necessary ordering among segments.
Program

User's view of a program

39
 LOGICAL VIEW OF SEGMENTATION

1 4

3
2
4

3
Segment Table

User space
Physical memory space
• In paging we store the pages in frames and keep the mapping in page table
• In segmentation instead of pages we have segments that are kept in the
frames and we keep the mapping in segmentation table
• Unlike pages segments can be of variable size
40
 SEGMENTATION ARCHITECTURE
• Logical address consists of a two tuple:
• <segment-number, offset>,
• Segment-table base register (STBR) points to the segment table’s location in
memory
• Segment-table length register (STLR) indicates number of segments used by a
program;
• segment number s is legal if s < STLR Base contains the
Segment Table base address of the
Ensure that s < STLR. If segment where the
yes then adds STBR to it s segment resides in
and then index the memory.
Segment table. limit base

CPU (s,d)
Each segment table entry
has: Memory
- Base contains the starting
y
physical address where the < +
segment resides in memory. Limit field inside PA
the Segment n

- Limit specifies the length Table refers to error

the length of the
of the segment.
segment inside the
main memory.

41
 SEGMENTATION EXAMPLE

Subroutine Stack
Segment 3 1400
Segment 0 Segment 0
2400
Symbol
Table
SQRT Segment 4 3200

Main Segment 3
Segment 1
Program
Segment 2 4300
Segment 2
4700
Logical Address Space
Segment 4

5700
Segment Table 6300
Segment 1
limit base 6700
0 1000 1400
1 400 6300
2 400 4300
3 1100 3200
4 1000 4700

42
 SAMPLE PROBLEMS
Problem 36
Consider the given segment table, What are the Physical
addresses for the following logical addresses: Segment Table
• (2,399) limit base
0 1000 1400
• (4,0) 1 400 6300
2 400 4300
• (4,1000) 3 1100 3200
4 1000 4700
• (3,1300)
• (6,297)
Problem 37
Consider the given segment table, What are the
Physical addresses for the following logical Seg Base Len
addresses:
• 0,430 0 219 600
1 2300 14
• 1,10
2 90 100
• 2,500 3 1327 580
• 3,400 4 1952 96

• 4,112

43
Problem 38
SAMPLE PROBLEMS
Segment # Length Base
Consider the given segment table, What are the 0 100 1200
Physical addresses for the following logical 0
addresses:
1 1200 1210
• (0, 0) 0
2 190 1330
• (2, 120)
0
• (6, 10) 3 444 1550
0
• (5, 3399)
4 19308 1800
• (4, 1200) 8
• (0, 99) 5 3400 5000

Problem 39
Consider the above segment table, if segment table base register (STBR)
contains 36500 and segment table entry size (STES) is 64 bits then what
will be size of segment table? Also compute the address of the last entry?

44
 SAMPLE PROBLEMS
Problem 40
• Compare between Segmentation and Base/Bound Address Translation
Techniques
1. Segmentation supports generalized base and bound with support of multiple segments at once
2. Protection: Different segments can have different protections
3. Flexibility: Can separately grow both stack and heap. Enables sharing of code and other segments if
needed

Problem 41
• What is the main difference between paging of memory and
segmentation of memory? List two ways in which this difference affects
the address translation hardware required with each scheme.

45
 EXTERNAL FRAGMENTATION IN SEGMENATION
• External fragmentation exist in segmentation

• Holes can be adjusted by compaction, i.e. shuffle segments

to place free memory together in one block

• Compaction is possible only if relocation is dynamic and is

done at execution time

• So in segmentation we need run time address binding, i.e.

dynamically a segment of process can be shifted to another
location within the process address space within the main
memory

46
 INTRODUCTION
TO
PAGED SEGMENTATION

47
 PAGED SEGMENTATION
• When the segments size become too large the larger is the
External Fragmentation

• To prevent it, we page the segments (like we paged the Page

Table)

• In paging, against every process we had a Page Table which used

to map the pages of that particular process with the frames in
the Physical memory where those pages were loaded

• Here every segment will be further divided into pages and their
mapping information is kept in the Page Table

• So every segment will have a Page Table. This way there will
be no External fragmentation
48
 PAGED SEGMENTATION EXAMPLE

1
1
Subroutine Stack
Segment 3 2
Segment 0
0
Symbol 3 3
Table 0
-
SQRT Segment 4 1 1
-
Segment 1 Main 2 126
Program -
Segment 2 3 10
10 3
Logical Address Space
-
Page Table
-
-
126 2

Here we have divided segment 4 into four pages and kept that information in page table.

49
 PAGED SEGMENTATION EXAMPLE
• Logical address is still <s,d>, with s used to index the segment table
• Each segment table entry consist of the tupple <seg-length, page-
table-base>
• The logical address is legal if d < seg-length.
• Segment offset, d, is partitioned into two parts: p and d’
• p is used to index the page table associated with segment s
• d’ is used as offset within a page.
• p indexes the page table to retrieve frame, f, and physical address (f,d’)
is formed.
Max size of segment

s d

index segment
table
Maximum possible number p d’
of segments within a
process
index page table offset within the page p
Maximum possible
number of pages Size of a page
within a segment
50
TRANSLATION (LA - PA) IN PAGED SEGMENTATION

d < seg-len
Seg-len >= d

d’ is the offset
within the page

51
 SAMPLE PROBLEM
Problem 42
Consider MULTICS on a GE 345 processor, with Logical
Address of 34 bits and page size of 1 KB. s is of 18 bits and
d is of 16 bits.
– What is the largest segment size?
– What is the maximum number of segments per process?
– Give maximum number of pages per segment.
– Give the LA format including the no of bits for p and d’

52
 SAMPLE PROBLEM
Problem 43
• Consider a process in MULTICS with its segment # 15
having 5096 bytes. The page size is 1 KB. The process
generates a Logical Address of (15, 3921).
– Is it a legal address? If yes why?
– How many pages does the segment have?
– What page does the logical address refer to, and what is
its offset?
– What is the P.A if page#3 (i.e. fourth page) is in frame
12?

53
Problem 44
SAMPLE PROBLEMS
Segment # Length Base
Consider the given segment table. How many page 0 100 1200
tables will be constructed for the process whose 0
segments are shown in the segment table?
1 1200 1210
Problem 45 0
2 190 1330
Consider the given segment table. If the system
0
implements paged-segmentation with the page size
of 2 KB, then compute the page number and offset 3 444 1550
0
for the logical address of (4, 12765). Also compute
the number of pages in segment 4 and the address 4 19308 1800
of the 3rd entry in the page table (Assume PTES is 8
4 Bytes) 5 3400 5000

Problem 46
Consider the above segment table, if segment table base register (STBR)
contains 36500 and segment table entry size (STES) is 64 bits then what
will be size of segment table? Also compute the address of the last entry?

54
 SAMPLE PROBLEM
Problem 47
Consider a logical address in paged segmentation (16, 7865), where 16 is
segment number and 7865 is offset. Suppose segment 16 has length of
15690 bytes. Page size is 1 KB. Calculate following:
• Number of pages in segment number 16
• In which page the above said offset will reside?
• How would you represent the above address in <s, p, d’> format?
• Let the page p is stored at frame 30, what would be the physical
address?

55
We’re done for now, but
Todo’s for you after this
lecture…
• Go through the slides and Book Sections: 8.4 - 8.8
• Solve all the sample problems given in slides to
understand the concepts discussed in class

56