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    Tutorial For Design Compiler: Shell Prompt

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    sudhakar kandi
    1) The tutorial provides steps to use Design Compiler to synthesize a Verilog design on the Linuxlab server. 2) It involves logging in, setting up the ESE461 environment, writing Verilog and TCL files, and using the dc_shell command to compile the design. 3) Upon successful compilation, timing, power, area and other reports will be generated for analysis and optimization of the design.

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    Tutorial For Design Compiler: Shell Prompt

    Uploaded by

    sudhakar kandi
    83 views7 pages
    1) The tutorial provides steps to use Design Compiler to synthesize a Verilog design on the Linuxlab server. 2) It involves logging in, setting up the ESE461 environment, writing Verilog and TCL files, and using the dc_shell command to compile the design. 3) Upon successful compilation, timing, power, area and other reports will be generated for analysis and optimization of the design.

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    dc tutorial

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    1) The tutorial provides steps to use Design Compiler to synthesize a Verilog design on the Linuxlab server. 2) It involves logging in, setting up the ESE461 environment, writing Verilog and TCL files, and using the dc_shell command to compile the design. 3) Upon successful compilation, timing, power, area and other reports will be generated for analysis and optimization of the design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    83 views7 pages

    Tutorial For Design Compiler: Shell Prompt

    Uploaded by

    sudhakar kandi
    1) The tutorial provides steps to use Design Compiler to synthesize a Verilog design on the Linuxlab server. 2) It involves logging in, setting up the ESE461 environment, writing Verilog and TCL files, and using the dc_shell command to compile the design. 3) Upon successful compilation, timing, power, area and other reports will be generated for analysis and optimization of the design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 7

    Tutorial for Design Compiler

    STEP 1: Login to the Linux system on Linuxlab server. Start a terminal (the shell
    prompt). (If you don’t know how to login to Linuxlab server, look at here)

    Click here to open a shell window

    Fig. 1 The screen when you login to the Linuxlab through equeue
    STEP 2: Build work environment for class ESE461.
    In the terminal, execute the following command:
    module add ese461
    This command will build work environment for class ESE461. You could perform
    “module avail” in the terminal to find the available modules on Linuxlab before
    you do “module add ese461” . Make sure ese461 is presented when you execute
    this command.

    1.Find the available modules

    2.Make sure ese461 is presented

    3.This command will set up the work


    environment for class ESE461

    Fig. 2 Build work environment for class ESE461 using module


    1
    STEP 3: Getting started with Verilog
    • Creating a new folder (better if you have all the files for a project in a
    specific folder).
    • Enter into this new folder and start writing your Verilog script in a new file
    (.v file). Example code for modeling an counter is here
    Note: We do not need tech bench here, because test bench is for simulation,
    but here we do RTL synthesis, which is the next step after simulation.

    Use gedit to edit the .v files


    (gedit is a commonly used GUI editor on Linux )

    Fig. 3 Edit module file using gedit


    STEP 4: Writing constraints file - “.tcl” file
    Example tcl file for counter above is here.
    Based on the example tcl file:
    • Lines where modifications are required specific to model:
     Set Path to Verilog files
     Top module of the design have to be specified (To specify the Hierarchy)
     Specifying the clock port used in the model
     Clock frequency at which the model is operated
    Note: Please go through the provided .tcl file to check other options by yourself.
    Create or edit the .tcl file using gedit

    Fig. 4 Edit tcl file using gedit

    List all your designed verilog files here

    Tell the design compiler the top module of the design


    (You should not what is the top module of your design)

    Specify the period of your clock input(unit: ps)


    Frequency = 1/The period of clock

    Specify the input of the clock of your design

    Fig. 5 Lines that modifications are required


    2
    STEP 5: Compile your code
    • In the terminal, change the directory to where your model (Counter.v) and
    tcl(compiledc.tcl) files are present by using this command:
    cd <path>
    For example:
    cd ~/ESE461/DCTutorial/
    (Remark: ‘~’ means home directory on Linux)
    • Compile the files by typing in the terminal:
    dc_shell-t -f <file>.tcl
    In the above example, it should be:
    dc_shell-t -f compiledc.tcl
    After run this command, there might be some warning but no error
    presented in the terminal. Otherwise you need to check your code or tcl file
    and correct them according to the related messages.
    Note: The oldest messages might be lost due to too many lines printed on
    the terminal. In this situation you could redirect the output to a file:
    dc_shell-t -f compiledc.tcl > compiledc.log
    Then you can open compiledc.log using gedit and search in it. The “>” here
    is the sign for Output Redirection in Linux shell.

    3
    After successfully done STEP 1~ STEP 5, you will find the following report
    files(name of the files are defined in tcl file above) in your project folder:
    Note: my_toplevel following is defined in tcl file. In the above example
    my_toplevel is Counter
    1.Timing Analysis reports:
    • <my_toplevel>_min_timing.repC
    • <my_toplevel>_max_timing.repC
    • <my_toplevel>_out_min_timing.repC
    Make sure the timing report requirements are MET. You can observe which
    module in the design is giving the maximum delay and optimize accordingly.
    Example:

    Fig. 6 Partial of timing report(Counter_min_timing.repC)


    4
    2. Power Analysis reports:
    • <my_toplevel>_power.repC
    Design Compiler gives the detailed information about the static and dynamic
    power.
    Example:

    Fig. 7 Partial of power report(Counter_power.repC)

    5
    3. Area Analysis reports:
    • <my_toplevel>_area.repC
    Area report file generated using design compiler contains detail information
    about the size of each cell used for this model. Units for Virginia tech library are
    micro meters.
    Example:

    Fig. 8 Partial of area report(Counter_area.repC)


    4. Design Analysis reports:
    Important information found in this report is the operating conditions. VT library
    only support normal conditions for operation. But in technology libraries
    provided by the vendor there are some extreme conditions (WCCO – worst case
    conditions) available for getting the maximum values to verify the performance of
    the model.
    Example:
    • <my_toplevel>_area.repC

    Fig. 9 Partial of design report(Counter_area.repC)


    6
    Additional Information for Design Compiler:
    The process that Design Compiler does is RTL synthesis. This means, converting
    a gate level logic Verilog file to transistor level Verilog with the help of
    Technology library provided by the foundry.

    Useful links:
    http://lyle.smu.edu/~manikas/SDC_help/dvtut.pdf
    http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/dc.pdf

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