A Comparative Analysis of Different

Types of Multipliers
Monu Kumari* and Sunita Malik**

The paper presents an analytical comparison of different types of multipliers like booth, array
and wallace tree multipliers based on different performance metrics such as power, area and
speed by reducing the partial products. Partial products are mainly responsible for complexity
and area, so the paper focuses on reducing the partial product stage. It is found that wallace
tree multiplier is best among all the above multipliers. As the multiplier size increases, the
complexity also increases in wallace tree, so booth multiplier is best for large size.

Keywords: Booth multiplier, Wallace tree multiplier, Propagation delay, Partial product, Power
consumption

Introduction
In today’s era, a high speed system requires a multiplier to perform complex binary
multiplication. Thus multiplier becomes a significant component in high speed devices.
It is seen from literature, that most of the instructions and almost all of the DSP
algorithms are executed by multipliers. High speed multiplication is the primary
requirement of high performance system. In many algorithms, multiplication is used
as one of the essential operations. Addition and multiplication of two binary numbers
are mostly used in arithmetic operation in high performance devices (Honglan et al.,
2015). Today, multipliers have a very effective role in digital signal processing systems
and a wide range of applications (Soniya and Suresh, 2013). Statistics indicate that
3/4th of commands in microprocessor are based on addition and multiplication (Soniya
and Suresh, 2013). Addition requires more time than multiplication at large scale, so
we require a high speed multiplier. High speed processing demand has been increasing
exponentially with time.
The paper is structured as follows: first it explains the various multipliers in
literature review; then it defines the basic multiplication operation and its
requirement, followed by array multiplier; then it describes booth multiplier; next it
explains wallace multiplier, followed by a comparative analysis of different types of
* M. Tech Student, Department of Electronics and Communications, Deenbandhu Chhotu Ram University
of Science & Technology, Murthal, Sonipat, Haryana, India; and is the corresponding author.
E-mail: [email protected]
* * Assistant Professor, Department of Electronics and Communications, Deenbandhu Chhotu Ram
University of Science & Technology, Murthal, Sonipat, Haryana, India. E-mail: [email protected]

42
© 2019 IUP. All Rights Reserved. The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019
multipliers; then it defines the application of the multiplier and future scope; and
finally, the paper ends with conclusion.

Literature Review
Ron and Earl (2010) made a comparison between modified wallace tree multiplier and
conventional wallace tree multiplier. A reduced complexity wallace tree multiplier
favors a smaller number of partial products. Conventional wallace tree reduction
technique requires five times less number of the half adders in comparison to modified
wallace reduction, but modified wallace tree requires more number of full adders
for the reduction compared to conventional wallace tree reduction. A number of
half adder and full adder reduction techniques are used to increase the speed. For
fast multiplication, less number of partial products are required, which is reduced
by less number of gates. Half adder reduction does not contribute to partial product
reduction, but it reduces the complexity. Modified wallace reduction is less complex
than conventional because it reduces half adder by at least 80%. Modified Wallace
has less delay than convention Wallace tree reduction.

Cooper et al. (1998) described 16-bit multiplier design which is suitable for high
bit multiplication with low error. 105 µm CMOS process was used to design a modified
booth multiplier using gate level in Ella and resister level in Pascal. Han and Orshansky
(2013) presented energy efficient techniques to make the multiplier more efficient.
Approximate computing defines many areas in which they worked and made
multiplier more energy efficient using different techniques. Iffat (2012) described the
analysis of 8-bit Multiplier Accumulator (MAC) and calculated various factors like
power, speed and efficiency and then compared with the existing multipliers. Low
power and energy efficient electronic designs are most important factors at large-
scale of integration.

Jagadeesh and Venkata Chary (2012) proposed a new method of multiplication

by combining multiplier and accumulator (MAC) for high speed multimedia
information and DSP application. For power reduction, Spurious Power Suppression
Techniques (SPST) and delay are reduced by MAC accumulator which accumulate the
intermediate results i.e., sum and carry bit instead of output of final full adder. Aravind
et al. (2016) described the performance of various multipliers in terms of area, power,
propagation delay and IO Buffers for radix-4. According to them, partial products
can further be reduced and power can be saved. Modified booth multiplier is best
suited for high speed and low power application. Cho et al. (2004) proposed an error
compensation method for modified booth multiplier to reduce the quantization error.
Booth encoder outputs were used to generate error compensation bias to efficiently
compensate the quantization error. This method has resulted in reduced area and
low power consumption of the multiplier.

A Comparative Analysis of Different Types of Multipliers 43

 Anubhuti et al. (2017) presented the designing and implementation of 16 order
FIR filters using various multiplication techniques to get efficient delay, filter area and
power. Analysis of different types of adders such as RCA, Kogge Stone adder, Han
Carison and Brent Kung adder was done to design a high speed FIR filter. Add and
shift multiplication algorithm reduces the filter area and power but it increases the
power dissipation. Binary coefficient is represented in the form of canonical signed
digit to reduce the filter complexity. FIR filter is implemented with various multiplication
techniques such as wallace tree multiplier, vedic multiplier and add and shift algorithm
to reduced area, power and delay. A comparative analysis was done among these
techniques of FIR filter at different frequencies. Electronic Data Processing (EDP)
calculation shows that wallace tree multiplier is the best method of multiplication
among these techniques. The paper proposes a comparison based on:
• Electronic Data Processing; and
• Look Up Table (LUT)
Honglan et al. (2015) described the low power radix-8 booth multiplier for LPVLSI
design. Modified booth (or radix-4) algorithm has a better performance than
radix-8 booth multiplier because radix-4 multiplier has less number of partial
products than radix-8. Radix-4 is less complex because of less number of partial
products. But in the case of radix-8 booth multiplier, odd multiples of the
multiplicands are generated which increase the complexity. As compared to a
multiplier using radix-4 (or modified Booth) algorithm with radix-8, it is found that
radix-4 is much faster than radix-8. The paper uses 2 bit adder to find the triple
of the binary numbers. Low power, short critical path delay and small area are
required by this adder.
Soniya and Suresh (2013) presented various types of multipliers and accumulator
units. They compared different types of multipliers based on area, accuracy, power
and speed. Different types of multipliers such as wallace tree multiplier, sequential
multiplier, booth multiplier, array multiplier and combinational multiplier were studied
to find out the best multiplier in terms of the above parameters. Pipelined booth
multiplier was also used to improve power consumption and speed. To decrease
power consumption, SPST technique is used for removing the unwanted data.
Sequential multiplier is best for large binary number multiplication as compared to
combinational multiplier, and pipelined booth multiplication is best in terms of speed.
For low power and less area, SPST technique is the best.

Multiplier
In designing a multiplier, power consumption is a big issue (Sonia and Suresh, 2013).
By reducing the number of operations, power consumption can be minimized. Total
power depends on dynamic power consumption. If dynamic power is reduced, then

44 The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019

total power is also reduced. Multipliers are complex adder array. Multiplications are
expensive and slow operation, but today multiplication becomes an essential operation
in all digital signal processing applications. Nowadays, we require a system with low
power consumption with high speed. So low power and high speed demand has been
increased with time. And designers mostly focused on designing low power and high
speed system. An effective multiplier must have high speed and low power, physically
packed together.
Figure 1 shows the multiplication between two 4-bit numbers in binary. A0-A3 was
the 1st multiplier and B0-B3 was the 2nd multiplier given as an input. Then 1st bit of
the 2nd multiplier (B0) was multiplied with all 4-bits of multiplier 1. Then 2nd bit (B1)
was multiplied. Here C was the carry, and then added, and after addition, B2
multiplied and then added and so on. Partial products were called intermediate signal
here. Y0-Y7 was generated which was the output. Figure 2 also shows internal
structure and designing of 4-bit array multiplier.

Figure 1: 4-Bit Multiplication

A3 A2 A1 A0

 B3 B2 B1 B0 Inputs

C A3  B0 A2  B0 A1  B0 A0  B0

+ A3  B1 A2  B1 A1  B1 A0  B1
Intermediate
Signals
C SUM SUM SUM SUM

+ A3  B2 A2  B3 A1  B2 A0  B2

C SUM SUM SUM SUM

+ A3  B3 A2  B3 A1  B3 A0  B3

C SUM SUM SUM SUM

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Outputs

A Comparative Analysis of Different Types of Multipliers 45

 Figure 2: Array Multiplier

x3 y 0 x2 y 0 x1 y 0 x0 y 0

0 0 0

x3 y 1 x2 x1 x0
FA FA FA
y1 y1 y1

x3 y 2 x2 x1 x0
FA FA FA
y2 y2 y2

x2 x1 x0
x3y3 FA FA FA
y3 y3 y3

+ + +

P7 P6 P5 P4 P3 P2 P1 P0

The following three steps are involved in a multiplication process (Fayed and
Bayoumi, 2002):
• Partial product generation;
• Partial product reduction; and
• Final addition
m bit partial products are created and the length of the formed product is
n + m bits long when multiplicand of n-bit multiply with multiplier of m-bit.
There are three types of multipliers:
• Array multiplier;
• Wallace tree multiplier; and
• Booth multiplier

46 The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019

Array Multiplier
Array multiplier is used for multiplication. It is also known as a multiplier with regular
structure. The circuits of array multiplier are randomly used with minimum complexity.
Add and shift process is used to establish multiplier circuit. According to their bit
orders, the partial products are shifted one by one and then added. For addition,
normal carry propagate adder is used to generate partial product. For N bit multiplier,
the entire number of required adders is N – 1, N being the length of the multiplier.
The number of bits of partial products produced is equal to the number of the
multiplier bits. Each partial product during multiplication is due to the multiplication
of one bit of multiplier with multiplicand.
The above multiplier calculation shows the multiplication between two 4-bit
numbers in binary. A0-A3 was the 1st multiplier and B0-B3 was the 2nd multiplier given
as an input. Then 1st bit of the 2nd multiplier (B0) was multiplied with all 4-bits of
multiplier1. Then 2nd bit (B1) was multiplied. Here C was the carry, and then added,
and after addition B2 multiplied and then added and so on. Partial products were
called intermediate signal here. Y0-Y7 was generated which was the output.

Advantages
• They are simply scalable.
• Array multiplier is used only with pipelined structure; because of their small
complexity, they have a regular structure and simple to place anywhere and route.
• Array multipliers are used only with minimum complexity.
• Transportation of array multiplier is very easy.

Disadvantages
• Large power consumption due to large number of partial products.
• They require more chip area due to large number of gates.

Booth Multiplier
Booth multiplication is required for the multiplication of two or more than two signed
numbers. Figure 3 shows multiplication of two 8-bit binary numbers using booth
multiplier.
The steps used for multiplication of binary numbers using booth algorithm are
given below: Assume A and B are two binary numbers. i is the number of bits in
A and B having j number of bits (i and j are equal).
Example of booth algorithms:
0111 x 0011
0111(+7)
0011(+3)

A Comparative Analysis of Different Types of Multipliers 47

 2’s Complement of multiplicand (0111):
1000 + 1 = 1001
Booth’s recoding of multiplier 0011 0 = 0 +1 0 –1
0111
0 -1 0 -1 1 11 1 1 00 1 2’s
complement of multiplicand
0 0 0 0 0 0 0
0 0 0 1 1 1 Add multiplicand
0 0 0 0 0

0 0 0 1 0 1 0 1 (21)

Figure 3: Block Diagram of Booth Multiplier

Y[7:0]
X[7:0]
8
8 8 8 8 8

0 Booth 3 Booth
x<0>
x<1> Encoder Decoder

x<1> Booth 3 Booth Sign Extend

x<2>
x<3> Encoder Decoder
9
x<3> Booth 3 Booth Sign Extend
x<4>
x<5> Decoder 7 2
Encoder
9 9
x<5> Booth 3 Booth Sign Extend
x<6>
x<7> Encoder Decoder 12-bit CLA Adder
9
Sign Extend 9 7
2
12-bit CLA Adder
9
7 2

12-bit CLA Adder

10

16-bit Output

Wallace Multiplier
A wallace tree multiplier that multiplies two integers has an efficient implementation
of circuits in hardware. It is a well-organized methodology for multiplication. Partial
products can be reduced using wallace multiplier, so its complexity is also reduced.
The time of addition of partial product can be decreased using wallace tree CSA
structure. By using compressor, we further increase the speed of existing wallace tree

48 The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019

multiplier. The number of adders used in existing wallace multiplier are reduced due
to addition of compressor. To reduce propagation delay, in addition, carry saver
algorithm is used by wallace tree multiplier, and it is a parallel multiplier. The
multiplication procedure using wallace tree multiplier has the following three stages:
the first stage is generation of partial product; the second stage considers grouping
of partial products; and reduction and final addition is done at the last and final
stage.
For n * n multiplication, n2 partial products are generated, which is summed by
carry save adder. Figure 4 shows 4-bit multiplication. 1 bit full adder is used in wallace
tree algorithm, and it is known as 3 input wallace tree circuit, and its output is sum
and carry. The output signal sum of full adder is directly supplied to the next stage
which is of same bit, but in the case of output signal carry of full adder is supplied
to next stage which is 1 bit higher. There are three stages existing in Wallace tree
multiplier, as shown in Figure 4. Two half adders are used at the first stage and four

Figure 4: Wallace Tree Multiplier

x3 y 2 x2 y 2 x3 y 1 x1 y 2 x3 y 0 x1 y 1 x2 y 0 x0 y 1
x3 y 3 x2 y 3 x1 y 3 x0 y 3 x2 y 1 x0 y 2 x1 y 0 x0 y 0
Partial Products

First Stage
HA HA

Second Stage
FA FA FA FA

Final Order

z7 z 6 z5 z4 z3 z2 z1 z0

A Comparative Analysis of Different Types of Multipliers 49

full adders are used at the second stage. The generated partial products are added
at the final stage using RCA. For FIR filter design, 16 bit wallace tree multiplier is used
for fast multiplication and minimum power consumption (Anubhuti et al., 2017).
Various kinds of techniques are used for low power and high speed multiplication
such as pipelined booth multiplication, in which pipelining of the booth multiplier
is used.

Advantages
• It reduces the number of partial products.
• It has the best multiplication algorithm for small size digital multiplier.

Disadvantages
• It has an irregular structure, and long wires are used.
• It requires large area, as more number of gates are required to perform
the multiplication.
• Complex layout.
• Layout of wallace tree multiplier suffers from more area.
• It is not used for large-sized digital multiplier because when we increase the
size, we need more number of half adders and full adders, and due to this,
delay is also increased.

Comparative Analysis
A comparative analysis of various characteristics such as delay, area and complexity
between array, wallace tree and booth multipliers was made (Table 1).

Table 1: A Comparison of Various Types of Multipliers

Array Wallace Tree Booth
Characteristic
Multiplier Multiplier Multiplier
Accuracy Less High As cycle length is
small, highest accuracy

Delay More Less Moderate

Area Due to a large It requires large area Small area and less
number of adders, it as more number of time are required for
requires maximum gate are required to addition and
area perform multiplication subtraction operation

Complexity Lesser High Higher

Power dissipation Higher High Lesser

Implementation on Less efficient Not efficient Most efficient

FPGA

50 The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019

Applications
• Used commonly in processor like digital signal processor and microprocessor.

• Signal processing system.

• Multimedia application such as 3D graph.

• Video processing.

• Digital filter.

Conclusion
Booth multiplier algorithm is best among all the multipliers in aspects of delay, area,
complexity, power and speed for signed number. Wallace multiplier is also good for
small digital multiplication, but as we know, its delay increases with increase in size
of digital multiplication. Power consumption is more in the case of array multiplier.
Optimum number of components is provided by array multiplier, but delay for this
multiplier is larger than wallace tree multiplier. Multiplication is important and an
essential arithmetic process in DSP applications.
Future Scope: By reducing partial product terms, the accuracy of the multiplier,
reduction area, power dissipation and complexity can be improved. Complexity and
power dissipation are the main parameters.&

References
1. Anubhuti Mittal, Ashutosh Nandi and Disha Yadav (2017), “Comparative Study
of 16-Order FIR Filter Design Using Different Multiplication Techniques”, IEEE,
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2. Aravind Kumar M, Ranga Rao O, Dileep M et al. (2016), “Performance Evaluation
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A Comparative Analysis of Different Types of Multipliers 51

 8. Iffat Fatima (2012), “Analysis of Multipliers in VLSI”, Journal of Global Research
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Reference # 70J-2019-02-05-01

52 The IUP Journal of Telecommunications, Vol. XI, No. 1, 2019

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