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RESEARCH ARTICLE OPEN ACCESS

Differential Amplifier using CMOS Technology

Saud Almusallam, Ali Ashkanani
ABSTRACT: This paper aims to explain how to design a differential amplifier using CMOS
technology. As indicated in Electronic contexts, the differential amplifier is one of the widely known
and the basic building block in creating an analog circuit. Its characteristics are measured by Gain, its
Bandwidth outcomes, and Common Mode Rejection Ratio (CMRR). We present a circuit comprising
bipolar and MOS transistors. Its course uses NMOS and PMOS devices wherein the N-channel will
be used to formulate differential pair, and P-channel current mirror load is applied. This design will
present its optimized architecture using 0.18 μm and a supply voltage of 1.8V and its simulation and
design is demonstrated using ADS tool.
Keywords: Differential Amplifier, CMOS
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Date Of Submission: 24-01-2019 Date Of Acceptance:08-02-2019
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I. INTRODUCTION MOS transistor enhances the strength of

Over the decades, the epoch of very-large- CMOS technology. CMOS technology is used to
scale integration (VLSI) technology has been satisfy all the design restrictions like power, speed,
contributed by the tremendous change in the and area by minimizing the feature size and using
electronics industry. Most significant changes were the optimization techniques. These techniques are
introduced in the market because of the invention used in lowering the supply voltage, using
of the MOS transistors. The small, medium and VTCMOS and MTCMOS, etc.
large-scale integration of the Integrated Circuits to CMOS differential amplifiers are more
over ultra-scale integration has changed and widely used for various applications as compared
modified the electronic world. to single-ended amplifiers. A fully differential
The differential amplifier is a form of amplifier that amplifier circuit produces two inputs and two
strengthens the difference between two voltages in outputs. In designing differential amplifiers,
a circuit. In electronic designs, we use a differential sensitivity is an essential specification. While the
amplifier to produce high voltage gain and high component is matching, their drift induces other
CMRR. Its main characteristics include very low output differential voltage that is unclear from the
bias current input, very high impedance input, and signal being processed. This voltage controls the
very low offset voltage. The essential benefit of minimum predictable differential voltage level.
differential mode from common mode is its higher Such mismatch could convert the common mode
immunity to noise. Also, differential amplifiers input signal to the differential output, wherein it is
provide better immunity to environmental noise, treated as the desired signal by the following
improve linearity, and more upper signal swing. stages.
It may operate in two modes: common mode and
differential mode. The common method produces a II. OBJECTIVE
zero voltage output result while the differential This paper demonstrates a design of a differential
mode produces a high voltage output result. Given amplifier using 0.18μmwith a supply voltage of
this, the differential amplifier generally has high 1.8V CMOS technology. From the various
CMRR. If the two input voltages are of similar topologies, we will use the NMOS PMOS current
value, the amp provides an output voltage value meter load to achieve the specifications and
that is almost zero. When the two input voltages purpose of the circuit.
are unequal, the amplifier produces a high voltage
output.The remarkable advantage of differential III. CONTENT
operation over common mode operation is its
1.1 The Role of Differential Amplifier
higher immunity to noise. Another advantage is the
increase in voltage swings, wherein the peak to and its Basics
peak voltage swing is equal to 2 [VDD - (VGS - The differential amplifier boosts the
VTH)]. difference between the two input signals
demonstrated as V+ and V-and rejects any common

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Saud Almusallam. IntJournal of Engineering Research and Applicationwww.ijera.com ISSN :
2248-9622 Vol. 9,Issue 2 (Series -I) Feb 2019, pp 31-37

signals from the two sources.Its ideal Figure2. Illustration of Supply Noise Reduction
characteristics are infinite bandwidth, gain, and
common mode rejection ratio (CMRR); and high
input impedance, less distortion, and low output
admittance. It is also characterized to have less
harmonic distortion and high output voltage swing.
Its characteristics test the effective performance of
the circuit.
These amplifiers are broadly used in linear
amplificationcircuits to obtain less distortion at the
output. They can be designed in multiple ways,
providing a result where output may be single or
double ended. However, the most commonly used
in designing a differential amplifier is the double
ended, wherein two inputs provide two outputs,
called a fully differential amplifier. Its advantage
over single ended is simple biasing, high linearity,
and high immunity to noise. But it has a large area
to cover.
Figure3. Basic Differential Pair

A feedback circuit like common mode is

used at the output of the amplifier to adjust the bias
current and therefore rejects the common mode
signals. Within the two types of offset voltages, the
input offset and output offset voltage, the latter is
defined as the difference from the final output
voltage to the ideal output voltage when a common
signal is applied at both end inputs. The same,
when the differential voltage gain divides the
output offset voltage; it is called the input offset
voltage.

Figure1. Illustration of DA’s High Immunity to

Noise Coupling

Figure4. Simple Differential Amplifier

From the circuit illustrated in Figure4,

when Vin1 and Vin2 have a huge unequal common
mode dc level, this means that the output response
has distortion.When Vin.cm changes, the M1 and M2
bias currents also change. Hence, the
transconductance of the devices and its output
common mode dc level change. This leads to a
small amplifier signal gain, which becomes the
problem.
To solve this issue, the circuit is modified by
applying a current source (Iss) to make the ID1 and
ID2independent from Vin.cm.The revised figure

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Saud Almusallam. IntJournal of Engineering Research and Applicationwww.ijera.com ISSN :
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below is the circuit incorporating the Iss current Figure7. Differential amplifier with current source
source. load

Figure7 demonstrates an active load

MOSFET differential amplifier. M1 and M2 form a
DA pair, while M5 is a sinking current that provides
bias to the amplifier. M3 and M4 form a current
mirror. As all transistors are considered in the
saturation region, and as the bulk of all transistor
connected to their respective sources, the current
that flows from M5 separated into two equal parts
flowing through M1, M3, M2, and M4 respectively.
Given this, transistors M3 and M4are linked to the
VDD supply while M5 is connected to VSS.
DA with Passive Load

Figure5. The Basic Differential Amplifier

When the two inputs Vin1 and Vin2 are equal, the
biasing current of the single transistor is equal, and
the output common mode level is VDD-.A minimum
bias current is needed to maintain the common
mode level.

Figure8. Basic Differential Amplifier with a

passive load

Figure5 is designed by using two n-

channel MOSFETs (M1 and M2) to form a
differential pair. RD resistors are used as a load to
drive the transistors into saturation. Vin1 and Vin2
are induced at the gate terminal of the MOS
Figure6. Input-output characteristics of a transistors, wherein they are opposite in phase and
differential amplifier equal in magnitude. Nodes X and Y are where the
output voltage is measured and in between these
nodes, the differential signal which has similar
magnitude and opposite phase to the inputs is
measured. Its primary advantage is greater output
voltage swing.

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Saud Almusallam. IntJournal of Engineering Research and Applicationwww.ijera.com ISSN :
2248-9622 Vol. 9,Issue 2 (Series -I) Feb 2019, pp 31-37

characteristics. When there is a gate to source

positive voltage, the current Id only flows when the
Vgsis higher than the threshold voltage. The
simulation of NMOS transistor is determined using
the BSIM-3 model while all parameter values are
sourced from the TSMC model file with 0.18μm
technology. NMOS length is considered 1μm and
10μm for width. And then the threshold voltage βis
determined and is used in further calculations.

Figure9. Differential Amplifier with Passive Load

and Current Source

Biasing problems are solved using the

constant current source, which is presented as Issin
the circuit. Figure9 shows constant current source
used to maintain the minimum bias current to avoid
the impacts of common mode level changes at the
output. A transistor replaces the ideal current
source in this circuit the deliver constant voltage
source while operated in the saturation region. This
acts as a constant current source.

1.2 DA with Active Load

The circuit shown below uses different
load through active components like a Figure10. NMOS Design
currentsource load. It helps if a diode is connected
to overcome the problem of decreasing the voltage
swing and its effect on gain because of the common
mode. We used PMOS transistors as a load to
select proper dimensions and bias current. In
achieving high gain, W/L of PMOS should
decrease.

Figure11. NMOS Simulation

Figure9. DA with active load
Figure11 shows that when the positive
gate voltage is applied to NMOS with Vgs=0, the
1.3 NMOS current Id does not exist even though there were
Biased with a positive gate to the source some positive Vds applied. To attain a significant
voltage Vgs=1.8V, anddrain to the source voltage amount of Id, a sufficiently high positive gate Vgs
Vds=1.5V, the NMOS transistor body is linked to a must be applied. The minimum gate to source
source. The result between Id and Vds shows its I-V

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voltage that produces the N-type inversion layer

draining the current flow becomes a threshold
voltage when Vgs is equal to Vt. When Vgs is less
than Vt, the Id=0. The Id only starts when Vgs>Vt. In
certain Vds, virtual channel deepens and Id
increasesasVgs is increased.

1.4 PMOS
Biased with a negative gate to the source
voltage Vgs=1.8V, and drain to the source Voltage
Vds= -1.5V, the PMOS transistor body is linked to
a source. The I-V characteristics demonstrate the
result between Id and Vds of different values of
Vgs and another graph of Id and Vgs. When there
is a gate to source negative voltage, the current Id
only flows when the Vgsis higher than the threshold
voltage. The simulation of PMOS transistor is
determined using the BSIM-3 model while all
parameter values are sourced from the TSMC
model file with 0.18 μmtechnology. PMOS length
is considered 1μm and 10μm for width. And then Figure13. PMOS Simulation
the threshold voltage β is determined and is used in
further calculations. Figure13 shows that when the negative
gate voltage is applied to NMOS with Vgs=0, the
current Id does not exist even though there were
some negativeVds applied. To attain a significant
amount of Id, a sufficiently high negative gate Vgs
must be applied. The minimum gate to source
voltage that produces the P-type inversion layer
draining the current flow becomes a threshold
voltage when Vgs is equal to Vt. When Vgs is less
than Vt, the Id=0. The Id only starts when Vgs>Vt. In
certain Vds, virtual channel deepens and Id
increasesasVgs is increased.

1.5 Differential Amplifier Design

The DA design comprises NMOS and
PMOS transistors. NMOS current mirror is usedIn
providing a stable current to the differential
amplifier, wherein all the body of the transistor are
connected to the source of respective transistors.
The VDD supply voltage is 1.8V. The input
terminals Vin1 and Vin2 connect to a sine wave
Figure12. PMOS Design having 0.8V Vdc, an amplitude of 1mv and Vdc 0.5V
with 180 phase shift respectively. From the Vout
terminal where the 10pf load is linked. Here,
BSIM3, NMOS, and PMOS model are used to
simulate a differential amplifier. As we consider al
MOS in the saturation region, the transient analysis
and simulation demonstrate Voutover Time. The
calculation of gain AC analysis is also presented.
We assume that the slew rate is 10v/μsec, we can
determine the current flowing through the transistor
from this slew rate and capacitance.
Slew Rate = (dv/dt) = I/CL
Equation 1
Considering ICMR+ = 1.6V and ICMR-= -1.6V,
we now determine the W/L for both M3 and M4.

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Since M1 and M2 are in the saturation region, we

use this equation:
Vds>Vgs-Vt, where Vt = 0.4V.
Thus, in saturation region, the equations for current
are:
Ids = _____β______
2(Vd-Vs)2
Equation 2

Ids = _____μCoxw_____
2L(Vd-Vs)2
Equation 3

The transconductance is,

Figure13. Transient Analysis

Equation 4

Gain BW = _____gm____
2πfCl
Equation 5

W/L = gm2 /2IdsμCoxw

Equation 6

To calculate M3 and M4 W/L ratio, equations 1 and

two will be used.

To calculate M1 and M2 W/L ration, equations Figure14. AC Analysis

3,4,5,6 will be used.

To calculate M5 and M6 W/L ratio, equation three

will be used.

Given that Ids = 100 μA, VDD = 1.8V, Gain BW =

4Mhz.

W/L (1,2) = 4

W/L (3,4) = 28

W/L (5,6) = 5

Figure15. AC Analysis Simulation

IV. RECOMMENDATIONS
The primary function of a differential
amplifier is to amplify the input signal, precisely
the difference between the two input voltages. You
will need active elements (components) to amplify
an input signal such as bipolar or unipolar
transistors like MOSFETs, FETs, and BJTs. With

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Saud Almusallam. IntJournal of Engineering Research and Applicationwww.ijera.com ISSN :
2248-9622 Vol. 9,Issue 2 (Series -I) Feb 2019, pp 31-37

only passive elements, a differential amplifier [2]. Bangadkar, Bhushan, Lamba, Amit, & Vipin
cannot be made.Active elements are needed. Bhure. Study of Differential Amplifiers
Specific circuits can be used for differential using CMOS, 2015. Volume 3, Issue 2, Part
amplifiers. However, it offers a wide array of 2. IJERGS.
responses. [3]. E.Sackinger&W.Guggenbuhl, “Design of
Ideally, differential amplifiers should have Fully Differential CMOSAmplifier for Clip
infinite gain and impedance with zero output Control Circuit" World Applied Science
impedance; while all the frequencies are Journal 3(1),pp. 110-113, 2008.
arithmetically perfect, which is in so many ways [4]. Jacob Millman and Arvin Grabel,
beyond passives. In constructing discrete elements, "Microelectronics," second edition,
commonly, a functional and fair device could be McGraw-Hill International Editions, 1987.
simple: at least two transistors and a push-pull [5]. Khaled N. Salama, Ahmed M. Soliman,
driver with two or more transistors, with some few CMOS OP trans-resistanceamplifier for
passives. MOSFETs are great for the drive because analog signal processing, Microelectronics
its impedance is high with currently produced near Journal, Vol.30, No.9,pp.235-245,
zero. December2018.
[6]. Mirabbasi, Shahriar. Analog CMOS
V. CONCLUSION Integrated Circuit. The University of British
A differential amplifier is designed to Columbia. Philip E. Allen,Douglas R.
amplify two input signals and determines its Holberg, CMOS Analog Circuit Design,
difference.To achieve this, a design is needed. This Second Ed, OxfordUniversity Press.
paper uses an active load to analyze the model. [7]. Popa, C. “Linearity Evaluation Technique
NMOS and PMOS were used, and Advance Design for CMOS Differential Amplifier”PROC.
System presents its simulations. Similarly, the 26th International Conference on
amplifier design is also shown by ADS. The circuit Microelectronics (MIEL 2008),
specifications are designed for applications of NIŠ,SERBIA, 2008.
operational amplifiers, and the W/L ratios are [8]. Razavi, B. Design of Analog CMOS
determined. Furthermore, the accuracy of the Integrated circuits,2002. McGraw-Hill,
results is enhanced by the ADS. NewDelhi.Silpa, Samaria & J. Srilatha.
VI. REFERENCES Design & Analysis of High Gain Differential
[1]. Adel S. Sedra and Kenneth C. Smith. Amp using various topologies, 2017, Vol. 4
Microelectronic Circuits, 4th edition, Oxford Issue 5. IRJET.
University Press, 1998.

Saud Almusallam "Differential Amplifier using CMOS Technology"International

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