POWER designer

Expert tips, tricks, and techniques for powerful designs

No. 127 www.national.com/powerdesigner

An Alternative Approach to Higher-Power

Boost Converters
— By David Baba, Product Applications Engineer

L ID D
A higher-power boost converter often requires special
IDS
consideration to minimize power losses and tempera- + Q +
(a) VIN t C R VOUT
ture rise in the FETs, diode, and inductor. Regarding -
DTS TS
VDS
-
FETs, many designers opt to place FETs in parallel to
reduce conduction losses. However, placing FETs in L IL (t)
parallel can increase transitional losses. This article
+ VL (t) - IC (t)
discusses a number of approaches that can be considered +
(b) VIN C R VOUT
to reduce total losses in boost FETs. Possible options -

include selecting lower gate-charge FETs, selecting

alternative controllers with higher gate-drive current, or
L IL (t)
using a gate driver such as the LM5112. An alternative
- VL (t) + IC (t)
approach using National Semiconductor’s PowerWise® +
LM25037 dual-output gate-drive controller and its (c) VIN
-
C R VOUT

benefits are considered as compared to using a single

gate-drive controller such as the LM5020. Further, this
article will examine ways to approximate total FET Figure 1. The Boost Converter during
the D and (1-D) Switching Period
losses and then make a selection from the potential
approaches that best suits the application requirement. VIN TS
VOUT
IL
General Overview of a Boost Converter ISW (PK)
IAVE
Figure 1 shows: a boost converter with its basic (a)
components, (a); the operation of the boost converter
DTS (1-D) TS
during the on period D, (b); and the operation during t

the off period (1-D), (c). ISW (PK)

All three waveforms in Figure 2 illustrate behavior ISW (PK)
IAVE
over one complete switching cycle. In (a), the inductor (b)
current can be seen; in (b), the switch current is DTS (1-D) TS
depicted; and in (c), the voltage across the FET is t

illustrated. VDS
VIN
The boost converter supplies a voltage that is always VOUT =
(1-D)
greater than its source voltage. The volt-second balance (c)
of the inductor L, for the D period, is added to the input DTS (1-D) TS
voltage during the (1-D) period and is rectified to the
Figure 2. Basic Behavioral Waveforms of the Boost Converter
POWER designer
An Alternative Approach to Higher-Power Boost Converters
output through the diode. The longer the D period, Conduction loss is an I2R term where I is the RMS
the shorter the 1-D period becomes, thereby switch current and R is the RDSON of the FET. For
increasing the voltage during the off time in order a boost converter, the conduction losses are shown
to maintain volt-second balance. in the following equations.
A benefit to the alternative approach using the
LM25037 PWM controller is evident in applications
where the output voltage is many times greater than EQ2 SW COND = I SWRMS2 x RDSON
the input. The relationship of input and output
voltage as it relates to the duty ratio is highlighted in
the following equation: Where

VOUT 1 Dx I 2+I
EQ1 EQ3 I SW =
3
( PEAK PEAK x I TROUGH + I TROUGH2)
VIN ( 1 − D) RMS

From Equation 1, it is apparent that a single-

channel gate-drive solution with a limited maximum
EQ4 IPEAK = 1.25 x IINAVE
duty ratio can inhibit large step-up ratios. Some
controllers have a maximum period of 80% which
will limit the step-up ratio to five times the input.
However, using the LM25037 controller presents
no such limitations. The reason for this is that the
EQ5 I TROUGH = 0.75 x IINAVE
alternating outputs of the LM25037 gate driver
have only a small dead time between the two
outputs which allows a maximum duty ratio beyond
80%. And therefore, it is possible to obtain output
voltages that are 10 times the input. I OUT
EQ6 IINAVE =
(1-D)
Losses in the Boost FET
Losses due to the boost FET can be separated into
three different categories, namely, conduction,
transition, and switching losses. Conduction and
transition losses are discussed as they are dissipated V OUT - V IN
EQ7 D=
directly in the FET which impacts thermal V OUT
performance.
Conduction Losses Note: Equations 3 and 4 relate to the peak-to-peak
Conduction losses in the boost FET are directly inductor current which is 50% of the average input
related to the output power of the boost converter, current.
the input voltage, the output voltage (relating to D),
and the RDSON of the FET.

2
 POWER designer

Transitional Losses
Transitional losses occur during the time period Volts/ ID
Current
when the FET is turning on or off. During steady- VDS
VGS
state operation before the FET turns on, the output
voltage is across the drain and the source of the
Plateau
FET. As the FET begins to turn on, current begins Voltage
flowing from the drain to the source after which the
VGS (TH)
voltage begins to fall. During this time, the current
is increasing as the voltage remains across the FET
and losses are incurred. During turn off, the exact
reverse occurs. Charge (nC)

Miller Charge (Q)

As the frequency increases, transitional losses
increase as more transitions occur per second.
Figure 3. Approximating Transitional Switching Time
Also, if transition times increase, transitional losses
increase because the FET endures a longer period of The charge relates to time and is proportional to the
time within the described loss period. Transitional gate-drive current being supplied to the gate of the
losses can be approximated by the following FET. The more available current, the quicker the
equations: FET will turn on. Conversely, turning off the FET
requires that the gate driver sinks current out of
the gate, and thus, the more current the gate driver
EQ8 TransLOSSES = 2 x VOUT x IINAVE x TTRANS x FSW can sink, and the faster the FET will turn off. For
the purpose of simplicity, it is assumed the turn-
on time is equal to the turn-off time, with the gate
Where driver providing the same source and sink-current
capability.
V IN Many FET datasheets include a graph that relates
EQ9 VOUT = the VGS on the Y axis with the charge on the X axis.
(1 - D)
Figure 3 has additional VDS and ID curves for relating
the topic being discussed. To estimate the charge
required to fully switch on a FET, the designer must
I OUT estimate the differential charge, shown as the Miller
EQ10 IINAVE =
(1 - D) charge. Another approximation can be made by
estimating the Miller charge to be approximately
FSW is the switching frequency and TTRANS is the 60% of the typical gate charge.
transitional switching time. The gate drive resistance for MOSFET gate drivers
Figure 3 depicts a graph showing the drain current is typically quoted in its datasheet. For the Bipolar
and the voltage across the FET and illustrates how Junction Transistor (BJT) output stage, it will not
much charge is required to fully turn on the FET. be quoted as a resistance. VSAT is quoted for a BJT

www.national.com/powerdesigner
3
POWER designer
An Alternative Approach to Higher-Power Boost Converters
output-driver stage. However, the VSAT information By way of example, a boost specification will be
provided can be used to approximate the drive considered using the two-switch approach and
resistance as is seen in the following equation. The compared to the single gate-drive, parallel-switch
VG DROP is the VSAT of the transistor output stage. approach.

VG DROP VIN = 12V

EQ11 = Dr iveR
GateCURRENT VOUT = 24V

IOUT = 6A
The voltage available to drive a FET needs to be
determined. This is simply calculated by subtracting Fsw = 300 kHz
the Miller plateau voltage from the total output
voltage at the gate drive. The voltage available to L = 3.6 μH
drive the FET after its threshold is met is:
Single Gate-Drive Parallel-FET Approach using
the LM5020 Controller
EQ12 VG AVAIL = VGATE - VGS (MP) Considering the previously-identified specification,
the designer may opt to use National’s LM5020
PWM controller. The LM5020 controller is a
Equation 11 calculates the resistance of the gate common selection for many boost applications
driver. From this calculation, the gate-drive current and serves as a good comparison in a typical design
is therefore: scenario.
Placing two FETs in parallel will increase switching
VG AVAIL losses as the gate charge will double and therefore
EQ13 IGATE = switching transition times will double. With high
Dr iveR + RG
RMS switch currents and the doubling of gate
charge, it is essential to select FETs that have a low
where, RG is the gate resistance of the FET. RDSON and a low gate charge. These types of FETs
tend to be more costly than FETs that have similar
Once the gate-drive current is determined, the RDSON with a higher gate charge. To address this
transitional time can be calculated: transitional loss issue, the FET selected for this
example is the SiR472DP FET from Vishay.
Charge Miller
EQ14 TTRANS = VIN
D

IGATE
LM 5020
Q1 Q2
C R
OUT 1
And the evaluation of transition losses (Equation 8)
is now possible.

Figure 4. A Single Gate-Drive Controller Switching

Two FETs in Parallel

4
 POWER designer

A traditional method of using a single gate-drive datasheet. By referencing the SiR472DP datasheet
controller switching two FETs in parallel is shown and using the VGS verses total gate charge (nC) in
in Figure 4. a graph similar to the one shown in Figure 3, the
From the calculation in Equation 7, Miller charge is shown to be 4 nC for a VDS of 24V.
The effective Miller charge doubles (8 nC) due to
two FETs being placed in parallel.
D = 0.5 The LM5020 datasheet does not provide gate-
drive resistance data as it has a BJT output stage,
and from Equation 6, the average input current is but the source resistance of the gate drive can still
calculated as: be estimated. The table on page 5 of the LM5020
datasheet shows the voltage drop (0.25V) of the
IINAVE = 12A gate-drive output for a given sourcing current
(0.05A). By dividing the current flowing out of the
gate drive into the voltage drop, the gate resistance
Choosing 50% of the average input current as being can be estimated. Using Equation 11 yields:
the peak-to-peak current in the inductor and using
Equations 4 and 5, this yields the following peak
and trough values: Dr iveR = 5Ω

IPEAK = 15A The LM5020 controller has an output gate-drive

voltage of 7.6V supplied by the VCC regulator; from
Equation 12:
ITROUGH = 9A
VG AVAIL = 4.6V
Using Equation 3, the switch RMS currents can be
calculated: A gate resistance of 1.8Ω (typical) is specified in
the SiR472DP datasheet. Using Equation 13, the
gate-drive current can be calculated:
ISWITCHRMS = 8.57A
IGATE = 0.68A
And the conduction losses also can now be calcu-
lated. The RDSON for the SiR472DP is 0.012Ω at Using Equation 14, the transitional time yields:
10V of gate-drive voltage. As two of these FETs are
placed in parallel, the effective RDSON, is half of this TTRANS = 11.76 ns
value (0.006Ω).
Using Equation 8, the transitional losses can be
SWCOND = 0.441W approximated to:

In order to evaluate Equation 8, the transitional TransLOSSES = 2W

switching time must be estimated. It is assumed the
VGS(th) of the SiR472DP is 1.85V (typical) from the

www.national.com/powerdesigner
5
POWER designer
An Alternative Approach to Higher-Power Boost Converters
By adding the conduction losses with transitional RDSON. Switching FETs independently, however,
losses, the total FET losses are obtained. Total no longer yields the 50% reduction in RDSON but
FET losses using the single gate-drive parallel-FET transitional losses are reduced.
method is: The RDSON of the SiR468DP is 0.0057Ω. The
duty ratio (D) for each FET is now reduced to 25%
FETLOSS TOTAL = 2.47W due to the independent switching of the FETs.
Using Equation 2 and using the revised effective D,
Half of the calculated power (1.24W) is dissipated we yield:
in each FET. ISWITCHRMS = 6.06A
There are alternative approaches in circumstances
where the single gate-drive approach is causing the SWCOND = 0.209W
FET to dissipate too much power. For example, a
single gate-drive controller with higher drive current There are two FETs dissipating the above conduction
(if one is available) can be employed or an additional losses. The total conduction losses are twice this
IC using the gate driver (LM5112) can be used. amount, therefore the total conduction losses in
Another alternative is to consider the dual gate- both FETs are:
driver approach.
SWCOND TOTAL = 0.42W
Dual-Output Gate-Driver Approach using the
LM25037 Controller
A basic schematic of the LM25037 dual gate driver Each gate drive of the LM25037 controller has the
switching the gates of two FETs independently is same gate-current drive capability as the LM5020
shown in Figure 5. controller. The datasheet specifications can be
referred to for more details.
VIN
D A gate resistance of 1.1Ω (typical) is specified in
LM 25037 Q1
the SiR468DP datasheet. Using Equation 13, the
OUT 1
C R
gate-drive current can be calculated as:
Q2
OUT 2

IGATE = 0.75A

It is assumed the VGS(th) of the SiR468DP is 2V

Figure 5. LM25037 Dual-Output Gate Drivers (typical) from the datasheet. From the SiR468DP
Switching Two FETs Independently
datasheet, using the VGS versus total gate charge
similar to the graph shown in Figure 3, the Miller
Switching two independent FETs from a dual gate- charge is shown to be 6 nC for a VDS of 22.5V. Using
drive controller typically allows the designer to a dual gate-drive controller switching independent
select low RDSON FETs with a higher gate charge. FETs reduces the transitional losses due to the
Higher gate-charge FETs tend to be less expensive halving of the effective Miller charge which decreases
than their lower gate-charge counterparts. the transitional switching times. Transitional
The two FETs selected to be switched independently switching time is calculated using Equation 14:
are the SiR468DP. As previously mentioned, driving
two FETs in parallel produces a 50% reduction in TTRANS = 7.96 ns

6
 POWER designer

R14 C19 TDK, C3216X7RIE475

TDK C3216X5RIC106 TDK, C3216X7RIE475 TDK, C3216X7RIE475 Sanyo, 35SVPD47M
TDK C3216X5RIC106 NI D1 NI
L1 TDK, C3216X7RIE475 L2 Sanyo, 35SVPD47M
+
C3 C4 3.6 μH C1 C2 C6 C8 330 nH C7 + C9
VIN 11V to 14V Coilcraft, SER2013-362ML IR, 42CTQ030S Coilcraft, 24V @ 6A
Pulse, PA1005.100NL DO1813-331
GND GND 11 L3 2 GND GND GND GND GND GND
R1
GND
GND
12 4 10k

GND
R2
10R Q1
Vishay,
SI7892BDP
R3
75k GND
R5
45.3k C10 U1 Q2
1 μF LM25037AMT Vishay,
VIN VCC SI7892BDP
GND
UVLO OUTA
R6 GND
5.9k REF OUTB C11 1000 pF
0.047 μF D4
RT1 RAMP BAT54 C12
470 pF R7
C20 RT2 CS C13 R8
GND 1k R9 18.2k
RES COMP
1k 100 nH
FB
AGND
PGND

SS
GND
R10 R11
19.6k 20k C14 R12 R13
C15 C17 C18 820 pF 1.5R 1k
4.7 μF C16 0.047 μF GND GND 4.7 μF
0.01 μF

GND GND GND GND GND GND GND GND GND

Figure 6. Application Example of a 12V IN, 24V OUT at 6A

From Equation 8: Summary

Using the LM25037 controller for higher-power
TransLOSSES = 1.37W boost applications is a simple straightforward
approach that can provide benefits over using a
typical single gate-drive controller. The benefits can
Including the conduction losses, the total losses in include higher step-up ratios and lower FET losses
both FETs are: due to the reduction in transitional losses. Although
there are a number of possible approaches to reduce
FETLOSS TOTAL = 1.79W
total FET losses in higher-power boost converters,
the equations in this article can be used to calculate
The total FET losses recovered using two total losses in the boost FETs for a number of
independent gate drives are: different approaches. Considering the 150W boost
converter example, it has been shown that total
FETLOSS REC = 2.47W - 1.79W = 0.675W losses in the FETs are reduced when comparing the
LM25037 dual-output gate-drive controller with
Each FET will dissipate 0.34W less. the LM5020 single-output gate-drive controller.

Figure 6 shows an example schematic of the boost

example considered.

www.national.com/powerdesigner
7
 Power Design Tools

Design, build, and test analog circuits in this online

design and prototyping environment.
www.national.com/webench

Expand your knowledge and understanding of

analog with our free online educational training
tool.
www.national.com/training

National’s monthly analog design technical

journal.
www.national.com/edge

Tools for Energy-Efficient Designs

Access white papers, reference designs, and application notes on
PowerWise® products and systems.
www.national.com/powerwise

National Semiconductor
2900 Semiconductor Drive
Don’t miss a single issue!
Santa Clara, CA 95051
Subscribe now to receive email alerts when
1 800 272 9959
new issues of Power Designer are available:
Mailing address:
PO Box 58090 www.national.com/powerdesigner
Santa Clara, CA 95052
Read our Signal Path Designer® online
Visit our website at:
www.national.com today at:

For more information, www.national.com/spdesigner

send email to:
[email protected]

©2009, National Semiconductor Corporation. National Semiconductor, , PowerWise, WEBENCH, and Signal Path Designer are registered trademarks of
National Semiconductor. All other brand or product names are trademarks or registered trademarks of their respective holders. All rights reserved.

550263-019
550263-019