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Digital Switching Design Using Verilog

This document contains a list of 10 questions related to digital system design and Verilog for an assignment. The questions cover topics such as flash and successive approximation ADCs, designing a Verilog input controller, serial interface standards, DACs, tri-state bus drivers, hardware/software co-design flow, system partitioning, verification plans, BIST techniques, and scan design and boundary scan. The questions range from levels 1 to 3 in Bloom's taxonomy of cognitive levels.

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Shrikant Jotawar
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34 views

Digital Switching Design Using Verilog

This document contains a list of 10 questions related to digital system design and Verilog for an assignment. The questions cover topics such as flash and successive approximation ADCs, designing a Verilog input controller, serial interface standards, DACs, tri-state bus drivers, hardware/software co-design flow, system partitioning, verification plans, BIST techniques, and scan design and boundary scan. The questions range from levels 1 to 3 in Bloom's taxonomy of cognitive levels.

Uploaded by

Shrikant Jotawar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Jain College of Engineering, Belagavi

Department of Electronics and Communication Engineering

Bloom’s
Q. No. Questions COs’ Cognitive
Levels
Explain flash ADc and successive approximation ADC with the help of diagram.
1 4 L2

Design and develop a verilog code for an input controller that has 8 bit
binary coded input from sensor. The value can be read from an 8 bit input
2 register. The controller should interrupt embedded Gumnut core when the 4 L2
input values changes. The controller is the only interrupt source in the
system.
3 Explain any four serial interface standards. 4 L2

4 Explain Digital-to-Analog Converters using R/2R ladder DAC. 4 L2

Write a verilog assignment that represents a tri-state bus driver for an 8 bit 4
5 L2
bus.
6 Explain the design flow of hardware/software co-design. 4 L3

7 Explain the logical partitioning and physical partitioning of system. 5 L2

8 What aspects of the design flow does a verification plan cover? 5 L1,L2

9 Explain Built-in self test (BIST) techniques 5 L2

10 Explain the terms scan design and boundary scan. 5 L2

Assignment

Semester: VI Date:9/05/2019
Subject with code: Digital system design using Verilog (15EC663)

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