Microprocessor
Microprocessor
8085 INTERRUPTS
Memory device
MP
IO device
stop
• Asynchronous Data Transfer: -
• Asynchronous means “at a regular interval”. In this method
data transfer is not based on predetermined timing pattern in
this technique the status of the IO device is checked by the
microprocessor before the data is transferred. This method is
invariably used in between microprocessor and IO devices.
Its used when the speed of the IO devices is slower than the speed of
the MP(MISMATCH) Its asynchronous to each other.
Its also called as “HANDSHAKING” mode.
Data Bus
MP IO Device
ACK
Ready
Handshaking Mode
Advantage: can be used even when the speed character is not known
Data bus
MP IO device
INTR REQUEST
INTR ACK
start Start ISS
Exe IO instru
Fetch & exe next instr
IO device 3
IO device
Problem :- when the interrupt line is active in either of 2 method, the
MP do not identifies which devices has sent the interrupt signal.
1) Polling
2) Daisy Chain
3) Multi Interrupt system
Interrupts
• An interrupt is considered to be an emergency signal that may be
serviced.
• The Microprocessor may respond to it as soon as possible.
Its needed to transfer data B/w the peripheral and the MP.
Types of Interrupts are:
1) S/w interrupt
2) H/w interrupt
3) Multi Interrupt System
Software Interrupts
• 8085 MP has 8 s/w interrupts. RST 0,RST 1, RST 2, RST 3, RST 4, RST
5,RST 6,RST 7. its known as restart (RST) Instruction.
• Syntax: RST n (where n varies from 0 to 7)
• One byte call instruction that transfers the program execution to a
specified m/y location on memory.
• RST instruction is similar to the call instruction.
• Address in the PC is stored on the stack before execution is
transferred to the RST call location
• When the MP encounters a return Instruction in subroutine with RST
instruction ie RET, the program returns to the address stored on stack.
RST instructions
• 8 RST instructions
Mnemonics Binary code Hex Call Location
Or Effect
Instruction D7 D6 D5 D4 D3 D2 D1 D0
D0
I0
Mnemonics Binary code Hex Call
D1
D7 D6 D D D D D1 D
Loc
atio
INT 0
5 4 3 2 0
n
D2
RST0 1 1 0 0 0 1 1 1 C7 0000
RST1 1 1 0 0 1 1 1 1 CF 0008 A0 D3
RST2 1 1 0 1 0 1 1 1 D7 0010 A1 D4
RST3 1 1 0 1 1 1 1 1 DF 0018 A2 D5
RST4 1 1 1 0 0 1 1 1 E7 0020
RST5
RST6
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
EF
F7
0028
0030
INT 7
RST7 1 1 1 1 1 1 1 1 FF 0038
D6
TRAP and
INTR
TYPES OF INTERRUPT:
SOFTWARE
AND HARDWARE
• The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
The 8085 Non-Vectored Interrupt Process
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables DI the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next
instruction on the stack and the program is transferred to ‘call’ location (ISR
Call) specified by the RST instruction
The 8085 Non-Vectored Interrupt
Process
1) 8085 MP has 4 maskable interrupts RST 7.5, 6.5, 5.5 and INTR
2) Its controlled by a single FF which is inside the MP
3) Interrupt enable FF is controlled using 2 instructions
• The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated
using the SIM instruction.
• This instruction takes the bit pattern in the Accumulator and applies it to the
interrupt mask enabling and disabling the specific interrupts.
How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0
M6.5
SDO
M5.5
M7.5
SDE
MSE
XXX
R7.5
Serial Data Out RST5.5 Mask
RST7.5 }
RST6.5 Mask 0 - Available
1 - Masked
Mask
Mask Set Enable
Enable Serial Data
0 - Ignore bits 0-2
0 - Ignore bit 7
1 - Set the masks according
1 - Send bit 7 to SOD pin
to bits 0-2
• Direct Memory Access (DMA) is a method that allows an input/output (I/O) device
to send or receive data directly to or from the main memory, bypassing the CPU to
speed up memory operations. The process is managed by a chip known as a DMA
controller (DMAC).
DMA
•DMA transfers are performed by a control circuit that is part of the I/O
device interface.
• It refer to this circuit as a DMA controller.
•The DMA controller performs the function that would normally be
carried out by the processer when accessing the main memory.
•Device wishing to perform DMA asserts the
processors bus request signal
• Processor completes the current bus cycle and then asserts the
bus grant signal to the device.
•The direct memory access (DMA) I/O technique provides direct access to the memory
while the microprocessor is temporarily disabled.
•A DMA controller temporarily borrows the address bus, data bus, and control bus from
the microprocessor and transfers the data bytes directly between an I/O port and a series
of memory locations.
Data bus
8085
Address bus I/O Device
MPU
DMA acknowledge
DMA Request
• The external DMA controller sends a signal on HOLD pin to the mp
• The mp completes the current operation and sends signal on HLDA to
make use of the address and data bus.
• For transfers the data between the two devices
• The DMA controller turns off the HOLD signal when the data
transferred between the IO device and memory and then the mp
takes back control of the buses.