// PIC18F4550 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1L
#pragma config PLLDIV = 1 // PLL Prescaler Selection bits (No prescale (4 MHz
oscillator input drives PLL directly))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits
([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 1 // USB Clock Selection bit (used in Full-Speed USB
mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary
oscillator block with no postscale)

// CONFIG1H
#pragma config FOSC = HSPLL_HS // Oscillator Selection bits (HS oscillator, PLL
enabled (HSPLL))
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe
Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit
(Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = ON // Brown-out Reset Enable bits (Brown-out Reset
enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown-out Reset Voltage bits (Minimum setting
2.05V)
#pragma config VREGEN = OFF // USB Voltage Regulator Enable bit (USB voltage
regulator disabled)

// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control
is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed
with RC1)
#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are
configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1
configured for higher power operation)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input
pin disabled)

// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack
full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply
ICSP enabled)
#pragma config ICPRT = OFF // Dedicated In-Circuit Debug/Programming Port
(ICPORT) Enable bit (ICPORT disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction
set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is
not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is
not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is
not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is
not code-protected)

// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block
(000000-0007FFh) is not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is
not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh)
is not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh)
is not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh)
is not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh)
is not write-protected)

// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit
(Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block
(000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is
not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-
001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-
003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-
005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-
007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block
(000000-0007FFh) is not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.

// Use project enums instead of #define for ON and OFF.

#include <xc.h>
#define SPI_MASTER_OSC_DIV64 0b00100010
#define SPI_DATA_SAMPLE_END 0b10000000
#define SPI_CLOCK_IDLE_LOW 0b00000000
#define SPI_IDLE_2_IDLE 0b01000000
#define _XTAL_FREQ 48000000

//spiInit(SPI_MASTER_OSC_DIV64, SPI_DATA_SAMPLE_END, SPI_CLOCK_IDLE_LOW,

SPI_IDLE_2_IDLE);
void spiInit(char sType, char sDataSample, char sClockIdle, char sTransmitEdge)
{
// TRISBbits.TRISB0 = 1;
 TRISCbits.TRISC7 = 0;
if(sType & 0b00000100) //If Slave Mode
{
SSPSTAT = sTransmitEdge;
TRISBbits.TRISB1 = 1;
}
else //If Master Mode
{
SSPSTAT = sDataSample | sTransmitEdge;
TRISBbits.TRISB1 = 0;
}
SSPCON1 = sType | sClockIdle;
}
void spiReceiveWait()
{
TXREG = 0x53;
while(!TXSTAbits.TRMT);
while ( !SSPSTATbits.BF ); // Wait for Data Receipt complete
}
void spiWrite(char dat) //Write data to SPI bus
{
SSPBUF = dat;
}
unsigned spiDataReady() //Check whether the data is ready to read
{
if(SSPSTATbits.BF)
return 1;
else
return 0;
}

char spiRead() // Read the received data

{

spiReceiveWait(); // Wait until all bits receive

TXREG = 0x52;
while(!TXSTAbits.TRMT);
return(SSPBUF); // Read the received data from the buffer
}

void main(void)
{
char valor,cont,valorl;
ADCON1=0x0F;
SPBRGH = 4;
SPBRG = 225;
BRG16 = 1;
BRGH = 1; // baud rate em velocidade alta

TRISCbits.TRISC6 = 1; // TX
// TRISCbits.TRISC7 = 1; // RX

// ADCON1=0x0f;
SYNC = 0; // configura��o para modo ass�ncrono
TXEN = 1; // habilita transmiss�o
SPEN = 1; // habilita porta serial
 CREN = 1; // habilita recep��o cont�nua
/* TRISCbits.TRISC7 = 0;
while(1)
{
PORTCbits.RC7 = 1;
for(cont=0;cont<10;cont++)
__delay_ms(10);

PORTCbits.RC7 = 0;
for(cont=0;cont<10;cont++)
__delay_ms(10);
}*/
/* while(1)
{
TXREG = 0x54;
while(!TXSTAbits.TRMT);
for(cont=0;cont<10;cont++)
__delay_ms(10);
}*/

TRISAbits.RA1=0;
TRISAbits.RA2=0;
TRISAbits.RA3=0;
PORTAbits.RA3 = 1; //Slave desligado
//RBPU = 0; //Enable PORTB internal pull up resistor
spiInit(SPI_MASTER_OSC_DIV64, SPI_DATA_SAMPLE_END, SPI_CLOCK_IDLE_LOW,
SPI_IDLE_2_IDLE);
TXREG = 0x54;
while(!TXSTAbits.TRMT);
while(1)
{
PORTAbits.RA1 = 1;
for(cont=0;cont<100;cont++)
__delay_ms(10);
PORTAbits.RA1 = 0; //LED1 apagado
PORTAbits.RA2 = 1; //LED2 Aceso
PORTAbits.RA3 = 0; //Slave Select
__delay_ms(1);

spiWrite(0x55);
PORTAbits.RA1 = 1;
// for(cont=0;cont<100;cont++)
__delay_ms(10);
valor = spiRead();
TXREG = valor;
while(!TXSTAbits.TRMT);
spiWrite(0x55);
valorl = spiRead();
TXREG = valorl;
while(!TXSTAbits.TRMT);
// TXREG = valorl;
// while(!TXSTAbits.TRMT);
__delay_ms(1);
PORTAbits.RA1 = 1; //LED2 Aceso
PORTAbits.RA2 = 0; //LED1 apagado
PORTAbits.RA3 = 1; //Slave down
for(cont=0;cont<100;cont++)
__delay_ms(10);
}
}