Digital Design through Verilog

Unit-3 Data Flow level & Switch level Modeling

Introduction

Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of
logic circuit. He should be aware of data flow of the design. The gate level modeling becomes
very complex for a VLSI circuit. Hence dataflow modeling became a very important way of
implementing the design.
In dataflow modeling most of the design is implemented using continuous assignments, which
are used to drive a value onto a net. The continuous assignments are made using the keyword
assign.

The assign statement

The assign statement is used to make continuous assignment in the dataflow modeling. The
assign statement usage is given below:

assign out = in0 + in1; // in0 + in1 is evaluated and then

assigned to out.

Note:

• The LHS of assign statement must always be a scalar or vector net or a concatenation. It
cannot be a register.
• Continuous statements are always active statements.
• Registers or nets or function calls can come in the RHS of the assignment.
• The RHS expression is evaluated whenever one of its operands changes. Then the result
is assigned to the LHS.
• Delays can be specified.

Examples:

assign out[3:0] = in0[3:0] & in1[3:0];

assign {o3, o2, o1, o0} = in0[3:0] | {in1[2:0],in2}; // Use of

concatenation.

Implicit Net Declaration:

wire in0, in1;

assign out = in0 ^ in1;

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 Digital Design through Verilog

In the above example out is undeclared, but verilog makes an implicit net declaration for out.

Implicit Continuous Assignment:

wire out = in0 ^ in1;

The above line is the implicit continuous assignment. It is same as,

wire out;
assign out = in0 ^ in1;

Delays

There are three types of delays associated with dataflow modeling. They are: Normal/regular
assignment delay, implicit continuous assignment delay and net declaration delay.

Normal/regular assignment delay:

assign #10 out = in0 | in1;

If there is any change in the operands in the RHS, then RHS expression will be evaluated after
10 units of time. Lets say that at time t, if there is change in one of the operands in the above
example, then the expression is calculated at t+10 units of time. The value of RHS operands
present at time t+10 is used to evaluate the expression.

Implicit continuous assignment delay:

wire #10 out = in0 ^ in1;

is same as

wire out;
assign 10 out = in0 ^ in1;

Net declaration delay:

wire #10 out;

assign out = in;

is same as

wire out;
assign #10 out = in;

Examples

1. Implementation of a 2x4 decoder.

2 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY
 Digital Design through Verilog

module decoder_2x4 (out, in0, in1);

output out[0:3];
input in0, in1;

// Data flow modeling uses logic operators.

assign out[0:3] = { ~in0 & ~in1, in0 & ~in1,
~in0 & in1, in0 & in1 };

endmodule

2. Implementation of a 4x1 multiplexer.

module mux_4x1 (out, in0, in1, in2, in3, s0, s1);

output out;
input in0, in1, in2, in3;
input s0, s1;

assign out = (~s0 & ~s1 & in0)|(s0 & ~s1 & in1)|
(~s0 & s1 & in2)|(s0 & s1 & in0);

endmodule

3. Implementation of a 8x1 multiplexer using 4x1 multiplexers.

module mux_8x1 (out, in, sel);

output out;
input [7:0] in;
input [2:0] sel;

wire m1, m2;

// Instances of 4x1 multiplexers.

mux_4x1 mux_1 (m1, in[0], in[1], in[2],
in[3], sel[0], sel[1]);
mux_4x1 mux_2 (m2, in[4], in[5], in[6],
in[7], sel[0], sel[1]);

assign out = (~sel[2] & m1)|(sel[2] & m2);

endmodule

4. Implementation of a Full adder.

module full_adder (sum, c_out, in0, in1, c_in);

output sum, c_out;

input in0, in1, c_in;

assign { c_out, sum } = in0 + in1 + c_in;

endmodule

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5. Implementation of a adder/subtractor .
module addSub(A, B, sel, Result);
input sel;
input [3:0] A,B;
output [3:0] Result;
wire [3:0] Result;
assign Result = (sel)? A + B : A - B;

endmodule

testAS.v
module main;
reg [3:0] A, B;
reg sel;
wire [3:0] Result;
addSub as1(A, B, sel, Result);
initial begin
A = 4'b0001;
B = 4'b1010;
end
initial begin
forever begin
#10
A = A + 1'b1;
B = B + 1'b2;
end
end
initial begin
sel = 1;
#200
sel = 0;
end

endmodule

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 Digital Design through Verilog

Switch Level Modeling:

Objectives

After completing this chapter, you will be able to ™

• Describe what is the structural modeling ™

• Describe how to instantiate switch primitives ™
• Describe how to model a design in switch primitives ™
• Describe how to specify delays in switches ™
• Describe other features of switch primitives

Definition: Usually, transistor level modeling is referred to model in hardware structures

using transistor models with analog input and output signal values. On the other hand,
gate level modeling refers to modeling hard-ware structures wing gate models with digital
input and output signal values between these two modeling schemes is referred to as switch
level modeling. At this level, a hardware component is described.

At the transistor level, but transistors only exhibit digital behavior and their input, and output
signal values are only limited to digital values. At the switch level, transistors behave as on-off
switches- Verilog uses a 4 value logic value system, so Verilog switch input and output
signals can take any of the four 0, 1, Z, and X logic values.

Switch level primitives:

Switches are unidirectional or bidirectional and resistive or non resistive, For each group those
primitives that switch on with a positive gate {like an NMOS transistor} and those that switch
on with a negative gate {like aPMOS transistor}. A unidirectional transistor passes
its input value to its output when it is switched on. A bidirectional transistor conducts both ways.
A resistive structure reduces the strength of its input logic when passing it to its output.
In addition to switch level primitives, pull-primitives that are used as pull-up and pull-
down resistors for tri-state outputs.

Switches unidirectional bidirectional Pull Gates

Standard cmos tran pullup

nmos tranif1

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 Digital Design through Verilog

pmos tranif0

Resistive rcmos rtran pulldown

rnmos rtranif1

rpmos rtranif0

Standard switches; pull primitives, and tri-state gates that behave like nmos and pmos.
Instantiations of these primitives and their corresponding symbols are also shown. cmos is a
unidirectional transmission gate with a true and complemented control lines. Nmos and pmos
are unidirectional pass gates representing NMOS and PMOS transistors respectively.

When such a resistive switch conducts, the strength of its output signal is one or two levels
below that of its input signal. Delay values for transition to 1, transition to 0, and transition
to Z can be specified in the #(to-1, to-0, to-z) format for unidirectional switches.
Bidirectional tran switches shown in figure are functionally equivalent to unidirectional
switches shown in the adjacent column of this figure. When conducting, the two inout ports
are connected and logic values flow in both directions.

Nmos and Pmos Switches:

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In Verilog nmos and pmos switches are instantiated as shown in below,

nmos n1(out, in, control); // instantiate a nmos switch

pmos p1(out, in, control); // instantiate a pmos switch

Since switches are Verilog primitives, like logic gates, the name of the instance is optional.
Therefore, it is acceptable to instantiate a switch without assigning an instance name.

nmos (out, in , control); // instantiate nmos switch ; no instance name

pmos (out, in, control); // instantiate pmos switch; no instance name

Value of the out signal is determined from the values of in and control signals. Some
combinations of in and control signals cause the gates to output to either a 1 or 0 or to an z
value without a preference for either value. The symbol L stands for 0 or Z; H stands for 1 or
z. Thus, the nmos switch conducts when its control signal is 1. If control signal is 0, the
output assumes a high impedance value. Similarly a pmos switch conducts if the control
signal is 0.

CMOS Switches

CMOS switches are declared with the keyword cmos. A cmos device can be modeled with a
nmos and a pmos device. The symbol for a cmos switch is shown in figure

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 Digital Design through Verilog

CMOS switch

A CMOS switch is instantiated as shown in below,

cmos cl(out, data, ncontrol, pcontrol);//instantiate cmos gate
or

cmos (out, data, ncontrol, pcontrol); //no instance name given

The ncontrol and pcontrol are normally complements of each other. When the ncontrol signal
is 1 and pcontrol signal is 0, the switch conducts. If ncontrol is 0 and pcontrol is 1, the output
of the switch is high impedance value. The cmos gate is essentially a combination of two
gates: one nmos and one pmos. Thus the cmos instantiation shown above is equivalent to the
following.

nmos (out, data, ncontrol); //instantiate a nmos switch

pmos (out, data, pcontrol); //instantiate a pmos switch

Since a cmos switch is derived from nmos and pmos switches, it is possible derive the
output value from Table, given values of data, ncontrol, and pcontrol signals.

Delay Specifications --- MOS/CMOS Switches

➢ Specify no delay
mos_sw [instance_name](output, input, …);
cmos [instance_name](output, input, …);
➢ Specify propagation delay only
mos_sw #(prop_delay)[instance_name](output, input, …);
cmos #(prop_delay)[instance_name](output, input, …);
➢ Specify both rise and fall times
mos_sw #(t_rise, t_fall)[instance_name](output, input, …);
cmos #(t_rise, t_fall)[instance_name](output, input, …);
➢ Specify rise, fall, and turn-off times
mos_sw #(t_rise, t_fall, t_off)[instance_name](output, input, …);
cmos #(t_rise, t_fall, t_off)[instance_name](output, input, …);

Bidirectional Switches
NMOS, PMOS and CMOS gates conduct from drain to source. It is important to have
devices that conduct in both directions. In such cases, signals on either side of the device

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can be the driver signal. Bidirectional switches are provided for this purpose. Three
keywords are used to define bidirectional switches: tran, tranif0, and tranifl.

Symbols for these switches are shown in figure below.

The tran switch acts as a buffer between the two signals inoutl and inout2. Either inoutl
or inout2 can be the driver signal. The tranif0 switch connects the two signals inoutl
and inout2 only if the control signal is logical 0. If the control signal is a logical 1, the
nondriver signal gets a high impedance value z. The driver signal retains value from its
driver. The tranifl switch conducts if the control signal is a logical 1.

These switches are instantiated as shown in below

tran tl(inoutl, inout2); //instance name tl is optional

tranifO (inoutl, inout2, control); //instance name is not specified

Resistive switches reduce signal strengths when signals pass through them. The changes
are shown below. Regular switches retain strength levels of signals from input to output.
The exception is that if the input is of supply, the output is of strength strong. Below
table shows the strength reduction due to resistive switches

Delay Specifications

➢ Specify no delay
bdsw name [instance name](in, out, control);
➢ Specify a turn-on and turn-off delay
bdsw name #(t_on_off)[instance name](in, out,control);
➢ Specify separately turn-on and turn-off delays
bdsw name #(t_on, t_off)[instance name](in, out, control);

Signal strengths:

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 Digital Design through Verilog

Drive Strength:

Assign strengths to some primitive types:

➢ The pulldown and pullup primitives can have one or two drive strengths

the simulator ignores the unneeded strength specification

pullup (weak1, weak0) (net1);

➢ The boolean primitives can have two drive strengths

must specify both drive strengths, or none

nand (highz1, strong) (net1,net2,net3);

➢ The trireg net type can have charge strengths

trireg (small) net1;

➢ The switch primitives CANNOT have drive strengths!

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Signal strength reductions:

Delay Specification on Switches:

MOS and CMOS switches

Delays can be specified for signals that pass through these switch-level elements.
Optional and appear immediately after the keyword for the switch.

➢ The unidirectional coms, nmos, and pmos switches can have rise, fall, and turn-
off delays
coms #(<delay>) (d, s, ng, pg);
nmos #(<rise_delay>,<fall_delay>) (d, s, g);
pmos #(<rise_delay>,<fall_delay>),<turnoff_delay>) (d, s, g);
➢ The bidirectional switches tranif0 and tranif1 can have turn-on and turn-off
delays,but no source-drain channel delays
tranif0 #(<delay>) (d, s, g);
tranif1 #(<turnon_delay>,<turnoff_delay>) (d, s, g);
➢ The pulldown,pullup,and tran gates cannot have delays
Note: You can specify delays in min:typ:max format.

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 Digital Design through Verilog

Delay Specification on NMOS and CMOS switches

Switch element Delay specification Examples

Pmos, Zero (no delay) pmos p1(out,data,control);

nmos, One (same delay on pmos#(1)

all transitions)
rpmos, p1(out,data,control);
Two (rise,fall)
rnmos nmos #(1,2)
Three p2(out,data,control);
(rise,fall,turnoff)
nmos #(1,3,2)
p2(out,data,control);

Cmos,rcmos Zero, one,two or three cmos #(5)

delays (same as c2(out,data,nctrl,pctrl);
above)
cmos #(1,2)
c1(out,data,nctrl,pctrl);

Bidirectional pass switches

Delay specification is interpreted slightly differently for bidirectional pass switches. These
switches do not delay signals passing through them. Instead, they have turn-on andturn-
off delays while switching. Zero, one, or two delays can b specified for bidirectional
switches, as shown in Table.

Switch Delay specification Examples

element
tran, rtran No delay specification
allowed
tranif1,rtranif1 Zero (no delay) rtranif0 rt1(inout1,inout2,control);

tranif0,rtranif0 One (both turn-on and tranif0#(3)

turn-off) T(inout1,inout2,control);

Two (turn-on, turn-off) tranif1#(1,2)

t1(inout1,inout2,control);

Delay Specification for Bidirectional Switches

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 Digital Design through Verilog

Examples:

1.CMOS inverter:

module mynot (input x, output f);

// internal declaration
supply1 vdd;
supply0 gnd;
// NOT gate body
pmos p1 (f, vdd, x);
nmos n1 (f, gnd, x);

endmodule

2. CMOS NAND

module my_nand (input x, y, output f);

supply1 vdd;
supply0 gnd;
wire a;
// NAND gate body
pmos p1 (f, vdd, x);
pmos p2 (f, vdd, y);
nmos n1 (f, a, x);
nmos n2 (a, gnd, y);
endmodule

3. Pseudo nMOS Gate:

module my_pseudo_nor(input x, y,
output f);
supply0 gnd;
// Pseudo nMOS gate body
nmos nx (f, gnd, x);
nmos ny (f, gnd, y);
pullup (f);
endmodule

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4. A 2-to-1 Multiplexer
module my_mux (out, s, i0, i1);
output out;
input s, i0, i1;
//internal wire
wire sbar; //complement of s
not (sbar, s);
//instantiate cmos switches
cmos (out, i0, sbar, s);
cmos (out, i1, s, sbar);
endmodule

14 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY