NMOS Transistors in Series/Parallel Connection

Lecture 6 ‹Transistors can be thought as a switch controlled by its

gate signal
CMOS Static & Dynamic Logic ‹NMOS switch closes when switch control input is high
Gates A B

Peter Cheung X Y Y = X if A and B

Department of Electrical & Electronic Engineering
Imperial College London A

X B Y = X if A OR B
Y

URL: www.ee.ic.ac.uk/pcheung/
E-mail: [email protected] NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors in Series/Parallel Connection Static CMOS Circuit

‹ Basic CMOS combinational circuits consist of:

PMOS switch closes when switch control input is low
• Complementary pull-up (p-type) and pull-down (n-type)

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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 Static CMOS
Example Gate: NAND

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Example Gate: NOR Complex Gate

‹ We can form complex combinational circuit

function in a complementary tree. The
procedure to construct a complementary tree is
as follow:-
• Express the boolean expression in an inverted
form
• For the n-transistor tree, working from the inner-
most bracket to the outer-most term, connect the
OR term transistors in parallel, and the AND
term transistors in series
• For the p-transistor tree, working from the inner-
most bracket to the outer-most term, connect the
OR term transistors in series, and the AND term
transistors in parallel

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 Example Gate: COMPLEX CMOS GATE Properties of Complementary CMOS Gates

V DD
1) High noise margins
:
B
V OH and V OL are at V DD and GND , respectively.
A
C 2) No static power consumption
:
There never exists a direct path betweenVDD and
D V SS (GND ) in steady-state mode.
OUT = D + A • (B+C)
3) Comparable rise and fall times:
A
D
(under the appropriate scaling conditions)
B C

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Transistor Sizing Propagation Delay Analysis - The Switch Model

• for symmetrical response (dc, ac) =

R ON

• for performance
V DD VDD V DD
V DD
Input Dependent Rp
Rp Rp Rp
B 8
A B B
A 4 Focus on worst- case A F Rp
Rn
C 8 F CL
B A
Rn
CL F
D 4 • assume µn=2* µp (i.e. n-channel A
Rn Rn Rn
CL
A
F transistors has 2 times the A B

A 2 transconductance as that of p-
D 1 channel.) (a) Inverter (b) 2-input NAND (c) 2-input NOR

B 2 C 2 t p = 0.69 Ron C L

(assuming that C L dominates!)

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 What is the Value of Ron? Analysis of Propagation Delay

V DD 1. Assume R n =R p = resistance of minimum

Rp Rp sized NMOS inverter

A B 2. Determine “Worst Case Input” transition

F (Delay depends on input values)
Rn
CL 3. Example: t pL H for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
t p L H = 0.69R p C L
2-input NAND 4. Example: t pH L for 2input NAND
- Worst case : TWO NMOS in series
t p H L = 0.69(2R n )C L

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Design for Worst Case Fast Complex Gate - Design Techniques

V DD V DD • Transistor Sizing:
V DD
As long as Fan-out Capacitance dominates
1 1 B 4 B 8

A
A 2 A 4 • Progressive Sizing:
B
C 4 C 8
F Out
2 In N MN
CL D 2 D 4 CL
B
F M1 > M2 > M3 > MN
F
A 2
A 2 In 3 C3
2 D 1 M3
D 1 Distributed RC-line
A B 2 C 2
B 2 C 2 In 2 M2 C2

In 1 M1 C1
Can Reduce Delay with more than 30%!
Here it is assumed that Rp = Rn
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 Fast Complex Gate - Design Techniques (2) Fast Complex Gate - Design Techniques (3)

• Transistor Ordering • Im proved Logic Design

critical path critical path

CL CL
In 3 M3 In 1 M1

In 2 M2 C2 C2
In 2 M2

In 1 M1 C1 C3
In 3 M3

(a) (b)
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Fast Complex Gate - Design Techniques (4) Example: Full Adder

VDD

• Buffering: Isolate Fan-in from Fan-out VD D

Ci A B
A B
A
B
Ci B VD D
A
X
Ci
Ci A S
Ci
A B B VD D
A B Ci A

CL CL Co B

C o = AB + C i(A+B)

28 transistors
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 A Revised Adder Circuit Ratioed Logic

V DD

VD D VDD A
V DD V DD VD D

A B B A B Ci B Resistive Depletion PMOS

Kill Load RL Load VT < 0 Load
"0" -Propagate V SS
A Ci
Co F F F
Ci S
In 1 In 1 In 1
A Ci In 2 PDN In 2 PDN In 2 PDN
"1" -Propagate In 3 In 3 In 3
Generate
A B B A B Ci A V SS V SS VS S
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
B

Goal: to reduce the num ber of devices over complementary CMOS

24 transistors
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Ratioed Logic Active Loads

VD D
VD D V DD
• N transistors + Load
Resistive
• V OH = V D D Depletion PMOS
Load RL VT < 0
Load Load

R PN V SS
• V OL =
F F
F R PN + R L
In 1 In 1
In 1 In 2 PDN In 2 PDN
• Assymetrical response In 3 In 3
In 2 PDN
In 3 • Static power consumption V SS V SS

• t pL = 0.69 R L C L depletion load NMOS pseudo-NMOS

V SS
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 Psuedo NMOS Pseudo-NMOS NAND Gate

‹ Disadvantages of previous circuit :

• Almost twice as many transistors as equivalent NMOS implementation.
• If there are too many series transistors in the tree, switching speed is VDD
reduced.
‹ Try a pseudo NMOS circuit:-

GND

‹ The pull-up p-channel transistor is always conducting.

• Disadvantages: high d.c. dissipation & slow rise time.
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Improved Loads (1) Example

V DD V DD

Out
M1 M2
Out

Out Out
B B B B
A
A
B PDN1 PDN2
B A A

V SS V SS

Dual Cascode Voltage Switch Logic (DCVSL) XOR-NXOR gate

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 Dynamic Logic Problem with Cascading Dynamic Logic

‹ There is another class of logic gates which relies on the use of a clock signal. This class of ‹ Problem with cascading such as a circuit:-
circuit is known as dynamic circuits. The clock signal is used to divide the gate operation into • Inputs can only be changed when Ø is low and must be stable when Ø is high.
two halves. In the first half, the output node is pre-charged to a high or low logic state. In the
• When Ø is low, both P1 and P2 are precharged to a high voltage. However when Ø is
second half of a clock cycle, the circuit evaluates the correct output state.
high, delay through on the output P1 may erroneously discharge P2.
‹ When Ø is low, Z is charged to high. When Ø is high, n logic block evaluates input, and
conditionally discharges Z. This circuit adds series resistance to the pull-down n-channel
transistor, therefore the fall time is increased slightly.
‹ This circuit is dynamic because during evaluation, the output high level at Z is maintained by
the stray capacitance at the output node. If Ø stays high (i.e. evaluation period) for a long
time, Z may eventually discharge to a low logic level.

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CMOS Domino Logic Alternating dynamic logic (1)

‹ Solution to the above problem:- ‹ Another possible scheme is to use alternate n and p logic blocks as shown below.
• Add an inverter to ensure that the output is low ‹ In this scheme, each alternate stage is pre-charged high and low. Each stage uses
during precharge, and prevent the next stage alternate n and p transistors to implement the gate function. Stage 1 makes at most one
from evaluating, until the current stage has high to low transition, while stage 2 makes at most one low to high transition for each
finished evaluation. evaluation. Since the p logic block will only change state if input is a low, this circuit
• This ensures that each stage (at the output of behaves like the domino logic.
the inverter) will make at most a single
transition from 0 -> 1.
• When many stages are cascaded, evaluation
proceeds from one stage to the next - similar
to dominos falling one after another.
‹ Disadvantages of domino logic:-
• Only non-inverting logic is possible, i.e. output
also high active
• Each gate needs an inverter; hence more
transistors
• Suffer from charge sharing effect (considered
later)

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 Alternating dynamic logic (2) Making a Dynamic Gate static

‹ A slight variation of this circuit is show below, where an inverter is added per stage to ‹ Finally, by adding a feedback pullup, we can make the circuit static.
increase flexibility. Here each stage can drive either n or p blocks and both low active and ‹ This circuit turns the originally dynamic gate into a static gate because the feedback
high active logic can be implemented. transistor can maintain a logic high level at the node Z for an indefinite length of time.
Without this feedback transistor, the charge stored at the node Z will eventually leak away.

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Pass Transistor Logic Pass Transistor Logic with feedback

‹ An alternative design style is to use pass transistors. The following is an example of a

multiplexer. ‹ This circuit uses only n transistors, therefore it is economical on transistor count.
‹ Complementary transmission gates are used here because n-channel pass transistors will In order to ensure that the 1 logic level is passed properly, a p pull-up transistor
pass 0 logic level well but, 1 logic level poorly. This is because in order for the n-transistor is added. This restores the 1 logic level at the input of the inverter.
to be ON, Vgs must be greater than Vth. Therefore each series n transistor will degrade the
1 logic level by Vth. The opposite is true with p-channel pass transistors: 0 logic level is
passed poorly.

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 Pass Transistor XOR gate 4-input NAND Gate
‹ Pass transistor logic can sometimes be very economical in implementing logic
functions. For example, an XOR gate can be implemented with just two
transmission gates:- Vdd
VD D

In 1 In 2 In 3 In 4
Out
In 1

In 2
Out
In 3

In 4

GND

In1 In2 In3 In4

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Standard Cell Layout Methodology Two Versions of (a+b).c

VD D V DD

metal1 VD D
x
x
Well

GND GND
V SS a c b a b c
Routing Channel
signals (a) Input order {a c b} (b) Input order {a b c}
polysilicon

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 Logic Graph Consistent Euler Path
x
VD D
x
b PUN c
j c c x i
V DD
a x i VD D

x b a
b a j
j
c
i PDN
GND GND
a b
{ a b c}
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Example: x = ab+cd
x x

b c b c

x V DD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d }

VD D

GND
a b c d
(c) stick diagram for ordering {a b c d}

PYKC 25-Jan-05 E4.20 Digital IC Design Lecture 6 - 43