A

Project Report On

ELECTRONIC VOTING MACHINE

Submitted in partial fulfilment of the requirements for award of the degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
K L N HARI SIMHA RAO (11703817)
B PRAVEEN (11709284)
V S N R SESHANK (11705174)

Under the guidance of

Mr.NAVEEN
In charge, VLSI
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
(A Government of India Enterprise)

DEPARTMENTOF ELECTRONICS AND COMMUNICATION

ENGINEERING
LOVELY PROFESSIONAL UNIVERSITY
DECLARATION

We hereby declare that the project entitled

ELECTRONICVOTINGMACHINE
submitted in partial fulfilment of the requirments for the award of
degree of Bachelor of Technology in Electronics and communication
Engineering.This dissertation is our original work and the project has
not formed the basis for the award of any degree , associate
ship,fellowship or any other similar titles and no part of it has been
published or sent for the publication at the time of submission.

K L N HARI SIMHA RAO (11703817)

B PRAVEEN (11709284)
V S N R SESHANK (11705174)
 ACKNOWLEDGEMENT

We wish to take this opportunity to express our deep gratitude to all those
who helped, encouraged, motivated and have extended their cooperation in
various ways during our project work. It is our pleasure to acknowledgement
the help of all those individuals who was responsible for foreseeing the
successful completion of our project.

We would like to thank Mr. N.S. SHEKAR BABU (In charge, CED) and
express our gratitude with great admiration and respect to our project guide
Mr. T. Naveen Kumar Reddy andMs. K. SIVA RAMALAKSHMI for their
valuable advice and help throughout the development of this project by
providing us with required information without whose guidance, cooperation
and encouragement, this project couldn’t have been materialized.

Last but not the least; we would like to thank the entire respondents for
extending their help in all circumstances.
K L N HARI SIMHA RAO (11703817)
B PRAVEEN (11709284)
V S N R SESHANK (11705174)

ORGANIZATION PROFILE

ECIL was setup under the department of Atomic Energy in the year 1967
with a view to generate a strong indigenous capability in the field of
professional grade electronic. The initial accent was on self-reliance and ECIL
was engaged in the Design Development Manufacture and Marketing of several
products emphasis on three technology lines viz. Computers, control systems
and communications. ECIL thus evolved as a multi-product company serving
multiple sectors of Indian economy with emphasis on import of country
substitution and development of products and services that are of economic and
strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into
collaboration with OSI Systems Inc. (www.osi-systems.com) and set up a joint
venture "ECIL_RAPSICAN LIMITED". This Joint Venture manufacture the
equipment’s manufactured by RAPSICAN, U.K, U.S.A with the same state of
art Technology, Requisite Technology is supplied by RAPSICAN and the final
product is manufactured at ECIL facility.
 Recognizing the need for generating quality IT professionals and to meet
the growing demand of IT industry, a separate division namely CED has been
established to impart quality and professional IT training under the brand name
of ECIT. ECIT, the prestigious offshoot of ECIL is an emerging winner and is
at the fore front of IT education in the country.

Mission
ECIL’s mission is to consolidate its status as a valued national asset in the
area of strategic electronics with specific focus on Atomic Energy, Defense,
Security and such critical sectors of strategic national importance.
Objectives
 To continue services to the country’s needs for the peaceful uses Atomic
Energy. Special and Strategic requirements of Defence and Space,
Electronics Security System and Support for Civil aviation sector.
 To establish newer Technology products such as Container Scanning
Systems and Explosive Detectors.
 To re-engineer the company to become nationally and internationally
competitive by paying particular attention to delivery, cost and quality in
all its activities.
 To explore new avenues of business and work for growth in strategic
sectors in addition to working realizing technological solutions for the
benefit of society in areas like Agriculture, Education, Health, Power,
Transportation, Food, Disaster Management etc.
Divisions
The Company is organized into divisions serving various sectors, national
and Commercial Importance. They are Divisions serving nuclear sector like
Control & Automation Division (CAD), Instruments & Systems Division (ISD),
Divisions Serving defence sector like Communications Division (CND),
Antenna Products Division (APD), Servo Systems Division (SSD) etc.,
Divisions handling Commercial Products are Telecom Division (TCD),
Customer Support Division (CSD), Computer Education Division (CED).
Exports
ECIL is currently operating in major business EXPORT segments like
Instruments and systems design, Industrial/Nuclear, Servo Systems, Antenna
Products, Communication, Control and Automation and several other
components.
Services
The company played a very significant role in the training and growth of
high calibre technical and managerial manpower especially in the fields of
Computers and Information Technology. Though the initial thrust was on
meeting the Control & Instrumentation requirements of the Nuclear Power
Program, the expanded scope of self-reliance pursued by ECIL enabled the
company to develop various products to cater to the needs of Defence, Civil
Aviation, Information & Broadcasting, Tele communications, etc.

ABSTRACT

Surpassing of the planned budget and delivery time is a common feature

during the implementation of building investments in Poland. Only a small
number of companies use effective methods of project monitoring during
investment performance. One of the popular tools used to control projects
with regard to cost and time is the earned value method (EVM). There is,
however, no detailed guidance how to deploy the method to the specific
characteristics and conditions during the execution of building investments.
This fact has contributed to this paper, which presents the results of
application and adaptation of the earned value method (EVM) and its further
extensions in the control of building projects during their execution (with
regard to cost and time), prediction of the final duration and costs, and
presentation of the effects resulting from calculations. The analyses were
performed in terms of the contractor for 5 selected completed and ongoing
building projects in Poland.

CONTENTS
1. VLSI Introduction
2. FPGA DESIGN
3. PROJECT DESCRIPTION
4. XILINX PROCEDURE
5. RTL SCHEMATIC
6. WAVEFORMS
7. APPLICATIONS
VLSI INTRODUCTION

Very-large-scale integration (VLSI) is the process of creating an integrated

circuit (IC) by combining thousands of transistors into a single chip. VLSI began
in the 1970s when complex semiconductor and communication technologies
were being developed. The microprocessor is a VLSI device. Before the
introduction of VLSI technology, most ICs had a limited set of functions they
could perform. An electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these into one chip. The
electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration
technologies and system design applications. With the advent of very large
scale integration (VLSI) designs, the number of applications of integrated
circuits (ICs) in high-performance computing, controls, telecommunications,
image and video processing, and consumer electronics has been rising at a very
fast pace. The current cutting-edge technologies such as high resolution and
low bit-rate video and cellular communications provide the end-users a
marvellous amount of applications, processing power and portability. This
trend is expected to grow rapidly, with very important implications on VLSI
design and systems design. 10 VLSI Design Flow The VLSI IC circuits design flow
is shown in the figure below. The various levels of design are numbered and
the blocks show processes in the design flow. Specifications comes first, they
describe abstractly, the functionality, interface, and the architecture of the
digital IC circuit to be designed.

XILINX PROCEDURE

Software Overview The ISE® software controls all aspects of the design flow. Through the
Project Navigator interface, you can access all of the design entry and design
implementation tools.

You can also access the files and documents associated with your project. Project Navigator
Interface By default, the Project Navigator interface is divided into four panel sub-windows,
as seen in Figure 2-1. On the top left are the Start, Design, Files, and Libraries panels, which
include display and access to the source files in the project as well as access to running
processes for the currently selected source. The Start panel provides quick access to 16
opening projects as well as frequently access reference material, documentation and
tutorials. At the bottom of the Project Navigator are the Console, Errors, and Warnings
panels, which display status messages, errors, and warnings. To the right is a multi-
document interface (MDI) window referred to as the Workspace. The Workspace enables
you to view design reports, text files, schematics, and simulation waveforms. Each window
can be resized, undocked from Project Navigator, moved to a new location within the main
Project Navigator window, tiled, layered, or closed. You can use the View > Panels menu
commands to open or close panels. You can use the Layout > Load Default Layout to
restore the default window layout. These windows are discussed in more detail in the
following sections Processes Pane The Processes pane is context sensitive, and it changes
based upon the source type selected in the Sources pane and the top-level source in your
project. From the Processes pane, you can run the functions necessary to define, run, and
analyze your design. The Processes pane provides access to the following functions:

• Design Summary/Reports Provides access to design reports, messages, and summary of

results data. Message filtering can also be performed.
• Design Utilities Provides access to symbol generation, instantiation templates, viewing
command line history, and simulation library compilation.

• User Constraints Provides access to editing location and timing constraints.

• Synthesis Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic,
and synthesis reports. Available processes vary depending on the synthesis tools you use.

• Implement Design Provides access to implementation tools and post implementation

analysis tools.

• Generate Programming File Provides access to bit stream generation.

• Configure Target Device Provides access to configuration tools for creating programming
files and programming the device. The Processes pane incorporates dependency
management technology. The tools keep track of which processes have been run and
which processes need to be run. Graphical status indicators display the state of the flow at
any given time. When you select a process in the flow, the software automatically runs the
processes necessary to get to the desired step. For example, when you run the Implement
Design process, Project Navigator also runs the Synthesis process because implementation
is dependent on up-to-date synthesis results Files Panel The Files panel provides a flat,
sortable list of all the source files in the project. Files can be sorted by any of the columns
in the view. Properties 17 for each file can be viewed and modified by right-clicking on the
file and selecting Source Properties

Libraries Panel The Libraries panel enables you to manage HDL libraries and their
associated HDL source files. You can create, view, and edit libraries and their associated
sources.

Console Panel The Console provides all standard output from processes run from Project
Navigator. It displays errors, warnings, and information messages. Errors are signified by a
red X next to the message; while warnings have a yellow exclamation mark (!).

Errors Panel The Errors panel displays only error messages. Other console messages are
filtered out.

Warnings Panel The Warnings panel displays only warning messages. Other console
messages are filtered out.

Error Navigation to Source You can navigate from a synthesis error or warning message in
the Console, Errors, or Warnings panel to the location of the error in a source HDL file. To
do so, select the error or warning message, right-click the mouse, and select Go to Source
from the right-click menu. The HDL source file opens, and the cursor moves to the line with
the error. Error Navigation to Answer Record You can navigate from an error or warning
message in the Console, Errors, or Warnings panel to relevant Answer Records on the
Support page of the Xilinx® website. To navigate to the Answer Record, select the error or
warning message, right-click the mouse, and select Go to Answer Record from the right-
click menu. The default Web browser opens and displays all Answer Records applicable to
this message.

Workspace The Workspace is where design editors, viewers, and analysis tools open. These
include ISE Text Editor, Schematic Editor, Constraint Editor, Design Summary/Report
Viewer, RTL and Technology Viewers, and Timing Analyzer. Other tools such as the
PlanAhead™ software for I/O planning and Floor planning, ISim, third-party text editors,
XPowerAnalyzer, and iMPACT open in separate windows outside the main Project
Navigator environment when invoked.

Design Summary/Report Viewer The Design Summary provides a summary of key design
data as well as access to all of the messages and detailed reports from the synthesis and
implementation tools. The summary lists high-level information about your project,
including overview information, a device utilization summary, performance data gathered
from the Place and Route (PAR) report, constraints information, and summary information
from all reports with links to the individual reports. A link to the System Settings report
provides information on environment variables and tool settings used during the design
implementation.

Starting the ISE Software

To start the ISE software, double-click the ISE Project Navigator icon on your desktop, or
select Start to> All Programs > Xilinx ISE Design Suite > ISE Design Tools > Project Navigator

Creating a New Project To create a new project using the New Project Wizard, do the
following:

1. From Project Navigator, select File > New Project. The New Project Wizard appears.

2. In the Location field, browse to c:\xilinx_or to the directory in which you installed the
project.

3. In the Name field, enter .

4. Verify that HDL is selected as the Top-Level Source Type, and click Next.

5. Select the following values in the New Project Wizard—Device Properties page:
• Product Category: All

• Family: Spartan3A and Spartan3AN

• Device: XC3S700A

• Package: FG484

• Speed: -5

• Synthesis Tool: XST (VHDL/Verilog)

• Simulator: ISim (VHDL/Verilog)

• Preferred Language: VHDL or Verilog depending on preference. This will determine the
default language for all processes that generate HDL files. Other properties can be left at
their default values. 6. Click Next, then Finish to complete the project creation.

Design Description

The design used in this tutorial is a hierarchical, HDL-based design, which means that the
top-level design file is an HDL file that references several other lower-level macros. The
lower-level macros are either HDL modules or IP modules. The design begins as an
unfinished design. Throughout the tutorial, you will complete the design by generating
some of the modules from scratch and by completing others from existing files. When the
design is complete, you will simulate it to verify the design functionality. In the runner’s
stopwatch design, there are five external inputs and four external output buses. The
system clock is an externally generated signal. The following list summarizes the input and
output signals of the design.

Inputs

Outputs

Functional blocks

To run the integrated simulation process in ISE:

1. Select the counter test bench waveform in the Sources in Project window. You can see
Xilinx ISE Simulator processes in the Processes for Source window.

2. Double-click on the Simulate Behavioral Model process in the Project window.

create a waveform in Xilinx

1. In the Sources tab, select the test bench waveform file for which you will generate the
self-checking test bench.
2. In the Processes tab, expand Xilinx ISE Simulator, then expand Simulate behavioral
Model. 3. Right-click the Generate Self-Checking Test Bench process, and select Properties.
20

ELECTRONIC VOTING MACHINE

VHDL MODULE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity voting_machine is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

ysrcp : in STD_LOGIC;

tdp : in STD_LOGIC;

jsp : in STD_LOGIC;

select_party : in STD_LOGIC;

count1_op : out STD_LOGIC_VECTOR (5 downto 0);

count2_op : out STD_LOGIC_VECTOR (5 downto 0);

count3_op : out STD_LOGIC_VECTOR (5 downto 0));

end voting_machine;

architecture Behavioral of voting_machine is

signal count1,count2,count3: std_logic_vector(5 downto 0);

signal state: std_logic_vector(5 downto 0);

constant initial: std_logic_vector(5 downto 0):= "000001";

constant check: std_logic_vector(5 downto 0):= "000010";

constant ysrcp_state: std_logic_vector(5 downto 0):= "000100";

constant tdp_state: std_logic_vector(5 downto 0):= "001000";

constant jsp_state: std_logic_vector(5 downto 0):= "010000";

constant done: std_logic_vector(5 downto 0):= "100000";

begin

process(clk,reset,ysrcp,tdp,jsp)

begin

if(reset='1') then

count1<=(others=>'0');

count2<=(others=>'0');

count3<=(others=>'0');

state<=initial;

else

if(rising_edge(clk) and reset='0') then

case state is

when initial=>

--NSL

if(ysrcp='1' or tdp='1' or jsp='1') then

state<=check;

else
 state<=initial;

end if;

--OFL

when check =>

--NSL

if(ysrcp='1') then

state<=ysrcp_state;

elsif(tdp='1') then

state<=tdp_state;

elsif(jsp='1') then

state<=jsp_state;

else

state<=check;

end if;

--OFL

when ysrcp_state =>

--NSL

if(select_party='1') then

state<=done;

else

state<=ysrcp_state;

end if;

--OFL

count1<=count1 + 1;

when tdp_state =>

--NSL
 if(select_party='1') then

state<=done;

else

state<=tdp_state;

end if;

--OFL

count1<=count2 + 1;

when jsp_state =>

--NSL

if(select_party='1') then

state<=done;

else

state<=jsp_state;

end if;

--OFL

count1<=count3 + 1;

when done =>

--NSL

state<=initial;

--OFL

when others=>

state<=initial;

end case;

end if;

end if;

end process;

count1_op<=count1;
count2_op<=count2;

count3_op<=count3;

end Behavioral;

Vhdl test bench

-------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY votingmachine_tb IS

END votingmachine_tb;

ARCHITECTURE behavior OF votingmachine_tb IS

COMPONENT voting_machine

PORT(

clk : IN std_logic;

reset : IN std_logic;

ysrcp : IN std_logic;

tdp : IN std_logic;

jsp : IN std_logic;

select_party : IN std_logic;

count1_op : OUT std_logic_vector(5 downto 0);

count2_op : OUT std_logic_vector(5 downto 0);

count3_op : OUT std_logic_vector(5 downto 0)

);

END COMPONENT;
 --Inputs

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal ysrcp : std_logic := '0';

signal tdp : std_logic := '0';

signal jsp : std_logic := '0';

signal select_party : std_logic := '0';

--Outputs

signal count1_op : std_logic_vector(5 downto 0);

signal count2_op : std_logic_vector(5 downto 0);

signal count3_op : std_logic_vector(5 downto 0);

constant clk_period : time := 5 ns;

BEGIN

uut: voting_machine PORT MAP (

clk => clk,

reset => reset,

ysrcp => ysrcp,

tdp => tdp,

jsp => jsp,

select_party => select_party,

count1_op => count1_op,

count2_op => count2_op,

count3_op => count3_op

 );

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

stim_proc: process

begin

wait for 100 ns;

wait for clk_period*10;

reset<='1';

wait for 10 ns;

reset<='0';

ysrcp<='0';

tdp<='0';

jsp<='0';

ysrcp<='1';

wait for 10 ns;

ysrcp<='0';

wait for 10 ns;

select_party<='1';

wait for 10 ns;

select_party<='0';

wait for 10 ns;

ysrcp<='1';
wait for 10 ns;

ysrcp<='0';

wait for 10 ns;

select_party<='1';

wait for 10 ns;

select_party<='0';

wait for 10 ns;

ysrcp<='1';

wait for 10 ns;

ysrcp<='0';

wait for 10 ns;

select_party<='1';

wait for 10 ns;

select_party<='0';

wait for 10 ns;

tdp<='1';

wait for 10 ns;

tdp<='0';

wait for 10 ns;

select_party<='1';

wait for 10 ns;

select_party<='0';

wait for 10 ns;

jsp<='1';

wait for 10 ns;

jsp<='0';

wait for 10 ns;

select_party<='1';

wait for 10 ns;

select_party<='0';

wait for 10 ns;

wait;

end process;

END;

RTL Schematic

WAVEFORM
APLLICATIONS OFEVM

Following are the applications of watchdog timer:

• Electronic Voting Machine (also known as EVM ) is voting using electronic

means to either aid or take care of the chores of casting and counting votes.
An
EV
M
is
desi
gne
d
wit
h
two
unit
s:
the
control unit and the balloting unit.

• The EVM aims to make the electoral process secure, fair and transparent.