Week 7: Assignment Solutions

1. What does the declaration “reg [7:0] data[15:0]” indicate?

a. A 2-dimensional array with 8 rows and 16 columns, where every
element is a single bit.
b. An array of 16 bytes.
c. An array of 8 words, each word consisting of 16 bits.
d. None of the above.
Correct answer is (b).
“reg [7:0]” indicates that each data item is a 8-bit vector (i.e. a byte).
“data[15:0]” indicates that it is an array of size 16.
2. What does the declaration “reg data[7:0][15:0]” indicate?
a. A 2-dimensional array with 8 rows and 16 columns, where every
element is a single bit.
b. An array of 16 bytes.
c. An array of 8 words, each word consisting of 16 bits.
d. None of the above.
Correct answer is (a).
Here there is no size specifier after “reg”, which indicates that each data
element is 1-bit in size. The two dimensions after “data” indicates that it is
a 2-dimensional array of single-bit numbers.
3. What does the following code segment implement?
tri [0:15] common; wire dir;
wire [0:15] A, B;
assign common = (dir == 0) ? A : 16’hzzzz;
assign B = (dir == 1) ? common : 16’hzzzz;
a. A gating logic that connects A and B through common.
b. A bus multiplexer with dir as the select signal.
c. A bidirectional data bus that connects A and B to common.
d. None of the above.
Correct answer is (c).
If “dir = 0”, “A” gets assigned to “common”; i.e. data flows from “A” to
“common”, by the first “assign” statement.
If “dir = 1”, “common” gets assigned to “B”, i.e. data flows from “common”
to “B”.
So, “common” is a bidirectional data but that gets connected to “A” or “B”
depending on the control signal “dir”.

4. Which of the following is true for register banks?

a. Register read operation can be carried out using blocking
assignment.
b. Register write operation is carried out using non-blocking
statement in synchronism with the clock.
c. A register read and register write operation can be carried out
simultaneously.
d. All of the above. *
 Correct answer is (d).
All the statements (a), (b) and (c) are true.
5. For an n-stage pipeline implementation of some computation, the
maximum speedup that can be obtained is upper bounded by:
a. 2n
b. n
c. 2n
d. None of the above
Correct answer is (b).
The maximum speedup that can be obtained in a pipeline is upper
bounded by the number of stages.
6. Consider the following processors, where the inter-stage pipeline
registers are assumed to be of zero latency, and the stage delays are
specified in nanoseconds. Which of the following pipelines will have the
highest clock frequency?
a. 4-stage pipeline with stage delays 1, 2, 2 and 1
b. 4-stage pipeline with stage delays 1, 1.5, 1.5, and 1.5
c. 5-stage pipeline with stage delays 0.5, 1, 1, 0.6 and 1
d. 5-stage pipeline with stage delays 0.5, 0.5, 0.3, 1 and 1.1
Correct answer is (c).
Maximum clock frequency is limited by the slowest pipeline stage. The
slowest pipeline stage is the smallest in option (c), namely, “1”. For (a), it
is “2”; for (b), it is “1.5”; and for (d) it is “1.1”.
7. The stage delays in a 4-stage pipeline are 800, 500, 400 and 300
nanoseconds. The first stage is replaced with a functionally equivalent
design involving two stages with respective delays 600 and 350
nanoseconds. The throughput of the pipeline increases by …………
percent.
Correct answer is 33.3%.
Pipeline 1: To process n data, time = 3 + 800n
Throughput = 1/800 (approx.)
Pipeline 2: To process n data, time = 4 + 600n
Throughput = 1/600 (approx..)
% improvement = (1/600 – 1/800) / (1/800) * 100 = 33.3

8. Which of the following is false for the inter-stage register stages in a

pipeline.
a. They should be implemented either using master-slave flip-flops
or using latches/flip-flops with non-overlapping clocks for
adjacent stages.
b. The outputs generated by a stage can be stored in the inter-stage
register stage itself.
c. During synthesis, the registers get mapped to combinational
circuits during optimization.
d. None of the above.
Correct answer is (c).
The register stages are essential for overlapped operation in a pipeline,
and as such cannot be implemented using combinational circuits.
To avoid race conditions, we must satisfy (a). The statement (b) is also
true for a pipeline implementation.
9. Why is it required to forward the same value from one pipeline register
stage to the next at times without any change?
a. The stage is a dummy stage not doing any computation.
b. The value is required by a subsequent stage of the pipeline.
c. It helps in reducing the delays in pipeline implementation.
d. None of the above.
Correct answer is (b).
Several instructions execute in overlapped fashion in a pipeline. A
particular instruction may require a value computed in an earlier stage
much later in the pipeline. To ensure that the following instruction(s) do
not overwrite the value, it must be forwarded to the following pipeline
register stage(s).

10. What function does the following switch-level model realize?

module surprise (in1, in2, out);
input in1, in2; output out;
supply1 vplus; supply0 vgnd;
wire t;
pmos (t, vplus, in1);
pmos (out, t, in2);
nmos (out, vgnd, in1);
nmos (out, vgnd, in2);
endmodule
a. NAND
b. Exclusive OR
c. NOR
d. Exclusive NOR
Correct answer is (c).
When both “in1” and “in2” are 0, the two pmos switches connected to
“vplus” are turned on, and hence the output is 1.
When any of the inputs is 1, the corresponding nmos switch connects the
outout to ground; thus the output is 0.
This is the NOR function.
11. The value assigned to b (in unsigned decimal) after execution of the
following code segment will be …………
reg [2:0] a; reg [4:0] b; reg[1:0] c;
integer val;
initial
begin
val = 333;
{a,b,c} = val;
end
The binary equivalent of 333 is “0 1 0 1 0 0 1 1 0 1”, with leading 0’s. After
the assignment statement, the least significant 2 bits will be assigned to
“c” (i.e. 2’b01), the next 5 bits are assigned to “b” (i.e. 5’b10011), and the
next 3 bits to “a” (i.e. 3’b010). So the value of “b” in decimal will be 19.
12. Suppose we are construction a 8-to-1 multiplexer using cmos switches. In
addition to three NOT gates, the number of cmos switches required will
be …………
 For a 8-to-1 multiplexer, there will be 8 rows in which the switches will
be arranged. Since there are 3 select inputs, every row will get selected
for some combination of the select lines. So we need 3 switches in every
row. The total number of switches required will be 3 x 8 = 24.
13. Which of the following statements are true?
a. A tranif0 switch allows bidirectional flow of data between the
two end terminals when the control signal is 0.
b. A tranif0 switch allows bidirectional flow of data between the
two end terminals when the control signal is 1.
c. A tranif1 switch allows bidirectional flow of data between the
two end terminals when the control signal is 0.
d. A tranif1 switch allows bidirectional flow of data between the
two end terminals when the control signal is 1.
Correct answers are (a) and (d).
This follows from the definition of “transif0” and “tranif1” switches.
14. Which of the following signal types has the highest signal strength?
a. supply1
b. highz
c. pullup
d. pulldown
Correct answer is (a).
“supply1” and “supply0” are the strongest signals in terms of strength as
they are directly connected to the power supply.