A SCHEMATIC ADIABATIC DESIGN OF CMOS CIRCUIT FOR

MEASUREMENT OF LOW POWER DISSIPATION

Murli Manohar Hinnawar Sanjeev Kumar
Assist. Prof RKDFIST Bhopal RKDFIST Bhopal
[email protected]

ABSTRACT energy stored in the load capacitors rather than the traditional

Power dissipation becoming a limiting factor in VLSI circuits way of discharging the load capacitors to the ground and

and systems. Due to relatively high complexity of VLSI systems wasting this energy. Power reduction is achieved by recovering

used in various applications, the power dissipation in CMOS the energy in the recover phase of the supply clock.

inverter, arises from it’s switching activity, which is mainly KEYWORDS

influenced by the supply voltage and effective capacitance. The Static cmos, adiabatic logic, microwind tool etc.
low-power requirements of present electronic systems have 1.POWER DISSIPATION IN CMOS CIRCUITS
challenged the scientific research towards the study of Power dissipation in digital CMOS circuits can be classified
technological, architectural and circuital solutions that allow a into two types: dynamic power dissipation and static power
reduction of the energy dissipated by an electronic circuit. One dissipation. Dynamic power dissipation is due to high-to-low
of the main causes of energy dissipation in CMOS circuits is and low-to-high signal switching in circuits. Static power
due to the charging and discharging of the node capacitances of dissipation depends on the logic states of the circuit. It does not
the circuits, present both as a load and as parasitic. Such part of depend on signal switching. The average power dissipation in a
the total power dissipated by a circuit is called dynamic power. digital CMOS circuit can be given by the following equation
In order to reduce the dynamic power, an alternative approach
Pavg = Psw + Psc + Pleak + Pstatic
to the traditional techniques of power consumption reduction,
named adiabatic switchingtechnique is use. Adiabatic switching Where, Psw is the capacitive switching power dissipation,

is an approach to low-power digital circuits that differs Psc is the short-circuit power dissipation, Pleak is the power

fundamentally from other practical low-power techniques. The dissipation due to leakage currents and Pstatic is the static

term adiabatic comes from thermodynamics, used to describe a power dissipation due to non-leakage static currents.

process in which there is no exchange of heat with the Capacitive switching power and short-circuit power are

environment. When adiabatic switching is used, the signal components of dynamic power dissipation. Leakage power is a

energies stored on circuit capacitances may be recycled major component of static power dissipation in CMOS circuits,

instead of dissipated as heat. The adiabatic switching technique though there might be some non-leakage currents that

can achieve very low power dissipation, but at the expense of contribute to a small percentage of static power dissipation.

circuit complexity. Adiabatic logic offers a way to reuse the

 switching power is the largest contributor to dynamic power

. dissipation. Capacitive switching power is the power

dissipation caused by charging and discharging of capacitances.
In digital CMOS circuits, capacitances are formed from
parasitic in the transistors and interconnection wires. These
parasitic capacitances cannot be eliminated. Their estimation is
crucial for dynamic power analysis and optimizations. Consider
the inverter in Fig 2 Assume that initially it is in steady state
with input at logic HIGH and output at logic LOW. If there is a
falling transition at the input from HIGH to LOW as shown in
Figure 2 (a), then the nmos transistor turns off while the pmos
transistor turns on. The capacitance, CL, is charged from the
power supply. This charging process draws energy equal to

2
CVDD from the power supply. Half of this is dissipated
immediately in the PMOS transistors and the interconnect,
while the other half is stored on the load capacitance. If the
input undergoes a rising transition from LOW to HIGH as
shown in Figure 2(b), then the pmos transistor turns off while
the nmos transistor turns on. The capacitance CL is completely
discharged. The energy stored in the capacitor gets dissipated
across the nmos and the interconnect. In summary, every time a
capacitive node switches from ground to VDD (and back to
Fig 1 CMOS Inverter for Power Analysis. 2
ground), energy of CVDD is consumed. This leads to the

1.1static power dissipation conclusion that CMOS power consumption depends on the
Ideally, leakage power dissipation is the only source of static switching activity of the signals involved. We can define
power dissipation in fully complementary digital CMOS activity, α as the expected number of zero to one transition per
circuits. In properly designed circuits non-leakage static data cycle. If this is coupled with the average data rate, f,
currents can be avoided. Static power dissipation can however which may be the clock frequency in a synchronous system,
result from degenerated voltage levels at the inputs to static then the effective frequency of nodal charging is given the
gates. Bus contention ,signal conflicts due to multiple drivers, product of the activity and the data rate: αf. This leads to the
leakage current drawn continuously from the power supply also following formulation for the average CMOS power
result in static power dissipation. consumption:
1.2 Dynamic Power Dissipation 2
Pdyn = a CVDD f
Dynamic power dissipation is the most significant source of
power dissipation in digital CMOS circuits and capacitive
So, to reduce the power dissipation, the circuit designer can
minimize the switching event, decrease the node capacitance,
reduce the voltage swing or apply a combination of these
methods. Yet, in all these cases, the energy drawn from the
power supply is used only once before being dissipated. To
increase the energy efficiency of the logic circuits, other
measures can be introduced for recycling the energy drawn
from the power supply. In order to reduce the dynamic power,
an alternative approach to the traditional techniques of power
consumption reduction, named adiabatic switchingtechnique is
use. Adiabatic switching is an approach to low-power digital
circuits that differs fundamentally from other practical low- A B C
power techniques. The term adiabatic comes from
thermodynamics, used to describe a process in which there is
Fig 2 (A) Cmos Inverter (B)Charging Capacitor (C) Discharging
no exchange of heat with the environment. When adiabatic Capacitor
switching is used, the signal energies stored on circuit
capacitances may be recycled instead of dissipated as heat. The
1.3Short Circuit Power Dissipation
adiabatic switching technique can achieve very low power
Short circuit power is a component of dynamic power
dissipation, but at the expense of circuit complexity. Adiabatic
dissipation in CMOS circuits. It is caused by the flow of short
logic offers a way to reuse the energy stored in the load
circuit current between supply and ground during switching or
capacitors rather than the traditional way of discharging the
transition in signal values. Consider the inverter in Fig 2
load capacitors to the ground and wasting this energy. Power
Whenever there is a transition in the input signal, there is short
reduction is achieved by recovering the energy in the recover
duration in which the input signal is between the threshold
phase of the supply clock. f specifies the number of times the
voltages of the nmos and the pmos transistors and both
capacitor charges and discharges in a given clock period. In an
transistors are turned on. This causes short circuit current to
ideal synchronous circuit running at a clock frequency f the
flow from supply to ground and results in short circuit power
maximum rate of change of any signal will be f. Hence, the
dissipation. If symmetric fall and rise times and threshold
activity factor a will be a fraction between 0 and 1. The factor a.
voltages are assumed, the short circuit power dissipation in a
f is equal to the rate at which the capacitor CL charges and
CMOS inverter can be approximately given by the following
discharges.
equation.
Psc=K.(Vdd–2VT) 3.t.N.f
Where, K is a constant that depends on the transistor sizes and
the technology, VT is the magnitude of the threshold voltage of
the nmos and pmos transistors, t is the input rise/fall time,
N is number of transitions at inverter’s output and f is the clock
frequency.
Note that N = 2.a, where a is the activity factor. = I 2*R*T
1.4Leakage Power Dissipation = (C*Vdd/T)
Leakage power dissipation is a component of static power =(2RC/T)CVdd2
dissipation in CMOS circuits. It is caused by the presence of Thus we can say that the dissipated energy is smaller than for
leakage currents in the MOS transistors. The major sources of the conventional case if the charging time T >>2RC and can be
leakage current in CMOS circuits are made small by increasing the charging time. A portion of the
i) Subthreshold channel conduction current. energy thus stored in the capacitance can also be reclaimed by
ii) Gate Direct Tunneling Current reversing the current source direction, allowing the charge to be
iii) Reverse Biased PN-junction current. transferred from the capacitance back into the supply. Adiabatic
When a transistor is logically turned off, a non-zero leakage logic circuits thus require non-standard power supplies with
current flows through the channel. This happens when the gate time-varying voltage, also called pulsed power supplies.
voltage is below the threshold voltage. Hence, this leakage
current is known as subthreshold leakage. Gate direct tunneling
current occurs from tunneling of electrons or holes from the
bulk and source or drain overlap region through the gate oxide
potential barrier into the gate or vice-versa. The tunneling
current increases exponentially with the decrease in the oxide
thickness and with increase in the potential drop across oxide.
2. PRINCIPLE OF ADIABATIC
SWITCHING
The word ADIABATIC comes from a Greek word that is used to
describe thermodynamic processes that exchange no energy
with the environment and therefore, no energy loss in the form
of dissipated heat. The signal energies stored in the circuit
capacitances are recycled instead, of being dissipated as heat.
The adiabatic logic is also known as ENERGY RECOVERY
CMOS . Adiabatic switching can be achieved by ensuring that
Fig 3 Circuit explaining Adiabatic Switching.
the potential across the switching devices is kept arbitrarily
small. This can be achieved by charging the capacitor from a 3. ADIABATIC LOGIC CIRCUITS
time varying voltage source or constant current source as shown Practical adiabatic families can be classified as either Partially
in Fig. 3. Here, R represents the on-resistance of the pMOS adiabatic IC or fully adiabatic. In a Partially adiabatic circuits,
network. Also note that a constant charging current corresponds some charge is allowed to be transferred to the ground, while
to a linear voltage ramp. The energy dissipation in conventional in a fully adiabatic circuits, all the charge on the load
CMOS circuits is caused by the channel resistance of the capacitance is recovered by the power supply. Fully adiabatic
transistor. The dissipation through the channel resistance R is circuits face a lot of problems with respect to the operating
then: speed and the inputs power clock synchronization. Partially
Ediss = P*T Adiabatic families include the following: Efficient Charge
Recovery Logic (ECRL), Improved Efficient Charge Recovery
Logic (IECRL), 2N-2N2P Adiabatic Logic, Positive
Feedback Adiabatic Logic (PFAL), NMOS Energy Recovery
Logic (NERL), Clocked Adiabatic Logic (CAL), True Single-
Phase Adiabatic Logic (TSEL), Source-coupled Adiabatic
Logic (SCAL).
Some Fully adiabatic logic families include:
Pass transistor Adiabatic Logic (PAL). Split- Rail Charge
Recovery Logic (SCRL).

4.RESULTS

Fig 5 Adiabatic Inverter logic IECRL voltage vs time

Fig 6 Adiabatic Inverter voltage and current

Fig4 Adiabatic Inverter logic

 fig 8 shows the energy dissipation in LPAL inverter. It may be
noted that energy is being recovered after every input cycle.

Fig 9 Adiabatic Inverter logic PFAL

Fig 7 Adiabatic Inverter power dissipation from supply to output (1
uW)

Fig 8 Adiabatic
Fig10 Adiabatic Inverter logic PFAL voltage vs time
Inverter maximum current from supply to output (0.130mA). Positive Feedback Adiabatic Logic (PFAL)
Improved Efficient Charge Recovery Logic (IECRL) IECRL , PFAL [Vetu96], like IECRL, is also based around a pair of cross
improves ECRL with the addition of a pair of cross-coupled coupled inverters. However, whilst in IECRL the NMOS
NMOS devices. This produces a logic family that is based devices used to evaluate the function are connected between the
around a pair of cross-coupled inverters, a structure that is outputs and ground, in PFAL, these evaluation NMOS devices
identical to the storage elements in a Static RAM (SRAM). The are connected between the outputs and the power-clock. The
cross-coupled NMOS devices are an improvement over ECRL similarities between PFAL and IECRL gates are such that
because they provide a pulldown path to ground that remains IECRL gates can be easily converted into PFAL gates. This is
even after the charge is recovered from the gates of the done by re-labeling the outputs so that their assertion levels are
evaluation FETs. However, because of the two extra NMOS swapped, and connecting the NMOS evaluation devices
devices, it will require a larger area in which to be between the power-clock and the outputs rather than between
implemented. Fig 4 shows an inverter/buffer (also in buffer ground and the outputs. This can be made as easy to achieve in
configuration) implemented using the IECRL style. Fig. 7 and layout as it is in abstract representations of the circuit. When
the power-clock is in its recovery phase, the NMOS devices
between the outputs and the power-clock can allow complete
recovery of those outputs. This means that the low-power
performance of PFAL can be enhanced by making it fully
reversible Fig 9 and fig 10 shows an inverter/buffer
implemented in the PFAL style.

5.CONCLUSION
Power reduction is achieved by recovering the energy in the
recover phase of the supply clock. If input changes from zero
to Vdd, the voltage drops abruptly across the load capacitor
and ground through NMOS. Adiabatic logic achieves low power
by maintaining small potential differences across the transistors
while they are conducting, and allowing the charge stored in
the output load capacitors to be recycled . A power-clock
supply plays an important role in adiabatic switching. When it
ramps up or down steadily, the power-clock supply causes a
very small drop across the switching device. The power-clock
supply not only supplies the energy but also recovers it.
Adiabatic inverters are the simplest form of benchmark circuit
to demonstrate the principle of energy recovery and the
adiabatic principle.

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