AMBA

Ref: AMBA Specification Rev. 2.0

1
Outline
„ Overview
„ AHB
„ APB
„ Test methodology

SoC Design Lab Shao-Yi Chien 2

Outline
„ Overview
„ AHB
„ APB
„ Test methodology

SoC Design Lab Shao-Yi Chien 3

BUS Brief
„ In a system, various subsystems must have
interfaces to one another
„ The bus serves as a shared communication link
between subsystems
„ Advantages
… Low cost
… Versatility

„ Disadvantage
… Performance bottleneck
SoC Design Lab Shao-Yi Chien 4
AMBA Introduction
„ Advanced Microcontroller Bus Architecture
… An on-chip communication standard
„ Three buses defined
… AHB (Advanced High-performance Bus)
… ASB (Advanced System Bus)
… APB (Advanced Peripheral Bus)

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AMBA History
„ AMBA 1.0
… ASB and APB
… Tri-state implementation
„ AMBA 2.0
… AHB, ASB, and APB
… Multiplexer architecture to eliminate timing problem
„ AMBA 3.0
… AMBA Advanced eXtensible Interface (AXI)

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A Typical AMBA System
„ Processors or other masters/slaves can be
replaced

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AHB
„ High performance
„ Pipelined operation
„ Multiple bus masters (up to 16)
„ Burst transfers
„ Split transactions
„ Bus width: 8, 16, 32, 64, 128 bits
„ Mux-type bus
„ Single clock edge (rising edge) design
„ Recommended for new designs

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ASB
„ High performance
„ Pipelined operation
„ Multiple bus masters
„ Burst transfers
„ Bus width: 8, 16, 32 bits
„ Tristate-type bus
„ Falling edge design

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APB
„ Lower power
„ Latched address and control
„ Simple interface
„ Suitable for many peripherals
„ Single clock edge (rising edge) design
„ Appears as a local secondary bus that is
encapsulated as a single AHB or ASB slave
devices

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AHB Components
„ AHB master
… Initiate a read/write operation
… Only one master is allowed to use the bus
… uP, DMA, DSP, …
„ AHB slave
… Respond to a read/write operation
… Address mapping
… External memory I/F, APB bridge, internal memory, …
„ AHB arbiter
… Ensure that which master is active
… Arbitration algorithm is not defined in ABMA spec.
„ AHB decoder
… Decode the address and generate select signal to slaves
SoC Design Lab Shao-Yi Chien 11
APB Components
„ AHB2APB Bridge
… Provides latching of all address, data, and control
signals
… Provides a second level of decoding to generate
slave select signals for the APB peripherals
„ All other modules on the APB are APB slaves
… Un-pipelined
… Zero-power interface
… Timing can be provided by decode with strobe timing
… Write data valid for the whole acess

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Notes on the AMBA Specification

„ Technology independent
„ Not define electrical characteristics
„ Timing specification only at the cycle level
… Exact timing requirements will depend on the
process technology used and operation
frequency

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Outline
„ Overview
„ AHB
„ APB
„ Test methodology

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AHB Bus Interconnection
Arbiter

Decoder
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AHB Transfer Sequence Grants the bus ownership
to the master
Initiate a request
to arbiter Arbiter Address & control
broadcasted to all
Drives address slaves, only the
and control signal selected slave
response

Drive the HREADY

signal high for
Decoder completion
SoC Design Lab Shao-Yi Chien 16
AHB Signals
Name Source Description
HCLK Clock source Bus clock
HRESETn Reset controller Reset
HADDR[31:0] Master Address bus
HTRANS[1:0] Master Transfer type
HWRITE Master Transfer direction
HSIZE[2:0] Master Transfer size
HBURST[2:0] Master Burst type
HPROT[3:0] Master Protection control
HWDATA[31:0] Master Write data bus
HSELx Decoder Slave select
HRDATA[31:0] Slave Read data bus
HREADY Slave Transfer done
HRESP[1:0] Slave Transfer response (status)
SoC Design Lab Shao-Yi Chien 17
Basic AHB Signals
„ HRESETn
… Active low
„ HADDR[31:0]
… The 32-bits system address bus
„ HWDATA[31:0]
… Write data bus, from master to slave
„ HRDATA[31:0]
… Read data bus, from slave to master
SoC Design Lab Shao-Yi Chien 18
Basic AHB Signals (cont.)
„ HTRANS
… Indicates the type of the current transfer
„ NONSEQ, SEQ, IDLE, or BUSY
„ HSIZE
… Indicate the size of the transfer
„ HBURST
… Indicate the burst type of the transfer
„ HRESP
… Shows the status of bus transfer, from slave to master
„ OKAY, ERROR, RETRY, or SPLIT

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Basic AHB Signals (cont.)
„ HREADY
… High: the slave indicate the transfer done
… Low: the slave extend the transfer

„ HREADY_IN
… From decoder
… Decoder tell the slave that the bus is available
… Not explained in AMBA spec. 2.0 !!

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Basic AHB Transfers
„ Two distinct sections
… The address phase, only one cycle
… The data phase, may required several cycles,
achieved by HREADY signals
„ Pipeline transaction
… Address phase is before the data phase

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Basic AHB Transfers (cont.)
„ A simple transfer with no wait state

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Basic AHB Transfers (cont.)
„ A simple transfer with two wait states

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Basic AHB Transfers (cont.)
„ Multiple transfers

For the transfer before A For A For B For C

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Transfer Type
„ HTRANS[1:0]: transfer type
… Four types, IDLE, BUSY, NONSEQ,SEQ
„ 00 : IDLE
… Notransfers
… When master grant bus, but no transfer

„ 01 : BUSY
… Allow the master to insert IDLE cycle during
transfers
SoC Design Lab Shao-Yi Chien 25
Transfer Type (cont.)
„ 10 : NOSEQ
… Indicate a single transfer
… or the first transfer of a burst
… The address & control signals are unrelated to
the previous transfer
„ 11 : SEQ
… Indicate
the following transfers
… The address is related to the previous transfer

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Transfer Type Example

Delayed by the master Delayed by the slave

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AHB Control Signals
„ HWRITE
… High : write
… Low : read

„ HSIZE[2:0]
… 000 : 8 bits … 100 : 128 bits
… 001 : 16 bits … 101 : 256 bits
… 010 : 32 bits … 110 : 512 bits
… 011 : 64 bits … 111 : 1024 bits
… The max is constrained by the bus configuration
… 32 bits (010) is often used
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Burst Operation
„ AHB burst operations
… 4-beat, 8-beat, 16-beat, single transfer, and
undefined-length transfer
… Both incrementing & wrapping burst
„ Incrementing burst
… Sequential,the address is just the increment of the
previous one
„ Wrapping burst
… Ifthe start address is not aligned (size x beats), the
address will wrap when the boundary is reached
… Ex: 4-beat warping burst of word (4-byte):
0x34Æ0x38Æ0x3CÆ0x30
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 Address Calculation Example
„ The address calculation is according to HSIZE and HBURST
„ Example: HSIZE = 010 (32 bits) with starting address = 0x48
HBURST Type Address
000 SINGLE 0x48
001 INCR 0x48, 0x4C, 0x50,… The most useful
010 WRAP4 0x48, 0x4C, 0x40, 0x44
011 INCR4 0x48, 0x4C, 0x50, 0x54
100 WRAP8 0x48, 0x4C, 0x50, 0x54, 0x58, 0x5c, 0x40, 0x44
101 INCR8 0x48, 0x4C, 0x50, 0x54, 0x58, 0x5c, 0x60, 0x64
110 WRAP16 0x48, 0x4C,…, 0x7c, 0x40, 0x44
111 INCR16 0x48, 0x4C,…, 0x7c, 0x80, 0x84
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Important!!
„ Burst transfer can’t cross the 1K boundary
… Because the minimal address range for a
slave is 1 KB
… NONSEQ → SEQ → 1KB Boundary →
NONSEQ → SEQ…
„ The master do not attempt to start a fixed-
length incrementing burst which would
cause this boundary to be crossed

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Example: 4-Beat Wrapping Burst

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Example: 4-Beat Incrementing
Burst

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Example: Undefined-Length Burst
Start a new burst

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Address Decoding
„ HSELx : slave select
… Indicate the slave is selected by a master
„ A central address decoder is used to
provide the select signal
„ A slave should occupy at least 1KB of
memory space
„ An additional default slave is used to fill up
the memory map
SoC Design Lab Shao-Yi Chien 35
Address Decoding (cont.)

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Slave Response
„ The slave accessed must respond the
transfer
„ The slave may
… Complete the transfer
… Insert wait state
… Signal an error to indicate the transfer failure
… Delay the transfer, leave the bus available for
other transfer (split)
SoC Design Lab Shao-Yi Chien 37
Slave Response Signals
„ HREADY : transfer done
„ HRESP[1:0] : transfer response
„ 00 : OKAY
… Successful
„ 01 : ERROR
… Error
„ 10 : RETRY
… The transfer is not completed
… Ask the master to perform a retry transfer

„ 11 : SPLIT
… The transfer is not completed
… Ask the master to perform a split transfer
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Two-cycle Response
„ HRESP[1:0]
… OKAY: single cycle response
… ERROR : two-cycle response
… RETRY : two-cycle response
… SPLIT : two-cycle response

„ Two-cycle response is required because

of the pipeline nature of the bus. This
allows sufficient time for the master to
handle the next transfer
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Retry Response Example

1st 2nd
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ERROR Response Example
„ An error response which needs three cycles

Additional cycle
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Different Between Retry and Split

„ The major difference is the way of arbitration

… RETRY: the arbiter will continue to use the normal
priority
… SPLIT: the arbiter will adjust the priority scheme so
that any other master requesting the bus will get
access
„ Requires extra complexity in both the slave and the arbiter
„ A bus master should treat RETRY and SPLIT in
the same manner

SoC Design Lab Shao-Yi Chien 42

Data Bus
„ Non-tri-state, separate read & write buses
„ Endianness
… Not specified in the AMBA spec.
… All the masters and slaves should of the same
endianness
… Dynamic endianness is not supported

„ For IP design, only IPs which will be used in

wide variety of applications should be made bi-
endian

SoC Design Lab Shao-Yi Chien 43

Active Bytes Lanes for a 32-bit
Little-Endian Data Bus

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Active Bytes Lanes for a 32-bit Big-
Endian Data Bus

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AHB Arbitration Signals
Name Source Description

HBUSREQx Master Bus request

HLOCKx Master Locked transfers

HGRANTx Arbiter Bus grant

HMASTER[3:0] Arbiter Master number

HMASTLOCK Arbiter Locked sequence

HSPLITx[15:0] Slave (SPLIT- Split completion request

capable)

SoC Design Lab Shao-Yi Chien 46

Arbitration Signals (cont.)
„ HBUSREQ
… Bus request
„ HLOCKx :
… High: the master requires locked access to the
bus
„ HGRANTx
… Indicatethe master x accessible to the bus
… Master x gains ownership: HGRANTx=1 &
HREADY=1

SoC Design Lab Shao-Yi Chien 47

Arbitration Signals (cont.)
„ HMASTER[3:0]
… Indicate which master is transferring, information
for splitting
„ HMASTLOCK
… Indicate the master is performing a locked transfer

„ HSPLITx[15:0]
… Used by the slave to indicate the arbiter which
master should be allowed to re-attempt a split
transaction
… Each bit corresponds to a single master

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Arbitration Example (1)
„ Granting access with no wait state

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Arbitration Example (2)
„ Granting access with wait states

Get grant!
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Arbitration Example (3)
„ Handover after burst

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Bus Master Grant Signals

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Notes
„ For a fixed length burst, it is not necessary to
continue request the bus
„ For a undefined length burst, the master should
continue to assert the request until it has started
the last transfer
„ If no master requests the bus, grant to the
default master with HTRANS=IDLE
„ It is recommended that the master inserts an
IDLE transfer after any locked sequence to
provide the opportunity for changing arbitration
SoC Design Lab Shao-Yi Chien 53
Split Transfer Sequence
„ The master starts the transfer.
„ If the slave decides that it may take a number of cycles
to obtain the data, it gives a SPLIT transfer response.
The slave record the master number, HMASTER.
Then the arbiter change the priority of the masters.
„ The arbiter grants other masters, bus master handover.
„ When the slave is ready to complete the transfer, it
asserts the appropriate bit of the HSPLITx bus to the
arbiter.
„ The arbiter restores the priority
„ The arbiter will grant the master so it can re-attempt the
transfer
„ Finish
SoC Design Lab Shao-Yi Chien 54
Preventing Deadlock
„ It is possible for deadlock if a number of different
masters attempt to access a slave which issues SPLIT
or RETRY

„ The slave can withstand a request from every master

in the system, up to a maximum of 16. It only needs to
record the master number. (can ignore address and
control)
„ A slave which issues RETRY responses must only
be accessed by one master at a time.
… Some hardware protection mechanisms, such as ERROR
message, can be used.

SoC Design Lab Shao-Yi Chien 55

AHB Master Interface

SoC Design Lab Shao-Yi Chien 56

AHB Slave Interface
HREADY_IN

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AHB Arbiter

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AHB Decoder

SoC Design Lab Shao-Yi Chien 59

Review on AHB
„ Main components
… Master, slaves, arbiter, decoder
„ How the transfer progress
… The pipelined scheme
„ How to increase the performance
… Burst read/write
„ Arbitration
… Bus ownership handover
SoC Design Lab Shao-Yi Chien 60
Implementation
„ Both master port & slave port in your design
… Read/write data via master port
… Configured by the others via slave port
… Such as some parameters set by the processor

Master Slave
Wrapper

Design

SoC Design Lab Shao-Yi Chien 61

Outline
„ Overview
„ AHB
„ APB
„ Test methodology

SoC Design Lab Shao-Yi Chien 62

APB Signals
Name Description
PCLK Bus clock
PRESETn APB reset
PADDR[31:0] APB address bus
PSELx APB select
PENABLE APB strobe
PWRITE APB transfer direction
PRDATA APB read data bus
PWDATA APB write data bus

SoC Design Lab Shao-Yi Chien 63

APB Signals (cont.)
„ PADDR[31:0]
… Address bus, driven by the peripheral bus bridge unit
„ PSELx
… A signal from the secondary decoder to each peripheral bus
slave x
„ PENABLE
… Used to time all accesses on the peripheral bus
„ PWRITE
… High: write
… Low: read
„ PRDATA and PWDATA
… Up to 32-bits wide

SoC Design Lab Shao-Yi Chien 64

Stage Diagram
„ SETUP and
ENABLE state: last
for only one cycle

SoC Design Lab Shao-Yi Chien 65

 Write Transfer
SETUP ENABLE
cycle cycle

Require or
clean Write! Write!
transition

The glitch is acceptable

SoC Design Lab Shao-Yi Chien 66
Read Transfer
SETUP ENABLE
cycle cycle

Read!

SoC Design Lab Shao-Yi Chien 67

APB Bridge

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APB Slave

SoC Design Lab Shao-Yi Chien 69

Interfacing APB to AHB – Read

PRDATA can be directly routed back to HRDATA,

or registering the read data at the end of enable cycle then drive back
allows the AHB to run at a higher clock
SoC Design Lab Shao-Yi Chien 70
Interfacing APB to AHB – Write

The first write transfer can occur with zero wait stages

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Interfacing APB to AHB – Back to
Back Transfers

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Outline
„ Overview
„ AHB
„ APB
„ Test methodology

SoC Design Lab Shao-Yi Chien 73

AMBA Test Interface
„ With the test interface, each module can
be tested only using transfers from the bus

AHB

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AMBA Test Interface

SoC Design Lab Shao-Yi Chien 75

Signals for Test Interface
„ TCLK
… Test clock
… Assigned HCLK during test mode
„ TREQA
… Test burst request A, is required as a dedicated device pin
… Used to request entry into the test mode
„ TREQB
… TREQA/TREQA can indicate the type of test vector
„ TACK
… Test acknowledge, required as a dedicated device pin
… TREQA and TREQB signals are only sampled by the TIC when
TACK is HIGH

SoC Design Lab Shao-Yi Chien 76

Control Signals
„ During normal operation

TREQA TREQB TACK Description

0 0 0 Normal operation

1 0 0 Enter test mode request

0 1 0 Reserved

- - 1 Test mode entered

SoC Design Lab Shao-Yi Chien 77

Control Signals
„ During test operation
TREQA TREQB TACK Description

- - 0 Current access incomplete

1 1 1 Address vector, control

vector, or turnaround vector
(to switch the direction of
TBUS)
1 0 1 Write vector

0 1 1 Read vector

0 0 1 Exit test mode

SoC Design Lab Shao-Yi Chien 78

How to Distinguish Address,
Control, and Turnaround Vectors?
„ Single address/control vector is address
vector
„ Burst of address/control vectors are all
address vectors, but the last one is
control vector
„ A read vector, or burst of read vectors, is
always followed by a turnaround vector
(AHB requires two turnaround vectors)

SoC Design Lab Shao-Yi Chien 79

Incremental Addressing
„ The TIC may support incrementing of the
bus address
„ A typical implementation would use an 8-
bit address incrementer, up to 1kB
boundary
„ Only supports undefined-length transfer

SoC Design Lab Shao-Yi Chien 80

Control Vector
Bit
Position
Description „ HSIZE[2]=0: only
0 Control vector valid (valid: 1) support 8, 16, 32-
1 Reserved bit
2 HSIZE[0] „ Use HLOCK signal
3 HSIZE[1]
carefully, it may
4 HLOCK
5 HPROT[0]
lock up the bus
6 HPROT[1]
7 Address increment enable
8 Reserved
9 HPROT[2]
10 HPROT[3]
SoC Design Lab Shao-Yi Chien 81
FSM of TIC
The first vector is address

Turnaround vectors
SoC Design Lab Shao-Yi Chien 82
Enter Test Mode

Enter test mode

HCLKÅTCLK

SoC Design Lab Shao-Yi Chien 83

Write Test Vectors

Write

Pipelined

Wait

SoC Design Lab Shao-Yi Chien 84

Read Test Vectors

Tri-state Tri-state

Wait

LASTREAD
TURNAROUND
There must be a tri-state
after address and read vector
SoC Design Lab Shao-Yi Chien 85
Control Vector

SoC Design Lab Shao-Yi Chien 86

Read-to-Write and Write-to-Read

Read Write

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Other Topics
„ AHB-Lite
„ Multi-layer AHB

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AHB-Lite
„ AHB-Lite
…A subset of the full AHB specification
… Only one single bus master used
… No need of the request/grant protocol to the
arbiter
… No arbiter
… No Retry/Split response from slaves
… No master-to-slave multiplexor

SoC Design Lab Shao-Yi Chien 89

AHB-Lite Interchangeability
Component Full AHB system AHB-Lite
system
Full AHB master ok ok
AHB-Lite master Need standard AHB ok
master wrapper

AHB slave (no ok ok

Retry/Split)
AHB slave with ok Need standard
Retry/Split AHB slave wrapper

SoC Design Lab Shao-Yi Chien 90

AHB-Lite Block Diagram

SoC Design Lab Shao-Yi Chien 91

Multi-layer AHB
„ Multi-layer AHB
… Enables parallel access paths between multiple
masters and slaves by an interconnection matrix
… Increase the overall bus bandwidth
… More flexible system architecture
„ Make slaves local to a particular layer
„ Make multiple slaves appear as a single slave to the
interconnection matrix
„ Multiple masters on a single layer

SoC Design Lab Shao-Yi Chien 92

Multi-layer AHB
„ A simple multi-layer system

SoC Design Lab Shao-Yi Chien 93

Multi-layer AHB
„ Local slaves
… Slave#4 and Slave #5 can only be accessed by
Master #2

SoC Design Lab Shao-Yi Chien 94

Multi-layer AHB
„ Multiple slaves on
one slave port
… Combine low-bandwidth
slaves together
… Combine salves usually
accessed by the same
master together

SoC Design Lab Shao-Yi Chien 95

Multi-layer AHB
„ Multiple masters on
one layer
… Combine masters which
have low-bandwidth
requirements together
… Combine special masters
together

SoC Design Lab Shao-Yi Chien 96

Communications
between Different IPs

97
Communications
„ CPU (master) ÅÆ IP (slave)
„ IP (master) ÅÆ IP (slave)

SoC Design Lab Shao-Yi Chien 98

Memory Mapped I/O
„ Each slave occupies a range of (>1KB)
address space in the system
„ All the slaves are addressable
„ Memory mapped register/memory
„ CPU/IP and read/write data to other IP as
read/write data from/to memory

SoC Design Lab Shao-Yi Chien 99

Communication between IPs
„ After the master is granted by the arbiter, it
can access all the slaves on the bus
Slave 1
Master 1 (0x10000
–0x20000)
0x32000
Slave 3 0x31000 Write(address, data)
Slave 2 0x30000
Read(address, data)
Slave 2
Master 2 (0x30000
–0x31000) Ex:
Write(0x30020, 0x0)
0x20000
Read(0x30100, &temp)
Slave 3 Slave 1
Master 3 (0x31000
–0x32000)
0x10000

SoC Design Lab Shao-Yi Chien 100

An IP Can Have Both Mater and
Slave I/F

Master Slave

Slave Master

SoC Design Lab Shao-Yi Chien 101

Communication between CPU and
IP
„ CPU is always the master Slave 1
CPU (0x10000
„ The IP is always the –0x20000)
slave
„ The IP can initiate the Interrupt
feedback with interrupt Slave 2
(0x30000
„ After interrupt, the CPU –0x31000)

enters interrupt mode, Interrupt Interrupt

Controller
and the interrupt is
handled with interrupt Slave 3
(0x31000
service routine (ISR) –0x32000)

SoC Design Lab Shao-Yi Chien 102

Example: DMA
Address Function
0x00 1: start, 0:
DMA
CPU INT (0x30000–
stop
0x31000) 0x04 Status.
M M M S
0: ready;
1: busy
0x08 Source
S S address
Memory 1 Memory 2
(0x10000– (0x20000– 0x0C Destination
0x20000) 0x30000)
address
0x10 Size

SoC Design Lab Shao-Yi Chien 103

Example: DMA
„ Step 0: CPU check the
status of DMA to make
sure it is ready to be
used
… While(1)
… {
… Read(0x30004, &status)
… if(status == 0)
… break;
… }

SoC Design Lab Shao-Yi Chien 104

Example: DMA
„ Step 1: CPU sets the
(source address),
(destination address),
and (size) with the slave
I/F
… Write(0x30008, 0x10000)
… Write(0x3000C, 0x20000)
… Write(0x30010, 0x100)
„ Step 2: starts DMA
… Write(0x30000, 0x1)

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Example: DMA

„ Step 3: DMA moves

data from memory 1
to memory 2 with the
two master I/F

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Example: DMA

„ Step 4: DMA
interrupts CPU
„ Step 5: CPU checks
the status of DMA
… Read(0x30004, &status)

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