rl78 I1c

User’s Manual
RL78/I1C
16 User’s Manual: Hardware
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com Rev. 2.00 Aug 2018

Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits,
software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and
damages incurred by you or third parties arising from the use of these circuits, software, or information.
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information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and
application examples.
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(Rev.4.0-1 November 2017)

NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers This manual is intended for user engineers who wish to understand the functions of the
RL78/I1C and design and develop application systems and programs for these devices.
The target products are as follows.
● 64-pin: R5F10NLG, R5F10NLE

● 80-pin: R5F10NMJ, R5F10NMG, R5F10NME
● 100-pin: R5F10NPJ, R5F10NPG
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The RL78/I1C manual is separated into two parts: this manual and the software edition
(common to the RL78 Family).
RL78/I1C RL78 Microcontroller

User’s Manual User’s Manual
Hardware Software
● Pin functions ● CPU functions

● Internal block functions ● Instruction set
● Interrupts ● Explanation of each instruction
● Other on-chip peripheral functions
● Electrical specifications
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
● To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in the
PDF file and specifying it in the “Find what:” field.
● How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
● To know details of the RL78/I1C Microcontroller instructions:
→ Refer to the separate document RL78 Family Software User’s Manual
(R01US0015E).
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary ...×××× or ××××B
Decimal ...××××
Hexadecimal ...××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices

Document Name Document No.
RL78/I1C User’s Manual Hardware This manual

RL78 Family Software User’s Manual R01US0015E
Documents Related to Flash Memory Programming

PG-FP5 Flash Memory Programmer User’s Manual –

RL78, 78K, V850, RX100, RX200, RX600 (Except RX64x), R8C, SH R20UT2923E
Common R20UT2922E
Setup Manual R20UT0930E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
RENESAS MICROCOMPUTER RL78 FAMILY R01CP0003E

Semiconductor Package Mount Manual R50ZZ0003E
Semiconductor Reliability Handbook R51ZZ0001E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features ........................................................................................................................................... 1

1.2 List of Part Numbers ...................................................................................................................... 5
1.3 Pin Configuration (Top View) ........................................................................................................ 6
1.3.1 64-pin products ................................................................................................................................. 6
1.3.2 80-pin products ................................................................................................................................. 7
1.3.3 100-pin products ............................................................................................................................... 8
1.4 Pin Identification............................................................................................................................. 9
1.5 Block Diagram .............................................................................................................................. 10
1.5.1 64-pin products ............................................................................................................................... 10
1.5.2 80-pin products ............................................................................................................................... 11
1.5.3 100-pin products ............................................................................................................................. 12
1.6 Outline of Functions..................................................................................................................... 13
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 16
2.1 Port Function ................................................................................................................................ 16

2.1.1 64-pin products ............................................................................................................................... 17
2.1.2 80-pin products ............................................................................................................................... 19
2.1.3 100-pin products ............................................................................................................................. 22
2.2 Functions Other than Port Pins .................................................................................................. 25
2.2.1 With functions for each product ...................................................................................................... 25
2.2.2 Description of Functions ................................................................................................................. 27
2.3 Connection of Unused Pins ........................................................................................................ 30
2.4 Block Diagrams of Pins ............................................................................................................... 32
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 46
3.1 Memory Space .............................................................................................................................. 46

3.1.1 Internal program memory space ..................................................................................................... 53
3.1.2 Mirror area ...................................................................................................................................... 56
3.1.3 Internal data memory space ........................................................................................................... 58
3.1.4 Special function register (SFR) area ............................................................................................... 58
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 58
3.1.6 Data memory addressing ................................................................................................................ 59
3.2 Processor Registers..................................................................................................................... 60
3.2.1 Control registers ............................................................................................................................. 60
3.2.2 General-purpose registers .............................................................................................................. 62
3.2.3 ES and CS registers ....................................................................................................................... 63
3.2.4 Special function registers (SFRs) ................................................................................................... 64
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 69
Index-1
3.3 Instruction Address Addressing................................................................................................. 81
3.3.1 Relative addressing ........................................................................................................................ 81
3.3.2 Immediate addressing .................................................................................................................... 81
3.3.3 Table indirect addressing ................................................................................................................ 82
3.3.4 Register direct addressing .............................................................................................................. 82
3.4 Addressing for Processing Data Addresses ............................................................................. 83
3.4.1 Implied addressing.......................................................................................................................... 83
3.4.2 Register addressing ........................................................................................................................ 83
3.4.3 Direct addressing ............................................................................................................................ 84
3.4.4 Short direct addressing ................................................................................................................... 85
3.4.5 SFR addressing .............................................................................................................................. 86
3.4.6 Register indirect addressing ........................................................................................................... 87
3.4.7 Based addressing ........................................................................................................................... 88
3.4.8 Based indexed addressing ............................................................................................................. 92
3.4.9 Stack addressing ............................................................................................................................ 93
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 97
4.1 Port Functions .............................................................................................................................. 97

4.2 Port Configuration ........................................................................................................................ 97
4.2.1 Port 0 .............................................................................................................................................. 98
4.2.2 Port 1 .............................................................................................................................................. 98
4.2.3 Port 2 .............................................................................................................................................. 99
4.2.4 Port 3 .............................................................................................................................................. 99
4.2.5 Port 4 .............................................................................................................................................. 99
4.2.6 Port 5 ............................................................................................................................................ 100
4.2.7 Port 6 ............................................................................................................................................ 100
4.2.8 Port 7 ............................................................................................................................................ 100
4.2.9 Port 8 ............................................................................................................................................ 100
4.2.10 Port 12 ........................................................................................................................................ 101
4.2.11 Port 13 ........................................................................................................................................ 101
4.2.12 Port 15 ........................................................................................................................................ 101
4.3 Registers Controlling Port Function ........................................................................................ 102
4.3.1 Port mode registers (PMxx) .......................................................................................................... 106
4.3.2 Port registers (Pxx) ....................................................................................................................... 107
4.3.3 Pull-up resistor option registers (PUxx) ........................................................................................ 108
4.3.4 Port input mode registers (PIMxx) ................................................................................................ 109
4.3.5 Port output mode registers (POMxx) ............................................................................................ 110
4.3.6 A/D port configuration register (ADPC) ......................................................................................... 111
4.3.7 Global digital input disable register (GDIDIS) ............................................................................... 112
4.3.8 Peripheral I/O redirection register (PIOR0) ................................................................................... 113
4.3.9 LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)............................................................. 114
Index-2
4.3.10 LCD input switch control register (ISCLCD) ................................................................................ 117
4.4 Port Function Operations .......................................................................................................... 118
4.4.1 Writing to I/O port.......................................................................................................................... 118
4.4.2 Reading from I/O port ................................................................................................................... 118
4.4.3 Operations on I/O port .................................................................................................................. 118
4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) ..................................... 119
4.4.5 Handling different potential (1.8 V, 2.5 V, 3 V) by using I/O buffers .............................................. 119
4.5 Register Settings When Using Alternate Function ................................................................. 121
4.5.1 Basic concept when using alternate function ................................................................................ 121
4.5.2 Register settings for alternate function whose output function is not used ................................... 122
4.5.3 Register setting examples for used port and alternate functions .................................................. 123
4.5.4 Operation of ports that alternately function as SEGxx pins ........................................................... 132
4.5.5 Operation of ports that alternately function as VL3, CAPL, CAPH pins ......................................... 133
4.6 Cautions When Using Port Function ........................................................................................ 135
4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) ................................................ 135
4.6.2 Notes on specifying the pin settings ............................................................................................. 136
CHAPTER 5 OPERATION STATE CONTROL ................................................................................... 137
5.1 Configuration of Operation State Control ................................................................................ 137

5.2 Registers Controlling Operation State Control ....................................................................... 139
5.2.1 Flash operating mode select register (FLMODE).......................................................................... 139
5.2.2 Flash operating mode protect register (FLMWRP) ....................................................................... 141
5.2.3 Regulator mode control register (PMMC) ..................................................................................... 141
5.3 Initial Setting of Flash Operation Modes.................................................................................. 142
5.4 Transitions between Flash Operation Modes .......................................................................... 143
5.5 Details of Flash Operation Modes ............................................................................................ 144
5.5.1 Details of HS (high-speed main) mode ......................................................................................... 144
5.5.2 Details of LS (low-speed main) mode ........................................................................................... 145
5.5.3 Details of LP (low-power main) mode ........................................................................................... 146
5.5.4 Details on LV (low-voltage main) mode ........................................................................................ 147
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 148
6.1 Functions of Clock Generator ................................................................................................... 148

6.2 Configuration of Clock Generator ............................................................................................ 151
6.3 Registers Controlling Clock Generator .................................................................................... 153
6.3.1 Clock operation mode control register (CMC) ............................................................................... 153
6.3.2 System clock control register (CKC) ............................................................................................. 155
6.3.3 Clock operation status control register (CSC) ............................................................................... 157
6.3.4 Sub clock operation mode control register (SCMC) ...................................................................... 159
6.3.5 Sub clock operation status control register (SCSC) ...................................................................... 161
6.3.6 Oscillation stabilization time counter status register (OSTC) ........................................................ 161
Index-3
6.3.7 Oscillation stabilization time select register (OSTS) ..................................................................... 163
6.3.8 Subsystem clock select register (CKSEL) .................................................................................... 165
6.3.9 Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2) ............................................................. 166
6.3.10 Subsystem clock supply option control register (OSMC) ............................................................ 171
6.3.11 High-speed on-chip oscillator frequency select register (HOCODIV).......................................... 173
6.3.12 Middle-speed on-chip oscillator frequency select register (MOCODIV) ...................................... 174
6.3.13 Frequency measurement clock select register (FMCKS)............................................................ 175
6.3.14 PLL control register (DSCCTL) ................................................................................................... 176
6.3.15 Main clock control register (MCKC) ............................................................................................ 177
6.3.16 Peripheral clock control register (PCKC) .................................................................................... 178
6.4 System Clock Oscillator ............................................................................................................ 179
6.4.1 X1 oscillator .................................................................................................................................. 179
6.4.2 XT1 oscillator ................................................................................................................................ 179
6.4.3 High-speed on-chip oscillator........................................................................................................ 183
6.4.4 Middle-speed on-chip oscillator .................................................................................................... 183
6.4.5 Low-speed on-chip oscillator ........................................................................................................ 183
6.4.6 Phase-locked loop (PLL) .............................................................................................................. 183
6.5 Clock Generator Operation........................................................................................................ 184
6.6 Controlling Clock........................................................................................................................ 186
6.6.1 Example of setting high-speed on-chip oscillator .......................................................................... 186
6.6.2 Example of setting X1 oscillation clock ......................................................................................... 188
6.6.3 Example of setting XT1 oscillation clock ....................................................................................... 190
6.6.4 Procedure for settings when the XT1 oscillator is not to be used as the CPU/peripheral
hardware clock ........................................................................................................................... 191
6.6.5 CPU clock status transition diagram ............................................................................................. 192
6.6.6 Condition before changing CPU clock and processing after changing CPU clock ........................ 198
6.6.7 Time required for switchover of CPU clock and main system clock .............................................. 204
6.6.8 Conditions before clock oscillation is stopped .............................................................................. 206
6.7 Resonator and Oscillator Constants ........................................................................................ 207
CHAPTER 7 HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION

FUNCTION ........................................................................................................................ 208
7.1 High-speed On-chip Oscillator Clock Frequency Correction Function ................................ 208
7.2 Register ....................................................................................................................................... 209
7.2.1 High-speed on-chip oscillator clock frequency correction control register (HOCOFC).................. 209
7.3 Operation ..................................................................................................................................... 210
7.3.1 Operation overview ....................................................................................................................... 210
7.3.2 Operation procedure ..................................................................................................................... 213
7.4 Usage Notes ................................................................................................................................ 214
7.4.1 SFR access .................................................................................................................................. 214
7.4.2 Operation during standby state ..................................................................................................... 214
Index-4
7.4.3 Changing high-speed on-chip oscillator frequency select register (HOCODIV) ............................ 214
CHAPTER 8 TIMER ARRAY UNIT ...................................................................................................... 215
8.1 Functions of Timer Array Unit ................................................................................................... 216

8.1.1 Independent channel operation function ....................................................................................... 216
8.1.2 Simultaneous channel operation function ..................................................................................... 217
8.1.3 8-bit timer operation function (channels 1 and 3 only) .................................................................. 218
8.1.4 LIN-bus supporting function (channel 7 only) ............................................................................... 219
8.2 Configuration of Timer Array Unit ............................................................................................ 220
8.2.1 Timer count register mn (TCRmn) ................................................................................................ 225
8.2.2 Timer data register mn (TDRmn) .................................................................................................. 227
8.3 Registers Controlling Timer Array Unit.................................................................................... 228
8.3.1 Peripheral enable register 0 (PER0) ............................................................................................. 229
8.3.2 Peripheral reset control register 0 (PRR0) .................................................................................... 230
8.3.3 Timer clock select register m (TPSm) ........................................................................................... 231
8.3.4 Timer mode register mn (TMRmn)................................................................................................ 234
8.3.5 Timer status register mn (TSRmn)................................................................................................ 239
8.3.6 Timer channel enable status register m (TEm) ............................................................................. 240
8.3.7 Timer channel start register m (TSm) ........................................................................................... 241
8.3.8 Timer channel stop register m (TTm)............................................................................................ 242
8.3.9 Timer input select register 0 (TIS0)............................................................................................... 243
8.3.10 Timer output enable register m (TOEm) ..................................................................................... 244
8.3.11 Timer output register m (TOm) ................................................................................................... 245
8.3.12 Timer output level register m (TOLm) ......................................................................................... 246
8.3.13 Timer output mode register m (TOMm) ...................................................................................... 247
8.3.14 Input switch control register (ISC) ............................................................................................... 248
8.3.15 Noise filter enable register 1 (NFEN1) ........................................................................................ 249
8.3.16 Registers controlling port functions of pins to be used for timer I/O ............................................ 251
8.4 Basic Rules of Timer Array Unit ............................................................................................... 252
8.4.1 Basic rules of simultaneous channel operation function ............................................................... 252
8.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................................ 254
8.5 Operation of Counter ................................................................................................................. 255
8.5.1 Count clock (fTCLK) ........................................................................................................................ 255
8.5.2 Start timing of counter................................................................................................................... 257
8.5.3 Operation of counter ..................................................................................................................... 258
8.6 Channel Output (TOmn Pin) Control ........................................................................................ 263
8.6.1 TOmn pin output circuit configuration ........................................................................................... 263
8.6.2 TOmn pin output setting ............................................................................................................... 264
8.6.3 Cautions on channel output operation .......................................................................................... 265
8.6.4 Collective manipulation of TOmn bit ............................................................................................. 270
8.6.5 Timer Interrupt and TOmn pin output at operation start ................................................................ 271
Index-5
8.7 Timer Input (TImn) Control ........................................................................................................ 272
8.7.1 TImn input circuit configuration ..................................................................................................... 272
8.7.2 Noise filter ..................................................................................................................................... 272
8.7.3 Cautions on channel input operation ............................................................................................ 273
8.8 Independent Channel Operation Function of Timer Array Unit ............................................. 274
8.8.1 Operation as interval timer/square wave output ........................................................................... 274
8.8.2 Operation as external event counter ............................................................................................. 280
8.8.3 Operation as input pulse interval measurement ........................................................................... 285
8.8.4 Operation as input signal high-/low-level width measurement ...................................................... 289
8.8.5 Operation as delay counter ........................................................................................................... 293
8.9 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 298
8.9.1 Operation as one-shot pulse output function ................................................................................ 298
8.9.2 Operation as PWM function .......................................................................................................... 305
8.9.3 Operation as multiple PWM output function .................................................................................. 312
8.10 Cautions When Using Timer Array Unit ................................................................................. 320
8.10.1 Cautions when using timer output............................................................................................... 320
CHAPTER 9 REALTIME CLOCK WITH INDEPENDENT POWER SUPPLY.................................. 321
9.1 Overview ...................................................................................................................................... 321

9.2 Register Descriptions ................................................................................................................ 324
9.2.1 Peripheral enable register 2 (PER2) ............................................................................................. 327
9.2.2 64-Hz counter (R64CNT) .............................................................................................................. 328
9.2.3 Second counter (RSECCNT)/binary counter 0 (BCNT0) .............................................................. 329
9.2.4 Minute counter (RMINCNT)/binary counter 1 (BCNT1) ................................................................ 330
9.2.5 Hour counter (RHRCNT)/binary counter 2 (BCNT2) ..................................................................... 331
9.2.6 Day-of-week counter (RWKCNT)/binary counter 3 (BCNT3) ........................................................ 332
9.2.7 Date counter (RDAYCNT) ............................................................................................................ 333
9.2.8 Month counter (RMONCNT) ......................................................................................................... 334
9.2.9 Year counter (RYRCNT) ............................................................................................................... 334
9.2.10 Second alarm register (RSECAR)/binary counter 0 alarm register (BCNT0AR) ......................... 335
9.2.11 Minute alarm register (RMINAR)/binary counter 1 alarm register (BCNT1AR) ........................... 336
9.2.12 Hour alarm register (RHRAR)/binary counter 2 alarm register (BCNT2AR) ............................... 337
9.2.13 Day-of-week alarm register (RWKAR)/binary counter 3 alarm register (BCNT3AR)................... 338
9.2.14 Date alarm register (RDAYAR)/binary counter 0 alarm enable register (BCNT0AER) ............... 339
9.2.15 Month alarm register (RMONAR)/binary counter 1 alarm enable register (BCNT1AER) ............ 340
9.2.16 Year alarm register (RYRAR)/binary counter 2 alarm enable register (BCNT2AER) .................. 341
9.2.17 Year alarm enable register (RYRAREN)/binary counter 3 alarm enable register
(BCNT3AER) .............................................................................................................................. 342
9.2.18 RTC control register 1 (RCR1).................................................................................................... 343
Index-6
9.2.23 RCR5 guard register (RCR5GD) ................................................................................................ 351
9.2.24 Time error adjustment register (RADJ) ....................................................................................... 351
9.2.25 Time capture control register y (RTCCRy) (y = 0 to 2) ............................................................... 352
9.2.26 Second capture register y (RSECCPy) (y = 0 to 2)/BCNT0 capture register y (BCNT0CPy)
(y = 0 to 2) .................................................................................................................................. 354
9.2.27 Minute capture register y (RMINCPy) (y = 0 to 2)/BCNT1 capture register y (BCNT1CPy)
(y = 0 to 2) .................................................................................................................................. 355
9.2.28 Hour capture register y (RHRCPy) (y = 0 to 2)/BCNT2 capture register y (BCNT2CPy)
(y = 0 to 2) .................................................................................................................................. 356
9.2.29 Date capture register y (RDAYCPy) (y = 0 to 2)/BCNT3 capture register y (BCNT3CPy)
(y = 0 to 2) .................................................................................................................................. 357
9.2.30 Month capture register y (RMONCPy) (y = 0 to 2) ...................................................................... 358
9.2.31 RTC status register (RSR) .......................................................................................................... 359
9.2.32 Sub clock operation mode control register (SCMC) .................................................................... 361
9.2.33 Sub clock operation status control register (SCSC) .................................................................... 363
9.2.34 RTC power-on-reset status register (RTCPORSR) .................................................................... 364
9.2.35 Time capture event input noise filter enable register (RTCICNFEN) .......................................... 365
9.3 Operation .................................................................................................................................. 366
9.3.1 Outline of initial settings of registers after power on ..................................................................... 366
9.3.2 Initialization procedure .................................................................................................................. 367
9.3.3 Clock and count mode setting procedure ..................................................................................... 368
9.3.4 Setting the time procedure ............................................................................................................ 369
9.3.5 30-second adjustment procedure ................................................................................................. 370
9.3.6 Reading 64-Hz counter and time .................................................................................................. 371
9.3.7 Alarm function ............................................................................................................................... 372
9.3.8 Procedure for disabling alarm interrupt ......................................................................................... 373
9.3.9 Time error adjustment function ..................................................................................................... 373
9.3.9.1 Automatic adjustment.................................................................................................. 374
9.3.9.2 Adjustment by software ............................................................................................... 375
9.3.9.3 Procedure for changing the mode of adjustment ........................................................ 375
9.3.9.4 Procedure for stopping adjustment ............................................................................. 375
9.3.9.5 Time capture function.................................................................................................. 376
9.3.10 Noise filter operation for RTCICn pin (n = 0 to 2)........................................................................ 377
9.4 Interrupt Sources........................................................................................................................ 378
9.5 Event Link Output....................................................................................................................... 380
9.5.1 Interrupt handling and event linking .............................................................................................. 380
9.6 Usage Notes ................................................................................................................................ 381
9.6.1 Register writing during counting.................................................................................................... 381
9.6.2 Use of periodic interrupts .............................................................................................................. 381
9.6.3 RTCOUT (1-Hz/64-Hz) clock output ............................................................................................. 381
Index-7
9.6.4 Notes when writing to and reading from registers ......................................................................... 382
9.6.5 Changing the count mode ............................................................................................................. 382
9.6.6 Stop procedure ............................................................................................................................. 383
9.6.7 Caution of shortwave detection function ....................................................................................... 383
CHAPTER 10 FREQUENCY MEASURE CIRCUIT ............................................................................. 384
10.1 Frequency Measurement Circuit............................................................................................. 384

10.2 Configuration of Frequency Measurement Circuit ............................................................... 384
10.3 Registers Controlling Frequency Measurement Circuit ....................................................... 385
10.3.1 Peripheral enable register 1 (PER1) ........................................................................................... 386
10.3.3 Frequency measurement count register L (FMCRL)................................................................... 388
10.3.4 Frequency measurement count register H (FMCRH) ................................................................. 388
10.3.5 Frequency measurement control register (FMCTL) .................................................................... 389
10.3.6 Frequency measurement clock select register (FMCKS)............................................................ 390
10.4 Frequency Measurement Circuit Operation .......................................................................... 391
10.4.1 Setting frequency measurement circuit....................................................................................... 391
10.4.2 Frequency measurement circuit operation timing ....................................................................... 392
CHAPTER 11 12-BIT INTERVAL TIMER ............................................................................................ 393
11.1 Functions of 12-bit Interval Timer........................................................................................... 393

11.2 Configuration of 12-bit Interval Timer .................................................................................... 393
11.3 Registers Controlling 12-bit Interval Timer ........................................................................... 394
11.3.2 Peripheral reset control register 2 (PRR2) .................................................................................. 395
11.3.4 12-bit interval timer control register (ITMC) ................................................................................ 397
11.4 12-bit Interval Timer Operation ............................................................................................... 398
11.4.1 12-bit interval timer operation timing ........................................................................................... 398
11.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP
mode .......................................................................................................................................... 399
CHAPTER 12 8-BIT INTERVAL TIMER .............................................................................................. 400
12.1 Overview .................................................................................................................................... 400

12.2 I/O Pins ...................................................................................................................................... 402
12.3 Registers ................................................................................................................................... 402
12.3.1 8-bit interval timer counter register ni (TRTni) (n = 0, 1, i = 0, 1) ................................................ 403
12.3.2 8-bit interval timer counter register n (TRTn) (n = 0, 1) ............................................................... 403
12.3.3 8-bit interval timer compare register ni (TRTCMPni) (n = 0, 1, i = 0, 1) ...................................... 404
12.3.4 8-bit interval timer compare register n (TRTCMPn) (n = 0, 1) ..................................................... 404
12.3.5 8-bit interval timer control register n (TRTCRn) (n = 0, 1) ........................................................... 405
Index-8
12.3.6 8-bit interval timer division register n (TRTMDn) (n = 0, 1) ......................................................... 406
12.4 Operation................................................................................................................................. 407
12.4.1 Count mode ................................................................................................................................ 407
12.4.2 Timer operation........................................................................................................................... 408
12.4.3 Start/stop timing .......................................................................................................................... 410
12.4.3.1 When count source (fSX) is selected .......................................................................... 410
12.4.3.2 When count source (fSX/2m) is selected ..................................................................... 412
12.4.4 Timing for updating compare register values .............................................................................. 414
12.5 Notes on 8-Bit Interval Timer................................................................................................... 415
12.5.1 Changing settings of operating mode ......................................................................................... 415
12.5.2 Accessing compare registers ...................................................................................................... 415
12.5.3 8-bit interval timer setting procedure ........................................................................................... 415
CHAPTER 13 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................... 416
13.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 416

13.2 Configuration of Clock Output/Buzzer Output Controller .................................................... 417
13.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 417
13.3.1 Clock output select registers n (CKSn) ....................................................................................... 417
13.3.2 Registers controlling port functions of pins to be used for clock or buzzer output ...................... 419
13.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 420
13.4.1 Operation as output pin .............................................................................................................. 420
13.5 Cautions of Clock Output/buzzer Output Controller............................................................. 420
CHAPTER 14 WATCHDOG TIMER ..................................................................................................... 421
14.1 Functions of Watchdog Timer ................................................................................................. 421

14.2 Configuration of Watchdog Timer .......................................................................................... 422
14.3 Register Controlling Watchdog Timer.................................................................................... 423
14.3.1 Watchdog timer enable register (WDTE) .................................................................................... 423
14.4 Operation of Watchdog Timer ................................................................................................. 424
14.4.1 Controlling operation of watchdog timer ..................................................................................... 424
14.4.2 Setting overflow time of watchdog timer ..................................................................................... 426
14.4.3 Setting window open period of watchdog timer........................................................................... 427
14.4.4 Setting watchdog timer interval interrupt..................................................................................... 429
CHAPTER 15 A/D CONVERTER ......................................................................................................... 430
15.1 Function of A/D Converter ....................................................................................................... 430

15.2 Configuration of A/D Converter .............................................................................................. 433
15.3 Registers Controlling A/D Converter...................................................................................... 435
15.3.3 A/D converter mode register 0 (ADM0) ....................................................................................... 438
Index-9
15.3.6 10-bit A/D conversion result register (ADCR) ............................................................................. 451
15.3.7 8-bit A/D conversion result register (ADCRH) ............................................................................. 451
15.3.8 Analog input channel specification register (ADS) ...................................................................... 452
15.3.9 Conversion result comparison upper limit setting register (ADUL) ............................................. 453
15.3.10 Conversion result comparison lower limit setting register (ADLL) ............................................. 453
15.3.11 A/D test register (ADTES) ......................................................................................................... 454
15.3.12 Registers controlling port function of analog input pins............................................................. 454
15.4 A/D Converter Conversion Operations .................................................................................. 455
15.5 Input Voltage and Conversion Results .................................................................................. 457
15.6 A/D Converter Operation Modes ............................................................................................. 458
15.6.1 Software trigger mode (select mode, sequential conversion mode) ........................................... 458
15.6.2 Software trigger mode (select mode, one-shot conversion mode) .............................................. 459
15.6.3 Software trigger mode (scan mode, sequential conversion mode) ............................................. 460
15.6.4 Software trigger mode (scan mode, one-shot conversion mode) ............................................... 461
15.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................. 462
15.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) ................................ 463
15.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ............................... 464
15.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode).................................. 465
15.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) ................................... 466
15.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) ................................... 467
15.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................. 468
15.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ..................................... 469
15.7 A/D Converter Setup Flowchart .............................................................................................. 470
15.7.1 Setting up software trigger mode ................................................................................................ 470
15.7.2 Setting up hardware trigger no-wait mode .................................................................................. 471
15.7.3 Setting up hardware trigger wait mode ....................................................................................... 472
15.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected
(example for software trigger mode and one-shot conversion mode) ......................................... 473
15.7.5 Setting up test mode ................................................................................................................... 474
15.8 SNOOZE Mode Function .......................................................................................................... 475
15.9 How to Read A/D Converter Characteristics Table ............................................................... 479
15.10 Cautions for A/D Converter ................................................................................................... 481
CHAPTER 16 TEMPERATURE SENSOR 2........................................................................................ 485
16.1 Functions of Temperature Sensor .......................................................................................... 485

16.2 Registers ................................................................................................................................... 486
16.2.2 Temperature sensor control test register (TMPCTL) .................................................................. 487
Index-10
16.3 Setting Procedures................................................................................................................... 488
16.3.1 Starting operation of the temperature sensor ............................................................................. 488
16.3.2 Switching modes......................................................................................................................... 489
CHAPTER 17 24-BIT ΔΣ A/D CONVERTER...................................................................................... 490
17.1 Functions of 24-bit ΔΣ A/D Converter .................................................................................... 490

17.1.1 I/O pins ....................................................................................................................................... 493
17.1.2 Pre-amplifier ............................................................................................................................... 493
17.1.3 ΔΣ A/D converter ........................................................................................................................ 493
17.1.4 Reference voltage generator ...................................................................................................... 494
17.1.5 Phase adjustment circuits (PHCn) .............................................................................................. 494
17.1.6 Digital filter (DF) .......................................................................................................................... 494
17.1.7 Zero-cross detection ................................................................................................................... 494
17.1.8 High-pass filter (HPF) ................................................................................................................. 494
17.2 Registers ................................................................................................................................... 495
17.2.1 ΔΣ A/D converter mode register (DSADMR) .............................................................................. 496
17.2.2 ΔΣ A/D converter gain control register 0 (DSADGCR0).............................................................. 498
17.2.3 ΔΣ A/D converter gain control register 1 (DSADGCR1).............................................................. 499
17.2.4 ΔΣ A/D converter HPF control register (DSADHPFCR) .............................................................. 500
17.2.5 ΔΣ A/D converter interrupt control register (DSADICR) .............................................................. 501
17.2.6 ΔΣ A/D converter interrupt clear register (DSADICLR) ............................................................... 504
17.2.7 ΔΣ A/D converter interrupt status register (DSADISR) ............................................................... 505
17.2.8 ΔΣ A/D converter phase control register n (DSADPHCRn) (n = 0, 1, 2, 3) ................................. 506
17.2.9 ΔΣ A/D converter conversion result register n (DSADCRnL, DSADCRnM, DSADCRnH)
(n = 0, 1, 2, 3) ............................................................................................................................. 507
17.2.10 ΔΣ A/D converter conversion result register n (DSADCRn) (n = 0, 1, 2, 3)............................... 509
17.2.11 Peripheral enable register 1 (PER1) ......................................................................................... 510
17.2.12 Peripheral reset control register 1 (PRR1) ................................................................................ 511
17.2.13 Peripheral clock control register (PCKC) .................................................................................. 512
17.3 Operation ................................................................................................................................... 513
17.3.1 Operation of 24-bit ΔΣ A/D converter.......................................................................................... 514
17.3.2 Procedure for switching from normal operation mode to neutral missing mode ......................... 516
17.3.3 Interrupt operation ...................................................................................................................... 517
17.3.3.1 Zero-cross detection interrupt operation ................................................................... 517
17.3.3.2 ΔΣ A/D conversion end interrupt operation ............................................................... 519
17.3.4 Operation in standby state .......................................................................................................... 519
17.4 Notes on Using 24-Bit ΔΣ A/D Converter ............................................................................... 520
17.4.1 External pins ............................................................................................................................... 520
17.4.2 SFR access ................................................................................................................................ 520
17.4.3 Setting operating clock ............................................................................................................... 521
17.4.4 Cycle measurement of the zero-cross detection interrupt by using ELC .................................... 522
17.4.5 Zero-cross detection interrupt software-clear ............................................................................. 522
Index-11
17.4.6 Input range ................................................................................................................................. 522
CHAPTER 18 SERIAL ARRAY UNIT .................................................................................................. 523
18.1 Functions of Serial Array Unit................................................................................................. 524

18.1.1 3-wire serial I/O (CSI00, CSI10, CSI30) ..................................................................................... 524
18.1.2 UART (UART0 to UART3) .......................................................................................................... 525
18.1.3 Simplified I2C (IIC00, IIC10, IIC30) ............................................................................................. 526
18.1.4 IrDA ............................................................................................................................................ 526
18.2 Configuration of Serial Array Unit .......................................................................................... 527
18.2.1 Shift register ............................................................................................................................... 531
18.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) ............................................................... 531
18.3 Registers Controlling Serial Array Unit.................................................................................. 533
18.3.2 Serial clock select register m (SPSm)......................................................................................... 535
18.3.3 Serial mode register mn (SMRmn) ............................................................................................. 536
18.3.4 Serial communication operation setting register mn (SCRmn) ................................................... 537
18.3.5 Serial data register mn (SDRmn) ................................................................................................ 540
18.3.6 Serial flag clear trigger register mn (SIRmn) ............................................................................... 542
18.3.7 Serial status register mn (SSRmn) ............................................................................................. 543
18.3.8 Serial channel start register m (SSm) ......................................................................................... 545
18.3.9 Serial channel stop register m (STm) ......................................................................................... 546
18.3.10 Serial channel enable status register m (SEm) ......................................................................... 547
18.3.11 Serial output enable register m (SOEm) ................................................................................... 548
18.3.12 Serial output register m (SOm) ................................................................................................. 549
18.3.13 Serial output level register m (SOLm) ....................................................................................... 550
18.3.14 Serial standby control register 0 (SSC0) ................................................................................... 552
18.3.15 Input switch control register (ISC) ............................................................................................. 553
18.3.16 Noise filter enable register 0 (NFEN0) ...................................................................................... 554
18.3.17 Registers controlling port functions of serial input/output pins .................................................. 555
18.4 Operation Stop Mode ............................................................................................................... 557
18.4.1 Stopping the operation by units .................................................................................................. 558
18.4.2 Stopping the operation by channels............................................................................................ 559
18.5 Operation of 3-Wire Serial I/O (CSI00, CSI10, CSI30) Communication ............................... 560
18.5.1 Master transmission.................................................................................................................... 562
18.5.2 Master reception ......................................................................................................................... 572
18.5.3 Master transmission/reception .................................................................................................... 581
18.5.4 Slave transmission...................................................................................................................... 591
18.5.5 Slave reception ........................................................................................................................... 601
18.5.6 Slave transmission/reception ...................................................................................................... 608
18.5.7 SNOOZE mode function ............................................................................................................. 618
Index-12
18.5.8 Calculating transfer clock frequency ........................................................................................... 622
18.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI10, CSI30)
communication ........................................................................................................................... 624
18.6 Operation of UART (UART0 to UART3) Communication ...................................................... 625
18.6.1 UART transmission ..................................................................................................................... 627
18.6.2 UART reception .......................................................................................................................... 637
18.6.3 SNOOZE mode function ............................................................................................................. 644
18.6.4 Calculating baud rate .................................................................................................................. 652
18.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3)
communication ........................................................................................................................... 656
18.7 LIN Communication Operation ............................................................................................... 657
18.7.1 LIN transmission ......................................................................................................................... 657
18.7.2 LIN reception .............................................................................................................................. 660
18.8 Operation of Simplified I2C (IIC00, IIC10, IIC30) Communication ........................................ 665
18.8.1 Address field transmission .......................................................................................................... 667
18.8.2 Data transmission ....................................................................................................................... 673
18.8.3 Data reception ............................................................................................................................ 677
18.8.4 Stop condition generation ........................................................................................................... 682
18.8.5 Calculating transfer rate .............................................................................................................. 683
18.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC10, IIC30)
communication ........................................................................................................................... 685
CHAPTER 19 SERIAL INTERFACE IICA ........................................................................................... 686
19.1 Functions of Serial Interface IICA ........................................................................................... 686

19.2 Configuration of Serial Interface IICA .................................................................................... 689
19.3 Registers Controlling Serial Interface IICA ............................................................................ 692
19.3.3 IICA control register n0 (IICCTLn0) ............................................................................................ 694
19.3.4 IICA status register n (IICSn) ...................................................................................................... 699
19.3.5 IICA flag register n (IICFn) .......................................................................................................... 703
19.3.6 IICA control register n1 (IICCTLn1) ............................................................................................ 705
19.3.7 IICA low-level width setting register n (IICWLn) .......................................................................... 707
19.3.8 IICA high-level width setting register n (IICWHn) ........................................................................ 707
19.3.9 Port mode register 6 (PM6) ........................................................................................................ 708
2
19.4 I C Bus Mode Functions .......................................................................................................... 709
19.4.1 Pin configuration ......................................................................................................................... 709
19.4.2 Setting transfer clock by using IICWLn and IICWHn registers .................................................... 710
2
19.5 I C Bus Definitions and Control Methods .............................................................................. 712
19.5.1 Start conditions ........................................................................................................................... 712
19.5.2 Addresses ................................................................................................................................... 713
Index-13
19.5.3 Transfer direction specification ................................................................................................... 713
19.5.4 Acknowledge (ACK).................................................................................................................... 714
19.5.5 Stop condition ............................................................................................................................. 715
19.5.6 Wait ............................................................................................................................................ 716
19.5.7 Canceling wait ............................................................................................................................ 718
19.5.8 Interrupt request (INTIICAn) generation timing and wait control ................................................. 719
19.5.9 Address match detection method ............................................................................................... 720
19.5.10 Error detection .......................................................................................................................... 720
19.5.11 Extension code ......................................................................................................................... 720
19.5.12 Arbitration ................................................................................................................................. 721
19.5.13 Wakeup function ....................................................................................................................... 723
19.5.14 Communication reservation ...................................................................................................... 726
19.5.15 Cautions ................................................................................................................................... 730
19.5.16 Communication operations ....................................................................................................... 731
19.5.17 Timing of I2C interrupt request (INTIICAn) occurrence ............................................................. 739
19.6 Timing Charts ........................................................................................................................... 760
CHAPTER 20 IrDA ................................................................................................................................. 775
20.1 Functions of IrDA ..................................................................................................................... 775

20.2 Registers ................................................................................................................................... 776
20.2.3 IrDA control register (IRCR) ........................................................................................................ 778
20.3 Operation ................................................................................................................................... 779
20.3.1 IrDA communication operation procedure .................................................................................. 779
20.3.2 Transmission .............................................................................................................................. 780
20.3.3 Reception ................................................................................................................................... 781
20.3.4 Selecting high-level pulse width .................................................................................................. 781
20.4 Usage Notes on IrDA ................................................................................................................ 782
CHAPTER 21 LCD CONTROLLER/DRIVER ....................................................................................... 783
21.1 Functions of LCD Controller/Driver ........................................................................................ 784

21.2 Configuration of LCD Controller/Driver ................................................................................. 787
21.3 Registers Controlling LCD Controller/Driver ......................................................................... 789
21.3.1 LCD mode register 0 (LCDM0) ................................................................................................... 790
21.3.2 LCD mode register 1 (LCDM1) ................................................................................................... 793
21.3.4 LCD clock control register 0 (LCDC0) ......................................................................................... 796
21.3.5 LCD boost level control register (VLCD) ..................................................................................... 797
21.3.6 LCD input switch control register (ISCLCD) ................................................................................ 798
21.3.7 LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)........................................................... 800
Index-14
21.3.8 Port mode registers 0, 1, 3, 5, 7, 8 (PM0, PM1, PM3, PM5, PM7, PM8) .................................... 804
21.4 LCD Display Data Registers .................................................................................................... 805
21.5 Selection of LCD Display Register ......................................................................................... 809
21.5.1 A-pattern area and B-pattern area data display .......................................................................... 810
21.5.2 Blinking display (Alternately displaying A-pattern and B-pattern area data) ............................... 810
21.6 Setting the LCD Controller/Driver ............................................................................................... 811
21.7 Operation Stop Procedure ....................................................................................................... 814
21.8 Supplying LCD Drive Voltages VL1, VL2, VL3, and VL4 ............................................................ 815
21.8.1 External resistance division method ........................................................................................... 815
21.8.2 Internal voltage boosting method ................................................................................................ 817
21.8.3 Capacitor split method ................................................................................................................ 818
21.9 Common and Segment Signals .............................................................................................. 819
21.9.1 Normal liquid crystal waveform ................................................................................................... 819
21.10 Display Modes ........................................................................................................................ 828
21.10.1 Static display example .............................................................................................................. 828
21.10.2 Two-time-slice display example ................................................................................................ 831
21.10.3 Three-time-slice display example ............................................................................................. 834
21.10.4 Four-time-slice display example ............................................................................................... 838
21.10.5 Six-time-slice display example .................................................................................................. 842
21.10.6 Eight-time-slice display example............................................................................................... 845
CHAPTER 22 DATA TRANSFER CONTROLLER (DTC).................................................................. 849
22.1 Functions of DTC...................................................................................................................... 850

22.2 Configuration of DTC ............................................................................................................... 851
22.3 Registers Controlling DTC ...................................................................................................... 852
22.3.1 Allocation of DTC control data area and DTC vector table area ................................................. 853
22.3.2 Control data allocation ................................................................................................................ 854
22.3.3 Vector table ................................................................................................................................ 856
22.3.5 DTC control register j (DTCCRj) (j = 0 to 23) .............................................................................. 859
22.3.6 DTC block size register j (DTBLSj) (j = 0 to 23) .......................................................................... 860
22.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23) ................................................................... 860
22.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23)......................................................... 861
22.3.9 DTC source address register j (DTSARj) (j = 0 to 23) ................................................................. 861
22.3.10 DTC destination address register j (DTDARj) (j = 0 to 23) ........................................................ 861
22.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4) .............................................................. 862
22.3.12 DTC base address register (DTCBAR) ..................................................................................... 864
22.4 DTC Operation .......................................................................................................................... 865
22.4.1 Activation sources....................................................................................................................... 865
22.4.2 Normal mode .............................................................................................................................. 866
22.4.3 Repeat mode .............................................................................................................................. 869
Index-15
22.4.4 Chain transfers ........................................................................................................................... 872
22.5 Notes on DTC ............................................................................................................................ 874
22.5.1 Setting DTC control data and vector table .................................................................................. 874
22.5.2 Allocation of DTC control data area and DTC vector table area ................................................. 874
22.5.3 DTC pending instruction ............................................................................................................. 874
22.5.4 Operation when accessing data flash memory space................................................................. 875
22.5.5 Number of DTC execution clock cycles ...................................................................................... 875
22.5.6 DTC response time ..................................................................................................................... 876
22.5.7 DTC activation sources............................................................................................................... 876
22.5.8 Operation in standby mode status .............................................................................................. 877
CHAPTER 23 EVENT LINK CONTROLLER (ELC) ........................................................................... 878
23.1 Functions of ELC ...................................................................................................................... 878

23.2 Configuration of ELC ............................................................................................................... 878
23.3 Registers Controlling ELC ....................................................................................................... 879
23.3.1 Event output destination select register n (ELSELRn) (n = 00 to 21) .......................................... 880
23.3.2 Timer input select register 0 (TIS0)............................................................................................. 883
23.4 ELC Operation .......................................................................................................................... 885
23.5 Points for Caution when Using the ELC ................................................................................ 886
CHAPTER 24 INTERRUPT FUNCTIONS............................................................................................. 887
24.1 Interrupt Function Types ......................................................................................................... 887

24.2 Interrupt Sources and Configuration ..................................................................................... 887
24.3 Registers Controlling Interrupt Functions ............................................................................. 893
24.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) ................................. 896
24.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) ..................... 898
24.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) ........................................................ 899
24.3.4 External interrupt rising edge enable register (EGP0, EGP1), External interrupt falling edge
enable register (EGN0, EGN1) ................................................................................................... 901
24.3.5 Program status word (PSW) ....................................................................................................... 903
24.4 Interrupt Servicing Operations ............................................................................................... 904
24.4.1 Maskable interrupt request acknowledgment ............................................................................. 904
24.4.2 Software interrupt request acknowledgment ............................................................................... 907
24.4.3 Multiple interrupt servicing .......................................................................................................... 907
24.4.4 Interrupt servicing during division instruction .............................................................................. 911
24.4.5 Interrupt request hold.................................................................................................................. 913
CHAPTER 25 KEY INTERRUPT FUNCTION ..................................................................................... 914
25.1 Functions of Key Interrupt ...................................................................................................... 914
Index-16
25.2 Configuration of Key Interrupt ................................................................................................ 914
25.3 Register Controlling Key Interrupt ......................................................................................... 916
25.3.1 Key return control register (KRCTL) ........................................................................................... 916
25.3.2 Key return mode register 0 (KRM0) ............................................................................................ 917
25.3.3 Key return flag register (KRF) ..................................................................................................... 918
25.3.4 Port mode register 7 (PM7) ........................................................................................................ 919
CHAPTER 26 STANDBY FUNCTION .................................................................................................. 920
26.1 Standby Function ..................................................................................................................... 920

26.2 Registers Controlling Standby Function ............................................................................... 921
26.3 Standby Function Operation .................................................................................................... 922
26.3.1 HALT mode .................................................................................................................................. 922
26.3.2 STOP mode ................................................................................................................................ 929
26.3.3 SNOOZE mode........................................................................................................................... 935
CHAPTER 27 RESET FUNCTION........................................................................................................ 939
27.1 Timing of Reset Operation ...................................................................................................... 941

27.2 States of Operation During Reset Periods............................................................................. 943
27.3 Register for Confirming Reset Source ................................................................................... 946
27.3.1 Reset control flag register (RESF) .............................................................................................. 946
27.3.2 Power-on-reset status register (PORSR) .................................................................................... 949
27.3.3 RTC power-on-reset status register (RTCPORSR) .................................................................... 949
CHAPTER 28 POWER-ON-RESET CIRCUIT ...................................................................................... 952
28.1 Functions of Power-on-reset Circuit ...................................................................................... 952

28.2 Configuration of Power-on-reset Circuit ................................................................................ 953
28.3 Operation of Power-on-reset Circuit ...................................................................................... 953
CHAPTER 29 VOLTAGE DETECTOR ................................................................................................. 957
29.1 Functions of Voltage Detector ................................................................................................. 957

29.2 Configuration of Voltage Detector .......................................................................................... 958
29.3 Registers Controlling Voltage Detector .................................................................................. 961
29.3.1 Voltage detection register (LVIM) ............................................................................................... 961
29.3.2 Voltage detection level register (LVIS)........................................................................................ 962
29.3.3 VDD pin voltage detection control register (LVDVDD) ................................................................. 966
29.3.4 VBAT pin voltage detection control register (LVDVBAT) ............................................................ 967
29.3.5 VRTC pin voltage detection control register (LVDVRTC) ........................................................... 968
29.3.6 EXLVD pin voltage detection control register (LVDEXLVD) ....................................................... 969
29.4 Operation of Voltage Detector ................................................................................................. 970
Index-17
29.4.1 When used as reset mode .......................................................................................................... 970
29.4.2 When used as interrupt mode ..................................................................................................... 972
29.4.3 When used as interrupt and reset mode ..................................................................................... 974
29.4.4 Each power supply pin voltage detection setting procedure ....................................................... 979
29.5 Changing of LVD Detection Voltage Setting ......................................................................... 983
29.5.1 Changing of LVD detection voltage setting in LVD reset mode .................................................. 984
29.5.2 Changing of LVD detection voltage setting in LVD interrupt mode ............................................. 985
29.5.3 Changing of each power supply pin LVD detection voltage setting ............................................ 987
29.6 Cautions for Voltage Detector ................................................................................................. 988
CHAPTER 30 BATTERY BACKUP FUNCTION ................................................................................. 991
30.1 Functions of Battery Backup .................................................................................................. 991

30.1.1 Pin configuration ......................................................................................................................... 993
30.2 Registers ................................................................................................................................... 994
30.2.1 Battery backup power switching control register 0 (BUPCTL0) .................................................. 994
30.2.2 Battery backup power switching control register 1 (BUPCTL1) .................................................. 996
30.2.3 Global digital input disable register (GDIDIS) ............................................................................. 996
30.3 Operation ................................................................................................................................... 997
30.3.1 Battery backup function .............................................................................................................. 997
30.3.2 Using the battery backup function............................................................................................. 1001
30.4 Usage Notes ............................................................................................................................ 1007
CHAPTER 31 OSCILLATION STOP DETECTOR ............................................................................ 1008
31.1 Functions of Oscillation Stop Detector ................................................................................ 1008

31.2 Configuration of Oscillation Stop Detector ......................................................................... 1009
31.3 Registers Used by Oscillation Stop Detector ...................................................................... 1010
31.3.3 Subsystem clock supply option control register (OSMC) .......................................................... 1012
31.3.4 Oscillation stop detection control register (OSDC).................................................................... 1013
31.4 Operation of Oscillation Stop Detector ................................................................................ 1014
31.4.1 How the oscillation stop detector operates ............................................................................... 1014
31.5 Cautions on Using the Oscillation Stop Detector ............................................................... 1015
CHAPTER 32 SAFETY FUNCTIONS ................................................................................................. 1016
32.1 Overview of Safety Functions ............................................................................................... 1016

32.2 Registers Used by Safety Functions .................................................................................... 1017
32.3 Operation of Safety Functions .............................................................................................. 1017
32.3.1 Flash memory CRC operation function (high-speed CRC) ....................................................... 1017
32.3.1.1 Flash memory CRC control register (CRC0CTL) .................................................... 1018
32.3.1.2 Flash memory CRC operation result register (PGCRCL) ........................................ 1019
32.3.2 CRC operation function (general-purpose CRC) ...................................................................... 1021
Index-18
32.3.2.1 CRC input register (CRCIN) .................................................................................... 1021
32.3.2.2 CRC data register (CRCD) ...................................................................................... 1022
32.3.3 RAM parity error detection function .......................................................................................... 1023
32.3.3.1 RAM parity error control register (RPECTL) ............................................................ 1023
32.3.4 RAM guard function .................................................................................................................. 1025
32.3.4.1 Invalid memory access detection control register (IAWCTL) ................................... 1025
32.3.5 SFR guard function ................................................................................................................... 1026
32.3.6 Invalid memory access detection function ................................................................................ 1027
32.3.7 Frequency detection function .................................................................................................... 1029
32.3.7.1 Timer input select register 0 (TIS0) ......................................................................... 1030
32.3.8 A/D test function ....................................................................................................................... 1031
32.3.8.1 A/D test register (ADTES) ....................................................................................... 1032
32.3.8.2 Analog input channel specification register (ADS) .................................................. 1033
32.3.9 Digital output signal level detection function for I/O ports ......................................................... 1034
32.3.9.1 Port mode select register (PMS) ............................................................................. 1034
CHAPTER 33 AES FUNCTIONS ........................................................................................................ 1035
33. 1 AES Functions ....................................................................................................................... 1035
CHAPTER 34 REGULATOR ............................................................................................................... 1036
34.1 Regulator Overview ................................................................................................................ 1036

34.2 Register Controlling Regulator ............................................................................................. 1037
34.2.1 Regulator mode control register (PMMC) ................................................................................. 1037
CHAPTER 35 OPTION BYTE ............................................................................................................. 1038
35.1 Functions of Option Bytes .................................................................................................... 1038

35.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) ..................................................... 1038
35.1.2 On-chip debug option byte (000C3H/ 010C3H) ........................................................................ 1039
35.2 Format of User Option Byte .................................................................................................. 1040
35.3 Format of On-chip Debug Option Byte................................................................................. 1045
35.4 Setting of Option Byte............................................................................................................ 1046
CHAPTER 36 FLASH MEMORY ........................................................................................................ 1047
36.1 Serial Programming Using Flash Memory Programmer .................................................... 1048

36.1.1 Programming environment ....................................................................................................... 1050
36.1.2 Communication mode ............................................................................................................... 1050
36.2 Serial Programming Using External Device (that Incorporates UART) ............................ 1051
36.2.1 Programming environment ....................................................................................................... 1051
36.2.2 Communication mode ............................................................................................................... 1052
36.3 Connection of Pins on Board ................................................................................................ 1053
36.3.1 P40/TOOL0 pin ......................................................................................................................... 1053
Index-19
36.3.2 RESET pin ................................................................................................................................ 1053
36.3.3 Port pins ................................................................................................................................... 1054
36.3.4 REGC pin ................................................................................................................................. 1054
36.3.5 X1 and X2 pins ......................................................................................................................... 1054
36.3.6 Power supply ............................................................................................................................ 1054
36.4 Programming Method ............................................................................................................ 1055
36.4.1 Serial programming procedure ................................................................................................. 1055
36.4.2 Flash memory programming mode ........................................................................................... 1056
36.4.3 Selecting communication mode ................................................................................................ 1058
36.4.4 Communication commands ...................................................................................................... 1059
36.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) .......... 1061
36.6 Self-Programming .................................................................................................................. 1062
36.6.1 Self-programming procedure .................................................................................................... 1063
36.6.2 Boot swap function ................................................................................................................... 1064
36.6.3 Flash shield window function .................................................................................................... 1066
36.7 Security Settings .................................................................................................................... 1067
36.8 Data Flash ............................................................................................................................... 1069
36.8.1 Data flash overview ................................................................................................................... 1069
36.8.2 Register controlling data flash memory..................................................................................... 1070
36.8.2.1 Data flash control register (DFLCTL) ...................................................................... 1070
36.8.3 Procedure for accessing data flash memory ............................................................................. 1071
CHAPTER 37 ON-CHIP DEBUG FUNCTION ................................................................................... 1072
37.1 Connecting E1 On-chip Debugging Emulator ..................................................................... 1072

37.2 On-Chip Debug Security ID ................................................................................................... 1075
37.3 Securing of User Resources ................................................................................................. 1075
CHAPTER 38 BCD CORRECTION CIRCUIT ................................................................................... 1077
38.1 BCD Correction Circuit Function .......................................................................................... 1077

38.2 Registers Used by BCD Correction Circuit ......................................................................... 1077
38.2.1 BCD correction result register (BCDADJ) ................................................................................. 1077
38.3 BCD Correction Circuit Operation ........................................................................................ 1078
CHAPTER 39 32-BIT MULTIPLY-ACCUMULATOR ......................................................................... 1080
39.1 Function of 32-bit Multiply-accumulator .............................................................................. 1080

39.2 Configuration of 32-bit Multiply-accumulator ..................................................................... 1081
39.2.1 Multiplication data register A (MUL32UH, MUL32UL, MUL32SH, MUL32SL, MAC32UH,
MAC32UL, MAC32SH, MAC32SL) .......................................................................................... 1083
39.2.2 Multiplication data register B (MULBL, MULBH) ....................................................................... 1084
39.2.3 Multiplication result register (MULR0, MULR1, MULR2, MULR3)............................................. 1085
39.3 Register Controlling 32-bit Multiply-accumulator ............................................................... 1087
Index-20
39.3.3 Multiplication control register (MULC) ....................................................................................... 1088
39.4 Operations of 32-bit Multiply-accumulator .......................................................................... 1090
39.4.1 Basic operation ......................................................................................................................... 1090
39.4.2 Number of clocks for result availability...................................................................................... 1090
39.4.3 Switch of operation mode ......................................................................................................... 1091
39.4.4 Multiplication operation ............................................................................................................. 1091
39.4.5 Multiply-accumulation operation ............................................................................................... 1091
39.4.6 Fixed point mode ...................................................................................................................... 1092
39.4.7 Operation of fixed point mode ................................................................................................... 1093
39.4.8 Interrupt .................................................................................................................................... 1094
39.5 Operation of 32-bit Multiply-accumulator ............................................................................ 1095
39.6 Precautions for 32-bit Multiply-accumulator ....................................................................... 1099
39.6.1 Precautions during operation (MULST = 1) .............................................................................. 1099
CHAPTER 40 INSTRUCTION SET..................................................................................................... 1100
40.1 Conventions Used in Operation List .................................................................................... 1100

40.1.1 Operand identifiers and specification methods ......................................................................... 1100
40.1.2 Description of operation column ............................................................................................... 1101
40.1.3 Description of flag operation column......................................................................................... 1102
40.1.4 PREFIX instruction ................................................................................................................... 1102
40.2 Operation List ......................................................................................................................... 1103
CHAPTER 41 ELECTRICAL SPECIFICATIONS ............................................................................... 1121
41.1 Absolute Maximum Ratings .................................................................................................. 1122

41.2 Oscillator Characteristics ...................................................................................................... 1125
41.2.1 X1, XT1 oscillator characteristics .............................................................................................. 1125
41.2.2 On-chip oscillator characteristics .............................................................................................. 1126
41.2.3 PLL oscillator characteristics .................................................................................................... 1127
41.3 DC Characteristics ................................................................................................................. 1128
41.3.1 Pin characteristics..................................................................................................................... 1128
41.3.2 Supply current characteristics ................................................................................................... 1133
41.4 AC Characteristics ................................................................................................................. 1142
41.5 Peripheral Functions Characteristics................................................................................... 1146
41.5.1 Serial array unit......................................................................................................................... 1146
41.5.2 Serial interface IICA .................................................................................................................. 1170
41.6 Analog Characteristics .......................................................................................................... 1174
41.6.1 A/D converter characteristics .................................................................................................... 1174
41.6.2 24-bit ΔΣ A/D converter characteristics .................................................................................... 1176
41.6.3 Temperature sensor 2 characteristics ....................................................................................... 1179
41.6.4 POR circuit characteristics ........................................................................................................ 1180
Index-21
41.6.5 LVD circuit characteristics ........................................................................................................ 1180
41.6.6 Power supply voltage rising slope characteristics ..................................................................... 1181
41.7 Battery Backup Function ....................................................................................................... 1182
41.7.1 Power supply switching characteristics..................................................................................... 1182
41.7.2 VDD pin voltage detection characteristics .................................................................................. 1183
41.7.3 VBAT pin voltage detection characteristics ............................................................................... 1184
41.7.4 VRTC pin voltage detection characteristics .............................................................................. 1185
41.7.5 EXLVD pin voltage detection .................................................................................................... 1186
41.8 LCD Characteristics ............................................................................................................... 1187
41.8.1 Resistance division method ...................................................................................................... 1187
41.8.2 Internal voltage boosting method .............................................................................................. 1188
41.8.3 Capacitor split method .............................................................................................................. 1190
41.9 RAM Data Retention Characteristics .................................................................................... 1191
41.10 Flash Memory Programming Characteristics .................................................................... 1191
41.11 Dedicated Flash Memory Programmer Communication (UART) ..................................... 1191
41.12 Timing Specs for Switching Flash Memory Programming Modes .................................. 1192
CHAPTER 42 PACKAGE DRAWINGS .............................................................................................. 1193
42.1 64-pin Products ...................................................................................................................... 1193

42.2 80-pin Products ...................................................................................................................... 1194
42.3 100-pin Products .................................................................................................................... 1195
APPENDIX A REVISION HISTORY .................................................................................................... 1196
A.1 Major Revisions in This Edition ............................................................................................. 1196

A.2 Revision History of Preceding Editions ................................................................................ 1199
Index-22
RL78/I1C R01UH0587EJ0200
Rev.2.00
RENESAS MCU
Aug 31, 2018
CHAPTER 1 OUTLINE
1.1 Features
Ultra-low power consumption technology

● VDD = single power supply voltage of 1.7 to 5.5 VNote 1
● HALT mode
● STOP mode
● SNOOZE mode
RL78 CPU core

● CISC architecture with 3-stage pipeline
● Minimum instruction execution time: Can be changed from high speed (0.03125 µs: @ 32 MHz selection with PLL
clock, 0.04167 µs: @ 24 MHz selection with high-speed on-chip oscillator) to ultra-low speed (66.6 µs: @ 15 kHz
operation with low-speed on-chip oscillator)
● 16-bit multiplication, 16-bit multiply-accumulation, and 32-bit division are supported.
● Address space: 1 MB
● General-purpose registers: (8-bit register × 8) × 4 banks
● On-chip RAM: 6 KB to 16 KB
Code flash memory

● Code flash memory: 64 KB to 256 KB
● Block size: 1 KB
● Prohibition of block erase and rewriting (security function)
● On-chip debug function
● Self-programming (with boot swap function/flash shield window function)
Data flash memory

● Data flash memory: 2 KB
● Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash
memory
● Number of rewrites: 1,000,000 times (TYP.)
● Voltage of rewrites: VDD = 1.9 to 5.5 V
PLL clockNote 2
● 32 MHz is selectable (ΔΣ A/D converter is operable even when the PLL clock is selected as a CPU clock.)
High-speed on-chip oscillator

● Select from 1 to 24 MHz (TYP.). However when it is used as a clock for the ΔΣ A/D converter, select from 24 MHz
(TYP.), 12 MHz (TYP.), 6 MHz (TYP.), or 3 MHz (TYP.).
● High accuracy: ±1.0% (VDD = 1.9 to 5.5 V, TA = –20 to +85°C)
● On-chip high-speed on-chip oscillator clock frequency correction function
Notes 1. The minimum operating voltage of this product varies according to the VBATEN setting value.
When VBATEN = 0, the minimum operating voltage is 1.7 V.
As well, the minimum operating voltage of VRTC is 1.6 V.
2. R5F10NPJ, R5F10NMJ, R5F10NPG only.
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RL78/I1C CHAPTER 1 OUTLINE
Middle-speed on-chip oscillator

● Select from 4 MHz/2 MHz/1 MHz (However ΔΣ A/D converter is disabled.)
Operating ambient temperature

● TA = -40 to +85°C
Power management and reset function

● On-chip power-on-reset (POR) circuit for Internal VDDNote 1 power supply
● On-chip RTC power-on-reset (RTCPOR) circuit for VRTC power supply
● On-chip voltage detector (LVD) (Select interrupt and reset from 13 levels)
Voltage detective circuit

● Detective voltage for VDD pin (Select interrupt from 6 levels)
● Detective voltage for VBAT pin (Select interrupt from 7 levels)
● Detective voltage for VRTC pin (Select interrupt from 4 levels)
● Detective voltage for EXLVD pin (Select interrupt from 1 level)
Data transfer controller (DTC)

● Transfer mode: Normal mode, repeat mode, block mode
● Activation source: Start by interrupt sources
● Chain transfer function
Event link controller (ELC)

● Event signals of 22 types can be linked to the specified peripheral function.
On-chip 32-bit multiplier and multiply-accumulator

● 32 bits × 32 bits = 64 bits (Unsigned or signed)
● 32 bits × 32 bits + 64 bits = 64 bits (Unsigned or signed)
Serial interface
● CSI: 2 to 3 channels
● UART/UART (LIN-bus supported): 2 to 3 channels
● UART/IrDA: 1 channel
● Simplified I2C communication: 2 to 3 channels
● I2C communication: 1 channel
Timer
● 16-bit timer: 8 channels
● 12-bit interval timer: 1 channel
● 8-bit interval timer: 4 channels
● Independent power supply RTC: 1 channel (calendar for 99 years, alarm function, and clock correction function)
● Watchdog timer: 1 channel
● Oscillation stop detection circuit: 1 channel
LCD controller/driver
● Internal voltage boosting method, capacitor split method, and external resistance division method are switchable
● Segment signal output: 19 (15)Note 2 to 42 (38)Note 2
● Common signal output: 4 (8)Note 2
Notes 1. Either VDD or VBAT is selected by the battery backup function.

2. The values in parentheses are the number of signal outputs when 8 com is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
R01UH0587EJ0200 Rev.2.00 2
Aug 31, 2018
A/D converter
● 24-Bit ΔΣ A/D converter: 3 or 4 channels
● 8/10-bit resolution A/D converter (VDD = 1.9 to 5.5 V): 4 or 6 channels
● Internal reference voltage (1.45 V) and temperature sensor
I/O port
● I/O port: 35 to 68 (N-ch open drain I/O [6 V tolerance]: 3,
N-ch open drain I/O [VDD toleranceNote 1/EVDD toleranceNote 2]: 10 to 16)
● Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor
● Different potential interface: Can connect to a 1.8/2.5/3 V device
● On-chip clock output/buzzer output controller
● On-chip key interrupt function
AES circuit
● Cipher modes of operation: GCM/ECB/CBC
● Encryption key length: 128/192/256 bits
Others
● On-chip BCD (binary-coded decimal) correction circuit
● On-chip battery backup function
Notes 1. 64 pin products only

2. 80 pin, 100 pin products only
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
R01UH0587EJ0200 Rev.2.00 3
Aug 31, 2018
Օ ROM, RAM capacities

Code flash Data flash RAM RL78/I1C
64 pins 80 pins 100 pins
Note 1
256 KB 2 KB 16 KB - R5F10NMJ R5F10NPJ
Note 2
128 KB 2 KB 8 KB R5F10NLG R5F10NMG R5F10NPG
64 KB 2 KB 6 KB R5F10NLE R5F10NME -
Notes 1. This is about 15 KB when the self-programming function is used. (For details, refer to CHAPTER 3.)
2. This is about 7 KB when the self-programming function is used. (For details, refer to CHAPTER 3.)
R01UH0587EJ0200 Rev.2.00 4
Aug 31, 2018
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/I1C
Part No. R 5 F 1 0 N P J D x x x F B #30
Packaging specification
#30 : Tray (LFQFP)
#50 : Embossed Tape (LFQFP)
Package type:
FB : LFQFP, 0.50 mm pitch
ROM number (Omitted with blank products)

Fields of application:
D : Industrial applications, TA = -40°C to +85°C
ROM capacity:
E : 64 KB
G : 128 KB
J : 256 KB
Pin count:
L : 64-pin
M : 80-pin
P : 100-pin
RL78/I1C group
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Table 1-1. List of Ordering Part Numbers
Pin count Package Data flash Fields of Ordering Part Number

ApplicationNote
64 pins 64-pin plastic LFQFP mounted D R5F10NLEDFB#30, R5F10NLGDFB#30,

(10 × 10 mm, 0.5 mm pitch) R5F10NLEDFB#50, R5F10NLGDFB#50
80 pins 80-pin plastic LFQFP mounted D R5F10NMEDFB#30, R5F10NMGDFB#30,
(12 × 12 mm, 0.5 mm pitch) R5F10NMJDFB#30, R5F10NMEDFB#50,
R5F10NMGDFB#50, R5F10NMJDFB#50
100 pins 100-pin plastic LFQFP mounted D R5F10NPJDFB#30, R5F10NPGDFB#30,
(14 × 14 mm, 0.5 mm pitch) R5F10NPJDFB#50, R5F10NPGDFB#50
Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/I1C.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
R01UH0587EJ0200 Rev.2.00 5
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1.3 Pin Configuration (Top View)
1.3.1 64-pin products
● 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)
P16/SEG10/INTP7/(SI00)/(RxD0)/(SDA00)
P13/SEG7/SI10/RxD1/SDA10/INTP6
P15/SEG9/(SCK00)/(SCL00)
P17/SEG11/(SO00)/(TxD0)
P12/SEG6/SCK10/SCL10
P14/SEG8/SO10/TxD1
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P10/SEG4
P11/SEG5
COM0
COM1
COM2
COM3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ANIP3 49 32 P70/SEG16/KR0/(INTP0)
ANIN3 50 31 P71/SEG17/KR1/(INTP1)
ANIP2 51 30 P72/SEG18/KR2/TI01/TO01/(INTP2)
ANIN2 52 29 P73/SEG19/KR3/(INTP3)/(PCLBUZ1)
AVRT 53 28 P74/SEG20/KR4/(INTP4)/(PCLBUZ0)
AVCM 54 27 P30/SEG24/RxD2/IrRxD/TI07/TO07/INTP5
AVSS 55 26 P31/SEG25/TxD2/IrTxD/TI06/TO06
AREGC 56 RL78/I1C 25 P125/VL3/INTP1/TI05/TO05/PCLBUZ1
ANIP1 57 24 VL4
ANIN1 58
(Top View) 23 VL2
ANIP0 59 22 VL1
ANIN0 60 21 P126/CAPL/(TI04)/(TO04)
P23/ANI3 61 20 P127/CAPH/(TI03)/(TO03)
P22/ANI2/EXLVD 62 19 P62/(TI02)/(TO02)/(RTCOUT)
P21/AVREFM /ANI1 63 18 P61/SDAA0/(TI01)/(TO01)
P20/AVREFP /ANI0 64 17 P60/SCLA0/(TI00)/(TO00)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD
P06/SI00/RxD0/SDA00/TI03/TO03/INTP4/TOOLRxD
P43/TI00/TO00/PCLBUZ0/RTCOUT
P05/SCK00/SCL00/TI04/TO04/INTP3
P40/TOOL0
P137/INTP0
P123/XT1
P121/X1
VRTC
REGC
P122/X2/EXCLK
P124/XT2/EXCLKS
VSS/EVSS0
VDD/EVDD0
VBAT
RESET
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0).
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P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD/SEG37
P16/SEG10/(SI00)/(RxD0)/(SDA00)
P81/SEG13/(SI10)/(RxD1)/(SDA10)
P17/SEG11/(SO00)/(TxD0)
P82/SEG14/(SO10)/(TxD1)
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P10/SEG4
P11/SEG5
P12/SEG6
P13/SEG7
P14/SEG8
COM0
COM1
COM2
COM3
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P06/SI00/RxD0/SDA00/TI03/TO03/TOOLRxD/SEG36 61 40 P83/SEG15
P05/SCK00/SCL00/TI04/TO04/INTP3/SEG35 62 39 P70/SEG16/KR0/(INTP0)
P04/SO10/TxD1/TI05/TO05/INTP4/SEG34 63 38 P71/SEG17/KR1/(INTP1)
P03/SI10/RxD1/SDA10/TI06/TO06/SEG33 64 37 P72/SEG18/KR2/(INTP2)
P02/SCK10/SCL10/TI07/TO07/INTP5/SEG32 65 36 P73/SEG19/KR3/(INTP3)
AVRT 68 33 P76/SEG22/KR6/(INTP6)
AVCM 69 32 P77/SEG23/KR7/(INTP7)
AVSS 70 RL78/I1C 31
30
P30/SEG24/(TI07)/(TO07)
AREGC 71 P31/SEG25/(TI06)/(TO06)
ANIP1 72 (Top View) 29 P32/SEG26/(PCLBUZ1)
ANIN1 73 28 P33/SEG27/(PCLBUZ0)
ANIP0 74 27 P125/VL3/INTP1/(TI05)/(TO05)
ANIN0 75 26 VL4
P23/ANI3 76 25 VL2
P22/ANI2/EXLVD 77 24 VL1
P21/AVREFM/ANI1 78 23 P126/CAPL/(TI04)/(TO04)
P20/AVREFP /ANI0 79 22 P127/CAPH/(TI03)/(TO03)
P56/TxD2/IrTxD 80 21 P62/(TI02)/(TO02)/(RTCOUT)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P41/INTP6/TI01/TO01/PCLBUZ1
RESET
VBAT
P55/RxD2/IrRxD
P40/TOOL0
P123/XT1
P137/INTP0
VRTC
P60/SCLA0/(TI00)/(TO00)
P61/SDAA0/(TI01)/(TO01)
P150/RTCOUT/RTCIC0
P152/RTCIC2
P151/RTCIC1
P124/XT2/EXCLKS
P121/X1
P122/X2/EXCLK
VDD
REGC
VSS/EVSS0
EVDD0
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).

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P16/SEG10/(SI00)/(RxD0)/(SDA00)
P81/SEG13/(SI10)/(RxD1)/(SDA10)
P84/SEG40/SI30/RxD3/SDA30
P17/SEG11/(SO00)/(TxD0)
P82/SEG14/(SO10)/(TxD1)
P57/SEG39/SCK30/SCL30
P85/SEG41/SO30/TxD3
P56/SEG38/TxD2/IrTxD
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P10/SEG4
P11/SEG5
P12/SEG6
P13/SEG7
P14/SEG8
COM0
COM1
COM2
COM3
EVDD1
EVSS1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P55/SEG37/RxD2/IrRxD 76 50 P83/SEG15
P54/SEG36 77 49 P70/SEG16/KR0/(INTP0)
P53/SEG35 78 48 P71/SEG17/KR1/(INTP1)
P52/SEG34 79 47 P72/SEG18/KR2/(INTP2)
P51/SEG33 80 46 P73/SEG19/KR3/(INTP3)
P50/SEG32 81 45 P74/SEG20/KR4/(INTP4)
ANIN2 85 41 P30/SEG24/(TI07)/(TO07)
AVRT 86 40 P31/SEG25/(TI06)/(TO06)
AVCM 39
AVSS
87
88
RL78/I1C 38
P32/SEG26/(PCLBUZ1)
P33/SEG27/(PCLBUZ0)
AREGC 89 (Top View) 37 P34/SEG28
ANIP1 90 36 P35/SEG29
ANIN1 91 35 P36/SEG30
ANIP0 92 34 P37/SEG31
ANIN0 93 33 P125/VL3/INTP1/(TI05)/(TO05)
P25/ANI5 94 32 VL4
P24/ANI4 95 31 VL2
P23/ANI3 96 30 VL1
P22/ANI2/EXLVD 97 29 P126/CAPL/(TI04)/(TO04)
P21/AVREFM/ANI1 98 28 P127/CAPH/(TI03)/(TO03)
P20/AVREFP/ANI0 99 27 P62/(TI02)/(TO02)/(RTCOUT)
P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD 100 26 P61/SDAA0/(TI01)/(TO01)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P04/SO10/TxD1/TI05/TO05/INTP4
P06/SI00/RxD0/SDA00/TI03/TO03/TOOLRxD
P60/SCLA0/(TI00)/(TO00)
P41/TI01/TO01/PCLBUZ1/INTP6
P03/SI10/RxD1/SDA10/TI06/TO06
P43/TI00/TO00/PCLBUZ0
P150/RTCOUT/RTCIC0
P40/TOOL0
P152/RTCIC2
P151/RTCIC1
P137/INTP0
P123/XT1
P42/INTP7
P121/X1
VRTC
P122/X2/EXCLK
P124/XT2/EXCLKS
REGC
VSS/EVSS0
VDD
EVDD0
RESET
VBAT
Cautions 1. Make EVSS1 the same potential as VSS/EVSS0.

2. Make EVDD1 the same potential as EVDD0.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).

2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD1 pins and connect
the VSS and EVSS1 pins to separate ground lines.
R01UH0587EJ0200 Rev.2.00 8
Aug 31, 2018
1.4 Pin Identification
ANI0 to ANI5: Analog Input P137: Port 13

ANIN0 to ANIN3, P150 to P152: Port 15
ANIP0 to ANIP3: Analog Input for ΔΣ ADC PCLBUZ0,
AREGC: Regulator Capacitance for ΔΣ ADC PCLBUZ1: Programmable Clock Output/Buzzer
AVCM: Control for ΔΣ ADC Output
AVREFM: A/D Converter Reference Potential REGC: Regulator Capacitance
(– side) Input RESET: Reset
AVREFP: A/D Converter Reference Potential RTCOUT: Real-time Clock Correction Clock
(+ side) Input (1 Hz/64 Hz) Output
AVRT: Reference Potential for ΔΣ ADC RTCIC0 to RTCIC2: RTC Time Capture Event Input
AVSS: Ground for ΔΣ ADC RxD0 to RxD3: Receive Data for UART
CAPH, CAPL: Capacitor Connection SCL00, SCL10,
for LCD Controller/Driver SCL30: Serial Clock Output for Simplified IIC
COM0 to COM7: Common Signal Output for LCD SDA00, SDA10,
Controller/Driver SDA30: Serial Data Input/Output for Simplified IIC
EVDD0, EVDD1: Power Supply for Port SCLA0 : Serial Clock Input/Output for IICA0
EVSS0, EVSS1: Ground for Port SDAA0: Serial Data Input/Output for IICA0
EXCLK: External Clock Input SCK00, SCK10,
(Main System Clock) SCK30: Serial Clock Input/Output for CSI
EXCLKS: External Clock Input SEG0 to SEG41: Segment Signal Output for LCD
(Subsystem clock) Controller/Driver
EXLVD: External Input for Low Voltage SI00, SI10, SI30: Serial Data Input for CSI
Detector SO00, SO10, SO30: Serial Data Output for CSI
INTP0 to INTP7: Interrupt Request From Peripheral TI00 to TI07: Timer Input
IrRxD: Receive Data for IrDA TO00 to TO07: Timer Output
IrTxD: Transmit Data for IrDA TOOL0: Data Input/Output for Tool
KR0 to KR7: Key Return TOOLRxD,
P02 to P07: Port 0 TOOLTxD: Data Input/Output for External Device
P10 to P17: Port 1 TxD0 to TxD3: Transmit Data for UART
P20 to P25: Port 2 VBAT: Battery Backup Power Supply
P30 to P37: Port 3 VDD: Power Supply
P40 to P43: Port 4 VL1 to VL4: Voltage for Driving LCD
P50 to P57: Port 5 VRTC: RTC Power Supply
P60 to P62: Port 6 VSS: Ground
P70 to P77: Port 7 X1, X2: Crystal Oscillator (Main System
P80 to P85: Port 8 Clock)
P121 to P127: Port 12 XT1, XT2: Crystal Oscillator (Subsystem Clock)
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1.5 Block Diagram
TIMER ARRAY
UNIT (8ch) PORT 0 3 P05 to P07
TI00/TO00/P43
(TI00/TO00/P60) ch0
PORT 1 8 P10 to P17
TI01/TO01/P72
(TI01/TO01/P61) ch1
32-bit MULTIPLY PORT 2 4 P20 to P23
TI02/TO02/P07 ACCUMULATOR
ch2
(TI02/TO02/P62)
2 ANI2/P22, ANI3/P23 PORT 3 2 P30, P31
TI03/TO03/P06 10-BIT A/D
ch3 CONVERTER (4ch)
(TI03/TO03/P127) ANI0/AVREFP /P20
ANI1/AVREFM /P21 PORT 4 2 P40, P43
TI04/TO04/P05
ch4
(TI04/TO04/P126)
KEY RETURN 5 KR0 to KR4
TI05/TO05/P125 ch5
TI06/TO06/P31 ch6 PORT 6 3 P60 to P62

ELC
TI07/TO07/P30
ch7 PORT 7 5 P70 to P74
RxD0/P06
(RxD0/P16) AES
8- BIT INTERVAL
TIMER 0 ch00 LCD 19 SEG0 to SEG11, SEG16 to SEG20, 4 P121 to P124
SEG24, SEG25 PORT 12
ch01 CONTROLLER/ 3 P125 to P127
DRIVER 8 COM0 to COM7
8- BIT INTERVAL VL1 to VL4 PORT 13 P137
RAM SPACE
TIMER 1 ch10 FOR LCD DATA CAPH
ch11 CAPL
SERIAL SDAA0/P61
SERIAL ARRAY INTERFACE IICA0 SCLA0/P60 POWER ON RESET/
POR/LVD
UNIT0 (2ch) VOLTAGE
CONTROL
VOLTAGE DETECTOR
UART0 REGC
RxD0/P06(RxD0/P16) REGULATOR
TxD0/P07(TxD0/P17) LINSEL
RL78
CPU RESET CONTROL
RxD1/P13 CODE FLASH MEMORY,
UART1 CORE
TxD1/P14 DATA FLASH MEMORY
SCK00/P05(SCK00/P15) MUL & DIV ON-CHIP DEBUG TOOL0/P40
SI00/P06(SI00/P16) CSI00
SO00/P07(SO00/P17) SYSTEM
SCK10/P12 CONTROL RESET
CSI10 X1/P121
SI10/P13 HIGH-SPEED
ON-CHIP X2/EXCLK/P122
SO10/P14 OSCILLATOR
SCL00/P05(SCL00/P15)
IIC00 MIDDLE-SPEED
SDA00/P06(SDA00/P16) ON-CHIP
OSCILLATOR (4 MHz)
SCL10/P12 RAM
IIC10
SDA10/P13
SERIAL ARRAY
RxD0/P06 (RxD0/P16)
UNIT1 (1ch)
INTP0/P137(INTP0/P70)
UART2 VDD/EVDD0 VSS/EVSS0 VBAT TOOLRxD/P06, INTP1/P125 (INTP1/P71)
RxD2/IrRxD/P30 TOOLTxD/P07
TxD2/IrTxD/P31 IrDA INTP2/P07(INTP2/P72),
INTERRUPT
CONTROL INTP3/P05(INTP3/P73),
4
INTP4/P06(INTP4/P74),
BUZZER OUTPUT PCLBUZ0/P43 INTP5/P30
2 (PCLBUZ0/P74), INTP6/P13,
PCLBUZ1/P125 2
CLOCK OUTPUT INTP7/P16
(PCLBUZ1/P73)
24-bit ΔΣ A/D CONTROL
WINDOW
CONVERTER (4ch)
WATCHDOG
ANIN0 BCD CRC TIMER
ΔΣ ADC0
ANIP0 ADJUSTMENT LOW-SPEED
12- BIT INTERVAL
ANIN1 ON-CHIP
ΔΣ ADC1 SUB CLOCK TIMER OSCILLATOR
ANIP1 FREQUENCY
DATA TRANSFER
ANIN2 CONTROLLER
MEASUREMENT
ΔΣ ADC2 INDEPENDENT POWER
ANIP2 (DTC) SUPPLY RTC
HIGH-SPEED ON-CHIP XT1/P123
ANIN3 SUB CLOCK
ΔΣ ADC3 OSCILLATOR CLOCK
ANIP3 BATTERY BACKUP OSCILLATOR XT2/EXCLKS/P124
FREQUENCY
FUNCTION Power
AVCM CORRECTION supply REAL-TIME
FUNCTION separation CLOCK RTCOUT/P43
AREGC
(RTCOUT/P62)
AVRT RTC POWER
OSCILLATION STOP
AVSS DETECTOR ON RESET
VSS VRTC
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
R01UH0587EJ0200 Rev.2.00 10
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TIMER ARRAY
(TI00/TO00/P60) ch0
PORT 1 8 P10 to P17
TI01/TO01/P41
(TI01/TO01/P61) ch1
ch2
(TI02/TO02/P62)
2 ANI2/P22, ANI3/P23 PORT 3 4 P30 to P33
ch3 CONVERTER (4ch)
ANI1/AVREFM/P21 PORT 4 2 P40, P41
TI04/TO04/P05
ch4
(TI04/TO04/P126)
TI05/TO05/P04 KEY RETURN 8 KR0 to KR7 PORT 5 2 P55, P56
ch5
(TI05/TO05/P125)
TI06/TO06/P03
ch6 PORT 6 3 P60 to P62
(TI06/TO06/P31) ELC
TI07/TO07/P02
(TI07/TO07/P30) ch7 PORT 7 8 P70 to P77
RxD0/P06
(RxD0/P16) AES
PORT 8 4 P80 to P83

8- BIT INTERVAL
TIMER 0 ch00 LCD 34 SEG0 to SEG27, SEG32 to SEG37 4 P121 to P124
PORT 12
ch01 CONTROLLER/ 3 P125 to P127
DRIVER 8 COM0 to COM7
8- BIT INTERVAL VL1 to VL4 PORT 13 P137
RAM SPACE
TIMER 1 ch10 FOR LCD DATA CAPH
ch11 CAPL
PORT 15 3 P150 to P152
SERIAL SDAA0/P61
SERIAL ARRAY INTERFACE IICA0 SCLA0/P60
POWER ON RESET/
UNIT0 (2ch) POR/LVD
VOLTAGE VOLTAGE
REGC CONTROL
UART0 REGULATOR DETECTOR
RxD0/P06(RxD0/P16)
TxD0/P07(TxD0/P17) LINSEL
RL78
RxD1/P03(RxD1/P81) CPU RESET CONTROL
UART1 CODE FLASH MEMORY,
TxD1/P04(TxD1/P82) CORE DATA FLASH MEMORY
SCK00/P05(SCK00/P15) MUL & DIV
CSI00 ON-CHIP DEBUG TOOL0/P40
SI00/P06(SI00/P16)
SO00/P07(SO00/P17)
SCK10/P02(SCK10/P80) SYSTEM RESET
SI10/P03(SI10/P81) CSI10 CONTROL X1/P121
SO10/P04(SO10/P82) HIGH-SPEED X2/EXCLK/P122
SCL00/P05(SCL00/P15) ON-CHIP
IIC00 OSCILLATOR
SDA00/P06(SDA00/P16)
MIDDLE-SPEED
SCL10/P02(SCL10/P80) RAM ON-CHIP
IIC10 OSCILLATOR (4 MHz)
SDA10/P03(SDA10/P81)
PLL CLOCK (32MHz)
SERIAL ARRAY
UNIT1 (1ch) RxD0/P06 (RxD0/P16)
UART2 VDD EVDD0 VSS/EVSS VBAT TOOLRxD/P06,
RxD2/IrRxD/P55 INTP1/P125 (INTP1/P71)
TOOLTxD/P07
TxD2/IrTxD/P56 IrDA INTP2/P07(INTP2/P72),
INTERRUPT
CONTROL INTP3/P05(INTP3/P73),
4
INTP4/P04(INTP4/P74),
BUZZER OUTPUT (PCLBUZ0/P33), INTP5/P02(INTP5/P75)
2 PCLBUZ1/P41 INTP6/P41(INTP6/P76),
(PCLBUZ1/P32) 2
CLOCK OUTPUT (INTP7/P77)
24-bit ΔΣ A/D CONTROL
CONVERTER (3ch) WINDOW
WATCHDOG
ANIN0 BCD CRC TIMER
ΔΣ ADC0
ANIP0 ADJUSTMENT LOW-SPEED
12- BIT INTERVAL
ANIN1 ON-CHIP
ΔΣ ADC1 SUB CLOCK TIMER OSCILLATOR
ANIP1 FREQUENCY
DATA TRANSFER
ANIN2 CONTROLLER
MEASUREMENT
ΔΣ ADC2 INDEPENDENT POWER
ANIP2 (DTC) SUPPLY RTC
HIGH-SPEED ON-CHIP XT1/P123
OSCILLATOR CLOCK SUB CLOCK
BATTERY BACKUP OSCILLATOR XT2/EXCLKS/P124
FREQUENCY
FUNCTION Power
AVCM CORRECTION supply 3 RTCIC0-RTCIC2
REAL-TIME
AREGC FUNCTION separation CLOCK RTCOUT/P150
(RTCOUT/P62)
AVRT
OSCILLATION STOP RTC POWER
AVSS DETECTOR ON RESET
VSS VRTC
R01UH0587EJ0200 Rev.2.00 11
Aug 31, 2018
TIMER ARRAY
TI00/TO00/P43
ch0
(TI00/TO00/P60) PORT 1 8 P10 to P17
TI01/TO01/P41
(TI01/TO01/P61) ch1
ch2
(TI02/TO02/P62)
4 ANI2/P22 to ANI5/P25 PORT 3 8 P30 to P37
ch3 CONVERTER (6ch)
ANI1/AVREFM/P21
TI04/TO04/P05 PORT 4 4 P40 to P43
ch4
(TI04/TO04/P126)
TI05/TO05/P04 KEY RETURN 8 KR0 to KR7 8
ch5 PORT 5 P50 to P57
(TI05/TO05/P125)
TI06/TO06/P03
(TI06/TO06/P31) ch6 ELC PORT 6 3 P60 to P62
TI07/TO07/P02
(TI07/TO07/P30) ch7
RxD0/P06 PORT 7 8 P70 to P77
(RxD0/P16) AES
8- BIT INTERVAL PORT 8 6 P80 to P85

TIMER 0 ch00
LCD 42 SEG0 to SEG41
ch01 4 P121 to P124
CONTROLLER/ PORT 12
DRIVER 8 COM0 to COM7 3 P125 to P127
8- BIT INTERVAL
TIMER 1 VL1 to VL4
ch10 RAM SPACE PORT 13 P137
ch11 FOR LCD DATA CAPH
CAPL
PORT 15 3 P150-P152
SERIAL ARRAY SERIAL SDAA0/P61
UNIT0 (2ch) INTERFACE IICA0 SCLA0/P60
POWER ON RESET/
RxD0/P06(RxD0/P16) UART0 POR/LVD
VOLTAGE
VOLTAGE CONTROL
TxD0/P07(TxD0/P17) LINSEL REGC DETECTOR
REGULATOR
RxD1/P03(RxD1/P81)
UART1 RL78
TxD1/P04(TxD1/P82)
CPU RESET CONTROL
CODE FLASH MEMORY,
SCK00/P05(SCK00/P15) CORE DATA FLASH MEMORY
SI00/P06(SI00/P16) CSI00
MUL & DIV
SO00/P07(SO00/P17) ON-CHIP DEBUG TOOL0/P40
SCK10/P02(SCK10/P80)
SI10/P03(SI10/P81) CSI10
SYSTEM RESET
SO10/P04(SO10/P82) CONTROL X1/P121
IIC00 HIGH-SPEED X2/EXCLK/P122
SDA00/P06(SDA00/P16) ON-CHIP
OSCILLATOR
IIC10 MIDDLE-SPEED
SDA10/P03(SDA10/P81) RAM ON-CHIP
OSCILLATOR (4 MHz)
SERIAL ARRAY PLL CLOCK (32MHz)

UNIT1 (2ch)
RxD0/P06 (RxD0/P16)
RxD2/IrRxD/P55 UART2
TxD2/IrTxD/P56 IrDA VDD EVDD0 EVDD1 VSS/EVSS0 EVSS1 VBAT TOOLRxD/P06, INTP1/P125 (INTP1/P71)
TOOLTxD/P07
RxD3/P84 INTP2/P07(INTP2/P72),
UART3 INTERRUPT
TxD3/P85 CONTROL INTP3/P05(INTP3/P73),
4
SCK30/P57 INTP4/P04(INTP4/P74),
SI30/P84 CSI30 BUZZER OUTPUT PCLBUZ0/P43 INTP5/P02(INTP5/P75)
SO30/P85 2 (PCLBUZ0/P33), INTP6/P41(INTP6/P76),
SCL30/P57 PCLBUZ1/P41 2
CLOCK OUTPUT INTP7/P42(INTP7/P77)
IIC30 (PCLBUZ1/P32)
SDA30/P84 CONTROL WINDOW
24-bit ΔΣ A/D WATCHDOG
CONVERTER (4ch) CRC TIMER
BCD
ANIN0 ADJUSTMENT LOW-SPEED
ΔΣ ADC0 12- BIT INTERVAL
ANIP0 ON-CHIP
SUB CLOCK TIMER OSCILLATOR
ANIN1 FREQUENCY
ΔΣ ADC1 DATA TRANSFER
ANIP1 MEASUREMENT INDEPENDENT POWER
CONTROLLER
ANIN2 (DTC) SUPPLY RTC
ΔΣ ADC2 HIGH-SPEED ON-CHIP
ANIP2 SUB CLOCK XT1/P123
OSCILLATOR CLOCK XT2/EXCLKS/P124
ANIN3 BATTERY BACKUP OSCILLATOR
ΔΣ ADC3 FREQUENCY Power
ANIP3 FUNCTION
CORRECTION supply REAL-TIME 3 RTCIC0-RTCIC2
FUNCTION separation CLOCK RTCOUT/P150
AVCM (RTCOUT/P62)
AREGC RTC POWER
OSCILLATION STOP
AVRT DETECTOR ON RESET
AVSS
VSS VRTC
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1.6 Outline of Functions

(1/3)
Item 64-pin 80-pin 100-pin
R5F10NLEDFB R5F10NLGDFB R5F10NMEDFB R5F10NMGDFB R5F10NMJDFB R5F10NPGDFB R5F10NPJDFB

Code flash memory (KB) 64 KB 128 KB 64 KB 128 KB 256 KB 128 KB 256 KB
Data flash memory (KB) 2 KB
RAM (KB) 6 KB 8 KBNote 1 6 KB 8 KBNote 1 16 KBNote 2 8 KBNote 1 16 KBNote 2
Address space 1 MB
Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock clock HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.5 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.9 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.7 to 5.5 V),
LP (Low-power main) mode: 1 MHz (VDD = 1.9 to 5.5 V)
High -speed on-chip HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
oscillator clock (fIH) HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.5 to 5.5 V),
MAX.: 24 MHz HS (High-speed main) mode: 1 to 12 MHz (VDD = 2.4 to 5.5 V),
Middle -speed on- LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.9 to 5.5 V),
chip oscillator clock LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.7 to 5.5 V),
(fIM) LP (Low-power main) mode: 1 MHz (VDD = 1.9 to 5.5 V)
MAX.: 4 MHz
PLL clock (fPLL) - HS (High-speed main) mode: 32 MHz
(VDD = 2.8 to 5.5 V)
Subsystem Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
clock oscillator clock 32.768 kHz (TYP.): VDD = 1.7 to 5.5 V
(fSX)
Low-speed on-chip 15 kHz (TYP.): VDD = 1.7 to 5.5V
oscillator clock (fIL)
High-speed on-chip oscillator clock Correct the frequency of the high-speed on-chip oscillator clock by the subsystem clock.
frequency correction function
General-purpose register 8 bits × 8 registers × 4 banks
Minimum instruction execution time 0.03125 µs (PLL clock: fPLL = 32 MHz selection)
0.04167 µs (High-speed on-chip oscillator: fIH = 24 MHz operation)
30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation)
66.6 µs (Low-speed on-chip oscillator: fIL = 15 kHz operation)
Instruction set ● Data transfer (8/16 bits)
● Adder and subtractor/logical operation (8/16 bits)
● Multiplication (16 bits × 16 bits), division (32 bits ÷ 32 bits)
● Multiplication and accumulation (16 bits × 16 bits + 32 bits)
● Rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc.
I/O port Total 35 52 68
CMOS I/O 27 44 60
CMOS input 5 5 5
CMOS output - - -
N-ch O.D I/O 3 3 3
(6 V tolerance)
Notes 1. In the case of the 8 KB, this is about 7 KB when the self-programming function is used.
2. In the case of the 16 KB, this is about 15 KB when the self-programming function is used.
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(2/3)

Timer 16-bit timer TAU 8 channels
Watchdog timer 1 channel
12-bit interval timer 1 channel
8/16-bit interval timer 4 channels (8-bit)/2 channels (16-bit)
Independent power 1 channel
supply real-time
clock (RTC)
Oscillation stop 1 channel
detection circuit
Timer output Timer outputs: 8 channels
PWM outputs: 7Note 1
RTC output 1 channel
● 1 Hz/64 Hz (subsystem clock: fSUB = 32.768 kHz)
RTC time capture - 3 channels
input
Clock output/buzzer output 2
● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
● 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
10-bit resolution A/D converter 4 channels 4 channels 6 channels
24-Bit ΔΣ A/D Converter 4 channels 3 channels 4 channels
SNDR Typ. 80 dB (gain ×1)
Min. 69 dB (gain ×16)
Min. 65 dB (gain ×32)
Sampling frequency 3.906 kHz/1.953 kHz
PGA ×1, ×2, ×4, ×8, ×16, ×32
2C:
Serial CSI/UART/simplified I 2 channels 2 channels 3 channels
interface UART/IrDA 1 channel
2
I C bus 1 channel
32-bit multiplier and multiply- 32 bits × 32 bits = 64 bits (Unsigned or signed) (5 clock)
accumulator 32 bits × 32 bits + 64 bits = 64 bits (Unsigned or signed) (5 clock)
<R> Data transfer controller (DTC) 36 sources 38 sources

Event link Event input 9
controller (ELC) Event trigger input 13
LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division method
are switchable.
Segment signal output 19 (15)Note 2 34 (30)Note 2 42 (38)Note 2
Common signal output 4 (8)Note 2
Vectored Internal 41 41 44
interrupt sources External 9 12 12
Notes 1. The number of outputs varies, depending on the setting of channels in use and the number of the master
(see 8.9.3 Operation as multiple PWM output function).
2. The values in parentheses are the number of signal outputs when 8 com is used.
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(3/3)

Key interrupt input 5 8
AES circuit Cipher modes of operation: GCM/ECB/CBC
Encryption key length: 128/192/256-bit
Reset MCU ● Reset by RESET pin
● Internal reset by watchdog timer
● Internal reset by power-on-reset of internal VDDNote 1 power supply
● Internal reset by voltage detector of internal VDDNote 1 power supply
● Internal reset by illegal instruction executionNote 2
● Internal reset by RAM parity error
● Internal reset by illegal-memory access
RTC ● RTC circuit reset by RTC Power-on-reset
Power-on-reset circuit Internal VDD ● Power-on-reset: 1.51 V (TYP.)
Note 1
● Power-down-reset: 1.50 V (TYP.)
VRTC ● RTC Power-on-reset: 1.52 V (TYP.)
● RTC Power-down-reset: 1.50 V (TYP.)
Voltage detector Internal VDD ● Rising edge: 1.77 V to 4.06 V (13 stages)
Note 1
● Falling edge: 1.73 V to 3.98 V (13 stages)
VDD ● Rising edge: 2.54 V to 3.78 V (6 stages)
VBAT ● Rising edge: 2.12 V to 2.74 V (7 stages)
VRTC ● Rising edge: 2.22 V to 2.84 V (4 stages)
EXLVD ● Rising edge: 1.33 V
● Falling edge: 1.28 V
Battery backup CPU VDD/VBAT
function ΔΣ A/D VDD/VBAT
Converter
RTC VRTC (independent power supply)
On-chip debug function Provided
Power supply voltage VDD = 1.7 to 5.5 V
Operating ambient temperature TA = –40 to +85°C

2. This reset occurs when instruction code FFH is executed.
This reset does not occur during emulation using an in-circuit emulator or an on-chip debugging emulator.
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RL78/I1C CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1 Port Function
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 2-1. Pin I/O Buffer Power Supplies
(1) 64-pin products
Power Supply Corresponding Pins

VDD Port pins other than P20 to P23, P121 to P124, and P137Note 1
VDD or VBATNotes 2, 3 ● P20 to P23, P121, P122, and P137
● RESET, REGC
● ANIP0 to ANIP3, ANIN0 to ANIN3
VRTC P123, P124
(2) 80-pin products

EVDD Port pins other than P20 to P23, P121 to P124, P137 and P150 to
P152Note 1
VDD or VBATNotes 2, 3 ● P20 to P23, P121, P122, P137, and P150 to P152
● RTCIC0 to RTCIC2
● RESET, REGC
VRTC P123, P124
(3) 100-pin products

EVDD0 Port pins other than P20 to P25, P121 to P124, P137 and P150 to
P152Note 1
VDD or VBATNotes 2, 3 ● P20 to P25, P121, P122, P137 and P150 to P152
● RTCIC0 to RTCIC2
● RESET, REGC
VRTC P123, P124
Notes 1. When using the battery backup function, the power supply of the internal I/O buffer of this pin is powered
from the VDD pin even when switch to power from VBAT pin. If the power of the VDD pin is lost, make sure
the input voltage does not exceed the absolute maximum rating.
2. The power supply pin for the I/O buffers can be switched between VDD and VBAT by using the battery
backup function.
3. The input/output signal voltage of the pin that is defined as “VDD or VBAT” must match the supply voltage of
the I/O buffer.
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Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.

(1/2)
Function Name Pin Type I/O After Reset Alternate Function Function
Released
P05 8-5-10 I/O Input port SCK00/SCL00/TI04/ Port 0.
TO04/INTP3 3-bit I/O port.
P06 SI00/RxD0/TI03/TO03/ Input/output can be specified in 1-bit units.
SDA00/INTP4/TOOLRxD Use of an on-chip pull-up resistor can be specified
by software setting at input port.
P07 7-5-10 SO00/TxD0/TI02/TO02/ Input of P05 and P06 can be set to TTL input
INTP2/TOOLTxD buffer.
Output of P05 to P07 can be set to N-ch open-
drain output (VDD tolerance).
P10 7-5-4 I/O Digital input SEG4 Port 1.
P11 invalidNote 1 SEG5 8-bit I/O port.
Input/output can be specified in 1-bit units.
P12 8-5-10 SEG6/SCK10/SCL10
Use of an on-chip pull-up resistor can be specified
P13 SEG7/INTP6/SI10/RxD1/ by software setting at input port.
SDA10/ Input of P12, P13, P15, and P16 can be set to TTL
P14 7-5-10 SEG8/SO10/TxD1 input buffer.
P15 8-5-10 SEG9/(SCK00)/(SCL00)
drain output (VDD tolerance).
P16 SEG10/INTP7/(SI00)/ Can be set to LCD outputNote 2.
(RxD0)/(SDA00)
P17 7-5-10 SEG11/(SO00)/(TxD0)
P20 4-3-3 I/O Analog input AVREFP/ANI0 Port 2.
P21 port AVREFM/ANI1 4-bit I/O port.
P22 4-17-1 ANI2/EXLVD
Can be set to analog inputNote 3.
P23 4-3-3 ANI3
P30 8-5-10 I/O Digital input SEG24/INTP5/TI07/ Port3.
invalidNote 1 TO07/RxD2/IrRxD 2-bit I/O port.
P31 7-5-10 SEG25/TI06/TO06/TxD2/ Input/output can be specified in 1-bit units.
IrTxD Use of an on-chip pull-up resistor can be specified
by software setting at input port.
Can be set to LCD outputNote 2.
Input of P30 can be set to TTL input buffer.
Output of P31 can be set to N-ch open drain
output(VDD tolerance).
Notes 1. “Digital input invalid” refers to the state in which all the digital outputs, digital inputs, and LCD outputs are
disabled.
2. Digital or LCD for each pin can be selected with the port mode register x (PMx) and the LCD port function
register x (PFSEGx) (can be set in 1-bit unit).
3. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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Released
P40 7-1-3 I/O Input port TOOL0 Port 4.

P43 TI00/TO00/PCLBUZ0/ 2-bit I/O port.
RTCOUT Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
P60 12-1-2 I/O Input port SCLA0/(TI00)/(TO00) Port 6.

P61 SDAA0/(TI01)/(TO01) 3-bit I/O port.
P62 12-1-1 (TI02)/(TO02)/
Output of P60 to P62 can be set to N-ch open-drain
(RTCOUT)
output (6 V tolerance).
P70 7-5-4 I/O Digital input SEG16/KR0/(INTP0) Port 7.
P71 invalidNote 1 SEG17/KR1 /(INTP1) 5-bit I/O port.
P72 SEG18/KR2/TI01/
TO01/(INTP2)
P73 SEG19/KR3/(INTP3)/ Can be set to LCD outputNote 2.
(PCLBUZ1)
P74 SEG20/KR4/(INTP4)/
(PCLBUZ0)
P121 2-2-1 Input Input port X1 Port 12.
P122 X2/EXCLK 3-bit I/O port and 4-bit input only port.
For only P125 to P127, input/output can be specified in
P123 XT1
1-bit units.
P124 XT2/EXCLKS For only P125 to P127, use of an on-chip pull-up resistor
P125 7-5-6 I/O Digital input VL3/INTP1/TI05/TO05/ can be specified by a software setting at input port.
invalid Note 1
PCLBUZ1 P125 to P127 can be set to LCD outputNote 2.
P126 7-5-5 CAPL/(TI04)/(TO04)

P127 CAPH/(TI03)/(TO03)
P137 2-1-2 Input Input port INTP0 Port 13.
1-bit input only port.
RESET 3-1-1 Input – – Input only pin for external reset.

Use of an on-chip pull-up resistor can be always
specified.
When external reset is not used, leave open.
disabled.
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Released
P02 8-5-10 I/O Digital input SEG32/SCK10/SCL10/ Port 0.
invalidNote 1 TI07/TO07/INTP5 6-bit I/O port.
P03 SEG33/SI10/RxD1/TI06/
TO06/SDA10 by a software setting at input port.
P04 7-5-10 SEG34/SO10/TxD1/TI05/ Input of P02, P03, P05, and P06 can be set to TTL
TO05/INTP4 input buffer.
P05 8-5-10 SEG35/SCK00/SCL00/
drain output (EVDD tolerance).
TI04/TO04/INTP3
P06 SEG36/SI00/RxD0/TI03/
TO03/SDA00/TOOLRxD
P07 7-5-10 SEG37/SO00/TxD0/TI02/
TO02/INTP2/TOOLTxD
invalidNote 1 8-bit I/O port.
P11 SEG5
P12 SEG6 Use of an on-chip pull-up resistor can be specified
P13 SEG7 by a software setting at input port.
Input of P15 and P16 can be set to TTL input
P14 SEG8 buffer.
P15 8-5-10 SEG9/(SCK00)/(SCL00) Output of P15 to P17 can be set to N-ch open-
drain output (EVDD tolerance).
P16 SEG10/(SI00)/
(RxD0)/(SDA00)
P17 7-5-10 SEG11/(SO00)/(TxD0)
port 4-bit I/O port.
P21 AVREFM/ANI1
P22 4-17-1 ANI2/EXVLD Can be set to analog inputNote 3.
P23 4-3-3 ANI3
P30 7-5-4 I/O Digital input SEG24/(TI07)/(TO07) Port 3.
invalidNote 1 4-bit I/O port.
P31 SEG25/(TI06)/(TO06)
P32 SEG26/(PCLBUZ1) Use of an on-chip pull-up resistor can be specified
P33 SEG27/(PCLBUZ0) by a software setting at input port.
2-bit I/O port.
P41 8-1-3 TI01/TO01/PCLBUZ1/
INTP6
by a software setting at input port.
disabled.
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Released
P55 8-5-10 I/O Input port RxD2/IrRxD Port 5.

P56 TxD2/IrTxD 2-bit I/O port.
Input of P55 can be set to TTL input buffer.
Output of P56 can be set to N-ch open-drain output
(EVDD tolerance).
P62 12-1-1 (TI02)/(TO02)/
(RTCOUT)
output (6 V tolerance).
P71 invalidNote 1 SEG17/KR1/(INTP1) 8-bit I/O port.
P72 SEG18/KR2/(INTP2)
P73 SEG19/KR3/(INTP3) by a software setting at input port.
P74 SEG20/KR4/(INTP4) Can be set to LCD outputNote 2.
P80 8-5-10 I/O Digital input SEG12/(SCL10)/ Port 8.
invalidNote 1 (SCK10) 4-bit I/O port.
P81 SEG13/(RxD1)/ Input/output can be specified in 1-bit units.
(SDA10)/(SI10) Use of an on-chip pull-up resistor can be specified
P82 7-5-10 SEG14/(TxD1) /(SO10)
Input of P80 and P81 can be set to TTL input buffer.
P83 7-5-4 SEG15 Output of P80 to P82 can be set to N-ch open-drain
output (EVDD tolerance).
disabled.
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Released

P122 X2/EXCLK 3-bit I/O port and 4-bit input dedicated port.
For pins P125 to P127, input/output can be specified
P123 XT1
in 1-bit units.
P124 XT2/EXCLKS For pins P125 to P127, use of an on-chip pull-up
P125 7-5-6 I/O Digital input VL3/INTP1/(TI05)/(TO05) resistor can be specified by a software setting at input
invalidNote 1 port.
P126 7-5-5 CAPL/(TI04)/(TO04)
For pins P125 to P127, can be set to LCD outputNote 2.
P127 CAPH/(TI03)/(TO03)
1-bit input dedicated port.
P150 4-3-6 I/O Input port RTCOUT/RTCIC0 Port 15.

P151 RTCIC1 3-bit I/O port.
P152 RTCIC2
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
specified.
disabled.
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(1/3)
Function Pin Type I/O After Reset Alternate Function Function
Name Released
P02 8-5-10 I/O Input port SCK10/SCL10/TI07/ Port 0.

TO07/INTP5 6-bit I/O port.
P03 SI10/RxD1/TI06/TO06/ Input/output can be specified in 1-bit units.
SDA10 Use of an on-chip pull-up resistor can be specified by a
P04 7-5-10 SO10/TxD1/TI05/TO05/
Input of P02, P03, P05, and P06 can be set to TTL input
INTP4
buffer.
P05 8-5-10 SCK00/SCL00/TI04/ Output of P02 to P07 can be set to N-ch open-drain
TO04/INTP3 output (EVDD tolerance).
P06 SI00/RxD0/TI03/TO03/
SDA00/TOOLRxD
P07 7-5-10 SO00/TxD0/TI02/TO02/
INTP2/TOOLTxD
P11 invalidNote 1 SEG5 8-bit I/O port.
P12 SEG6
P13 SEG7 software setting at input port.
P14 SEG8 Input of P15 and P16 can be set to TTL input buffer.
P15 8-5-10 SEG9/(SCK00)/(SCL00)
P16 SEG10/(SI00)/(RxD0)/ Can be set to LCD outputNote 2.
(SDA00)
P17 7-5-10 SEG11/(SO00)/(TxD0)
P21 AVREFM/ANI1 6-bit I/O port.
P22 4-17-1 ANI2/EXLVD
Can be set to analog inputNote 3.
P23 4-3-3 ANI3
P24 ANI4
P25 ANI5
disabled.
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Name Released
P30 7-5-4 I/O Digital input SEG24/(TI07)/(TO07) Port 3.

P31 invalidNote 1 SEG25/(TI06)/(TO06) 8-bit I/O port.
P32 SEG26/(PCLBUZ1)
P33 SEG27/(PCLBUZ0) software setting at input port.
P34 SEG28 Can be set to LCD outputNote 2.
P35 SEG29
P36 SEG30
P37 SEG31
P41 8-1-3 TI01/TO01/PCLBUZ1/ 4-bit I/O port.
INTP6 Input/output can be specified in 1-bit units.
P42 INTP7
P43 7-1-3 TI00/TO00/PCLBUZ0
P51 invalidNote 1 SEG33 8/-bit I/O port.
P52 SEG34
P53 SEG35 software setting at input port.
P54 SEG36 Input of P55 and P57 can be set to TTL input buffer.
Output of P56 and P57 can be set to N-ch open-drain
P55 8-5-10 SEG37/RxD2/IrRxD
P56 SEG38/TxD2/IrTxD Can be set to LCD outputNote 2.
P57 SEG39/SCK30/SCL30
P62 12-1-1 (TI02)/(TO02)/
(RTCOUT)
output (6V tolerance).
disabled.
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Name Released

P71 invalidNote 1 SEG17/KR1/(INTP1) 8-bit I/O port.
P73 SEG19/KR3/(INTP3) software setting at input port.
P74 SEG20/KR4/(INTP4) Can be set to LCD outputNote 2.
P80 8-5-10 I/O Digital input SEG12/(SCL10)/ Port 8.
invalidNote 1 (SCK10) 6-bit I/O port.
P81 SEG13/(RxD1)/ Input/output can be specified in 1-bit units.
(SDA10)/(SI10) Use of an on-chip pull-up resistor can be specified by a
P82 7-5-10 SEG14/(TxD1) /(SO10)
Input of P80, P81, and P84 can be set to TTL input
P83 7-5-4 SEG15 buffer.
P84 8-5-10 SI30/RxD3/SDA30/ Output of P80 to P82, P84, and P85 can be set to N-ch
SEG40 open-drain output (EVDD tolerance).
Can be set to LCD output Note 2.
P85 7-5-10 SO30/TxD3/SEG41
P122 X2/EXCLK 3-bit I/O port and 4-bit input only port.
For only P125 to P127, input/output can be specified in 1-
P123 XT1
bit units.
P124 XT2/EXCLKS For only P125 to P127, use of an on-chip pull-up resistor
P125 7-5-6 I/O Digital input VL3/INTP1/(TI05)/(TO05) can be specified by a software setting at input port.
invalidNote 1 CAPL/(TI04)/(TO04) P125 to P127 can be set to LCD output Note 2.
P126 7-5-5
P127 CAPH/(TI03)/(TO03)
1-bit input only port.
P150 4-3-6 I/O Input port RTCOUT/RTCIC0 Port 15.

P151 RTCIC1 3-bit I/O port.
P152 RTCIC2
specified.
disabled.
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2.2 Functions Other than Port Pins
2.2.1 With functions for each product

(1/2)
Function Name 100-pin 80-pin 64-pin Function Name 100-pin 80-pin 64-pin Function Name 100-pin 80-pin 64-pin
ANI0 √ √ √ RxD2 √ √ √ VL1 √ √ √
ANI1 √ √ √ RxD3 √ – – VL2 √ √ √
ANI2 √ √ √ TxD0 √ √ √ VL3 √ √ √
ANI3 √ √ √ TxD1 √ √ √ VL4 √ √ √
ANI4 √ – – TxD2 √ √ √ CAPH √ √ √
ANI5 √ – – TxD3 √ – – CAPL √ √ √
ANIN0 √ √ √ SCK00 √ √ √ X1 √ √ √
ANIN1 √ √ √ SCK10 √ √ √ X2 √ √ √
ANIN2 √ √ √ SCK30 √ – – EXCLK √ √ √
ANIN3 √ – √ SI00 √ √ √ XT1 √ √ √
ANIP0 √ √ √ SI10 √ √ √ XT2 √ √ √
ANIP1 √ √ √ SI30 √ – – EXCLKS √ √ √
ANIP2 √ √ √ SO00 √ √ √ VDD √ √ √
ANIP3 √ – √ SO10 √ √ √ EVDD0 √ √ √
INTP0 √ √ √ SO30 √ – – EVDD1 √ – –
INTP1 √ √ √ SCL00 √ √ √ VBAT √ √ √
INTP2 √ √ √ SCL10 √ √ √ VRTC √ √ √
INTP3 √ √ √ SCL30 √ – – AVREFP √ √ √
INTP4 √ √ √ SDA00 √ √ √ AVREFM √ √ √
INTP5 √ √ √ SDA10 √ √ √ VSS √ √ √
INTP6 √ √ √ SDA30 √ – – EVSS0 √ √ √
INTP7 √ √ √ SDAA0 √ √ √ EVSS1 √ – –
KR0 √ √ √ SCLA0 √ √ √ AVRT √ √ √
KR1 √ √ √ IrRxD √ √ √ AVCM √ √ √
KR2 √ √ √ IrTxD √ √ √ AREGC √ √ √
KR3 √ √ √ TI00 √ √ √ AVSS √ √ √
KR4 √ √ √ TI01 √ √ √ TOOLRxD √ √ √
KR5 √ √ – TI02 √ √ √ TOOLTxD √ √ √
KR6 √ √ – TI03 √ √ √ TOOL0 √ √ √
KR7 √ √ – TI04 √ √ √ COM0 √ √ √
RTCIC0 √ √ – TI05 √ √ √ COM1 √ √ √
RTCIC1 √ √ – TI06 √ √ √ COM2 √ √ √
RTCIC2 √ √ – TI07 √ √ √ COM3 √ √ √
EXLVD √ √ √ TO00 √ √ √ COM4 √ √ √
PCLBUZ0 √ √ √ TO01 √ √ √ COM5 √ √ √
PCLBUZ1 √ √ √ TO02 √ √ √ COM6 √ √ √
RTCOUT √ √ √ TO03 √ √ √ COM7 √ √ √
REGC √ √ √ TO04 √ √ √ SEG0 √ √ √
RESET √ √ √ TO05 √ √ √ SEG1 √ √ √
RxD0 √ √ √ TO06 √ √ √ SEG2 √ √ √
RxD1 √ √ √ TO07 √ √ √ SEG3 √ √ √
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Function Name 100-pin 80-pin 64-pin Function Name 100-pin 80-pin 64-pin Function Name 100-pin 80-pin 64-pin
SEG4 √ √ √ SEG17 √ √ √ SEG30 √ – –
SEG5 √ √ √ SEG18 √ √ √ SEG31 √ – –
SEG6 √ √ √ SEG19 √ √ √ SEG32 √ √ –
SEG7 √ √ √ SEG20 √ √ √ SEG33 √ √ –
SEG8 √ √ √ SEG21 √ √ – SEG34 √ √ –
SEG9 √ √ √ SEG22 √ √ – SEG35 √ √ –
SEG10 √ √ √ SEG23 √ √ – SEG36 √ √ –
SEG11 √ √ √ SEG24 √ √ √ SEG37 √ √ –
SEG12 √ √ – SEG25 √ √ √ SEG38 √ – –
SEG13 √ √ – SEG26 √ √ – SEG39 √ – –
SEG14 √ √ – SEG27 √ √ – SEG40 √ – –
SEG15 √ √ – SEG28 √ – – SEG41 √ – –
SEG16 √ √ √ SEG29 √ – –
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2.2.2 Description of Functions

(1/2)
Function Name I/O Function
ANI0 to ANI5 Input A/D converter analog input (see Figure 15-45 Analog Input Pin Connection)
ANIN0 to ANIN3 Input 24-bit ΔΣ-type A/D converter analog input.
These are the negative input pins.
ANIP0 to ANIP3 Input 24-bit ΔΣ-type A/D converter analog input.
These are the positive input pins.
INTP0 to INTP7 Input External interrupt request input.
Specified the valid edge: Rising edge, falling edge, or both rising and falling edges.
INTP0 is a pin that operates at an internal VDD. When using a battery backup function,
the input threshold value is adjusted to the selected power supply (VDD or VBAT).
Maximum allowed input voltage is 5.5 V. If unused, pull up to VBAT or VDD, whichever is
higher.
PCLBUZ0, PCLBUZ1 Output Clock output/buzzer output
REGC – Pin for connecting regulator output stabilization capacitance for internal operation.
Connect this pin to VSS via a capacitor (0.47 to 1 µF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal
voltage.
RTCOUT Output Independent power supply RTC (1 Hz/64 Hz) output
RESET Input This is the active-low system reset input pin.
An on-chip pull-up resistor is always valid.
When the external reset pin is not used, leave open.
RxD0 to RxD3 Input Serial data input pins of serial interface UART0 to UART3
TxD0 to TxD3 Output Serial data output pins of serial interface UART0 to UART3
SCK00, SCK10, SCK30 I/O Serial clock I/O pin of serial interface CSI00, CSI10, and CSI30
SI00, SI10, SI30 Input Serial data input pin of serial interface CSI00, CSI10, and CSI30
SO00, SO10, SO30 Output Serial data output pin of serial interface CSI00, CSI10, and CSI30
IrRxD Input Receive data for IrDA
IrTxD Output Transmit data for IrDA
SCL00, SCL10, SCL30 Output Serial clock output pins of serial interface IIC00, IIC10, and IIC30
SDA00, SDA10, SDA30 I/O Serial data I/O pins of serial interface IIC00, IIC10, and IIC30
SCLA0 I/O Serial clock I/O pins of serial interface IICA0
SDAA0 I/O Serial data I/O pins of serial interface IICA0
TI00 to TI07 Input The pins for inputting an external count clock/capture trigger to 16-bit timers 00 to 07
TO00 to TO07 Output Timer output pins of 16-bit timers 00 to 07
VL1 to VL4 – LCD drive voltage
CAPH, CAPL – Connecting a capacitor for LCD controller/driver
X1, X2 – If an external 24-bit ΔΣ type A/D converter is used for external clock input, a 12 MHz
oscillator must be connected.
EXCLK Input External clock input for main system clock
XT1, XT2 – Resonator connection for subsystem clock
EXCLKS Input External clock input for subsystem clock
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Function Name I/O Function
VDD – <64-pin >

Positive power supply for all pins other than P123 and P124.
Power supply for the 24-bit ΔΣ type A/D converter
<80-pin >
Positive power supply for P20 to P23, P121 to P122, P137, P150 to P152, and other than
ports
<100-pin>
Positive power supply for P20 to P25, P121 to P122, P137, P150 to P152, and other than
ports
EVDD0, EVDD1 – Positive power supply for ports (other than P20 to P25, P121 to P124, P137, P150 to P152)
VBAT – Power supply for battery backup
VRTC – Power supply for RTC.
Positive power supply for P123 and P124
AVREFP Input Positive reference voltage input of the A/D converter
AVREFM Input Negative reference voltage input of the A/D converter
VSS – <64-pin >
Ground voltage for all pins
<80-pin >
Ground voltage for P20 to P23, P121 to P124, P137, P150 to P152, and other than ports.
<100-pin >
Ground voltage for P20 to P25, P121 to P124, P137, P150 to P152 and other than ports
EVSS0, EVSS1 – Ground voltage for ports (other than P20 to P25, P121 to P124, P137, and P150 to P152)
AVRT – Reference voltage for 24-bit ΔΣ A/D converter
AVCM – Common mode voltage for 24-bit ΔΣ A/D converter
AREGC – Regulator capacitance for 24-bit ΔΣ A/D converter
AVSS – Ground voltage for 24-bit ΔΣ A/D converter
TOOLRxD Input UART reception pin for the external device connection used during flash memory
programming
TOOLTxD Output UART transmission pin for the external device connection used during flash memory
programming
TOOL0 I/O Data I/O for flash memory programmer or debugger
COM0 to COM7 Output LCD controller/driver common signal outputs
EXLVD Input Low voltage detector for external pin
RTCIC0 to RTCIC2 Input RTC time capture event input
KR0 to KR7 Input Key interrupt input
SEG0 to SEG41 Output LCD controller/driver segment signal outputs
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Caution The relationship between the voltage on P40/TOOL0 and the operating mode after release from the
reset state is as follows.
Table 2-2. Relationships between the Voltage on P40/TOOL0 and Operating Mode
After Release from the Reset State
P40/TOOL0 Operating Mode

EVDD0 Normal operating mode
0V Flash memory programming mode
For details, see 36.4 Programming Method.
Remarks 1. Use bypass capacitors (about 0.1 µF) as noise and latch up countermeasures with relatively thick wires
at the shortest distance to VDD to VSS, EVDD0 to EVSS0, and EVDD1 to EVSS1 lines.
2. For the products that do not have an EVDD0 pin, replace EVDD0 with VDD.
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2.3 Connection of Unused Pins
Table 2-3 shows the connections of unused pins.
Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function.
Table 2-3. Connection of Unused Pins (1/2)
Pin Name I/O Recommended Connection of Unused Pins
P02 to P07 I/O Input: Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P10 to P17 <When setting to port I/O>
Input: Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
<When setting to segment output>
Leave open.
P20 to P25 Input: Independently connect to VDD or VSS via a resistor. In addition,
individually connect to VSS via a resistor when using a battery backup
function.
Output: Leave open.
Output: Leave open.
Leave open.
P40/TOOL0 Input: Independently connect to EVDD0 via a resistor or leave open.
Output: Leave open.
P41 to P43 Input: Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
Output: Leave open.
Leave open.
Output: Set the port’s output latch to 0 and leave the pin open, or set the port’s
output latch to 1 and independently connect the pin to EVDD0 or EVSS0 via
a resistor.
Remark For the products that do not have an EVDD0 or EVSS0 pin, replace EVDD0 with VDD, and replace EVSS0 with VSS.
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Table 2-3. Connection of Unused Pins (2/2)
Pin Name I/O Recommended Connection of Unused Pins
P70 to P77 I/O <When setting to port I/O>

Output: Leave open.
Leave open.
P121, P122 Input Independently connect to VDD or VSS via a resistor. In addition, individually
connect to VSS via a resistor when using a battery backup function.
P123, P124 Input Independently connect to VSS via a resistor.
P125 to P127 I/O Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor.
Output: Leave open.
P137 Input Independently connect to VDD or VSS via a resistor. In addition, individually
connect to VSS via a resistor when using a battery backup function.
P150 to P152 I/O Leave open.
RESET Input Leave open.
REGC – Connect to VSS via capacitor (0.47 to 1 µF).
COM0 to COM7 Output Leave open.
ANIP0 to ANIP3 Input Leave open.
ANIN0 to ANIN3
VL1, VL2, VL4 – Leave open.
VBAT – Connect directly to VSS. In addition, if the VBAT pin is not used, be sure to set the
VBATEN bit to 0 with software.
VRTC – Directly connect to VSS.
AVRT, AVCM – Connect to AVSS via capacitor (0.47 µF).
AVSS – Make AVSS the same potential as VSS.
AREGC – Connect to AVSS via capacitor (0.47 µF).
Remark For the products that do not have an EVDD0 or EVSS0 pin, replace EVDD0 with VDD, and replace EVSS0 with VSS.
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2.4 Block Diagrams of Pins
Figures 2-1 to 2-15 show the block diagrams of the pins described in 2.1.1 64-pin products, 2.1.2 80-pin products,
and 2.1.3 100-pin products. For the 64-pin products, replace EVDD1 and EVSS1 with VDD and VSS. For the 80-pin
products, replace EVDD1 and EVSS1 with EVDD0 and EVSS0, respectively.
Figure 2-1. Pin Block Diagram for Pin Type 2-1-2
Alternate
function
RD
Internal bus
Pmn
VDD
RESET RESET
Remark For alternate functions, see 2.1 Port Function.
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Clock generator
CMC
OSCSEL/
OSCSELS
RD Alternate
function
Internal bus
P122/X2/EXCLK/Alternate function
P124/XT2/EXCLKS/Alternate function
CMC
EXCLK, OSCSEL/
EXCLKS, OSCSELS
N-ch P-ch
RD Alternate
function
P121/X1/Alternate function
P123/XT1/Alternate function
Remark For alternate functions, see 2.1 Port Function.
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WRADPC
0: Analog input
1: Digital I/O
ADPC
RDPORT
0 1
Internal bus
0
WRPORT
VDDNote
Output latch
(Pmn) P-ch
WRRM Pmn
PM register N-ch
(PMmn)
VSS
WRPMS
PMS register
P-ch
A/D converter
N-ch
Note Either VDD or VBAT selected by the battery backup function.
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VRTC
Alternate function
(Independent Level
power supply RTC) shifter
Alternate function
(interrupt)
Note
VDD
WDPU
PU register
(PUmn) P-ch
VDD Note
RDPORT
1
Schmitt2
0
Internal bus
0 Note
WDPORT VDD
Output latch
(Pmn) P-ch
WDPMS
Pmn
PMS register N-ch

WDPM
PM register VSS
(PMmn)
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WRADPC
0: Analog input
1: Digital I/O
ADPC
RDPORT
0 1
Internal bus
0
WRPORT
VDDNote
Output latch
(Pmn) P-ch
WRRM Pmn
PM register N-ch
(PMmn)
VSS
WRPMS
PMS register
P-ch
A/D converter
N-ch
Voltage detector
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Alternate
function
EVDD1
WDPU
PU register
(PUmn) P-ch
RDPORT Schmitt2
1
Internal bus
0 1
WDPORT 0
EVDD1
Output latch
(Pmn)
WDPMS P-ch
Pmn
PMS register
N-ch
WDPM
PM register EVSS1
(PMmn)
Alternate
function
(SAU)
Alternate
function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit
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Alternate
function
EVDD1
WRPU
PU register
(PUmn) P-ch
RDPORT Schmitt2
0 1
Internal bus
WRPORT 0
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
N-ch
WRPM
PM register EVSS1
(PMmn)
WRPFSEG
PFSEG register
(PFSEGmn)
Alternate
function
(SAU)
Alternate
function
(other than SAU)
LCD controller/ P-ch

driver
N-ch

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Alternate
function
WRPU EVDD1
PU register
(PUmn)
P-ch
WRISCLCD
ISCLCD register
(LSCCAP)
RDPORT Schmitt2
0 1
Internal bus
WRPORT 0
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
N-ch
WRPM
PM register
EVSS1
(PMmn)
WRLCDM0
LCDM0 register
(MDSET1, 0)
Alternate
function
(SAU)
Alternate
function
(other than SAU)
driver
N-ch

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Alternate
function
WRPU EVDD1
PU register
(PUmn)
P-ch
WRISCLCD
ISCLCD register
(LSCVL3)
RDPORT Schmitt2
0 1
Internal bus
WRPORT 0
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
N-ch
WRPM
PM register EVSS1
(PMmn)
WRLCDM0
LCDM0 register
(LBAS1, 0)
Alternate
function
(SAU)
Alternate
function
(other than SAU)

driver
N-ch

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Alternate
function
WRPU EVDD1
PU register
(PUmn)
P-ch
RDPORT Schmitt2
0 1
Internal bus
WRPORT 0
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
WRPM N-ch
PM register
EVSS1
(PMmn)
WRPOM
POM register
(POMmn)
WRPFSEG
PFSEG register
(PFSEGmn)
Alternate
function
(SAU)
Alternate
function
(other than SAU)

driver N-ch
Caution A through current may flow through if the pin is in the intermediate potential, because the input
buffer is also turned on when the pin is in N-ch open-drain output mode by port output mode register
(POMx).

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Alternate
function
EVDD1
WRPU
PU register
(PUmn) P-ch
WRPM
PIM register
(PIMmn)
RDPORT Schmitt2
1
Internal bus
0 1
WRPORT 0 TTL
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
N-ch
WRPM
PM register EVSS1
(PMmn)
Alternate
function
(SAU)
Alternate
function
(other than SAU)

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Alternate
function
WRPU EVDD1
PU register
(PUmn) P-ch
WRPM
PIM register
(PIMmn)
RDPORT Schmitt2
0 1
Internal bus
WRPORT 0 TTL
EVDD1
Output latch
(Pmn)
WRPMS P-ch
Pmn
PMS register
N-ch
WRPM
PM register EVSS1
(PMmn)
WRPOM
POM register
(POMmn)
WRPFSEG
PFSEG register
(PFSEGmn)
Alternate
function
(SAU)
Alternate LCD controller/ P-ch

function driver
(other than SAU) N-ch
Cautions 1 A through current may flow through if the pin is in the intermediate potential, because the input
buffer is also turned on when the pin is in N-ch open-drain output mode by port output mode
register (POMx).
2 Because of TTL input buffer structure, if the port input mode register (PIMx) is set in TTL input
buffer, a through current may flow through in the case of high level input. It is recommended to
input a low level to prevent a through current.

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Alternate
function
RDPORT
Schmitt1
0
Internal bus
WRPORT
Output latch
(Pmn)
WRPM Pmn
PM register N-ch
(PMmn)
EVSS1
Alternate
function
(SAU)
Alternate
function
(other than SAU)
buffer is turned on when the pin is in output mode.

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Alternate
function
RDPORT
1 Schmitt1
0 1
Internal bus
WRPORT 0
Output latch
(Pmn)
WRPMS
PMS register
WRPM Pmn
PM register N-ch
(PMmn)
EVSS1
Alternate
function
(SAU)
Alternate
function
(other than SAU)
buffer is turned on when the pin is in output mode.

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RL78/I1C CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the RL78/I1C can access a 1 MB address space. Figures 3-1 to 3-3 show the memory maps.
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Figure 3-1. Memory Map (R5F10NLE, R5F10NME)

FFFFFH 0FFFFH
Special function register (SFR)
256 bytes
FFF00H
F F E F FH General-purpose register
32 bytes
F F EE 0H
FFEDFH
Notes 1, 2
RAM Program area
6 KB
FE700H
FE6FFH
Mirror 01FFFH
49.75 KB
010CEH
F2 0 0 0H 010CDH On-chip debug security
F1FFFH ID setting areaNote 3
Reserved
F1 8 0 0H 010C4H 10 bytes
F17FFH 010C3H Option byte areaNote 3
Data flash memory
2 KB 010C0H 4 bytes
F 1 0 0 0H
010BFH Boot cluster 1
F0FFFH CALLT table area
Reserved
F 0 8 0 0H 64 bytes
01080H
F07FFH
Data memory Special function register (2nd SFR) 0 1 0 7 FH
space 2 KB
F0 0 0 0H
E F F F FH Vector table area
128 bytes
01000H
00FFFH
Reserved Program area
000CEH
000CDH On-chip debug security
ID setting areaNote 3
000C4H 10 bytes
000C3H Option byte areaNote 3 Boot cluster 0Note 4
000C0H 4 bytes
000BFH
CALLT table area
64 bytes
00080H
10000H 0 0 0 7 FH
0FFFFH
Program Vector table area

Code flash memory
memory 128 bytes
64 KB
space
00000H 00000H
Notes 1. Do not allocate RAM addresses which are used as a stack area, a data buffer used for flash library, an
argument of library function, a branch destination of vector interrupt processing, and a DTC transfer
destination/transfer source to the area FFE20H to FFEDFH when performing self-programming or rewriting
of the data flash memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 36.7 Security Settings).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes
when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM
parity error resets to enabled (RPERDIS = 0). For details, see 32.3.3 RAM parity error detection
function.
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Figure 3-2. Memory Map (R5F10NLG, R5F10NMG, R5F10NPG)

FFFFFH 1FFFFH
256 bytes
FFF00H
32 bytes
F F E E 0H
FFEDFH
Notes 1, 2, 5
RAM Program area
8 KB
FDF00H
FDEFFH
Mirror 01FFFH
47.75 KB
010CEH
F2000H
Reserved 010C4H 10 bytes
F1800H
010C3H Option byte areaNote 3
F17FFH
Data flash memory 010C0H 4 bytes
F1000H 2 KB 010BFH Boot cluster 1
Reserved 64 bytes
F0800H 01080H
Data memory F07FFH 0 1 0 7 FH
space Special function register (2nd SFR)
F0000H 2 KB
Vector table area
E F F F FH 128 bytes
01000H
00FFFH
000CEH
000C4H 10 bytes
000C0H 4 bytes
000BFH
CALLT table area
64 bytes
20000H 00080H
1FFFFH 0 0 0 7 FH

Code flash memory
memory 128 bytes
128 KB
space
00000H 00000H
For R5F10NLG and R5F10NMG, flash library uses a part of RAM area from FDF00H. For RAM area that
flash library uses, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).
5. When using the trace function of on-chip debugging, area FE300H to FE6FFH is disabled.
function.
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Figure 3-3. Memory Map (R5F10NMJ, R5F10NPJ)

FFFFFH 3FFFFH
256 bytes
FFF00H
32 bytes
F F E E 0H
FFEDFH
RAMNotes 1, 2, 5 Program area
16 KB
FBF00H
FBEFFH
Mirror 01FFFH
39.75 KB
010CEH
F 2 0 0 0H
Reserved 010C4H 10 bytes
F 1 8 0 0H
010C3H Option byte areaNote 3
F17FFH
Data flash memory 010C0H 4 bytes
F 1 0 0 0H 2 KB 010BFH Boot cluster 1
Reserved 64 bytes
F 0 8 0 0H 01080H
Data memory F07FFH 0 1 0 7 FH
space Special function register (2nd SFR)
F 0 0 0 0H 2 KB
Vector table area
E F F F FH 128 bytes
01000H
00FFFH
000CEH
000C4H 10 bytes
000C0H 4 bytes
000BFH
CALLT table area
64 bytes
40000H 00080H
3FFFFH 0 0 0 7 FH

memory Code flash memory
256 KB 128 bytes
space
00000H 00000H
The RAM area used by the flash library starts at FBF00H. For RAM area that flash library uses, see Self
RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).
5. When using the trace function of on-chip debugging, area FC300H to FC6FFH is disabled.
function.
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Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
3FFFFH
Block FFH
3FC00H
3FBFFH
007FFH
Block 01H
00400H
003FFH
Block 00H 1 KB
00000H
(R5F10NPJ, R5F10NMJ)
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
Address Value Block Address Value Block Address Value Block Address Value Block
Number Number Number Number
00000H to 003FFH 00H 08000H to 083FFH 20H 10000H to 103FFH 40H 18000H to 183FFH 60H
00800H to 00BFFH 02H 08800H to 08BFFH 22H 10800H to 10BFFH 42H 18800H to 18BFFH 62H
00C00H to 00FFFH 03H 08C00H to 08FFFH 23H 10C00H to 10FFFH 43H 18C00H to 18FFFH 63H
01800H to 01BFFH 06H 09800H to 09BFFH 26H 11800H to 11BFFH 46H 19800H to 19BFFH 66H
01C00H to 01FFFH 07H 09C00H to 09FFFH 27H 11C00H to 11FFFH 47H 19C00H to 19FFFH 67H
02000H to 023FFH 08H 0A000H to 0A3FFH 28H 12000H to 123FFH 48H 1A000H to 1A3FFH 68H
02400H to 027FFH 09H 0A400H to 0A7FFH 29H 12400H to 127FFH 49H 1A400H to 1A7FFH 69H
02800H to 02BFFH 0AH 0A800H to 0ABFFH 2AH 12800H to 12BFFH 4AH 1A800H to 1ABFFH 6AH
02C00H to 02FFFH 0BH 0AC00H to 0AFFFH 2BH 12C00H to 12FFFH 4BH 1AC00H to 1AFFFH 6BH
03000H to 033FFH 0CH 0B000H to 0B3FFH 2CH 13000H to 133FFH 4CH 1B000H to 1B3FFH 6CH
03400H to 037FFH 0DH 0B400H to 0B7FFH 2DH 13400H to 137FFH 4DH 1B400H to 1B7FFH 6DH
03800H to 03BFFH 0EH 0B800H to 0BBFFH 2EH 13800H to 13BFFH 4EH 1B800H to 1BBFFH 6EH
03C00H to 03FFFH 0FH 0BC00H to 0BFFFH 2FH 13C00H to 13FFFH 4FH 1BC00H to 1BFFFH 6FH
04000H to 043FFH 10H 0C000H to 0C3FFH 30H 14000H to 143FFH 50H 1C000H to 1C3FFH 70H
04400H to 047FFH 11H 0C400H to 0C7FFH 31H 14400H to 147FFH 51H 1C400H to 1C7FFH 71H
04800H to 04BFFH 12H 0C800H to 0CBFFH 32H 14800H to 14BFFH 52H 1C800H to 1CBFFH 72H
04C00H to 04FFFH 13H 0CC00H to 0CFFFH 33H 14C00H to 14FFFH 53H 1CC00H to 1CFFFH 73H
05000H to 053FFH 14H 0D000H to 0D3FFH 34H 15000H to 153FFH 54H 1D000H to 1D3FFH 74H
05400H to 057FFH 15H 0D400H to 0D7FFH 35H 15400H to 157FFH 55H 1D400H to 1D7FFH 75H
05800H to 05BFFH 16H 0D800H to 0DBFFH 36H 15800H to 15BFFH 56H 1D800H to 1DBFFH 76H
05C00H to 05FFFH 17H 0DC00H to 0DFFFH 37H 15C00H to 15FFFH 57H 1DC00H to 1DFFFH 77H
06000H to 063FFH 18H 0E000H to 0E3FFH 38H 16000H to 163FFH 58H 1E000H to 1E3FFH 78H
06400H to 067FFH 19H 0E400H to 0E7FFH 39H 16400H to 167FFH 59H 1E400H to 1E7FFH 79H
06800H to 06BFFH 1AH 0E800H to 0EBFFH 3AH 16800H to 16BFFH 5AH 1E800H to 1EBFFH 7AH
06C00H to 06FFFH 1BH 0EC00H to 0EFFFH 3BH 16C00H to 16FFFH 5BH 1EC00H to 1EFFFH 7BH
07000H to 073FFH 1CH 0F000H to 0F3FFH 3CH 17000H to 173FFH 5CH 1F000H to 1F3FFH 7CH
07400H to 077FFH 1DH 0F400H to 0F7FFH 3DH 17400H to 177FFH 5DH 1F400H to 1F7FFH 7DH
07800H to 07BFFH 1EH 0F800H to 0FBFFH 3EH 17800H to 17BFFH 5EH 1F800H to 1FBFFH 7EH
07C00H to 07FFFH 1FH 0FC00H to 0FFFFH 3FH 17C00H to 17FFFH 5FH 1FC00H to 1FFFFH 7FH
Remark R5F10NME, R5F10NLE: Block numbers 00H to 3FH

R5F10NPG, R5F10NMG, R5F10NLG: Block numbers 00H to 7FH
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Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
Address Value Block Address Value Block Address Value Block Address Value Block
Number Number Number Number
20000H-203FFH 80H 28000H-283FFH A0H 30000H-303FFH C0H 38000H-383FFH E0H

20800H-20BFFH 82H 28800H-28BFFH A2H 30800H-30BFFH C2H 38800H-38BFFH E2H
20C00H-20FFFH 83H 28C00H-28FFFH A3H 30C00H-30FFFH C3H 38C00H-38FFFH E3H
21800H-21BFFH 86H 29800H-29BFFH A6H 31800H-31BFFH C6H 39800H-39BFFH E6H
21C00H-21FFFH 87H 29C00H-29FFFH A7H 31C00H-31FFFH C7H 39C00H-39FFFH E7H
22000H-223FFH 88H 2A000H-2A3FFH A8H 32000H-323FFH C8H 3A000H-3A3FFH E8H
22400H-227FFH 89H 2A400H-2A7FFH A9H 32400H-327FFH C9H 3A400H-3A7FFH E9H
22800H-22BFFH 8AH 2A800H-2ABFFH AAH 32800H-32BFFH CAH 3A800H-3ABFFH EAH
22C00H-22FFFH 8BH 2AC00H-2AFFFH ABH 32C00H-32FFFH CBH 3AC00H-3AFFFH EBH
23000H-233FFH 8CH 2B000H-2B3FFH ACH 33000H-333FFH CCH 3B000H-3B3FFH ECH
23400H-237FFH 8DH 2B400H-2B7FFH ADH 33400H-337FFH CDH 3B400H-3B7FFH EDH
23800H-23BFFH 8EH 2B800H-2BBFFH AEH 33800H-33BFFH CEH 3B800H-3BBFFH EEH
23C00H-23FFFH 8FH 2BC00H-2BFFFH AFH 33C00H-33FFFH CFH 3BC00H-3BFFFH EFH
24000H-243FFH 90H 2C000H-2C3FFH B0H 34000H-343FFH D0H 3C000H-3C3FFH F0H
24400H-247FFH 91H 2C400H-2C7FFH B1H 34400H-347FFH D1H 3C400H-3C7FFH F1H
24800H-24BFFH 92H 2C800H-2CBFFH B2H 34800H-34BFFH D2H 3C800H-3CBFFH F2H
24C00H-24FFFH 93H 2CC00H-2CFFFH B3H 34C00H-34FFFH D3H 3CC00H-3CFFFH F3H
25000H-253FFH 94H 2D000H-2D3FFH B4H 35000H-353FFH D4H 3D000H-3D3FFH F4H
25400H-257FFH 95H 2D400H-2D7FFH B5H 35400H-357FFH D5H 3D400H-3D7FFH F5H
25800H-25BFFH 96H 2D800H-2DBFFH B6H 35800H-35BFFH D6H 3D800H-3DBFFH F6H
25C00H-25FFFH 97H 2DC00H-2DFFFH B7H 35C00H-35FFFH D7H 3DC00H-3DFFFH F7H
26000H-263FFH 98H 2E000H-2E3FFH B8H 36000H-363FFH D8H 3E000H-3E3FFH F8H
26400H-267FFH 99H 2E400H-2E7FFH B9H 36400H-367FFH D9H 3E400H-3E7FFH F9H
26800H-26BFFH 9AH 2E800H-2EBFFH BAH 36800H-36BFFH DAH 3E800H-3EBFFH FAH
26C00H-26FFFH 9BH 2EC00H-2EFFFH BBH 36C00H-36FFFH DBH 3EC00H-3EFFFH FBH
27000H-273FFH 9CH 2F000H-2F3FFH BCH 37000H-373FFH DCH 3F000H-3F3FFH FCH
27400H-277FFH 9DH 2F400H-2F7FFH BDH 37400H-377FFH DDH 3F400H-3F7FFH FDH
27800H-27BFFH 9EH 2F800H2FBFFH BEH 37800H-37BFFH DEH 3F800H-3FBFFH FEH
27C00H-27FFFH 9FH 2FC00H-2FFFFH BFH 37C00H-37FFFH DFH 3FC00H-3FFFFH FFH
Remark R5F10NPJ, R5F10NMJ: Block numbers 00H to FFH
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3.1.1 Internal program memory space

The internal program memory space stores the program and table data.
The RL78/I1C products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number Internal ROM

Structure Capacity
R5F10NME, R5F10NLE Flash memory 65536 × 8 bits (00000H to 0FFFFH)
R5F10NPG, R5F10NMG, R5F10NLG 131072 × 8 bits (00000H to 1FFFFH)
R5F10NPJ, R5F10NMJ 262144 × 8 bits (00000H to 3FFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area

The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump
address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
To use the boot swap function, set a vector table also at 01000H to 0107FH.
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Table 3-3. Vector Table (1/2)
Vector Table Address Interrupt Source

0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE
0004H INTWDTI
0006H INTLVI
0008H INTP0
000AH INTP1
000CH INTP2
000EH INTP3
0010H INTP4
0012H INTP5
0014H INTST2
0016H INTSR2
0018H INTSRE2
001AH INTCR
001CH INTAES/INTAESF
001EH INTST0/INTCSI00/INTIIC00
0020H INTIICA0
0022H INTSR0
0024H INTSRE0
INTTM01H
0026H INTST1/INTCSI10/INTIIC10
0028H INTSR1
002AH INTSRE1
INTTM03H
002CH INTTM00
0030H INTFM
0032H INTTM01
0034H INTTM02
0036H INTTM03
0038H INTAD
003AH INTRTCALM/INTRTCPRD
003CH INTIT
003EH INTKR
0040H INTST3/INTCSI30/INTIIC30
0042H INTSR3
0044H INTDSAD
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Table 3-3. Vector Table (2/2)
Vector Table Address Interrupt Source

0046H INTTM04
0048H INTTM05
004AH INTP6
004CH INTP7
004EH INTRTCIC0
0050H INTRTCIC1
0052H INTRTCIC2
0054H INTTM06
0056H INTTM07
0058H INTIT00
005AH INTIT01
005CH INTSRE3
005EH INTMACLOF
0060H INTOSDC
0062H INTFL
0064H INTDSADZC0
0066H INTDSADZC1
0068H INTIT10
006AH INTIT11
006CH INTLVDVDD
006EH INTLVDVBAT
0070H INTLVDVRTC
0072H INTLVDEXLVD
007EH BRK
(2) CALLT instruction table area

The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
(3) Option byte area

A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H
when the boot swap is used. For details, see CHAPTER 35 OPTION BYTE.
(4) On-chip debug security ID setting area

A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at
000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 37 ON-CHIP
DEBUG FUNCTION.
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3.1.2 Mirror area

The RL78/I1C mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 128 KB or
more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the
code flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used,
and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to
the SFR, extended SFR, RAM, and use prohibited areas.
See 3.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
Example R5F10NPG, R5F10NMG, R5F10NLG (Flash memory: 128 KB, RAM: 8 KB)
FFFFF H
Special-function register (SFR)

256 bytes
FFF00H
F F E E 0H 32 bytes
FFEDF H For example, 0D589H is mirrored to
RAM FD589H. Data can therefore be read
8 KB
by MOV A, !D589H, instead of MOV
FDF00H
FDEFF H ES, #00H and MOV A, ES:!D589H.
Mirror
(same data as 02000H to 0DEFFH)
F2000H
F 1F F FH
Reserved
F1800H
F17FFH Data flash memory
F1000H 2 KB
F 0F F FH
Reserved
F0800H
F07FFH
Special-function register (2nd SFR)
2 KB
F0000H
EFFFFH
Mirror
Reserved
20000 H
1F F F FH
Code flash memory
0DF00H
0 DEF F H
Code flash memory
02000 H
01FFF H Code flash memory
00000 H
The PMC register is described below.
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● Processor mode control register (PMC)

This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-4. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>
PMC 0 0 0 0 0 0 0 MAA
MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH

1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH
Cautions 1. In products with 64 KB flash memory, be sure to clear bit 0 (MAA) of this register to 0 (default
value).
2. After setting the PMC register, wait for at least one instruction and access the mirror area.
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3.1.3 Internal data memory space

The RL78/I1C products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number Internal RAM
R5F10NME, R5F10NLE 6144 × 8 bits (FE700H to FFEFFH)

R5F10NPG, R5F10NMG, R5F10NLG 8192 × 8 bits (FDF00H to FFEFFH)
R5F10NPJ, R5F10NMJ 16384× 8 bit (FBF00H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are executed. (Instructions
cannot be executed in the area to which general-purpose registers are allocated.) Four general-purpose register banks
consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM
area. The internal RAM is used as stack memory.
Cautions 1. The space (FFEE0H to FFEFFH) that the general-purpose registers are allocated cannot be used
for fetching instructions or as a stack area.
2. Do not allocate RAM addresses which are used as a stack area, a data buffer used for flash library,
a branch destination of vector interrupt processing, and a DTC transfer destination/transfer
source to the area FFE20H to FFEDFH when performing self-programming or rewriting of the data
flash memory.
3. Use of the RAM areas of the following products is prohibited when performing self-programming
or rewriting of the data flash memory, because these areas are used for each library.
R5F10NPJ, R5F10NMJ: FBF00H-FC309H
R5F10NMG, R5F10NLG: FDF00H-FE309H
4. The internal RAM area of the following products cannot be used as a stack memory when using
the trace function of on-chip debugging.
R5F10NPJ, R5F10NMJ: FC300H-FC6FFH
R5F10NMG, R5F10NLG: FE300H-FE6FFH
3.1.4 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table
3-5 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see
Table 3-6 in 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assigned.
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3.1.6 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
RL78/I1C, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are
available for use. Figure 3-4 shows correspondence between data memory and addressing. For details of each
addressing, see 3.4 Addressing for Processing Data Addresses.
Figure 3-5. Correspondence Between Data Memory and Addressing
FFFFFH
FFF20H Special function register (SFR) SFR addressing
FFF1FH 256 bytes
FFF00H
F F E F FH General-purpose register Short direct
32 bytes Register addressing addressing
F F EE0H
FFEDFH
FFE20H RAM
FFE1FH 6/8/16 KB
Mirror
F2 0 0 0H
F1FFFH
Reserved
F1 8 0 0H
F17FFH Data flash memory
2 KB
F1 0 0 0H Direct addressing
F0FFFH
Reserved
F0 8 0 0H Register indirect addressing
F07FFH
Special function register (2nd SFR) Based addressing
2 KB
F0 0 0 0H Based indexed addressing
E F F F FH
Reserved
Code flash memory

64/128/256 KB
00000H
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3.2 Processor Registers
The RL78/I1C products incorporate the following processor registers.
3.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)

The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-6. Format of Program Counter
19 0
PC
(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset
signal generation sets the PSW register to 06H.
Figure 3-7. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 ISP1 ISP0 CY
(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and maskable interrupt request acknowledgment is
controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)

When the operation result is zero or equal, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)

These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
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(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)

This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H, PRn3L) (see 24.3.3) can not be acknowledged. Actual vectored interrupt
request acknowledgment is controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-8. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is
incremented after read (restored) from the stack memory.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or a stack area.
3. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch
destination of vector interrupt processing, and a DTC transfer destination/transfer source to the
area FFE20H to FFEDFH when performing self-programming or rewriting of the data flash
memory.
4. Use of the RAM areas of the following products is prohibited when performing self-programming,
or rewriting of the data flash memory, because these areas are used for each library.
R5F10NPJ, R5F10NMJ: FBF00H-FC309H
R5F10NMG, R5F10NLG: FDF00H-FE309H
5. The internal RAM area of the following products cannot be used as a stack memory when using
the trace function of on-chip debugging.
R5F10NPJ, R5F10NMJ: FC300H-FC6FFH
R5F10NMG, R5F10NLG: FE300H-FE6FFH
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3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-
register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
Figure 3-9. Configuration of General-Purpose Registers
(a) Function name
16-bit processing 8-bit processing

FFEFFH
H
Register bank 0 HL
L
FFEF8H
D
Register bank 1 DE
E
FFEF0H
B
Register bank 2 BC
C
FFEE8H
A
Register bank 3 AX
X
FFEE0H
15 0 7 0
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3.2.3 ES and CS registers

The ES register and CS register are used to specify the higher address for data access and when a branch instruction
is executed (register direct addressing), respectively.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-10. Configuration of ES and CS Registers

7 6 5 4 3 2 1 0
ES 0 0 0 0 ES3 ES2 ES1 ES0
7 6 5 4 3 2 1 0
CS 0 0 0 0 CS3 CS2 CS1 CS0
The data area that can be accessed by using 16-bit addresses is the 64 KB from F0000H to FFFFFH. By using the ES
register, this area can be extended to the 1 MB from 00000H to FFFFFH.
Figure 3-11. Extension of Data Area Which Can Be Accessed
!saddr16 F 0000H - FFFFH
ES:!saddr16 0H - FH 0000H - FFFFH
FFFFFH
Special function register
(SFR) 256 bytes
!saddr16
Special function register

ES:!saddr16 Data memory space
(2nd SFR) 2 Kbytes
F0000H
EFFFFH
Code flash memory

00000H
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3.2.4 Special function registers (SFRs)

Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
● 1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (sfr.bit).
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation
can also be specified with an address.
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When
specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
● Symbol
Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.
● R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
● Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “–” indicates a bit unit for which manipulation is not possible.
● After reset
Indicates each register status upon reset signal generation.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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Table 3-5. SFR List (1/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset
1-bit 8-bit 16-bit
FFF00H Port register 0 P0 R/W √ √ – 00H
FFF0CH Port register 12 P12 R/W √ √ – Undefined
FFF0DH Port register 13 P13 R/W √ √ – Undefined
FFF0FH Port register 15 P15 R/W √ √ – 00H
FFF10H Serial data register 00 TXD0/ SDR00 R/W – √ √ 0000H
SIO00
FFF11H – – –
FFF12H Serial data register 01 RXD0 SDR01 R/W – √ √ 0000H
FFF13H – – –
FFF14H Serial data register 12 TXD3/ SDR12 R/WNote – √ √ 0000H
SIO30
FFF15H – – –
Note
FFF17H – – –
FFF18H Timer data register 00 TDR00 R/W – – √ 0000H
FFF19H
FFF1AH Timer data register 01 TDR01L TDR01 R/W – √ √ 00H
FFF1BH TDR01H – √ 00H
FFF1EH 10-bit A/D conversion result register ADCR R – – √ 0000H
FFF1FH 8-bit A/D conversion result register ADCRH R – √ – 00H
FFF20H Port mode register 0 PM0 R/W √ √ – FFH
FFF2CH Port mode register 12 PM12 R/W √ √ – FFH
FFF2FH Port mode register 15 PM15 R/W √ √ – FFH
FFF30H A/D converter mode register 0 ADM0 R/W √ √ – 00H
FFF31H Analog input channel specification register ADS R/W √ √ – 00H
FFF32H A/D converter mode register 1 ADM1 R/W √ √ – 00H
FFF34H Key return control register KRCTL R/W √ √ – 00H
FFF35H Key return flag register KRF R/W – √ – 00H
Note These registers for R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE can only be read.
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1-bit 8-bit 16-bit
FFF37H Key return mode register 0 KRM0 R/W √ √ – 00H
FFF38H External interrupt rising edge enable register 0 EGP0 R/W √ √ – 00H
FFF39H External interrupt falling edge enable register 0 EGN0 R/W √ √ – 00H
FFF3AH External interrupt rising edge enable register 1Note EGP1 R/W √ √ – 00H
FFF3BH External interrupt falling edge enable register 1Note EGN1 R/W √ √ – 00H
FFF3CH Multiplication data register B(L) MULBL R/W – – √ 0000H
FFF3DH
FFF3EH Multiplication data register B(H) MULBH R/W – – √ 0000H
FFF3FH
FFF40H LCD mode register 0 LCDM0 R/W – √ – 00H
FFF41H LCD mode register 1 LCDM1 R/W √ √ – 00H
FFF42H LCD clock control register 0 LCDC0 R/W – √ – 00H
FFF43H LCD boost level control register VLCD R/W – √ – 04H
FFF44H Serial data register 02 TXD1/ SDR02 R/W – √ √ 0000H
SIO10
FFF45H – – –
FFF47H – – –
FFF48H Serial data register 10 TXD2 SDR10 R/W – √ √ 0000H
FFF49H – – –
FFF4AH Serial data register 11 RXD2 SDR11 R/W – √ √ 0000H
FFF4BH – – –
FFF50H IICA shift register 0 IICA0 R/W – √ – 00H
FFF51H IICA status register 0 IICS0 R √ √ – 00H
FFF52H IICA flag register 0 IICF0 R/W √ √ – 00H
FFF65H
FFF66H Timer data register 03 TDR03L TDR03 R/W – √ √ 00H
FFF67H TDR03H – √ 00H
FFF69H
FFF6AH Timer data register 05 TDR05 R/W – – √ 0000H
FFF6BH
FFF6CH Timer data register 06 TDR06 R/W – – √ 0000H
FFF6DH
FFF6EH Timer data register 07 TDR07 R/W – – √ 0000H
FFF6FH
Note This register is incorporated with 100-or 80-pin products, but is not incorporated with 64-pin products.
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1-bit 8-bit 16-bit
FFF90H 12-bit interval timer control register ITMC R/W – – √ 0FFFH

FFF91H
FFFA0H Clock operation mode control register CMC R/W – √ – 00HNote 1
FFFA1H Clock operation status control register CSC R/W √ √ – C0HNote 1
FFFA2H Oscillation stabilization time counter status register OSTC R √ √ – 00H
FFFA3H Oscillation stabilization time select register OSTS R/W – √ – 07H
FFFA4H System clock control register CKC R/W √ √ – 00H
FFFA5H Clock output select register 0 CKS0 R/W √ √ – 00H
FFFA6H Clock output select register 1 CKS1 R/W √ √ – 00H
FFFA7H Subsystem clock select resister CKSEL R/W √ √ – 00H
FFFA8H Reset control flag register RESF R – √ – Undefined
Note 2
FFFA9H Voltage detection register LVIM R/W √ √ – 00HNote 2

FFFAAH Voltage detection level register LVIS R/W √ √ – 00H/01H/
81HNote 2
FFFABH Watchdog timer enable register WDTE R/W – √ – 1AH/9AH
Note 3
FFFACH CRC input register CRCIN R/W – √ – 00H

FFFD0H Interrupt request flag register 2L IF2L IF2 R/W √ √ √ 00H
FFFD1H Interrupt request flag register 2H IF2H R/W √ √ 00H
FFFD2H Interrupt request flag register 3L IF3L IF3 R/W √ √ √ 00H
FFFD4H Interrupt mask flag register 2L MK2L MK2 R/W √ √ √ FFH
FFFD5H Interrupt mask flag register 2H MK2H R/W √ √ FFH
FFFD6H Interrupt mask flag register 3L MK3L MK3 R/W √ √ √ FFH
Notes 1. This register is reset only by a power-on reset.

2. The reset values of the registers vary depending on the reset source as shown below.
Reset Source RESET Input Reset by POR Reset by Reset by Reset by RAM Reset by Reset by LVD
Execution of WDT Parity Error Illegal-Memory
Illegal Access
Register Instruction
RESF TRAP Cleared (0) Set (1) Held Held
WDTRF Held Set (1) Held
RPERF Held Set (1) Held
IAWRF Held Set (1)
LVIRF Held Set (1)
LVIM LVISEN Cleared (0) Held
LVIOMSK Held
LVIF
LVIS Cleared (00H/01H/81H) Clear
(00H/81H)Note 4
3. The reset value of the WDTE register is determined by the setting of the option byte.
4. When option byte LVIMDS1, LVIMDS0 = 0, 1: LVD reset is not generated.
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1-bit 8-bit 16-bit
FFFD8H Priority specification flag register 02L PR02L PR02 R/W √ √ √ FFH
FFFD9H Priority specification flag register 02H PR02H R/W √ √ FFH
FFFDAH Priority specification flag register 03L PR03L PR03 R/W √ √ √ FFH
FFFDCH Priority specification flag register 12L PR12L PR12 R/W √ √ √ FFH
FFFDDH Priority specification flag register 12H PR12H R/W √ √ FFH
FFFDEH Priority specification flag register 13L PR13L PR13 R/W √ √ √ FFH
FFFE0H Interrupt request flag register 0L IF0L IF0 R/W √ √ √ 00H
FFFE1H Interrupt request flag register 0H IF0H R/W √ √ 00H
FFFE2H Interrupt request flag register 1L IF1L IF1 R/W √ √ √ 00H
FFFE3H Interrupt request flag register 1H IF1H R/W √ √ 00H
FFFE4H Interrupt mask flag register 0L MK0L MK0 R/W √ √ √ FFH
FFFE5H Interrupt mask flag register 0H MK0H R/W √ √ FFH
FFFE6H Interrupt mask flag register 1L MK1L MK1 R/W √ √ √ FFH
FFFE7H Interrupt mask flag register 1H MK1H R/W √ √ FFH
FFFE8H Priority specification flag register 00L PR00L PR00 R/W √ √ √ FFH
FFFE9H Priority specification flag register 00H PR00H R/W √ √ FFH
FFFEAH Priority specification flag register 01L PR01L PR01 R/W √ √ √ FFH
FFFEBH Priority specification flag register 01H PR01H R/W √ √ FFH
FFFECH Priority specification flag register 10L PR10L PR10 R/W √ √ √ FFH
FFFEDH Priority specification flag register 10H PR10H R/W √ √ FFH
FFFEEH Priority specification flag register 11L PR11L PR11 R/W √ √ √ FFH
FFFEFH Priority specification flag register 11H PR11H R/W √ √ FFH
FFFF0H Multiply and accumulation register MACRL R/W – – √ 0000H
FFFF1H (L)
FFFF2H Multiply and accumulation register MACRH R/W – – √ 0000H
FFFF3H (H)
FFFFEH Processor mode control register PMC R/W √ √ – 00H
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
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3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit).
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
● Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
● R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
● Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “–” indicates a bit unit for which manipulation is not possible.
● After reset
Indicates each register status upon reset signal generation.
Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
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Table 3-6. Extended SFR (2nd SFR) List (1/11)
1-bit 8-bit 16-bit
F0010H A/D converter mode register 2 ADM2 R/W √ √ – 00H
F0011H Conversion result comparison upper limit setting ADUL R/W – √ – FFH
register
F0012H Conversion result comparison lower limit setting ADLL R/W – √ – 00H
register
F0013H A/D test register ADTES R/W – √ – 00H
F0030H Pull-up resistor option register 0 PU0 R/W √ √ – 00H
F003CH Pull-up resistor option register 12 PU12 R/W √ √ – 00H
F003FH Pull-up resistor option register 15 PU15 R/W √ √ – 07H
F0040H Port input mode register 0 PIM0 R/W √ √ – 00H
F0043H Port input mode register 3Note 3 PIM3 R/W √ √ – 00H
F0050H Port output mode register 0 POM0 R/W √ √ – 00H
F0053H Port output mode register 3Note 3 POM3 R/W √ √ – 00H
F0070H Noise filter enable register 0 NFEN0 R/W √ √ – 00H
F0071H Noise filter enable register 1 NFEN1 R/W √ √ – 00H
F0073H Input switch control register ISC R/W √ √ – 00H
F0074H Timer input select register 0 TIS0 R/W – √ – 00H
F0076H A/D port configuration register ADPC R/W – √ – 00H
F0077H Peripheral I/O redirection register 0 PIOR0 R/W – √ – 00H
F0078H Invalid memory access detection control register IAWCTL R/W – √ – 00H
F007AH Frequency measurement circuit clock select FMCKS R/W √ √ – 00H
register
F007BH Port mode select resister PMS R/W √ √ – 00H
F007DH Global digital input disable register GDIDIS R/W √ √ – 00H
F0090H Data flash control register DFLCTL R/W √ √ – 00H
F0098H Peripheral clock control register PCKC R/W √ √ – 00H
F00A8H High-speed on-chip oscillator frequency select HOCODIV R/W – √ – UndefinedNote 1
register
F00AAH Flash operation mode select register FLMODE R/W √ √ – Note 2
F00ABH Flash operating mode protect register FLMWRP R/W √ √ – 00H
Notes 1. The value set by FRQSEL2 to FRQSEL0 of the option byte 000C2H.
2. The reset value of the FLMODE register is determined by the setting of the option byte.
3. This register is incorporated with 64-pin products, but is not incorporated with 100- or 80-pin products.
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1-bit 8-bit 16-bit
F00F0H Peripheral enable register 0 PER0 R/W √ √ – 00H
F00F1H Peripheral reset control register 0 PRR0 R/W √ √ – 00H
F00F2H Mid-speed on-chip oscillator frequency select MOCODIV R/W – √ – 00H
register
F00F3H Subsystem clock supply option control register OSMC R/W √ √ – 00H
F00F5H RAM parity error control register RPECTL R/W √ √ – 00H
F00F8H Regulator mode control register PMMC R/W √ √ – 00H
F00F9H Power-on-reset status register PORSR R/W – √ – 00HNote
F00FAH Peripheral enable register 1 PER1 R/W √ √ – 00H
F00FBH Peripheral reset control register 1 PRR1 R/W √ √ – 00H
F00FCH Peripheral enable register 2 PER2 R/W √ √ – 00H
F00FDH Peripheral reset control register 2 PRR2 R/W √ √ – 00H
F00FEH BCD adjust result register BCDADJ R – √ – Undefined
F0100H Serial status register 00 SSR00L SSR00 R – √ √ 0000H
F0101H – – –
F0103H – – –
F0105H – – –
F0107H – – –
F0108H Serial flag clear trigger register 00 SIR00L SIR00 R/W – √ √ 0000H
F0109H – – –
F010AH Serial flag clear trigger register 01 SIR01L SIR01 R/W – √ √ 0000H
F010BH – – –
F010CH Serial flag clear trigger register 02 SIR02L SIR02 R/W – √ √ 0000H
F010DH – – –
F010EH Serial flag clear trigger register 03 SIR03L SIR03 R/W – √ √ 0000H
F010FH – – –
F0110H Serial mode register 00 SMR00 R/W – – √ 0020H
F0111H
F0113H
F0115H
F0117H
F0118H Serial communication operation setting register SCR00 R/W – – √ 0087H
F0119H 00
Note This register is reset only by a power-on reset.
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1-bit 8-bit 16-bit
F011AH Serial communication operation setting register SCR01 R/W – – √ 0087H
F011BH 01
F011CH Serial communication operation setting register SCR02 R/W – – √ 0087H

F011DH 02
F011EH Serial communication operation setting register SCR03 R/W – – √ 0087H

F011FH 03
F0120H Serial channel enable status register 0 SE0L SE0 R √ √ √ 0000H

F0121H – – –
F0122H Serial channel start register 0 SS0L SS0 R/W √ √ √ 0000H
F0123H – – –
F0124H Serial channel stop register 0 ST0L ST0 R/W √ √ √ 0000H
F0125H – – –
F0126H Serial clock select register 0 SPS0L SPS0 R/W – √ √ 0000H
F0127H – – –
F0128H Serial output register 0 SO0 R/W – – √ 0F0FH
F0129H
F012AH Serial output enable register 0 SOE0L SOE0 R/W √ √ √ 0000H
F012BH – – –
F0134H Serial output level register 0 SOL0L SOL0 R/W – √ √ 0000H
F0135H – – –
F0138H Serial standby control register 0 SSC0L SSC0 R/W – √ √ 0000H
F0139H – – –
F0141H – – –
F0143H – – –
F0145H – – –
F0147H – – –
F0148H Serial flag clear trigger register 10 SIR10L SIR10 R/W – √ √ 0000H
F0149H – – –
F014AH Serial flag clear trigger register 11 SIR11L SIR11 R/W – √ √ 0000H
F014BH – – –
F014CH Serial flag clear trigger register 12 SIR12L SIR12 R/WNote – √ √ 0000H
F014DH – – –
Note
F014EH Serial flag clear trigger register 13 SIR13L SIR13 R/W – √ √ 0000H
F014FH – – –
F0151H
F0153H
Note These registers for R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE can only be read.
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1-bit 8-bit 16-bit
F0154H Serial mode register 12 SMR12 R/WNote 1 – – √ 0020H/0000HNote 2
F0155H
F0156H Serial mode register 13 SMR13 R/WNote 1 – – √ 0020H/0000HNote 2
F0157H
F0158H Serial communication operation setting SCR10 R/W – – √ 0087H
F0159H register 10
F015AH Serial communication operation setting SCR11 R/W – – √ 0087H

F015BH register 11
F015CH Serial communication operation setting SCR12 R/WNote 1 – – √ 0087H/0000HNote 3

F015DH register 12
F015EH Serial communication operation setting SCR13 R/WNote 1 – – √ 0087H/0000HNote 3

F015FH register 13
F0160H Serial channel enable status register 1 SE1L SE1 R √ √ √ 0000H

F0161H – – –
F0162H Serial channel start register 1 SS1L SS1 R/W √ √ √ 0000H
F0163H – – –
F0164H Serial channel stop register 1 ST1L ST1 R/W √ √ √ 0000H
F0165H – – –
F0166H Serial clock select register 1 SPS1L SPS1 R/W – √ √ 0000H
F0167H – – –
F0168H Serial output register 1 SO1 R/W – – √ 0F0FH/0303HNote 4
F0169H
F016AH Serial output enable register 1 SOE1L SOE1 R/W √ √ √ 0000H
F016BH – – –
F0174H Serial output level register 1 SOL1L SOL1 R/W – √ √ 0000H
F0175H – – –
F0180H Timer counter register 00 TCR00 R – – √ FFFFH
F0181H
F0183H
F0185H
F0187H
F0189H
F018AH Timer counter register 05 TCR05 R – – √ FFFFH
F018BH
F018CH Timer counter register 06 TCR06 R – – √ FFFFH
F018DH
Notes 1. These registers for R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE can only be read.
2. R5F10NPJ, R5F10NMJ, R5F10NPG: 0020H
R5F10NMG, R5F10NLG, R5F10NME, R5F10NLE: 0000H
3. R5F10NPJ, R5F10NMJ, R5F10NPG: 0087H
4. R5F10NPJ, R5F10NMJ, R5F10NPG: 0F0FH
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1-bit 8-bit 16-bit
F018EH Timer counter register 07 TCR07 R – – √ FFFFH
F018FH
F0190H Timer mode register 00 TMR00 R/W – – √ 0000H
F0191H
F0193H
F0195H
F0197H
F0199H
F019AH Timer mode register 05 TMR05 R/W – – √ 0000H
F019BH
F019CH Timer mode register 06 TMR06 R/W – – √ 0000H
F019DH
F019EH Timer mode register 07 TMR07 R/W – – √ 0000H
F019FH
F01A0H Timer status register 00 TSR00L TSR00 R – √ √ 0000H
F01A1H – – –
F01A3H – – –
F01A5H – – –
F01A7H – – –
F01A9H – – –
F01AAH Timer status register 05 TSR05L TSR05 R – √ √ 0000H
F01ABH – – –
F01ACH Timer status register 06 TSR06L TSR06 R – √ √ 0000H
F01ADH – – –
F01AEH Timer status register 07 TSR07L TSR07 R – √ √ 0000H
F01AFH – – –
F01B0H Timer channel enable status register 0 TE0L TE0 R √ √ √ 0000H
F01B1H – – –
F01B2H Timer channel start register 0 TS0L TS0 R/W √ √ √ 0000H
F01B3H – – –
F01B4H Timer channel stop register 0 TT0L TT0 R/W √ √ √ 0000H
F01B5H – – –
F01B6H Timer clock select register 0 TPS0 R/W – – √ 0000H
F01B7H
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1-bit 8-bit 16-bit
F01B8H Timer output register 0 TO0L TO0 R/W – √ √ 0000H
F01B9H – – –
F01BAH Timer output enable register 0 TOE0L TOE0 R/W √ √ √ 0000H
F01BBH – – –
F01BCH Timer output level register 0 TOL0L TOL0 R/W – √ √ 0000H
F01BDH – – –
F01BEH Timer output mode register 0 TOM0L TOM0 R/W – √ √ 0000H
F01BFH – – –
F0230H IICA control register 00 IICCTL00 R/W √ √ – 00H
F0231H IICA control register 01 IICCTL01 R/W √ √ – 00H
F0232H IICA low-level width setting register 0 IICWL0 R/W – √ – FFH
F0233H IICA high-level width setting register 0 IICWH0 R/W – √ – FFH
F0234H Slave address register 0 SVA0 R/W – √ – 00H
F0240H Event output destination select register00 ELSELR00 R/W – √ – 00H
F024AH Event output destination select register10 ELSELR10 R/W – √ – 00H
F024BH Event output destination select register11 ELSELR11 R/W – √ – 00H
F024CH Event output destination select register12 ELSELR12 R/W – √ – 00H
F024DH Event output destination select register13 ELSELR13 R/W – √ – 00H
F024EH Event output destination select register14 ELSELR14 R/W – √ – 00H
F025FH Event output destination select register15 ELSELR15 R/W – √ – 00H
F0280H Multiplication data register A (L) (Unsigned) MUL32UL R/W – – √ 0000H
F0281H
F0282H Multiplication data register A (H) (Unsigned) MUL32UH R/W – – √ 0000H
F0283H
F0284H Multiplication data register A (L) (Signed) MUL32SL R/W – – √ 0000H
F0285H
F0286H Multiplication data register A (H) (Signed) MUL32SH R/W – – √ 0000H
F0287H
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1-bit 8-bit 16-bit
F0288H Multiply-accumulation data register A (L) MAC32UL R/W – – √ 0000H
F0289H (Unsigned)
F028AH Multiply-accumulation data register A (H) MAC32UH R/W – – √ 0000H

F028BH (Unsigned)
F028CH Multiply-accumulation data register A (L) MAC32SL R/W – – √ 0000H

F028DH (Signed)
F028EH Multiply-accumulation data register A (H) MAC32SH R/W – – √ 0000H

F028FH (Signed)
F0290H Multiplication result register 0 MULR0 R/W – – √ 0000H

F0291H
F0293H
F0295H
F0297H
F029AH Multiplication control register MULC R/W √ √ – 00H
F02D0H Oscillation stop detection register OSDC R/W – – √ 0FFFH
F02D1H
F02D8H High-speed on-chip oscillator clock frequency HOCOFC R/W – √ – 00H
correction control register
F02E0H DTC base address register DTCBAR R/W – √ – 00H
Note 1
F02E5H PLL control register DSCCTL R/W √ √ – 00H
F02E6H Main clock control registerNote 1 MCKC R/W √ √ – 00H
F02E8H DTC Activation Enable Register 0 DTCEN0 R/W √ √ – 00H
F02E9H DTC Activation Enable Register 1 DTCEN1 R/W √ √ – 00H
F02EAH DTC Activation Enable Register 2 DTCEN2 R/W √ √ – 00H
F02EBH DTC Activation Enable Register 3 DTCEN3 R/W √ √ – 00H
F02ECH DTC Activation Enable Register 4 DTCEN4 R/W √ √ – 00H
F02F0H Flash memory CRC control register CRC0CTL R/W √ √ – 00H
F02F2H Flash memory CRC operation result register PGCRCL R/W – – √ 0000H
F02F3H
F02FAH CRC data register CRCD R/W – – √ 0000H
F02FBH
F0300H LCD port function register 0 PFSEG0 R/W √ √ – F0H
F0301H LCD port function register 1 PFSEG1 R/W √ √ – FFH
F0302H LCD port function register 2 PFSEG2 R/W √ √ – FFH
F0303H LCD port function register 3 PFSEG3 R/W √ √ – FFH/0FHNote 2
F0304H LCD port function register 4 PFSEG4 R/W √ √ – FFH/3FHNote 3
F0305H LCD port function register 5 PFSEG5 R/W √ √ – 03H
F0308H LCD Input switch control register ISCLCD R/W √ √ – 00H
Notes 1. This register is incorporated in R5F10NPJ, R5F10NMJ, and R5F10NPG, but is not incorporated in
R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE.
2. R5F10NPJ, R5F10NMJ, R5F10NPG: FFH
R5F10NMG, R5F10NLG, R5F10NME, R5F10NLE: 0FH
3. R5F10NPJ, R5F10NMJ, R5F10NPG: FFH
R5F10NMG, R5F10NLG, R5F10NME, R5F10NLE: 3FH
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1-bit 8-bit 16-bit
F0312H Frequency measurement count register L FMCRL R – – √ 0000H
F0313H
F0314H Frequency measurement count register H FMCRH R – – √ 0000H
F0315H
F0316H Frequency measurement control register FMCTL R/W √ √ – 00H
F0330H Backup power switch control register 0 BUPCTL0 R/W √ √ – 00H
F0331H Backup power switch control register 1 BUPCTL1 R/W √ √ – 00H
F0332H VDD pin voltage detection control register LVDVDD R/W √ √ – 00H
F0333H VBAT pin voltage detection control register LVDVBAT R/W √ √ – 00H
F0334H VRTC pin voltage detection control register LVDVRTC R/W √ √ – 00H
F0335H EXLVD pin voltage detection control register LVDEXLVD R/W √ √ – 00H
F0350H 8-bit interval timer compare register 00 TRTC TRTC R/W – √ √ FFH
MP00 MP0
F0351H 8-bit interval timer compare register 01 TRTC R/W – √ FFH
MP01
F0352H 8-bit interval timer control register 0 TRTCR0 R/W √ √ – 00H
F0353H 8-bit interval timer frequency division register 0 TRTMD0 R/W – √ – 00H
F0358H 8-bit interval timer compare register 10 TRTC TRTC R/W – √ √ FFH
MP10 MP1
F0359H 8-bit interval timer compare register 11 TRTC R/W – √ FFH
MP11
F035AH 8-bit interval timer control register 1 TRTCR1 R/W √ √ – 00H
F035BH 8-bit interval timer frequency division register 1 TRTMD1 R/W – √ – 00H
F0380H RTC power-on-reset status register RTCPORSR R/W – √ – 00H
F0382H Noise filter enable register for RTCICn pin RTCICNFEN R/W – √ – 00H
(n = 0-2)
F0384H Sub clock operation mode control register SCMC R/W – √ – 00H
F0386H Sub clock operation status control register SCSC R/W √ √ – 40H
F03A0H IrDA control register IRCR R/W √ √ – 00H
F03B0H Temperature sensor control register TMPCTL R/W √ √ – 00H
F03C0H ΔΣ A/D converter mode register DSADMR R/W – – √ 0000H
F03C1H
F03C2H ΔΣ A/D converter gain control register 0 DSADGCR0 R/W – √ – 00H
F03C3H ΔΣ A/D converter gain control register 1 DSADGCR1 R/W – √ – 00H
F03C5H ΔΣ A/D converter HPF control register DSADHPFCR R/W – √ – 00H
F03C8H ΔΣ A/D converter interrupt control register DSADICR R/W – √ – 00H
F03C9H ΔΣ A/D converter interrupt clear register DSADICLR W – √ – 00H
F03CAH ΔΣ A/D converter interrupt status register DSADISR R – √ – 22H
F03D0H ΔΣ A/D converter phase control register 0 DSADPHCR0 R/W – – √ 0000H
F03D1H
F03D3H
F03D5H
F03D6H ΔΣ A/D converter phase control register 3Note DSADPHCR3 R/W – – √ 0000H
F03D7H
Note This register is incorporated with 100-or 64-pin products, but is not incorporated with 80-pin products.
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1-bit 8-bit 16-bit
F03E0H ΔΣ A/D converter conversion result register 0L DSADC DSAD R – √ √ 00H
R0L CR0
F03E1H ΔΣ A/D converter conversion result register 0M DSADC R – √ 00H
R0M
F03E2H ΔΣ A/D converter conversion result register 0H DSADCR0H R – √ – 00H
F03E4H ΔΣ A/D converter conversion result register 1L DSADC DSA R – √ √ 00H
R1L DCR
F03E5H ΔΣ A/D converter conversion result register 1M DSADC 1 R – √ 00H
R1M
F03E6H ΔΣ A/D converter conversion result register 1H DSADCR1H R – √ – 00H
F03E8H ΔΣ A/D converter conversion result register 2L DSADC DSAD R – √ √ 00H
R2L CR2
F03E9H ΔΣ A/D converter conversion result register 2M DSADC R – √ 00H
R2M
F03EAH ΔΣ A/D converter conversion result register 2H DSADCR2H R – √ – 00H
F03ECH ΔΣ A/D converter conversion result register 3L Note
DSADC DSAD R – √ √ 00H
R3L CR3
F03EDH ΔΣ A/D converter conversion result register 3MNote DSADC R – √ 00H
R3M
F03EEH ΔΣ A/D converter conversion result register 3HNote DSADCR3H R – √ – 00H
F0400H LCD display data memory 0 SEG0 R/W – √ – 00H
F040AH LCD display data memory 10 SEG10 R/W – √ – 00H
F040BH LCD display data memory 11 SEG11 R/W – √ – 00H
F040CH LCD display data memory 12 SEG12 R/W – √ – 00H
F040DH LCD display data memory 13 SEG13 R/W – √ – 00H
F040EH LCD display data memory 14 SEG14 R/W – √ – 00H
F040FH LCD display data memory 15 SEG15 R/W – √ – 00H
Note This register is incorporated with 100-or 64-pin products, but is not incorporated with 100- or 80-pin products.
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F041AH LCD display data memory 26 SEG26 R/W – √ – 00H
F041BH LCD display data memory 27 SEG27 R/W – √ – 00H
F041CH LCD display data memory 28 SEG28 R/W – √ – 00H
F041DH LCD display data memory 29 SEG29 R/W – √ – 00H
F041EH LCD display data memory 30 SEG30 R/W – √ – 00H
F041FH LCD display data memory 31 SEG31 R/W – √ – 00H
F0540H 8-bit interval timer count register 00 TRT00 TRT0 R – √ √ 00H
F0541H 8-bit interval timer count register 01 TRT01 R – √ 00H
F0548H 8-bit interval timer count register 10 TRT10 TRT1 R – √ √ 00H
F0549H 8-bit interval timer count register 11 TRT11 R – √ 00H
F0581H 64Hz counter R64CNT R – √ – Undefined
F0583H Second counter RSECCNT R/W – √ – Undefined
F0583H Binary counter 0 BCNT0 R/W – √ – Undefined
F0585H Minute counter RMINCNT R/W – √ – Undefined
F0587H Hour counter RHRCNT R/W – √ – Undefined
F0589H Week counter RWKCNT R/W – √ – Undefined
F058BH Day counter RDAYCNT R/W – √ – Undefined
F058DH Month counter RMONCNT R/W – √ – Undefined
F058EH Year counter RYRCNT R/W – – √ Undefined
F058FH
F0591H Second alarm register RSECAR R/W – √ – Undefined
F0591H Binary counter 0 alarm register BCNT0AR R/W – √ – Undefined
F0593H Minute alarm register RMINAR R/W – √ – Undefined
F0595H Hour alarm register RHRAR R/W – √ – Undefined
F0597H Week alarm register RWKAR R/W – √ – Undefined
F0599H Day alarm register RDAYAR R/W – √ – Undefined
F0599H Binary counter 0 alarm enable register BCNT0AER R/W – √ – Undefined
F059BH Month alarm register RMONAR R/W – √ – Undefined
F059BH Binary counter 1 alarm enable register BCNT1AER R/W – √ – Undefined
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1-bit 8-bit 16-bit
F059CH Year alarm register RYRAR R/W – – √ Undefined
F059DH
F059CH Binary counter 2 alarm enable register BCNT2AER R/W – – √ Undefined
F059DH
F059FH Year alarm enable register RYRAREN R/W – √ – Undefined
F059FH Binary counter 3 alarm enable register BCNT3AER R/W – √ – Undefined
F05A1H RTC status register RSR R/W – √ – Undefined
F05A3H RTC control register 1 RCR1 R/W – √ – Undefined
F05AFH Time error correction register RADJ R/W – √ – Undefined
F05B3H RTC control register 5 RCR5 R/W – √ – Undefined
F05B9H RCR5 guard register RCR5GD W – √ – 00H
F05C1H Time capture control register 0 RTCCR0 R/W – √ – Undefined
F05D3H Second capture register 0 RSECCP0 R – √ – Undefined
F05D3H BCNT 0 capture register 0 BCNT0CP0 R – √ – Undefined
F05D5H Minute capture register 0 RMINCP0 R – √ – Undefined
F05D7H Hour capture register 0 RHRCP0 R – √ – Undefined
F05DBH Day capture register 0 RDAYCP0 R – √ – Undefined
F05DBH BCNT 3 capture register 0 BCNT3CP0 R – √ – Undefined
F05DDH Month capture register 0 RMONCP0 R – √ – Undefined
F05E3H Second capture register 1 RSECCP1 R – √ – Undefined
F05E3H BCNT 0 capture register 1 BCNT0CP1 R – √ – Undefined
F05E5H Minute capture register 1 RMINCP1 R – √ – Undefined
F05E7H Hour capture register 1 RHRCP1 R – √ – Undefined
F05EBH Day capture register 1 RDAYCP1 R – √ – Undefined
F05EBH BCNT 3 capture register 1 BCNT3CP1 R – √ – Undefined
F05EDH Month capture register 1 RMONCP1 R – √ – Undefined
F05F3H Second capture register 2 RSECCP2 R – √ – Undefined
F05F3H BCNT 0 capture register 2 BCNT0CP2 R – √ – Undefined
F05F5H Minute capture register 2 RMINCP2 R – √ – Undefined
F05F7H Hour capture register 2 RHRCP2 R – √ – Undefined
F05FBH Day capture register 2 RDAYCP2 R – √ – Undefined
F05FBH BCNT 3 capture register 2 BCNT3CP2 R – √ – Undefined
F05FDH Month capture register 2 RMONCP2 R – √ – Undefined
Remark For SFRs in the SFR area, see Table 3-5 SFR List.
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3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: –128 to +127 or –32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 3-12. Outline of Relative Addressing
PC Instruction code
OP code
DISPLACE 8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-13. Example of CALL !!addr20/BR !!addr20
PC Instruction code
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 3-14. Example of CALL !addr16/BR !addr16
PC PCS PCH PCL Instruction code

OP code
Low Addr.
0000
High Addr.
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3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-15. Outline of Table Indirect Addressing
Instruction code
OP code
High Addr.
00000000 10 0
Low Addr.
Table address
Memory
0000
PC PCS PCH PCL
3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR
AX instructions.
Figure 3-16. Outline of Register Direct Addressing
Instruction code
OP code
CS rp
PC PCS PCH PCL
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3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Implied addressing can be applied only to MULU X.
Figure 3-17. Outline of Implied Addressing
Instruction code
OP code A register
Memory
(register area)
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
Figure 3-18. Outline of Register Addressing
Instruction code
OP code Register
Memory
(register bank area)
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3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
!addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES:!addr16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-19. Example of !addr16
MOV !addr16, A
FFFFFH
<1>
Instruction code
OP-code Target memory
Low Addr.
<1>
High Addr. F0000H
A 16-bit address <1> in the 64 KB area from

F0000H to FFFFFH specifies the target location
(for use in access to the 2nd SFRs etc.).
Memory
Figure 3-20. Example of ES:!addr16
ES: !addr16
FFFFFH
<1> <2>
Instruction code
Area from
OP-code Target memory X0000H to
Specifies the XFFFFH
Low Addr. address in memory
<2>
High Addr. X0000H
Specifies a
64 KB area
ES
00000H
The ES register <1> specifies a 64 KB area within the
overall 1 MB space as the four higher-order bits, X, of Memory
the address range.
A 16-bit address <2> in the area from X0000H to XFFFFH
and the ES register <1> specify the target location;
this is used for access to fixed data other than
that in mirrored areas.
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3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
SADDR Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 3-21. Outline of Short Direct Addressing
Instruction code
OP code
FFF1FH
saddr saddr
FFE20H
Memory
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20-
bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
SFR SFR name
SFRP 16-bit-manipulatable SFR name (even address)
Figure 3-22. Outline of SFR Addressing
Instruction code
FFFFFH
OP code SFR
FFF00H
SFR
Memory
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3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
– [DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
– ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-23. Example of [DE], [HL]
FFFFFH
[DE], [HL]
<1> <1>
Target memory
Instruction code <1>
Specifies the
<1>
address in memory
OP-code rp(HL/DE)
F0000H
Either pair of registers <1> specifies the target

location as an address in the 64 KB area from
F0000H to FFFFFH.
Memory
Figure 3-24. Example of ES:[DE], ES:[HL]
ES: [DE], ES: [HL]

<1> <2> <1> <2> FFFFFH
Target memory Area from

Instruction code <2> Specifies the X0000H to
<2> address in memory XFFFFH
OP-code rp(HL/DE)
X0000H
<1> <1> Specifies a

64 KB area
ES
The ES register <1> specifies a 64 KB area within the 00000H

overall 1 MB space as the four higher-order bits, X, of Memory
the address range.
Either pair of registers <2> and the ES register <1> specify
the target location in the area from X0000H to XFFFFH.
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3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as
a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used
to specify the target address.
[Operand format]
– [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
– word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
– word[BC] (only the space from F0000H to FFFFFH is specifiable)
– ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
– ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
– ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-25. Example of [SP+byte]
FFFFFH
Instruction code
<1> Target memory

<2> Stack area
Offset
<2> byte
Specifies a
<1> stack area
SP F0000H
SP (stack pointer) <1> indicates the stack as the

target.
By indicating an offset from the address (top of the
stack) currently pointed to by the stack pointer, Memory
“byte” <2> indicates the target memory (SP + byte).
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Figure 3-26. Example of [HL + byte], [DE + byte]
[HL + byte], [DE + byte]

<1> <2> <1> <2> FFFFFH
Instruction code
OP-code Target
Target memory
<2> Offset array
<2> byte of data
<1> Address of
an array Other data in
rp(HL/DE) the array
F0000H
Either pair of registers <1> specifies the address

where the target array of data starts in the 64 KB
area from F0000H to FFFFFH.
“byte” <2> specifies an offset within the array to
the target location in memory.
Memory
Figure 3-27. Example of word[B], word[C]
word [B], word [C]

<1> <2> <1> <2> FFFFFH
Array of
Instruction code Target memory
word-sized
<2> <2> Offset
OP-code r(B/C) data
Address of a word
Low Addr. <1> within an array
High Addr. F0000H
“word” <1> specifies the address where the target

array of word-sized data starts in the 64 KB area
from F0000H to FFFFFH.
Either register <2> specifies an offset within the
array to the target location in memory. Memory
Figure 3-28. Example of word[BC]
word [BC]
FFFFFH
<1> <2>
Target memory Array of

Instruction code <2>
<2> word-sized
Offset
OP-code data
rp(BC)
Address of a word
Low Addr. <1> within an array
<1>
F0000H
High Addr.
“word” <1> specifies the address where the target

array of word-sized data starts in the 64 KB area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory. Memory
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Figure 3-29. Example of ES:[HL + byte], ES:[DE + byte]
ES: [HL + byte], ES: [DE + byte]

<1> <2> <3> <1> <2> <3>
XFFFFH
Instruction code
<2>
OP-code <3> Target memory Target
Offset array
<3> byte of data
<2> Address of
an array Other data in
rp(HL/DE) the array
X0000H X0000H
<1> Specifies a
<1>
64 KB area
ES
The ES register <1> specifies a 64 KB

area within the overall 1 MB space as
the four higher-order bits, X, of the address range. Memory
Either pair of registers <2> specifies the address
where the target array of data starts in the 64 KB
area specified in the ES register <1>.
“byte” <3> specifies an offset within the array to the
target location in memory.
Figure 3-30. Example of ES:word[B], ES:word[C]
ES: word [B], ES: word [C]

<1> <2> <3> <1> <2> <3>
XFFFFH
Instruction code <3> Array of

<3> Target memory
Offset word-sized
OP-code
data
r(B/C)
Low Addr. <2>
Address of a word within an array
<2>
High Addr. X0000H
X0000H
<1> Specifies a
<1> 64 KB area
ES
The ES register <1> specifies a 64 KB area within the overall

Memory
1 MB space as the four higher-order bits, X, of the address range.
“word” <2> specifies the address where the target array of word-sizeddata
starts in the 64 KB area specified in the ES register <1>.
Either register <3> specifies an offset within the array to the target location
in memory.
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Figure 3-31. Example of ES:word[BC]
ES: word [BC]

<1> <2> <3> XFFFFH
Instruction code Target memory Array of

<3>
<3> word-sized
Offset
OP-code data
rp(BC)
<2>
Low Addr. Address of a word within an array
<2>
High Addr. X0000H X0000H
<1> <1> Specifies a
64 KB area
ES
The ES register <1> specifies a 64 KB area within the

overall 1 MB space as the four higher-order bits, X, of
the address range. Memory
“word” <2> specifies the address where the target array of
word-sized data starts in the 64 KB area specified in the
ES register <1>.
A pair of registers <3> specifies an offset within the array
to the target location in memory.
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3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
– [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
– ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-32. Example of [HL+B], [HL+C]
[HL +B], [HL+C]

<1> <2> <1> <2> FFFFFH
Target
Instruction code Target memory array
<2> Offset of data
OP-code r(B/C)
Address of
<1> an array Other data in
rp(HL) the array
F0000H
A pair of registers <1> specifies the address where the target

array of data starts in the 64 KB area from F0000H to FFFFFH.
Either register <2> specifies an offset within the array to the
target location in memory
Memory
Figure 3-33. Example of ES:[HL+B], ES:[HL+C]
ES: [HL +B], ES: [HL +C]

<1> <2> <3> <1> <2> <3>
XFFFFH
<3> <3> Target memory Target

array
Offset
Instruction code r(B/C) of data
<2> Address of
<2> the array Other data in
OP-code rp(HL) the array
X0000H X0000H
<3> byte
Specifies a
<1> <1> 64 KB area
ES
The ES register <1> specifies a 64 KB area within the overall

1 MB space as the four higher-order bits, X, of the address range. Memory
A pair of registers <2> specifies the address where the target
array of data starts in the 64 KB area specified in the ES
register <1>.
Either register <3> specifies an offset within the array to the
target location in memory.
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed
when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon
generation of an interrupt request.
Only the internal RAM area can be set as the stack area.
[Operand format]
– PUSH PSW AX/BC/DE/HL

POP PSW AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
Each stack operation saves or restores data as shown in Figures 3-33 to 3-38.
Figure 3-34. Example of PUSH rp
PUSH rp
<1> <2>
<1> SP
Instruction code SP - 1 Higher byte of rp
<3> SP - 2 Lower byte of rp Stack area
OP-code <2> SP
rp F0000H
Stack addressing is specified <1>.
The higher and lower bytes of the pair of registers indicated
by rp <2> are stored in addresses SP - 1 and SP - 2, respectively.
The value of SP <3> is decreased by two (if rp is the program
status word (PSW), the value of the PSW is stored in SP - 1 and
Memory
0 is stored in SP - 2).
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Figure 3-35. Example of POP
POP rp
<1> <2>
<1> SP+ 2
SP (SP+1)
Instruction code SP+ 1 Stack
SP (SP) area
OP-code <2> SP
F0000H
rp

The contents of addresses SP and SP + 1 are stored in the
lower and higher bytes of the pair of registers indicated by
rp <2>, respectively. Memory
The value of SP <3> is increased by two (if rp is the program
status word (PSW), the content of address SP + 1 is stored in
the PSW).
Figure 3-36. Example of CALL, CALLT
CALL
<1>
<1> SP SP - 1 Stack
Instruction code 00H
SP - 2 area
PC19 - PC16
OP-code SP - 3 PC15 - PC8
<3> SP - 4 PC7 - PC0
SP
<2>
F0000H
PC
Stack addressing is specified <1>. The value of the program

counter (PC) changes to indicate the address of the instruction Memory
following the CALL instruction.
00H, the values of PC bits 19 to 16, 15 to 8, and 7 to 0 are stored
in addresses SP - 1, SP - 2, SP - 3, and SP - 4, respectively <2>.
The value of the SP <3> is decreased by 4.
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Figure 3-37. Example of RET
RET
<1> SP+4
<1> SP SP+3 (SP+3)
Instruction code
SP+2 (SP+2) Stack
OP-code area
SP+1 (SP+1)
<3> SP (SP)
SP
<2> F0000H
PC

The contents of addresses SP, SP + 1, and SP + 2 are stored
in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>. Memory
The value of SP <3> is increased by four.
Figure 3-38. Example of Interrupt, BRK
<2>
PSW
SP Stack
Instruction code SP - 1 PSW
<1> SP - 2 PC19 - PC16 area
OP-code SP - 3 PC15 - PC8
or SP <3> SP - 4 PC7 - PC0
Interrupt
<2>
F0000H
PC
Stack addressing is specified <1>. In response to a BRK

instruction or acceptance of an interrupt, the value of the Memory
program counter (PC) changes to indicate the address of
the next instruction.
The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to
0 are stored in addresses SP - 1, SP - 2, SP - 3, and
SP - 4, respectively <2>.
The value of the SP <3> is decreased by 4.
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Figure 3-39. Example of RETI, RETB
RETI, RETB
<1> PSW
SP+4
<1> SP
Instruction code SP+3 (SP+3)
SP+2 (SP+2) Stack
OP-code SP+1 (SP+1) area
<3> SP (SP)
SP
<2> F0000H
PC

The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are Memory
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively
<2>.
The value of SP <3> is increased by four.
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RL78/I1C CHAPTER 4 PORT FUNCTIONS
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The RL78/I1C microcontrollers are provided with digital I/O ports, which enable variety of control operations.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS.
4.2 Port Configuration
Ports include the following hardware.
Table 4-1. Port Configuration
Item Configuration
Control registers Port mode registers (PM0 to PM8, PM12, PM15)

Port registers (P0 to P8, P12, P13, P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU8, PU12, PU15)
Port input mode registers (PIM0, PIM1, PIM5, PIM8)
Port output mode registers (POM0, POM1, POM5, POM8)
A/D port configuration register (ADPC)
Peripheral I/O redirection register (PIOR0)
Global digital input disable register (GDIDIS)
LCD port function registers (PFSEG0 to PFSEG5)
LCD input switch control register (ISCLCD)
Port ● 64-pin products
Total: 35 (CMOS I/O: 27 (N-ch open drain I/O [VDD tolerance]: 6), CMOS input: 5,
N-ch open drain I/O [6 V tolerance]: 3)
● 80-pin products
Total: 52 (CMOS I/O: 44 (N-ch open drain I/O [EVDD tolerance]: 14), CMOS input: 5,
● 100-pin products
Total: 68 (CMOS I/O: 60 (N-ch open drain I/O [EVDD tolerance]: 17), CMOS input: 5,
Pull-up resistor ● 64-pin products Total: 24
● 80-pin products Total: 41
● 100-pin products Total: 55
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4.2.1 Port 0
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P02 to P07 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P02, P03, P05 and P06 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
units using port input mode register 0 (PIM0).
Output from the P02 to P07 pins can be specified as N-ch open-drain output (VDD toleranceNote 1/ EVDD toleranceNote 2) in
1-bit units using port output mode register 0 (POM0).
This port can also be used for programming UART transmission/reception, serial interface data I/O, clock I/O, timer I/O,
and external interrupt request input. For the 80-pin products, this port can be used for segment output of LCD
controller/driver.
Reset signal generation sets port 0 to input mode. For the 80-pin products, P02 to P07 pins are set to the digital input
invalid modeNote 3.
Notes 1. For 64-pin products

2. For 80, 100-pin products
3. “Digital input invalid” refers to the state in which all the digital outputs, digital inputs, and LCD outputs are
disabled.
4.2.2 Port 1
Input to the P12Note 1, P13Note 1, P15, and P16 pins can be specified through a normal input buffer or a TTL input buffer
in 1-bit units using port input mode register 1 (PIM1).
Output from the P12 to P14Note 1 and P15 to P17 pins can be specified as N-ch open-drain output (VDD toleranceNote 1/
EVDD toleranceNote 2) in 1-bit units using port output mode register 1 (POM1).
This port can also be used for serial interface data I/O, clock I/O, and segment output of LCD controller/driver.
Reset signal generation sets port 1 to the digital input invalid modeNote 3.

disabled.
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4.2.3 Port 2
mode register 2 (PM2).
This port can also be used for analog inputs to the A/D converter, reference voltage inputs (positive and negative sides),
and an electric potential input for the detection of low external voltages.
To use P20/ANI0 to P25/ANI5 as digital I/O pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC). Use these pins starting from the upper bit.
To use P20/ANI0 to P25/ANI5 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit.
Reset signal generation sets port 2 to the analog input mode.
Table 4-2. Setting Functions of ANI0/P21 to ANI5/P25 Pins
ADPC Register PM2 Register ADS Register P20/AVREFP/ANI0, P21/AVREFM/ANI1,

P22/ANI2/EXLVD,
P23/ANI3, P24/ANI4, and P25/ANI5 Pins
Digital I/O selection Input mode × Digital input
Output mode × Digital output

Analog input selection Input mode Selects ANI. Analog input (to be converted)
(when ANI0 to ANI5 pins are used)
Does not select ANI. Analog input (not to be converted)
(when EXLVD pin is used)
Output mode Selects ANI. Setting prohibited
Does not select ANI.
Remark ×: don’t care
4.2.4 Port 3
For 64-pin products, input to the P30 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit
units using port input mode register 3 (PIM3). For 64-pin products, output from the P31 pin can be specified as N-ch open-
drain output (VDD tolerance) in 1-bit units using port output mode register 3 (POM3).
This port can also be used for clock/buzzer output, timer I/O, and segment output of LCD controller/driver. For 64-pin
products, this port can also be used for serial interface data I/O, transmission/reception for IrDA, and external interrupt
request input.
Reset signal generation sets port 3 to the digital input invalid modeNote.
Note “Digital input invalid” refers to the state in which all the digital outputs, digital inputs, and LCD outputs are
disabled.
4.2.5 Port 4
This port can also be used for external interrupt request input , clock/buzzer output, timer I/O, and data I/O for a flash
memory programmer/debugger.
Reset signal generation sets port 4 to input mode.
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4.2.6 Port 5
specified in 1-bit units by pull-up resistor option register 5 (PU5). Input to the P55 and P57 pins can be specified through a
normal input buffer or a TTL input buffer in 1-bit units using port input mode register 5 (PIM5). Output from the P56 and
P57 pins can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units using port output mode register 5
(POM5).
This port can also be used for serial interface data I/O, clock I/O, transmission/reception for IrDA, and segment output
of LCD controller/driver.
disabled.
4.2.7 Port 6
mode register 6 (PM6).
The output of the P60, P61, and P62 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O, clock I/O, timer I/O, and real-time clock correction clock output.
Reset signal generation sets port 6 to input mode.
4.2.8 Port 7
This port can also be used for segment output of LCD controller/driver, key interrupt input, and external interrupt
request input.
disabled.
4.2.9 Port 8
Input to the P80, P81, and P84 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 8 (PIM8).
Output from the P80 to P82, P84, and P85 pins can be specified as N-ch open-drain output (VDD toleranceNote 1/ EVDD
toleranceNote 2) in 1-bit units using port output mode register 8 (POM8).
This port can also be used for serial interface data I/O, clock I/O, and segment output of LCD controller/driver.
Reset signal generation sets port 8 to the digital input invalid modeNote 3.

disabled.
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4.2.10 Port 12
P125 to P127 are an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When the P125 to P127 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 are 4-bit input-only ports.
This port can also be used for connecting resonator for main system clock, connecting resonator for subsystem clock,
external clock input for main system clock, external clock input for subsystem clock, connecting a capacitor for LCD
controller/driver, power supply voltage pin for driving the LCD, external interrupt request input, and timer I/O.
Reset signal generation sets P121 to P124 to input mode. P125 to P127 are set in the digital invalid modeNote.
disabled.
4.2.11 Port 13
P137 is a 1-bit input-only port. P137 is fixed an input mode.
This port can also be used for external interrupt request input.
4.2.12 Port 15
specified in 1-bit units by pull-up resistor option register 15 (PU15). The default setting following assertion of the reset
signal is for the pull-up resistors of P150 to P152 to be enabled.
This port can also be used for RTC time capture input and real-time clock correction clock output.
Reset signal generation sets port 15 to input mode (connected to the internal pull-up resistor).
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4.3 Registers Controlling Port Function
Port functions are controlled by the following registers.
● Port mode registers (PMxx)

● Port registers (Pxx)
● Pull-up resistor option registers (PUxx)
● Port input mode registers (PIMxx)
● Port output mode registers (POMxx)
● A/D port configuration register (ADPC)
● Peripheral I/O redirection register (PIOR0)
● Global digital input disable register (GDIDIS)
● LCD port function registers (PFSEG0 to PFSEG5)
● LCD input switch control register (ISCLCD)
Caution Which registers and bits are included depends on the product. For registers and bits mounted on
each product, see Table 4-3. Be sure to set bits that are not mounted to their initial values.
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Table 4-3. PMxx, Pxx, PUxx, PIMxx, POMxx Registers and the Bits Mounted on Each Product (1/3)
Port Bit Name 64 80 100

PMxx Pxx PUxx PIMxx POMxx Pin Pin Pin
Register Register Register Register Register
Port 0 0 – – – – – – – –
1 – – – – – – – –
2 PM02 P02 PU02 PIM02 POM02 – √ √
3 PM03 P03 PU03 PIM03 POM03 – √ √
4 PM04 P04 PU04 – POM04 – √ √
5 PM05 P05 PU05 PIM05 POM05 √ √ √
6 PM06 P06 PU06 PIM06 POM06 √ √ √
7 PM07 P07 PU07 – POM07 √ √ √
Port 1 0 PM10 P10 PU10 – – √ √ √
1 PM11 P11 PU11 – – √ √ √
Note Note
2 PM12 P12 PU12 PIM12 POM12 √ √ √
3 PM13 P13 PU13 PIM13 Note POM13 Note √ √ √
4 PM14 P14 PU14 – POM14 Note √ √ √
5 PM15 P15 PU15 PIM15 POM15 √ √ √
6 PM16 P16 PU16 PIM16 POM16 √ √ √
7 PM17 P17 PU17 – POM17 √ √ √
Port 2 0 PM20 P20 – – – √ √ √
1 PM21 P21 – – – √ √ √
2 PM22 P22 – – – √ √ √
3 PM23 P23 – – – √ √ √
4 PM24 P24 – – – – – √
5 PM25 P25 – – – – – √
6 – – – – – – – –
7 – – – – – – – –
Note
Port 3 0 PM30 P30 PU30 PIM30 – √ √ √
Note
1 PM31 P31 PU31 – POM31 √ √ √
2 PM32 P32 PU32 – – – √ √
3 PM33 P33 PU33 – – – √ √
4 PM34 P34 PU34 – – – – √
5 PM35 P35 PU35 – – – – √
6 PM36 P36 PU36 – – – – √
7 PM37 P37 PU37 – – – – √
Note For 64-pin products
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Port 4 0 PM40 P40 PU40 – – √ √ √

1 PM41 P41 PU41 – – – √ √
2 PM42 P42 PU42 – – – – √
3 PM43 P43 PU43 – – – – √
4 – – – – – – – –
5 – – – – – – – –
6 – – – – – – – –
7 – – – – – – – –
Port 5 0 PM50 P50 PU50 – – – – √
1 PM51 P51 PU51 – – – – √
2 PM52 P52 PU52 – – – – √
3 PM53 P53 PU53 – – – – √
4 PM54 P54 PU54 – – – – √
5 PM55 P55 PU55 PIM55 – – √ √
6 PM56 P56 PU56 – POM56 – √ √
7 PM57 P57 PU57 PIM57 POM57 – – √
Port 6 0 PM60 P60 – – – √ √ √
1 PM61 P61 – – – √ √ √
2 PM62 P62 – – – √ √ √
3 – – – – – – – –
4 – – – – – – – –
5 – – – – – – – –
6 – – – – – – – –
7 – – – – – – – –
Port 7 0 PM70 P70 PU70 – – √ √ √
1 PM71 P71 PU71 – – √ √ √
2 PM72 P72 PU72 – – √ √ √
3 PM73 P73 PU73 – – √ √ √
4 PM74 P74 PU74 – – √ √ √
5 PM75 P75 PU75 – – – √ √
6 PM76 P76 PU76 – – – √ √
7 PM77 P77 PU77 – – – √ √
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Port 8 0 PM80 P80 PU80 PIM80 POM80 – √ √

1 PM81 P81 PU81 PIM81 POM81 – √ √
2 PM82 P82 PU82 – POM82 – √ √
3 PM83 P83 PU83 – – – √ √
4 PM84 P84 PU84 PIM84 POM84 – – √
5 PM85 P85 PU85 – POM85 – – √
6 – – – – – – – –
7 – – – – – – – –
Port 12 0 – – – – – – – –
1 – P121 – – – √ √ √
2 – P122 – – – √ √ √
3 – P123 – – – √ √ √
4 – P124 – – – √ √ √
5 PM125 P125 PU125 – – √ √ √
6 PM126 P126 PU126 – – √ √ √
7 PM127 P127 PU127 – – √ √ √
Port 13 0 – – – – – – – –
1 – – – – – – – –
2 – – – – – – – –
3 – – – – – – – –
4 – – – – – – – –
5 – – – – – – – –
6 – – – – – – – –
7 – P137 – – – √ √ √
Port 15 0 PM150 P150 PU150 – – – √ √
1 PM151 P151 PU151 – – – √ √
2 PM152 P152 PU152 – – – √ √
3 – – – – – – – –
4 – – – – – – – –
5 – – – – – – – –
6 – – – – – – – –
7 – – – – – – – –
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4.3.1 Port mode registers (PMxx)

These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Register Settings
When Using Alternate Function.
Figure 4-1. Format of Port Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 PM07 PM06 PM05 PM04 PM03 PM02 1 1 FFF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM4 1 1 1 1 PM43 PM42 PM41 PM40 FFF24H FFH R/W
PM6 1 1 1 1 1 PM62 PM61 PM60 FFF26H FFH R/W
PM12 PM127 PM126 PM125 1 1 1 1 1 FFF2CH FFH R/W
PM15 1 1 1 1 1 PM152 PM151 PM150 FFF2FH FFH R/W
PMmn Pmn pin I/O mode selection

(m = 0 to 8, 12, 15; n = 0 to 7)
0 Output mode (output buffer on)

1 Input mode (output buffer off)
Caution Be sure to set bits that are not mounted to their initial values.
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4.3.2 Port registers (Pxx)

These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
Reset signal generation clears these registers to 00H.
Note If P20 to P25 are set up as analog inputs of the A/D converter or comparator, when a port is read while in the
input mode, 0 is always returned, not the pin level.
Figure 4-2. Format of Port Register
P0 P07 P06 P05 P04 P03 P02 0 0 FFF00H 00H (output latch) R/W
P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W
P2 0 0 P25 P24 P23 P22 P21 P20 FFF02H 00H (output latch) R/W
P4 0 0 0 0 P43 P42 P41 P40 FFF04H 00H (output latch) R/W
P6 0 0 0 0 0 P62 P61 P60 FFF06H 00H (output latch) R/W
P8 0 0 P85 P84 P83 P82 P81 P80 FFF08H 00H (output latch) R/W
P12 P127 P126 P125 P124 P123 P122 P121 0 FFF0CH Undefined R/WNote
P13 P137 0 0 0 0 0 0 0 FFF0DH Undefined R/WNote
P15 0 0 0 0 0 P152 P151 P150 FFF0FH 00H (output latch) R/W
Pmn Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level

1 Output 1 Input high level
Note P121 to P124 and P137 are read-only.
Remark m = 0 to 8, 12, 13, 15 ; n = 0 to 7
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4.3.3 Pull-up resistor option registers (PUxx)

These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to normal output mode (POMmn = 0) and input mode (PMmn = 1) for the pins to
which the use of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be
connected to bits set to output mode and bits used as alternate-function output pins and analog setting (ADPC = 1),
regardless of the settings of these registers.
Reset signal generation clears these registers to 00H (PU4 is set to 01H, PU15 is set to 07H).
Caution When a port with the PIMn register is input from different potential device to TTL buffer, pull up to the
power supply of the different potential device via an external pull-up resistor by setting PUmn = 0.
Figure 4-3. Format of Pull-up Resistor Option Register
PU0 PU07 PU06 PU05 PU04 PU03 PU02 0 0 F0030H 00H R/W
PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W
PU4 0 0 0 0 PU43 PU42 PU41 PU40 F0034H 01H R/W
PU8 0 0 PU85 PU84 PU83 PU82 PU81 PU80 F0038H 00H R/W
PU12 PU127 PU126 PU125 0 0 0 0 0 F003CH 00H R/W
PU15 0 0 0 0 0 PU152 PU151 PU150 F003FH 07H R/W
PUmn Pmn pin on-chip pull-up resistor selection

(m = 0, 1, 3 to 5, 7, 8, 12, 15 ; n = 0 to 7)
0 On-chip pull-up resistor not connected

1 On-chip pull-up resistor connected
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4.3.4 Port input mode registers (PIMxx)

These registers set the input buffer in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 4-4. Format of Port Input Mode Register
PIM0 0 PIM06 PIM05 0 PIM03 PIM02 0 0 F0040H 00H R/W
PIM1 0 PIM16 PIM15 0 PIM13 Note PIM12 Note 0 0 F0041H 00H R/W
PIM3 Note 0 0 0 0 0 0 0 PIM30 Note F0043H 00H R/W
PIM5 PIM57 0 PIM55 0 0 0 0 0 F0045H 00H R/W
PIM8 0 0 0 PIM84 0 0 PIM81 PIM80 F0048H 00H R/W
PIMmn Pmn pin input buffer selection

(m = 0, 1, 3 Note, 5, 8 ; n = 0 to 7)
0 Normal input buffer

1 TTL input buffer
Note For 64-pin products
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4.3.5 Port output mode registers (POMxx)

These registers set the output mode in 1-bit units.
N-ch open drain output (VDD toleranceNote 1/EVDD toleranceNote 2) mode can be selected during serial communication
with an external device of the different potential, and for the SDA00 and SDA10 pins during simplified I2C communication
with an external device of the same potential.
In addition, POMxx register is set with PUxx register, whether or not to use the on-chip pull-up resistor.
Caution An on-chip pull-up resistor is not connected to a bit for which N-ch open drain output (VDD
toleranceNote 1/EVDD1 toleranceNote 2) mode (POMmn = 1) is set.
Figure 4-5. Format of Port Input Mode Register
POM0 POM07 POM06 POM05 POM04 POM03 POM02 0 0 F0050H 00H R/W
POM1 POM17 POM16 POM15 POM14 POM13 POM12 0 0 F0051H 00H R/W
Note 1 Note 1 Note 1
POM3 Note 1 0 0 0 0 0 0 POM31 0 F0053H 00H R/W

Note 1
POM5 POM57 POM56 0 0 0 0 0 0 F0055H 00H R/W
POM8 0 0 POM85 POM84 0 POM82 POM81 POM80 F0058H 00H R/W
POMmn Pmn pin output mode selection

(m = 0, 1, 5, 8 ; n = 0 to 7)
0 Normal output mode

1 N-ch open-drain output (VDD toleranceNote 1/EVDD1 toleranceNote 2) mode

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4.3.6 A/D port configuration register (ADPC)

This register switches the P20/AVREFP/ANI0, P21/AVREFM/ANI1, P22/ANI2/EXLVD, P23/ANI3, P24/ANI4, and P25/ANI5
pins to digital I/O of port or analog input of A/D converter or comparator.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Figure 4-6. Format of A/D Port Configuration Register (ADPC)
Address: F0076H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPC0
ADPC2 ADPC1 ADPC0 Analog input (A)/digital I/O (D) switching

ANI5/P25 ANI4/P24 ANI3/P23 ANI2/EXLVD/ ANI1/P21 ANI0/P20
P22
0 0 0 A A A A A A
0 0 1 D D D D D D
0 1 0 D D D D D A
0 1 1 D D D D A A
1 0 0 D D D A A A
1 0 1 D D A A A A
1 1 0 D A A A A A
Other than above Setting prohibited
Cautions 1. Set the port to analog input by ADPC register to the input mode by using port mode register 2
(PM2).
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. When using AVREFP and AVREFM, set ANI0 and ANI1 to analog input and set the port mode
register to the input mode.
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4.3.7 Global digital input disable register (GDIDIS)

This register is used to prevent through-current flowing from the input buffers which uses EVDD as power supply when
the battery backup function is enabled and power supply to EVDD is stopped.
By setting the GDIDIS0 bit to 1, input to any input buffer connected to EVDD is prohibited, preventing through-current
from flowing when the power supply connected to EVDD is turned off.
The GDIDIS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 4-7. Format of Global Digital Input Disable Register (GDIDIS)
Address: F007DH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
GDIDIS 0 0 0 0 0 0 0 GDIDIS0
GDIDIS0 Setting of input buffers using EVDD power supply
0 Input to input buffers permitted (default)

1 Input to input buffers prohibited. No through-current flows to the input buffers.
Turn off the EVDD power supply with the following procedure.
1. Prohibit input to input buffers (set GDIDIS0 = 1).
2. Turn off the EVDD power supply.
Turn on again the EVDD power supply with the following procedure.
1. Turn on the EVDD power supply.
2. Permit input to input buffers (set GDIDIS0 = 0).
Cautions 1. Do not input an input voltage equal to or greater than EVDD to an input port that uses EVDD as the
power supply.
2. When input to input buffers is prohibited (GDIDIS0 = 1), the value read from the port register (Pxx)
of a port that uses EVDD as the power supply is 1. When 1 is set in the port output mode register
(POMxx) (N-ch open drain output (EVDD tolerance) mode), the value read from the port register
(Pxx) is 0.
Remark Even when input to input buffers is prohibited (GDIDIS0 = 1), peripheral functions which do not use port
functions having EVDD as the power supply can be used.
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4.3.8 Peripheral I/O redirection register (PIOR0)

This register is used to specify whether to enable or disable the peripheral I/O redirect function.
This function is used to switch ports to which alternate functions are assigned.
Use the PIOR0 register to assign a port to the function to redirect and enable the function.
In addition, can be changed the settings for redirection until its function enable operation.
The PIOR0 register can be set by an 8-bit memory manipulation instruction.
Figure 4-8. Format of Peripheral I/O Redirection Register (PIOR0)

Symbol 7 6 5 4 3 2 1 0
PIOR0 0 0 0 PIOR04 PIOR03 PIOR02 PIOR01 PIOR00
Bit Function 100-pin 80-pin 64-pin

Setting value Setting value Setting value
0 1 0 1 0 1
Note
PIOR04 INTP0 P137 P70 P137 P70 P137 P70
INTP1 P125 P71 P125 P71 P125 P71
INTP2 P07 P72 P07 P72 P07 P72
INTP3 P05 P73 P05 P73 P05 P73
INTP4 P04 P74 P04 P74 P06 P74
INTP5 P02 P75 P02 P75 P30 –
INTP6 P41 P76 P41 P76 P13 –
INTP7 P42 P77 – P77 P16 –
PIOR03 PCLBUZ0 P43 P33 – P33 P43 P74
PCLBUZ1 P41 P32 P41 P32 P125 P73
RTCOUT P150 P62 P150 P62 P43 P62
PIOR02 SO10/TXD1 P04 P82 P04 P82 P14 –
SI10/RXD1/SDA10 P03 P81 P03 P81 P13 –
SCK10/SCL10 P02 P80 P02 P80 P12 –
PIOR01 SO00/TXD0 P07 P17 P07 P17 P07 P17
SI00/RXD0/SDA00 P06 P16 P06 P16 P06 P16
SCK00/SCL00 P05 P15 P05 P15 P05 P15
PIOR00 TI00/TO00 P43 P60 – P60 P43 P60
TI01/TO01 P41 P61 P41 P61 P72 P61
TI02/TO02 P07 P62 P07 P62 P07 P62
TI03/TO03 P06 P127 P06 P127 P06 P127
TI04/TO04 P05 P126 P05 P126 P05 P126
TI05/TO05 P04 P125 P04 P125 P125 –
TI06/TO06 P03 P31 P03 P31 P31 –
TI07/TO07 P02 P30 P02 P30 P30 –
Note Only the P137 pin is available for use as the interrupt when the battery backup function is in use and power is
being supplied through the VBAT pin.
The interrupt function cannot be used if the INTP0 function is assigned to P70 and power is being supplied
through the VBAT pin.
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4.3.9 LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)

These registers set whether to use pins P10 to P17, P30 to P37, P50 to P57, P70 to P77, P80 to P85 as port pins
(other than segment output pins) or segment output pins.
Reset signal generation sets these registers to FFH (PFSEG0 is set to F0H, and PFSEG5 is set to 03H).
Remark The correspondence between the segment output pins (SEGxx) and the PFSEG register (PFSEGxx bits)
and the existence of SEGxx pins in each product are shown in Table 4-4 Segment Output Pins in Each
Product and Correspondence with PFSEG Register (PFSEG Bits).
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Figure 4-9. Format of LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)
Address: F0300H After reset: F0H R/W

Symbol 7 6 5 4 3 2 1 0
PFSEG0 PFSEG07 PFSEG06 PFSEG05 PFSEG04 0 0 0 0
Address: F0301H After reset: FFH R/W

Symbol 7 6 5 4 3 2 1 0
PFSEG1 PFSEG15 PFSEG14 PFSEG13 PFSEG12 PFSEG11 PFSEG10 PFSEG09 PFSEG08

Note 3 Note 3 Note 3 Note 3

Symbol 7 6 5 4 3 2 1 0

Address: F0303H After reset: FFH (R5F10NPJ, R5F10NMJ, R5F10NPG), 0FH (R5F10NMG, R5F10NLG,
R5F10NME, R5F10NLE) R/W
Symbol 7 6 5 4 3 2 1 0

Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3 Note 3 Note 3
Symbol 7 6 5 4 3 2 1 0

Notes 1, 2 Notes 1, 2

Symbol 7 6 5 4 3 2 1 0
PFSEG5 0 0 0 0 0 0 PFSEG41 PFSEG40
PFSEGxx Port (other than segment output)/segment outputs specification of Pmn pins
(xx = 04 to (mn = 10 to 17, 30 to 37, 50 to 57, 70 to 77, 80 to 85)
41)
0 Used the Pmn pin as port (other than segment output)

1 Used the Pmn pin as segment output
Notes 1. For R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE, the initial value is 0.
Writing 1 to this bit does not affect operation, and the value read is 0.
2. Be sure to set "1" for 80-pin products.
3. Be sure to set "1" for 64-pin products.
Remark To use the Pmn pins as segment output pins (PFSEGxx = 1), be sure to set the PUmn bit of the PUm
register, POMmn bit of the POMm register, and PIMmn bit of the PIMm register to “0”.
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Table 4-4. Segment Output Pins in Each Product and Correspondence with PFSEG Register (PFSEG Bits)
Bit Name of PFSEG Register Corresponding SEGxx Pins Alternate Port 64-pin 80-pin 100-pin
PFSEG04 SEG4 P10 √ √ √
PFSEG10 SEG10 P16 √ √ √
PFSEG11 SEG11 P17 √ √ √
PFSEG12 SEG12 P80 – √ √
PFSEG13 SEG13 P81 – √ √
PFSEG14 SEG14 P82 – √ √
PFSEG15 SEG15 P83 – √ √
PFSEG16 SEG16 P70 √ √ √
PFSEG17 SEG17 P71 √ √ √
PFSEG18 SEG18 P72 √ √ √
PFSEG19 SEG19 P73 √ √ √
PFSEG20 SEG20 P74 √ √ √
PFSEG21 SEG21 P75 – √ √
PFSEG22 SEG22 P76 – √ √
PFSEG23 SEG23 P77 – √ √
PFSEG24 SEG24 P30 √ √ √
PFSEG25 SEG25 P31 √ √ √
PFSEG26 SEG26 P32 – √ √
PFSEG27 SEG27 P33 – √ √
PFSEG28 SEG28 P34 – – √
PFSEG29 SEG29 P35 – – √
PFSEG30 SEG30 P36 – – √
PFSEG31 SEG31 P37 – – √
PFSEG32 SEG32 80-pin products: P02 – √ √
100-pin products: P50
PFSEG38 SEG38 P56 – – √
PFSEG39 SEG39 P57 – – √
PFSEG40 SEG40 P84 – – √
PFSEG41 SEG41 P85 – – √
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4.3.10 LCD input switch control register (ISCLCD)

This register sets whether to use pins P125 to P127 as port pins (other than LCD function pins) or LCD function pins
(VL3, CAPL, CAPH).
The ISCLCD register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 4-10. Format of LCD input switch control register (ISCLCD)

Symbol 7 6 5 4 3 2 1 0
ISCLCD 0 0 0 0 0 0 ISCVL3 ISCCAP
ISCVL3 Control of schmitt trigger buffer of VL3/P125 pin
0 Makes digital input invalid (used as LCD function pin (VL3))

1 Makes digital input valid
ISCCAP Control of schmitt trigger buffer of CAPL/ P126 and CAPH/P127 pins
0 Makes digital input invalid (used as LCD function pins (CAPL,CAPH))

1 Makes digital input valid
Caution If ISCVL3 bit = 0 and ISCCAP bit = 0, set the corresponding port control registers as follows:
PU127 bit of PU12 register = 0, P127 bit of P12 register = 0
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change. Therefore, byte data can be written to the ports used for both input and output.
4.4.2 Reading from I/O port
(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
(2) Input mode

The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change. Therefore, byte data can be written to the
ports used for both input and output.
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4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V)

When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), it is possible to connect the
I/O pins of general ports by changing EVDD to accord with the power supply of the connected device.
4.4.5 Handling different potential (1.8 V, 2.5 V, 3 V) by using I/O buffers

It is possible to connect an external device operating on a different potential (1.8 V, 2.5 V or 3 V) by switching I/O
buffers with port input mode registers 0, 1, 3, 5, and 8 (PIM0, PIM1, PIM3, PIM5, and PIM8) and port output mode
registers 0, 1, 3, 5, and 8 (POM0, POM1, POM3, POM5, and POM8).
When receiving input from an external device with a different potential (1.8 V, 2.5 V or 3 V), set port input mode
registers 0, 1, 3, 5, and 8 (PIM0, PIM1, PIM3, PIM5, and PIM8) on a bit-by-bit basis to enable normal input (CMOS)/TTL
input buffer switching.
When outputting data to an external device with a different potential (1.8 V, 2.5 V or 3 V), set port output mode registers
0, 1, 3, 5, and 8 (POM0, POM1, POM3, POM5, and POM8) on a bit-by-bit basis to enable normal output (CMOS)/N-ch
open drain (VDD toleranceNote 1/EVDD toleranceNote 2) switching.
The connection of a serial interface is described in the following.

(1) Setting procedure when using input pins of UART0 to UART3, CSI00, CSI10, and CSI30 functions for the TTL
input buffer
In case of UART0: P06 (P16)

In case of UART2: P55
In case of CSI00: P05, P06 (P15, P16)
In case of CSI30: P57, P84
Remark Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR0).
<1> Using an external resistor, pull up externally the pin to be used to the power supply of the target device (on-
chip pull-up resistor cannot be used).
<2> Set the corresponding bit of the PIM0, PIM1, PIM3, PIM5, and PIM8 registers to 1 to switch to the TTL input
buffer. For VIH and VIL, refer to the DC characteristics when the TTL input buffer is selected.
<3> Enable the operation of the serial array unit and set the mode to the UART/CSI mode.
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(2) Setting procedure when using output pins of UART0 to UART3, CSI00, CSI10, and CSI30 functions in N-ch
open-drain output mode

<2> After reset release, the port mode changes to the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM0, POM1, POM3, POM5, and POM8 registers to 1 to set the N-ch open
drain output (VDD toleranceNote 1/EVDD toleranceNote 2) mode.
<5> Enable the operation of the serial array unit and set the mode to the UART/CSI mode.
<6> Set the output mode by manipulating the PM0, PM1, PM3, PM5, and PM8 registers.
At this time, the output data is high level, so the pin is in the Hi-Z state.

(3) Setting procedure when using I/O pins of IIC00, IIC10, and IIC30 functions with a different potential (1.8 V, 2.5
V, 3 V)

<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM0, POM1, POM5,and POM8 registers to 1 to set the N-ch open drain
output (VDD toleranceNote 1/EVDD toleranceNote 2) mode.
<5> Set the corresponding bit of the PIM0, PIM1, PIM5, and PIM8 registers to 1 to switch the TTL input buffer.
For VIH and VIL, refer to the DC characteristics when the TTL input buffer is selected.
<6> Enable the operation of the serial array unit and set the mode to the simplified I2C mode.
<7> Set the corresponding bit of the PM0, PM1, PM5, and PM8 registers to the output mode (data I/O is possible
in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.

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4.5 Register Settings When Using Alternate Function
4.5.1 Basic concept when using alternate function

In the beginning, for a pin also assigned to be used for analog input, use the ADPC register to specify whether to use
the pin for analog input or digital input/output.
Figure 4-11 shows the basic configuration of an output circuit for pins used for digital input/output. The output of the
output latch for the port and the output of the alternate SAU function are input to an AND gate. The output of the AND
gate is input to an OR gate. The output of an alternate function other than SAU (TAU, RTC2, clock/buzzer output, IICA,
etc.) is connected to the other input pin of the OR gate. When such kind of pins are used by the port function or an
alternate function, the unused alternate function must not hinder the output of the function to be used. An idea of basic
settings for this kind of case is shown in Table 4-5.
Figure 4-11. Basic Configuration of Output Circuit for Pins
WRPORT
EVDD0/EVDD1/VDD
Output latch
(Pmn)
P-ch
WRPM Pmn/
Alternate function
PM register N-ch
Internal bus
(PMmn)
WRPOM
VSS
POM register Note 1
(POMmn)
To input circuit
Alternate Note 2
function (SAU)
Alternate function Note 3

(other than SAU)
Notes 1. When there is no POM register, this signal should be considered to be low level (0).
2. When there is no alternate function, this signal should be considered to be high level (1).
3. When there is no alternate function, this signal should be considered to be low level (0).
Remark m: Port number (m = 0 to 8, 12, 13, 15); n: Bit number (n = 0 to 7)
Table 4-5. Concept of Basic Settings
Output Function of Used Pin Output Settings of Unused Alternate Function
Port Function Output Function for SAU Output Function for other than SAU
Output function for port – Output is high (1) Output is low (0)
Output function for SAU High (1) – Output is low (0)

Output function for other than SAU Low (0) Output is high (1) Output is low (0)Note
Note Since more than one output function other than SAU may be assigned to a single pin, the output of an unused
alternate function must be set to low level (0). For details on the setting method, see 4.5.2 Register settings
for alternate function whose output function is not used.
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4.5.2 Register settings for alternate function whose output function is not used
When the output of an alternate function of the pin is not used, the following settings should be made. Note that when
the peripheral I/O redirection function is the target, the output can be switched to another pin by setting the peripheral I/O
redirection register (PIOR0). This allows usage of the port function or other alternate function assigned to the target pin.
(1) SOp = 1, TxDq = 1 (settings when the serial output (SOp/TxDq) of SAU is not used)
When the serial output (SOp/TxDq) is not used, such as, a case in which only the serial input of SAU is used, set the
bit in serial output enable register m (SOEm) which corresponds to the unused output to 0 (output disabled) and set
the SOmn bit in serial output register m (SOm) to 1 (high). These are the same settings as the initial state.
(2) SCKp = 1, SDAr = 1, SCLr = 1 (settings when channel n in SAU is not used)
When SAU is not used, set bit n (SEmn) in serial channel enable status register m (SEm) to 0 (operation stopped
state), set the bit in serial output enable register m (SOEm) which corresponds to the unused output to 0 (output
disabled), and set the SOmn and CKOmn bits in serial output register m (SOm) to 1 (high). These are the same
settings as the initial state.
(3) TOmn = 0 (settings when the output of channel n in TAU is not used)
When the TOmn output of TAU is not used, set the bit in timer output enable register 0 (TOE0) which corresponds to
the unused output to 0 (output disabled) and set the bit in timer output register 0 (TO0) to 0 (low). These are the
same settings as the initial state.
(4) SDAAn = 0, SCLAn = 0 (setting when IICA is not used)

When IICA is not used, set the IICEn bit in IICA control register n0 (IICCTLn0) to 0 (operation stopped). This is the
same setting as the initial state.
(5) PCLBUZn = 0 (setting when clock/buzzer output is not used)

When the clock/buzzer output is not used, set the PCLOEn bit in clock output select register n (CKSn) to 0 (output
disabled). This is the same setting as the initial state.
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4.5.3 Register setting examples for used port and alternate functions
Register setting examples for used port and alternate functions are shown in Table 4-6. The registers used to control
the port functions should be set as shown in Table 4-6. See the following remark for legends used in Table 4-6.
Remark –: Not supported

×: don’t care
PIOR0x: Peripheral I/O redirection register
POMxx: Port output mode register
PMxx: Port mode register
Pxx: Port output latch
PUxx: Pull-up resistor option register
PIMcc: Port input mode register
PFSEG××: LCD port function register
ISCLCD: LCD input switch control register
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Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (1/10)
Pin Used Function PIOR0× POM×× PM×× P×× PFSEG×× Alternate Function Output 64-pin 80-pin 100-
Name Function I/O (ISCVL3, SAU Output Other than pin
Name ISCCAP)Note Function SAU
P02 P02 Input – × 1 × 0 – –
Output × 0 0 0/1 0
N-ch open × 1 0 0/1 0 SCL10 = 1 TO07 = 0 – √ √

drain output
SCL10 Output PIOR02 = 0 0/1 0 1 0 – TO07 = 0
SCK10 Input PIOR02 = 0 × 1 × 0 – –
Output PIOR02 = 0 0/1 0 1 0 – TO07 = 0
TI07 Input PIOR00 = 0 × 1 × 0 – – – √ √
TO07 Output PIOR00 = 0 0 0 0 0 SCL10 = 1 –
INTP5 Input PIOR04 = 0 × 1 × 0 – –
SEG32 Output × 0 0 0 1 – – – √ –
P03 P03 Input – × 1 × 0 – –
Output × 0 0 0/1 0
N-ch open × 1 0 0/1 0 SDA10 = 1 TO06 = 0

drain output
RxD1 Input PIOR02 = 0 × 1 × 0 – – – √ √
TI06 Input PIOR00 = 0 × 1 × 0 – –
TO06 Output PIOR00 = 0 0 0 0 0 SDA10 = 1 –
SDA10 I/O PIOR02 = 0 1 0 1 0 – TO06 = 0
SI10 Input PIOR02 = 0 × 1 × 0 – –
SEG33 Output × 0 0 0 1 – – – √ –
P04 P04 Input – × 1 × 0 – –
Output × 0 0 0/1 0
N-ch open × 1 0 0/1 0 TxD1/SO10 = 1 TO05 = 0

drain output
TxD1 Output PIOR02 = 0 0/1 0 1 0 – TO05 = 0 – √ √
TI05 Input PIOR00 = 0 × 1 × 0 – –
TO05 Output PIOR00 = 0 0 0 0 0 TxD1/SO10 = 1 –
INTP4 Input PIOR04 = 0 × 1 × 0 – –
SO10 Output PIOR02 = 0 0/1 0 1 0 – TO05 = 0
SEG34 Output × 0 0 0 1 – – – √ –
P05 P05 Input – × 1 × 0 – –
Output × 0 0 0/1 0
SCK00/SCL00
N-ch open × 1 0 0/1 0 TO04 = 0
=1
drain output
SCK00 Input × 1 × 0 – –
PIOR01 = 0
Output 0/1 0 1 0 – TO04 = 0 √ √ √
SCL00 Output PIOR01 = 0 0/1 0 1 0 – TO04 = 0
TI04 Input PIOR00 = 0 × 1 × 0 – –
TO04 Output PIOR00 = 0 0 0 0 0 SCK00/SCL00
–
=1
INTP3 Input PIOR04 = 0 × 1 × 0 – –
SEG35 Output × 0 0 0 1 – – – √ –
P06 P06 Input – × 1 × 0 – –
Output × 0 0 0/1 0 SDA00 = 1 TO03 = 0
N-ch open × 1 0 0/1 0
drain output
SI00 Input PIOR01 = 0 × 1 × 0 – –
PIOR01 = 0 × 1 × 0 √ √ √
RxD0 Input – –
TI03 Input PIOR00 = 0 × 1 × 0 – –
TO03 Output PIOR00 = 0 0 0 0 0 SDA00 = 1 –
SDA00 I/O PIOR01 = 0 1 0 1 0 – TO03 = 0
TOOLRxD Input × × 1 × 0 – –
SEG36 Output × 0 0 0 1 – – – √ –
INTP4 Input PIOR04 = 0 × 1 × 0 – – √ – –
Note ISCVL3 and ISCCAP are registers that correspond to P125, and P126 and P127, respectively.
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P07 P07 Input – × 1 × 0 – –
Output × 0 0 0/1 0
SO00/TxD0 =
N-ch open drain TO02 = 0
× 1 0 0/1 0 1
output
SO00 Output PIOR01 = 0 0/1 0 1 0 – TO02 = 0
TxD0 Output PIOR01 = 0 0/1 0 1 0 – TO02 = 0 √ √ √
TI02 Input PIOR00 = 0 × 1 × 0 – –
TO02 Output SO00/TxD0 =
PIOR00 = 0 0 0 0 0 –
1
INTP2 Input PIOR04 = 0 × 1 × 0 – –
TOOLTxD Output × 0/1 0 1 0 – –
SEG37 Output × 0 0 0 1 – – – √ –
P10 P10 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – √ √ √
SEG4 Output – – 0 0 1 – –
P11 P11 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – √ √ √
SEG5 Output – – 0 0 1 – –
P12 P12 Input SCK10/SCL10
– – 1 × 0 –
=1 √ √ √
Output × – 0 0/1 0
SCK10/SCL10 –
N-ch open drain
× 1 0 0/1 0 =1
√ – –
–
output
SEG6 Output × – 0 0 1 – – √ √ √
SCK10 Input PIOR02 = 0 × 1 × 0 – –
√ – –
Output PIOR02 = 0 0/1 0 1 0 – –
SCL10 Output PIOR02 = 0 0/1 0 1 0 – – √ – –
P13 P13 Input – – 1 × 0 – –
√ √ √
Output × – 0 0/1 0 –
N-ch open drain SDA10 = 1
× 1 0 0/1 0 – √ – –
output
SEG7 Output × – 0 0 1 – – √ √ √
INTP6 Input PIOR04 = 0 – 1 × 0 – –
SI10 Input PIOR02 = 0 × 1 × 0 – –
√ – –
RXD1 Input PIOR02 = 0 × 1 × 0 – –
SDA10 I/O PIOR02 = 0 1 0 1 0 – –
P14 P14 Input – – 1 × 0 – –
√ √ √
Output × – 0 0/1 0
SO10/TxD1 =
N-ch open drain –
× 1 0 0/1 0 1 √ – –
output
SEG8 Output × – 0 0 1 – – √ √ √
SO10 Output PIOR02 = 0 0/1 0 1 0 – –
√ – –
TxD1 Output PIOR02 = 0 0/1 0 1 0 – –
P15 P15 Input – × 1 × 0 – –
Output × 0 0 0/1 0
(SCK00/SCL00
N-ch open drain –
× 1 0 0/1 0 )=1
output
× 0 0 0 1
√ √ √
SEG9 Output – –
(SCK00) Input PIOR01 = 1 × 1 × 0 – –
Output PIOR01 = 1 0/1 0 1 0 – –
(SCL00) Output PIOR01 = 1 0/1 0 1 0 – –
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P16 P16 Input – × 1 × 0 – –
Output × 0 0 0/1 0
N-ch open (SDA00) = 1 –

× 1 0 0/1 0
drain output
SEG10 Output × 0 0 0 1 √ √ √
– –
(SI00) Input PIOR01 = 1 × 1 × 0 – –
(RxD0) Input PIOR01 = 1 × 1 × 0 – –
(SDA00) I/O PIOR01 = 1 1 0 0 0 – –
INTP7 Input PIOR04 = 0 – 1 × 0 – – √ – –
P17 P17 Input – × 1 × 0 – –
Output × 0 0 0/1 0
(SO00/TxD0) =
N-ch open –
× 1 0 0/1 0 1
drain output √ √ √
SEG11 Output × 0 0 0 1 – –
(SO00) Output PIOR01 = 1 0/1 0 1 0 – –
(TxD0) Output PIOR01 = 1 0/1 0 1 0 – –
Pin Used Function ADPC ADM2 PM×× P×× 64-pin 80-pin 100-pin
Name Function I/O
Name
P20 P20 Input 01H × 1 ×
Output 01H × 0 0/1
ANI0 Analog input 00x0xx0xB
00H/02H to 06H 1 × √ √ √
10x0xx0xB
AVREFP Reference
00H/02H to 06H 01x0xx0xB 1 ×
voltage input
P21 P21 Input 01H/02H × 1 ×
Output 01H/02H × 0 0/1
ANI1 Analog input 00H/03H to 06H xx00xx0xB 1 × √ √ √
AVREFM Reference
00H/03H to 06H xx10xx0xB 1 ×
voltage input
P22 P22 Input 01H to 03H × 1 ×
Output 01H to 03H × 0 0/1
√ √ √
ANI2 Analog input 00H/04H to 06H × 1 ×
EXLVD Analog input 00H/04H to 06H × 1 ×
P23 P23 Input 01H to 04H × 1 ×
Output 01H to 04H × 0 0/1 √ √ √
ANI3 Analog input 00H/05H/06H × 1 ×
P24 P24 Input 01H to 05H × 1 ×
Output 01H to 05H × 0 0/1 – – √
ANI4 Analog input 00H/06H × 1 ×
P25 P25 Input 01H to 06H × 1 ×
Output 01H to 06H × 0 0/1 – – √
ANI5 Analog input 00H × 1 ×
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P30 P30 Input – – 1 × 0 – –
Output × – 0 0/1 0 – (TO07) = 0 √ √ √
SEG24 Output × – 0 0 1 – –
(TI07) Input PIOR00 = 1 – 1 × 0 – – – √ √
TI07 Input PIOR00 = 0 – 1 × 0 – – √ – –
(TO07) Output PIOR00 = 1 – 0 0 0 – – – √ √
TO07 Output PIOR00 = 0 – 0 0 0 – – √ – –
RxD2 Input × – 1 × 0 – –
IrRxD Input × – 1 × 0 – – √ – –
INTP5 Input PIOR04 = 0 – 1 × 0 – –
P31 P31 Input – – 1 × 0 – –
× 0 0/1 0
√ √ √
Output – (TO06) = 0
N-ch open × 1 0 0/1 0 TxD2/IrTxD = 1
– √ – –
drain output
SEG25 Output × – 0 0 1 – – √ √ √
(TI06) Input PIOR00 = 1 – 1 × 0 – – – √ √
TI06 Input PIOR00 = 0 – 1 × 0 – – √ – –
(TO06) Output PIOR00 = 1 – 0 0 0 – – – √ √
TO06 Output PIOR00 = 0 – 0 0 0 – – √ – –
TxD2 Output × 0/1 0 1 0 – –
× 0/1 0 1 0
√ – –
IrTxD Output – –
P32 P32 Input – – 1 × 0 – –
Output × 0 0/1 0 (PCLBUZ1) =
– –
0 – √ √
SEG26 Output × – 0 0 1 – –
(PCLBUZ1) Output PIOR03 = 1 – 0 0 0 – –
P33 P33 Input – – 1 × 0 – –
Output × 0 0/1 0 (PCLBUZ0) =
– –
0 – √ √
SEG27 Output × – 0 0 1 – –
(PCLBUZ0) Output PIOR03 = 1 – 0 0 0 – –
P34 P34 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG28 Output – – 0 0 1 – –
P35 P35 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG29 Output – – 0 0 1 – –
P36 P36 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG30 Output – – 0 0 1 – –
P37 P37 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG31 Output – – 0 0 1 – –
P40 P40 Input – – 1 × – – –
Output – – 0 0/1 – – – √ √ √
TOOL0 I/O – – × × – – –
P41 P41 Input – – 1 × – – –
Output × 0 0/1 TO01 = 0 – √ √
– – –
PCLBUZ1 = 0
TI01 Input PIOR00 = 0 – 1 × – – –
PIOR00 = 0 0 0
√ √ √
TO01 Output – – – PCLBUZ1 = 0
PCLBUZ1 Output PIOR03 = 0 – 0 0 – – TO01 = 0
PIOR04 = 0 1 × – √ √
INTP6 Input – – – –
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P42 P42 Input – – 1 × – – –
– √ √
Output × – 0 0/1 – – –
INTP7 Input PIOR04 = 0 1 × – – – – – √
P43 P43 Input – – 1 × – – –
TO00 = 0 √ √ √
Output × – 0 0/1 – –
PCLBUZ0 = 0
TI00 Input PIOR00 = 0 – 1 × – – –
√ – √
TO00 Output PIOR00 = 0 – 0 0 – – PCLBUZ0 = 0
PCLBUZ0 Output PIOR03 = 0 – 0 0 – – TO00 = 0 √ – √
RTCOUT Output PIOR03 = 0 – 0 0 – – – √ – –
P50 P50 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG32 Output – – 0 0 1 – –
P51 P51 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG33 Output – – 0 0 1 – –
P52 P52 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG34 Output – – 0 0 1 – –
P53 P53 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG35 Output – – 0 0 1 – –
P54 P54 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – – √
SEG36 Output – – 0 0 1 – –
P55 P55 Input – – 1 × 0 – –
– √ √
Output – – 0 0/1 0 – –
RxD2 Input – – 1 × 0 – –
– √ √
IrRxD Input – – 1 × 0 – –
SEG37 Output – – 0 0 1 – – – – √
P56 P56 Input – – 1 × 0 – –
Output – – 0 0/1 0
– √ √
N-ch open drain TxD2/IrTxD = 1 –
– 1 0 0/1 0
output
TxD2 Output – 0/1 0 1 0 – –
– √ √
IrTxD Output – 0/1 0 1 0 – –
SEG38 Output – – 0 0 1 – – – – √
P57 P57 Input – – 1 × 0 – –
Output – – 0 0/1 0
SCK30/SCL30 – – √
N-ch open drain –
– 1 0 0/1 0 =1
output
SCK30 Input – × 1 × 0 – –
Output – 0/1 0 1 0 – –
– – √
SCL30 Output – 0/1 0 1 0 – –
SEG39 Output – – 0 0 1 – –
P60 P60 Input – – 1 × – – –
N-ch open drain
SCLA0 = 0
output × – 0 0/1 – –
(TO00) = 0
(6 V tolerance) √ √ √
SCLA0 I/O × – 0 0 – – (TO00) = 0
(TI00) Input PIOR00 = 1 – 1 × – – –
(TO00) Output PIOR00 = 1 – 0 0 – – SCLA0 = 0
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Name Function I/O (ISCVL3, SAU Output Other than SAU pin
Name ISCCAP)Note Function
P61 P61 Input – – 1 × – – –
N-ch open drain
SDAA0 = 0
output × – 0 0/1 – –
(TO01) = 0
SDAA0 I/O × – 0 0 – – (TO01) = 0
(TI01) Input PIOR00 = 1 – 1 × – – –
(TO01) Output PIOR00 = 1 – 0 0 – – SDAA0 = 0
P62 P62 Input – – 1 × – – –
N-ch open drain
(TO02) = 0
output × – 0 0/1 – –
(RTCOUT) = 0
(TI02) Input PIOR00 = 1 – 1 × – – –
(TO02) Output PIOR00 = 1 – 0 0 – – (RTCOUT) = 0
(RTCOUT) Output PIOR03 = 1 – 0 0 – – (TO02) = 0
P70 P70 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
SEG16 Output × – 0 0 1 – – √ √ √
KR0 Input × – 1 × 0 – –
(INTP0) Input PIOR04 = 1 – 1 × 0 – –
P71 P71 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
SEG17 Output × – 0 0 1 – – √ √ √
KR1 Input × – 1 × 0 – –
(INTP1) Input PIOR04 = 1 – 1 × 0 – –
P72 P72 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
KR2 Input × – 1 × 0 – – √ √ √
SEG18 Output × – 0 0 1 – –
(INTP2) Input PIOR04 = 1 – 1 × 0 – –
(TI01) Input PIOR00 = 1 – 1 × 0 – –
√ – –
(TO01) Output PIOR00 = 1 – 0 0 0 – –
P73 P73 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
KR3 Input × – 1 × 0 – – √ √ √
SEG19 Output × – 0 0 1 – –
(INTP3) Input PIOR04 = 1 – 1 × 0 – –
(PCLBUZ1) Output PIOR03 = 1 – 1 0 0 – – √ – –
P74 P74 Input – – 1 × 0 – –
Output × – 0 0/1 0 – (PCLBUZ0) = 0
KR4 Input × – 1 × 0 – – √ √ √
SEG20 Output × – 0 0 1 – –
(INTP4) Input PIOR04 = 1 – 1 × 0 – –
(PCLBUZ0) Output PIOR03 = 1 – 0 0 0 – – √ – –
P75 P75 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
KR5 Input × – 1 × 0 – – – √ √
SEG21 Output × – 0 0 1 – –
(INTP5) Input PIOR04 = 1 – 1 × 0 – –
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P76 P76 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
KR6 Input × – 1 × 0 – – – √ √
SEG22 Output × – 0 0 1 – –
(INTP6) Input PIOR04 = 1 – 1 × 0 – –
P77 P77 Input – – 1 × 0 – –
Output × – 0 0/1 0 – –
KR7 Input × – 1 × 0 – – – √ √
SEG23 Output × – 0 0 1 – –
(INTP7) Input PIOR04 = 1 – 1 × 0 – –
P80 P80 Input – × 1 × 0 – –
Output × 0 0 0/1 0
(SCK10/SCL10
N-ch open drain × 1 0 0/1 0 –
)=1
output
SEG12 Output × × 0 0 1 – √ √
– –
(SCL10) Output PIOR02 = 1 0/1 0 1 0 – –
(SCK10) Input PIOR02 = 1 × 1 × 0 – –
Output PIOR02 = 1 0/1 0 1 0 – –
P81 P81 Input – × 1 × 0 – –
Output × 0 0 0/1 0
–
N-ch open drain (SDA10) = 1
× 1 0 0/1 0
output –
SEG13 Output × × 0 0 1 – √ √
– –
(RxD1) Input PIOR02 = 1 × 1 × 0 – –
(SDA10) I/O PIOR02 = 1 1 0 1 0 – –
(SI10) Input PIOR02 = 1 × 1 × 0 – –
P82 P82 Input – × 1 × 0 – –
Output × 0 0 0/1 0
(TxD1/SO10) = –
N-ch open drain × 1 0 0/1 0 1
output –
– √ √
SEG14 Output × × 0 0 1 – –
(TxD1) Output PIOR02 = 1 0/1 0 1 0 – –
(SO10) Output PIOR02 = 1 0/1 0 1 0 – –
P83 P83 Input – – 1 × 0 – –
Output – – 0 0/1 0 – – – √ √
SEG15 Output – – 0 0 1 – –
P84 P84 Input – – 1 × 0 – –
Output – – 0 0/1 0
N-ch open drain SDA30 = 1 –
– 1 0 0/1 0
output
SEG40 Output 0 0 1 – – √
– – – –
SI30 Input – × 1 × 0 – –
RxD3 Input – × 1 × 0 – –
SDA30 I/O – 1 0 1 0 – –
P85 P85 Input – – 1 × 0 – –
Output – – 0 0/1 0 –
N-ch open drain SO30/TxD3 = 1
– 1 0 0/1 0 –
output – – √
SEG41 Output – – 0 0 1 – –
SO30 Output – 0/1 0 1 0 – –
TxD3 Output – 0/1 0 1 0 – –
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Pin Used Function CMC Register SCMC Register P×× 64-pin 80-pin 100-pin
Name Function I/O (EXCLK, OSCSEL) (EXCLKS, OSCSELS)
Name
P121 P121 Input 00/10/11 ×
√ √ √
X1 – 01 –
P122 P122 Input 00/10 – ×
X2 – 01 – √ √ √
EXCLK Input 11 –
P123 P123 Input 00/10/11 ×
√ √ √
XT1 – 01 –
P124 P124 Input – 00/10 ×
XT2 – 01 – √ √ √
EXCLKS Input 11 –
P125 P125 Input – – 1 × 1 – –
Output × 0 0/1 1 (TO05) = 0
– –
PCLBUZ1 = 0 √ √ √
VL3 – × – 1 × 0 – –
INTP1 Input PIOR04 = 0 – 1 × 1 – –
(TI05) Input PIOR00 = 1 – 1 × 1 – – – √ √
TI05 Input PIOR00 = 0 – 1 × 1 – – √ – –
(TO05) Output PIOR00 = 1 – 0 0 1 – PCLBUZ1 = 0 – √ √
TO05 Output PIOR00 = 0 – 0 0 1 – PCLBUZ1 = 0
√ – –
PCLBUZ1 Output PIOR03 = 0 – 0 0 1 – TO05 = 0
P126 P126 Input – – 1 × 1 – –
Output × – 0 0/1 1 – (TO04) = 0
CAPL – × – 1 × 0 – – √ √ √
(TI04) Input PIOR00 = 1 – 1 × 1 – –
(TO04) Output PIOR00 = 1 – 0 0 1 – –
P127 P127 Input – – 1 × 1 – –
Output × – 0 0/1 1 – (TO03) = 0
CAPH – × – 1 × 0 – – √ √ √
(TI03) Input PIOR00 = 1 – 1 × 1 – –
(TO03) Output PIOR00 = 1 – 0 0 1 – –
P137 P137 Input – – – × – – –
√ √ √
INTP0 Input PIOR04 = 0 – – × – – –
P150 P150 Input – × 1 × – – –
Output × – 0 0/1 – – –
– √ √
RTCOUT Output PIOR03 = 0 – 0 0 – – –
RTCIC0 Input × – 1 × – – –
P151 P151 Input – × 1 × – – –
Output – – 0 0/1 – – – – √ √
RTCIC1 Input – – 1 × – – –
P152 P152 Input – – 1 × – – –
Output – – 0 0/1 – – – – √ √
RTCIC2 Input – – 1 × – – –
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4.5.4 Operation of ports that alternately function as SEGxx pins

The functions of ports that also serve as segment output pins (SEGxx) can be selected by using the port mode register
(PMxx), and LCD port function registers 0 to 5 (PFSEG0 to PFSEG5).
Table 4-7. Settings of SEGxx/Port Pin Function
PFSEGxx Bit of PMxx Bit of Pin Function Initial Status

PFSEG0 to PFSEG5 Registers PMxx Register
1 1 Digital input invalid mode √
0 0 Digital output mode –
0 1 Digital input mode –
1 0 Segment output mode –
The following shows the SEGxx/port pin function status transitions.
Figure 4-12. SEGxx/Port Pin Function Status Transition Diagram
Reset status
Reset release
Digital input PMmn = 0 Segment

invalid mode output mode
PFSEGxx = 0
Digital input PMmn = 0 Digital output

mode mode
PMmn = 1
Caution Be sure to set the segment output mode before segment output starts (while SCOC of LCD mode
register 1 (LCDM1) is 0).
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4.5.5 Operation of ports that alternately function as VL3, CAPL, CAPH pins
The functions of the VL3/P125, CAPL/P126, CAPH/P127 pins can be selected by using the LCD input switch control
register (ISCLCD), LCD mode register 0 (LCDM0), and port mode register 12 (PM12).
(1) VL3/P125
Table 4-8. Settings of VL3/P125 Pin Function
Bias Setting ISCVL3 Bit of PM125 Bit of Pin Function Initial Status
(LBAS1 and LBAS0 Bits of ISCLCD Register PM12 Register
LCDM0 Register)
other than 1/4 bias method 0 1 Digital input invalid mode √

(LBAS1, LBAS0 = 00 or 01) 1 0 Digital output mode –
1/4 bias method 0 1 VL3 function mode –

(LBAS1, LBAS0 = 10)
The following shows the VL3/P125 pin function status transitions.
Figure 4-13. VL3/P125 Pin Function Status Transition Diagram
Reset status
Reset release
LBAS1, LBAS0 = 10 Digital input

invalid mode
ISCVL3 = 1
VL3 Digital input PMmn = 0 Digital output

function mode mode mode
PMmn = 1
Caution Be sure to set the VL3 function mode before segment output starts (while SCOC of LCD mode
register 1 (LCDM1) is 0).
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(2) CAPL/P126, CAPH/P127
Table 4-9. Settings of CAPL/P126, CAPH/P127 Pins Function
LCD Drive Voltage Generator ISCCAP Bit of PM126, PM127 Bits Pin Function Initial Status
(MDSET1 and MDSET0 Bits ISCLCD Register of PM12 Register
of LCDM0 Register )
External resistance division 0 1 Digital input invalid mode √

(MDSET1, MDSET0 = 00) 1 0 Digital output mode –
Internal voltage boosting or 0 1 CAPL/CAPH function mode –

capacitor split
(MDSET1, MDSET0 = 01 or
10)
The following shows the CAPL/P126 and CAPH/P127 pins function status transitions.
Figure 4-14. CAPL/P126 and CAPH/P127 Pins Function Status Transition Diagram
Reset status
Reset release
MDSET1, 0 = 01 or 10
Digital input
invalid mode
MDSET1, 0 = 00
ISCCAP = 1
CAPL/CAPH Digital input PMmn = 0 Digital output

PMmn = 1
Caution Be sure to set the CAPL/CAPH function mode before segment output starts (while SCOC of LCD
mode register 1 (LCDM1) is 0).
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4.6 Cautions When Using Port Function
4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn)

When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the RL78/I1C.
<1> The Pn register is read in 8-bit units.

<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 4-15. Bit Manipulation Instruction (P10)
1-bit manipulation
P10 instruction P10
Low-level output (set1 P1.0) High-level output
is executed for P10
bit.
P11 to P17 P11 to P17
Pin status: High-level Pin status: High-level
Port 1 output latch Port 1 output latch
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.

· In the case of P10, an output port, the value of the port output latch (0) is read.
· In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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4.6.2 Notes on specifying the pin settings

If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the
unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the
functions assigned by using the peripheral I/O redirection register (PIOR0). For details about the alternate output function,
see 4.5 Register Settings When Using Alternate Function.
No specific setting is required for input pins because the output function of their alternate functions is disabled (the
buffer output is Hi-Z).
Disabling the unused functions, including blocks that are only used for input or do not have output, is recommended to
lower power consumption.
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RL78/I1C CHAPTER 5 OPERATION STATE CONTROL
CHAPTER 5 OPERATION STATE CONTROL
The operating voltage, operating timing, and operating current of the internal circuit are optimized using flash operation
modes. Select an appropriate flash operation mode according to the supply voltage range and clock frequencies used to
operate the MCU.
The flash operation mode set by the option byte is selected for operation immediately after a reset release. Then, each
mode is selected according to register settings.
5.1 Configuration of Operation State Control
Operation state control is supported by the following hardware.
Table 5-1. Configuration of Operation State Control
Item Configuration
Option byte ● User option byte address: 000C2H
Control registers ● Flash operating mode select register (FLMODE)

● Flash operating mode protect register (FLMWRP)
● Regulator mode control register (PMMC)
Figure 5-1. Block Diagram of Operation State Control
VDD 1.7 V to 5.5 V

FLMWRP register FLMODE register PMMC register
FLMWEN MODE1 MODE0 Regulator MCSEL
Enable/disable Control regulator
FLMODE setting output
Set flash
operation mode
Code flash memory CPU
Data flash memory RAM Peripheral function
Option byte (000C2H)

CMODE1 CMODE0
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There are the following four flash operation modes.

● HS (high-speed main) mode
● LS (low-speed main) mode
● LV (low-voltage main) mode
● LP (low-power main) mode
The MCU can be operated efficiently by setting these flash operation modes according to MCU operating
conditions. Table 5-2 lists the features of each flash operation mode.
Table 5-2. Features of Each Flash Operation Mode
Flash Operation Mode Regulator Mode Recommended Operating Range Operating Current (typ.) Description
HS (high-speed main) Normal setting only 2.8 V to 5.5 V 1 MHz to 32 MHz 3.9 mA High-speed CPU operation (at 32
mode (MCSEL = 0) Note 3
(during operation at 24 MHzNote 3 (max.)) is possible in this
Note 1
MHz ) mode.
2.7 V to 5.5 V 1 MHz to 24 MHz
Suitable when CPU processing capacity
is required.
LS (low-speed main) Normal setting 1.9 V to 5.5 V 1 MHz to 8 MHz 1.3 mA The operating current and CPU operation
mode (MCSEL = 0) (during operation at 8 processing (at 8 MHz (max.)) are well-
MHzNote 1) balanced in this mode. To operate the
Low-power 1.9 V to 5.5 V 1 MHz to 4 MHz 0.7 mA CPU at 4 to 8 MHz, set regulator mode to
consumption (during operation at 4 the normal setting. When operating the
setting MHz Note 2

) CPU at 1 to 4 MHz, the operating current
(MCSEL = 1) can be reduced by setting regulator

mode to the low-power consumption
setting.
LP (low-power main) Low-power 1.9 V to 5.5 V 1 MHz 160 µA The CPU operates at 1 MHz in this
mode consumption (during operation at 1 mode.
setting only MHzNote 2) Low operating current is realized at 1
(MCSEL = 1) MHz.
LV (low-voltage main) Normal setting only 1.7 V to 5.5 V 1 MHz to 4 MHz 1.3 mA Low-voltage operation up to 1.7 V is
modeNote 1 (MCSEL = 0) (during operation at 4 possible in this mode. To operate the
MHz) CPU at the supply voltage range of 1.7 to
1.9 V, select this mode.
Notes 1. Operable only with the high-speed on-chip oscillator.

2. When the middle-speed on-chip oscillator operates.
3. This operation is only possible in the R5F10NPJ, R5F10NMJ, or R5F10NPG products when the PLL clock
(32 MHz) is selected.
The maximum operating frequency of the R5F10NMG, R5F10NME, R5F10NLG, and R5F10NLE products
is 24 MHz.
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5.2 Registers Controlling Operation State Control
Operation state control is controlled by the following registers.

● Flash operating mode select register (FLMODE)
● Flash operating mode protect register (FLMWRP)
5.2.1 Flash operating mode select register (FLMODE)

The FLMODE register is an 8-bit register used to control flash operation modes and operation of the code flash memory.
This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that the value of this register cannot
be changed when FLMWEN in the flash operation mode protect register (FLWRP) is 0.
Reset generation updates MODE1 and MODE0 with the set value of CMODE1 and CMODE0 in the option byte
(address: 000C2H).
Figure 5-2. Format of Flash Operating Mode Select Register (FLMODE)
Address: F00AAH After reset: 00H/80H/C0HNote 1 R/W

Symbol <7> <6> 5 4 3 2 1 0
FLMODE MODE1 MODE0 0 0 0 0 0 0
MODE1 MODE0 Selection of flash operation mode
0 0 LV (low-voltage main) mode

(Selectable when 1 MHz ≤ fCLK ≤ 4 MHz in LS mode.)
0 1 LP (low-power main) mode
(Selectable when 1.9 V ≤ VDD ≤ 5.5 V and fCLK = 1 MHz in LS mode. Note 2)
1 0 LS (low-speed main) mode
(Selectable when 1.9 V ≤ VDD ≤ 5.5 V and 1 MHz ≤ fCLK ≤ 8 MHz in HS mode, LP mode, or
LV mode.)
1 1 HS (high-speed main) mode
Selectable when 2.4 V ≤ VDD ≤ 5.5 V in LS mode.)
Notes 1. The initial value of the FLMODE register is set to the value of the MODE1 and MODE0 bits updated with the
set value of the CMODE1 and CMODE0 bits in the option byte (address: 000C2H).
2. After LP (low-power main) mode is selected, set the MCSEL bit in the regulator mode control register
(PMMC) to 1.
(Cautions are on the next page.)
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Cautions 1. The value of the FLMODE register cannot be changed when the FLMWEN bit in the flash
operation mode protect register (FLMWRP) is 0. Also, do not change the value of the FLMODE
register when the MCSEL bit in the regulator mode control register is 1.
When changing the value of the FLMODE register, first set the FLMWEN bit in the FLMERP
register to 1 while MCSEL is 0. After the value of the FLMODE register is changed, set the
FLMWEN bit to 0.
2. The MODE1 and MODE0 bits cannot be set when the CSS bit in the system clock control register
(CKC) is 1 (CPU/peripheral function operates on subsystem clock).
3. Do not change the value of the MODE1 and MODE0 bits using the DTC.
4. When changing the flash operation mode, make sure that operation is possible within the voltage
range and operating frequency range in the changed flash operation mode before changing the
mode.
5. The middle-speed on-chip oscillator cannot be used in LV (low-voltage main) mode. When
entering LV mode, first switch the operating clock to an oscillator other than the middle-speed
on-chip oscillator, and then enter LV mode.
6. When the flash operation mode is changed by the MODE1 and MODE0 bits, the CPU enters a wait
state for the following time until the mode changes. Interrupt requests are held pending during
this wait period.
Table 5-3. Flash Operation Mode Change Time
Flash Operation Mode Change Change Time
LS (low-speed main) mode → HS (high-speed main) mode 225 cyclesNote 1

LS (low-speed main) mode → LV (low-voltage main) mode 99 cyclesNotes 1, 2
LP (low-power main) mode → LS (low-speed main) mode 10 cyclesNote 1
LS (low-speed main) mode → LP (low-power main) mode 10 cyclesNote 1
LV (low-voltage main) mode → LS (low-speed main) mode 20 cyclesNote 1
HS (high-speed main) mode → LS (low-speed main) mode 30 cyclesNote 1
Notes 1. The cycle of the CPU/peripheral hardware clock (fCLK)

2. Switching of the mode from LS (low-speed main) mode to LV (low-voltage main) mode must proceed while
oscillation of the high-speed on-chip oscillator is stable.
Cautions 7. When rewriting the FLMODE register, insert one or more clock cycles after rewriting the FLMODE
register and before writing to this register. Do not write to the FLMODE register successively.
8. Do not change the FLMODE register when rewriting the flash memory.
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5.2.2 Flash operating mode protect register (FLMWRP)

The FLMWRP register is an 8-bit register used to control access to the flash operation mode select register. This
register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset generation sets this register to 00H.
Figure 5-3. Format of Flash Operating Mode Protect Register (FLMWRP)
Address: F00ABH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>
FLMWRP 0 0 0 0 0 0 0 FLMWEN
FLMWEN Control of flash operation mode select register (FLMODE)
0 Rewriting the FLMODE register is disabled

1 Rewriting the FLMODE register is enabled
5.2.3 Regulator mode control register (PMMC)

The PMMC register is an 8-bit register used to control the mode of the on-chip regulator. This register can be set by a
1-bit or 8-bit memory manipulation instruction.
Figure 5-4. Format of Regulator Mode Control Register (PMMC)
Address: F00F8H After reset: 00H R/W

Symbol 7 <6> 5 4 3 2 1 0
PMMC 0 MCSEL 0 0 0 0 0 0
MCSEL Control of regulator mode
0 Normal setting
1 Low-power consumption setting
Cautions 1. Do not change the flash operation mode select register (FLMODE) when MCSEL is 1.
2. Do not set MCSEL to 1 in HS (high-speed main) mode and LV (low-voltage main) mode.
3. In LS (low-speed main) mode, transition to the STOP mode is prohibited when MCSEL is 1.
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5.3 Initial Setting of Flash Operation Modes
The option byte (000C2H) is used to set the initial state of flash operation mode and the high-speed on-chip oscillator
after a reset is released.
Set an appropriate flash operation mode according to the VDD voltage and the high-speed on-chip oscillator frequency
at a reset release.
When a reset is released, the value of CMODE1 and CMODE0 is updated in MODE1 and MODE0 in the flash
operation mode select register (FLMODE) and the value of FRQSEL2 to FRQSEL0 is updated in the high-speed on- chip
oscillator frequency select register (HOCODIV).
Figure 5-5. Format of User Option Byte (000C2H)
Address: 000C2H
Symbol 7 6 5 4 3 2 1 0
CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
CMODE1 CMODE0 Selection of flash operation mode after reset release
0 0 LV (low-voltage main) mode

1 0 LS (low-speed main) mode
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 High-speed on-chip oscillator frequency
0 0 0 0 24 MHz
1 0 0 1 16 MHz
0 0 0 1 12 MHz
1 0 1 0 8 MHz
0 0 1 0 6 MHz
1 0 1 1 4 MHz
0 0 1 1 3 MHz
1 1 0 0 2 MHz
0 1 0 0 1.5 MHz
1 1 0 1 1 MHz
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5.4 Transitions between Flash Operation Modes
HS (high-speed main) mode, LS (low-speed main) mode, or LV (low-voltage main) mode can be selected as the flash
operation mode immediately after a reset release, by setting CMODE1 and CMODE0 in the option byte (000C2H). The
value of CMODE1 and CMODE0 is updated in the MODE1 and MODE0 bits in the flash operation mode select register
(FLMODE). After that, the flash operation mode can be changed by changing the value of the FLMODE register during
CPU operation.
Figure 5-6. State Transitions between Flash Operation Modes
HS (high-speed main) mode

CMODE1 = 1, CMODE0 = 1 FLMODE register PMMC register
MODE1 = 1 MODE0 = 1 MCSEL = 0
Reset release
Operating conditions: VDD = 2.1 V to 5.5 V Note 1
Option byte (000C2H) Note 5 fCLK = 1 MHz to 24 MHz
(A) MODE0 = 0
Option byte (000C2H) CMODE1 = 1, CMODE0 = 0
CMODE1 = 0, CMODE0 = 0 Reference operating current: 3.9 mA (24 MHz Note 2)
LS (low-speed main) mode
FLMODE register PMMC register
MODE1 = 1 MODE0 = 0 MCSEL = 0/1
(B) MODE0 = 1
• MCSEL = 0 (normal setting)
Operating conditions: VDD = 1.9 V to 5.5 V
fCLK = 1 MHz to 8 MHz
Reference operating current: 1.3 mA (8 MHz Note 2)

• MCSEL = 1 (low-power consumption setting) Note 4
(C) MODE1 = 0 Note 6 Operating conditions: VDD = 1.9 V to 5.5 V
fCLK = 1 MHz to 4 MHz
Reference operating current: 0.7 mA (4 MHz Note 3)
(D) MODE1 = 1
LV (low-voltage main) mode (E) MODE1 = 0, (F) MODE1 = 1,
MODE0 = 1, MODE0 = 0,
MODE1 = 0 MODE0 = 0 MCSEL = 0 MCSEL = 1 MCSEL = 0
fCLK = 1 MHz to 4 MHz LP (low-power main) mode
Reference operating current: 1.3 mA (4 MHz Note 2) MODE1 = 0 MODE0 = 1 MCSEL = 1

fCLK = 1 MHz
Reference operating current: 160 µA (1 MHz Note 3)
Notes 1. The operating frequency and operating voltage range are as follows.
1 MHz ≤ fCLK ≤ 6 MHz (2.1 V ≤ VDD ≤ 5.5 V)
2. Current when the high-speed on-chip oscillator operates.
3. Current when the middle-speed on-chip oscillator operates.
4. Transitions between flash operation modes or transition to the STOP mode cannot be made when MCSEL
= 1 (low- power consumption setting). When changing the flash operation mode or making transition to the
STOP mode, be sure to set MCSEL = 0 (normal setting) before changing the mode.
5. When CMODE1 and CMODE0 of the option byte (000C2H) are set to 1, operation is not guaranteed if a
reset is generated while the operating voltage is 2.4 V or lower after entry to the LS (low-speed main) mode.
6. When CMODE1 and CMODE0 of the option byte (000C2H) are set to 1 and 0 respectively, operation is not
guaranteed if a reset is generated while the operating voltage is 1.9 V or lower after entry to the LV (low-
voltage main) mode.
Cautions 1. When a reset is applied while the MCU operates, operation always starts in the flash operation
mode set by the option byte after a reset release. Therefore, make sure that operation does not
start outside the operating voltage range when a reset is released by setting the LVD detection
voltage to at least the operating voltage range of the flash operation mode set in the option byte.
2. Selecting the LV (low-voltage main) mode while the battery backup function is operating
(VBATEN = 1) is prohibited.
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5.5 Details of Flash Operation Modes
5.5.1 Details of HS (high-speed main) mode

HS (high-speed main) mode is suitable for applications that require CPU high-speed processing.
HS mode can be operated immediately after a reset release. Also, this mode can be entered from LS (low-speed main)
mode. When entering HS mode, make sure that the supply voltage is 2.4 V ≤ VDD ≤ 5.5 V in LS mode.
Operating in HS mode is suitable when the power supply voltage and operating frequency meet any of the following
conditions.
● 2.4 V ≤ VDD ≤ 5.5 V and the operating frequency is 8 MHz < fCLK ≤ 12 MHz
When 8 MHz or lower is used for operation, another mode can be used as the suitable flash operation mode.
Figure 5-7. Operating Range in HS Mode
32 MHz
CPU/peripheral hardware clock (fCLK)
24 MHz
16 MHz
12 MHz
8 MHz
: Operating range when HS mode is suitable
6 MHz
: Operating range when another mode is suitable
1 MHz
1.7 V 1.9 V 2.1 V 2.4 V 2.5 V 2.7 V 2.8 V 5.5 V

Supply voltage (VDD)
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5.5.2 Details of LS (low-speed main) mode

LS (low-speed main) mode supports both CPU processing capacity and operating voltage performance, suitable for
applications that require low-power consumption at 1 to 8 MHz.
LS mode can be operated immediately after a reset release. Also, this mode can be entered from HS (high-speed
main) mode, LV (low-voltage main) mode, or LP (low-power main) mode. When entering from HS mode to LS mode,
make sure that the operating frequency is 1 MHz ≤ fCLK ≤ 8 MHz.
In LS mode, low-power consumption can be set by the MCSEL bit in the regulator mode control register (PMMC).
When setting low-power consumption, set the MCSEL bit to 1 while the operating frequency is 1 MHz ≤ fCLK ≤ 4 MHz.
The suitable operating range in LS mode is when the supply voltage is 1.9 V ≤ VDD ≤ 5.5 V and the operating frequency
is 4 MHz < fCLK ≤ 8 MHz if MCSEL = 0, and when the supply voltage is 1.9 V ≤ VDD ≤ 5.5 V and the operating frequency is
1 MHz < fCLK ≤ 4 MHz if MCSEL = 1.
Figure 5-8. Operating Range in LS Mode (MCSEL = 0)

24 MHz
16 MHz
8 MHz : Operating range when LS mode (MCSEL = 0) is suitable
4 MHz : Operating range when another mode is suitable
1 MHz
1.7 V 1.9 V 2.4 V 2.7 V 5.5 V
Figure 5-9. Operating Range in LS Mode (MCSEL = 1)

24 MHz
16 MHz
8 MHz
: Operating range when LS mode (MCSEL = 1) is suitable
1 MHz
1.7 V 1.9 V 2.4 V 2.7 V 5.5 V
Caution When entering another flash operation mode, make sure that MCSEL = 0.
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5.5.3 Details of LP (low-power main) mode

LP (low-power main) mode can be use to operate the CPU on low power at a 1-MHz frequency.
LP mode can be entered from LS (low-speed main) mode. When entering from LS mode to LP mode, make sure the
operating frequency is fCLK = 1 MHz. After the mode is entered, set the MCSEL bit in the regulator mode control register to
1.
The suitable operating range in LP mode is when the supply voltage is 1.9 V ≤ VDD ≤ 5.5 V and the operating frequency
is 1 MHz.
Figure 5-10. Operating Range in LP Mode

24 MHz
16 MHz
8 MHz
: Operating range when LP mode is suitable
1 MHz
0.5 MHz
1.7 V 1.9 V 2.4 V 2.7 V 5.5 V
Cautions 1. When entering LS (low-speed main) mode, make sure that MCSEL = 0.
2. The 24-bit ΔΣ A/D converter cannot be used in LP (low-power main) mode or LV (low-voltage
main) mode.
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5.5.4 Details on LV (low-voltage main) mode

LV (low-voltage main) mode is suitable for applications that require operation at 1.9 V or lower.
LV mode can be operated immediately after a reset release. Also, this mode can be entered from LS (low-speed main)
mode. When entering from LS mode to LV mode, make sure that the operating frequency is 1 MHz ≤ fCLK ≤ 4 MHz.
The suitable operating range in LV mode is when the supply voltage is 1.7 V ≤ VDD < 1.9 V. When a supply voltage of
1.9 V ≤ VDD ≤ 5.5 V is used for operation, another mode can be used as the suitable flash operation mode.
Figure 5-11. Operating Range in LV Mode

24 MHz
16 MHz
8 MHz
: Operating range when LV mode is suitable
1 MHz
0.5 MHz
1.7 V 1.9 V 2.4 V 2.7 V 5.5 V
Cautions 1. The middle-speed on-chip oscillator cannot be used in LV (low-voltage main) mode. When
entering LV mode, first switch the operating clock to an oscillator other than the middle-speed
on-chip oscillator, and then enter LV mode.
2. Selecting the LV (low-voltage main) mode while the battery backup function is operating
(VBATEN = 1) is prohibited.
3. The 24-bit ΔΣ A/D converter cannot be used in LP (low-power main) mode or LV (low-voltage
main) mode.
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RL78/I1C CHAPTER 6 CLOCK GENERATOR
CHAPTER 6 CLOCK GENERATOR
6.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following six kinds of system clocks and clock oscillators are selectable.
(1) Main system clock

<1> X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHzNote by connecting a resonator to X1 pin and X2 pin.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
Note When the high-speed system clock (fMX) is supplied as the operating clock for the 24-bit ΔΣ A/D
converter, only the 12-MHz crystal resonator can be used.
<2> High-speed on-chip oscillator

The frequency at which to oscillate can be selected from among fIH = 24, 12, 6, 3, or 1.5 MHz (when the
FRQSEL3 bit is set to 0) or fIH = 16, 8, 4, 2, or 1 MHz (when the FRQSEL bit is set to 1) by using the option
byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-chip oscillator
clock. Oscillation can be stopped by executing the STOP instruction or setting of the HIOSTOP bit (bit 0 of
the CSC register).
The frequency specified by using an option byte can be changed by using the high-speed on-chip oscillator
frequency select register (HOCODIV). For details about the frequency, see Figure 6-14 Format of High-
Speed On-chip Oscillator Frequency Select Register (HOCODIV).
The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the
high-speed on-chip oscillator frequency select register (HOCODIV) are shown below.
Oscillation Frequency (MHz)

Power Supply Voltage
1 1.5 2 3 4 6 8 12 16 24
Note
2.7 V ≤ VDD ≤ 5.5 V √ √ √ √ √ √ √ √ √ √
Note
2.5 V ≤ VDD ≤ 5.5 V √ √ √ √ √ √ √ √ √ —
Note
2.4 V ≤ VDD ≤ 5.5 V √ √ √ √ √ √ √ √ — —
Note
1.9 V ≤ VDD ≤ 5.5 V √ √ √ √ √ √ √ — — —
1.7 V ≤ VDDNote ≤ 5.5 V √ √ √ √ √ — — — — —
Note This indicates the power supply voltage (that on the VDD or VBAT pin) selected by the battery back-up function.
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<3> Middle-speed on-chip oscillator

The frequency at which to oscillate can be selected from among fIM = 4, 2, 1 MHz (TYP.) by setting of the
MOCODIV bit (bits 0, 1 of the MOCODIV register). Oscillation can be stopped by executing the STOP
instruction or clearing of the MIOEN bit (bit 1 of the CSC register).
<4> PLL oscillatorNote 1

Selecting the PLL clock by setting the main clock control register (MCKC) and setting the PLL control register
(DSCCTL) causes the PLL to oscillate and produce a 32-MHz (fPLL) clock signal.
An external main system clock (fEX = 1 to 20 MHzNote 2) can also be supplied from the EXCLK/X2/P122 pin.
An external main system clock input can be disabled by executing the STOP instruction or setting of the
MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock), high-speed
on-chip oscillator clock, middle-speed on-chip oscillator clock, or PLL clockNote 1 can be selected.
The available frequency range of the main system clock varies depending on the power supply voltage VDD.
The operation voltage mode of the flash memory must be set with CMODE0 and CMODE1 of the option byte
(000C2H) (see CHAPTER 35 OPTION BYTE).
Notes 1. R5F10NPJ, R5F10NMJ, R5F10NPG only

2. When the high-speed system clock (fMX) is supplied as the operating clock for the 24-bit ΔΣ A/D
converter, supply a 12-MHz signal as the external main system clock (fEX).
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(2) Subsystem clock

<1> XT1 clock oscillator
This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 pin and XT2
pin. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register
(CSC)).
An external subsystem clock (fEXS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An
external subsystem clock input can be disabled by the setting of the XTSTOP bit.
<R> Caution The XT1 clock oscillator runs on the VRTC power-supply. It can operate after release from the
RTC power-on reset following the power supply to the VRTC pin being turned on. If the voltage
on the VRTC pin falls below the detection voltage (VPDR), an RTC power-on reset is generated and
the XT1 clock oscillator stops.
<2> Low-speed on-chip oscillator

This circuit oscillates a clock of fIL = 15 kHz (TYP.).
The low-speed on-chip oscillator clock can be used as the CPU clock. The following peripheral hardware is
driven by the low-speed on-chip oscillator clock.
● Watchdog timer
● 12-bit interval timer
● Frequency measurement circuit
● Oscillation stop detection circuit
● LCD controller/driver
This clock operates when any bit among bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of
the subsystem clock supply option control register (OSMC), or bit 0 of the subsystem clock select register
(CKSEL) is set to 1 (including multiple bits).
However, when WDTON = 1, WUTMMCK0 = 0, SELLOSC = 0, and bit 0 (WDSTBYON) of the option byte
(000C0H) is 0, oscillation of the low-speed on-chip oscillator stops if the HALT or STOP instruction is
executed.
Remark fX: X1 clock oscillation frequency

fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
fIM: Middle-speed on-chip oscillator clock frequency
fEX: External main system clock frequency
fXT: XT1 clock oscillation frequency
fEXS: External subsystem clock frequency
fIL: Low-speed on-chip oscillator frequency
fPLL: PLL clock frequency
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6.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 6-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2)
Subsystem clock supply option control register (OSMC)
High-speed on-chip oscillator frequency select register (HOCODIV)
Subsystem clock select register (CKSEL)
Middle-speed on-chip oscillator frequency select register (MOCODIV)
Frequency measurement clock select register (FMCKS)
Peripheral clock control register (PCKC)
PLL control register (DSCCTL)Note
Main clock control register (MCKC)Note
Sub clock operation mode control register (SCMC)
Sub clock operation status control register (SCSC)
Oscillators X1 oscillator
XT1 oscillator
Middle-speed on-chip oscillator
Low-speed on-chip oscillator
PLL oscillatorNote
Note R5F10NPJ, R5F10NMJ, R5F10NPG only
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<R> Figure 6-1. Block Diagram of Clock Generator

FRQSEL0 to FRQSEL3
CSC register HOCODIV register
HIOSTOP PCKC register
STOP mode signal DSADCK

fHOCO/Note 2
16 MHz (TYP.) 24 MHz (TYP.)
Selector
DSCCTL register 24-bit  A/D converter
8 MHz (TYP.) 12 MHz (TYP.) PCKC register
DSFRDIV1, DSFRDIV0,
PLLCK
DSCM, DSCON

fIH fPLL
1 MHz (TYP.) 1.5 MHz (TYP.) PLL MCKC register
CKC register CKSELR
MCM1 CKC register CKC register
MCM0 CSS
CSC register MOCODIV register CMC register
MIOEN XT1SELEN
fOCO fMAIN
Selector
Selector
STOP mode signal CPU clock
Selector
and
Middle-speed on-chip oscillator peripheral fCLK
4 MHz (TYP.), 2 MHz (TYP.), hardware CPU and each peripheral function
1 MHz (TYP.) fIM clock
CSC register source
MSTOP selection
CKC register
CLS
CKC register
MCS Clock output/buzzer output controller
CMC register
STOP mode signal EXCLK
High-speed system
X1/P121 clock oscillator
fX
Crystal/ceramic
Selector
fX fMX
oscillation
X2/EXCLK/P122 fEX
External input
fEX
clock
CKSEL register
SELLOSC
Low-speed on-chip
oscillator
(15 kHz (TYP.))

fIL fIL
Selector
fSUB
Note 3
SCSC register
Watchdog timer
OSCSELS, AMPHS1, AMPHS0 XTSTOP OSMC register OSMC register
SCMC register WUTMMCK0
RTCLPC Note 1
EXCLKS
CSC register
Subsystem clock XT1SELDIS 12-bit interval timer
8-bit interval timer
Selector
oscillator
XT1/P123 fSX LCD controller/driver
Crystal fXT Frequency measurement circuit
Selector
fXT
oscillation Clock output/buzzer output controller
XT2/EXCLKS/P124 External input
fEXS
fEXS
clock Independent power supply RTC
Notes 1. Setting the RTCLPC bit to 1 during a period in the STOP mode or in the HALT mode while the CPU is being
driven by the subsystem clock (fSUB) stops supply of the clock signal.
2. To supply the high-speed on-chip oscillator clock as the operating clock for the 24-bit ΔΣ A/D converter, set
the FRQSEL3 bit to 0 (fHOCO = 24 MHz). fHOCO/2 = 12 MHz is supplied regardless of the frequency setting of
the high-speed on-chip oscillator clock (fIH).
<R> 3. The blocks in the dotted lines run on the VRTC power-supply. They can operate after release from the RTC
power-on reset following the power supply to the VRTC pin being turned on. If the voltage on the VRTC pin
falls below the detection voltage (VPDR), an RTC power-on reset is generated and the blocks in the dotted
lines stop.

fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
fEX: External main system clock frequency
fMX: High-speed system clock frequency
fMAIN: Main system clock frequency
fXT: XT1 clock oscillation frequency
fEXS: External subsystem clock frequency
fSX: Sub clock
fSUB: Subsystem clock frequency
fCLK: CPU/peripheral hardware clock frequency
fIL: Low-speed on-chip oscillator clock frequency
fOCO: Main on-chip oscillator clock frequency (fIH or fIM)
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6.3 Registers Controlling Clock Generator
The following registers are used to control the clock generator.
● Clock operation mode control register (CMC)

● System clock control register (CKC)
● Clock operation status control register (CSC)
● Sub clock operation mode control register (SCMC)
● Sub clock operation status control register (SCSC)
● Oscillation stabilization time counter status register (OSTC)
● Oscillation stabilization time select register (OSTS)
● Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2)
● Subsystem clock supply option control register (OSMC)
● High-speed on-chip oscillator frequency select register (HOCODIV)
● Subsystem clock select register (CKSEL)
● Middle-speed on-chip oscillator frequency select register (MOCODIV)
● Frequency measurement clock select register (FMCKS)
● PLL control register (DSCCTL)
● Main clock control register (MCKC)
● Peripheral clock control register (PCKC)
Caution Which registers and bits are included depends on the product. Be sure to set registers and bits that
are not mounted in a product to their initial values.
6.3.1 Clock operation mode control register (CMC)

This register is used to set the operating mode of the X1/P121 and X2/EXCLK/P122 pins, to select the gain of the X1
oscillator, and to permit or prohibit selection of the XT1 oscillation clock or external subsystem clock.
The CMC register can be written only once by an 8-bit memory manipulation instruction after release from the reset
state. This register can be read by an 8-bit memory manipulation instruction.
Generation of reset signals other than an RTC power-on reset clears this register to 00H.
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Figure 6-2. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
CMC EXCLK OSCSEL 0 XT1SELEN 0 0 0 AMPH
EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin

pin operation mode
0 0 Input port mode Input port

0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 1 External clock input mode Input port External clock input
XT1SELEN Permits or prohibits selection of the XT1 oscillation clock (fXT) or external subsystem clock (fEXS) as the
CPU/peripheral hardware clock (fCLK)Notes 1, 2, 3
0 Prohibited (switching the clock by setting the CSS bit in the CKC register is disabled).
1 Permitted (switching the clock by setting the CSS bit in the CKC register is enabled).
AMPH Control of X1 clock oscillation frequency
0 1 MHz ≤ fX ≤ 10 MHz
1 10 MHz < fX ≤ 20 MHz
Notes 1. This bit only permits switching the clock by setting the CSS bit in the CKC register. Simply setting this bit
does not change the CPU/peripheral hardware clock (fCLK).
2. Setting this bit is not required if the low-speed on-chip oscillator clock (fIL) is selected as the CPU/peripheral
hardware clock (fCLK).
3. Be sure to write the same value as that of the OSCSELS bit in the SCMC register.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory manipulation
instruction. When using the CMC register with its initial value (00H), be sure to set the register to
00H after a reset ends in order to prevent malfunction due to a program loop. Such a malfunction
becomes unrecoverable when a value other than 00H is mistakenly written.
2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set by the clock
<R> operation status control register (CSC) or the sub clock operation status control register (SCSC).
3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
4. Specify the settings for the AMPH bit while fIH is selected as fCLK after a reset ends (before fCLK is
switched to fMX or fSUB).
5. Although the maximum system clock frequency is 32 MHz, the maximum frequency of the X1
oscillator is 20 MHz.
Remark fX: X1 clock frequency
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6.3.2 System clock control register (CKC)

This register is used to select a CPU/peripheral hardware clock and a main system clock.
The CKC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Generation of reset signals other than an RTC power-on reset clears this register to 00H.
Figure 6-3. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 00H R/WNote 1

Symbol <7> <6> <5> <4> 3 2 <1> <0>
CKC CLS CSS MCS MCM0 0 0 MCS1 MCM1
CLS Status of CPU/peripheral hardware clock (fCLK)
0 Main system clock (fMAIN)

1 Subsystem clock (fSUB)
CSS Selection of CPU/peripheral hardware clock (fCLK)
0 Main system clock (fMAIN)

1 Subsystem clock (fSUB)
MCS Status of Main system clock (fMAIN)
0 Main on-chip oscillator clock (fOCO)

1 High-speed system clock (fMX)
MCM0Note 2 Main system clock (fMAIN) operation control
0 Selects the main on-chip oscillator clock (fOCO) as the main system clock (fMAIN)
1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
MCS1 Status of Main on-chip oscillator clock (fOCO)
0 High-speed on-chip oscillator clock

1 Middle-speed on-chip oscillator clock
MCM1Note 2 Main on-chip oscillator clock (fOCO) operation control
0 High-speed on-chip oscillator clock

1 Middle-speed on-chip oscillator clock
Notes 1. Bits 7, 5, and 1 are read-only.

2. Changing the value of the MCM0 and MCM1 bits is prohibited while the CSS bit is set to 1.
Remark fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
fMX: High-speed system clock frequency
fMAIN: Main system clock frequency
fOCO: Main on-chip oscillator clock frequency (fIH or fIM)
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Cautions 1. Be sure to set bits 2 and 3 of the CKC register to 0.

2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is
changed, therefore, the clock supplied to peripheral hardware (except the independent power
supply RTC, 12-bit interval timer, clock output/buzzer output, LCD controller/driver, 8-bit interval
timer, frequency measurement circuit, oscillation stop detection circuit, and watchdog timer) is
also changed at the same time. Consequently, stop each peripheral function when changing the
CPU/peripheral hardware clock.
3. If the subsystem clock is used as the peripheral hardware clock, the operations of the A/D
converter and IICA are not guaranteed. For the operating characteristics of the peripheral
hardware, refer to the chapters describing the various peripheral hardware as well as CHAPTER
41 ELECTRICAL SPECIFICATIONS.
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6.3.3 Clock operation status control register (CSC)

This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock,
middle-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Generation of reset signals other than an RTC power-on reset sets this register to C0H.
Figure 6-4. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H After reset: C0H R/W

Symbol <7> <6> 5 4 3 2 <1> <0>
CSC MSTOP XT1SELDIS 0 0 0 0 MIOEN HIOSTOP
MSTOP High-speed system clock operation control

X1 oscillation mode External clock input mode Input port mode
0 X1 oscillator operating External clock from EXCLK pin is Input port

valid
1 X1 oscillator stopped External clock from EXCLK pin is
invalid
XT1SELDIS Control supply of the sub clock (fSX)Note 3 as the CPU/peripheral hardware clock (fCLK)Notes 1, 2
0 Enables clock supply.

1 Stops clock supply.
MIOEN Middle-speed on-chip oscillator clock operation control

0 Middle-speed on-chip oscillator stopped
1 Middle-speed on-chip oscillator operating
HIOSTOP High-speed on-chip oscillator clock operation control
0 High-speed on-chip oscillator operating

1 High-speed on-chip oscillator stopped
Notes 1. This bit only controls supply of the sub clock (fSX). It does not control oscillation of the XT1 oscillator.
2. Be sure to write 0 to this bit when the XT1 oscillation clock (fXT) or external subsystem clock (fEXS) is to be
used as the CPU/peripheral hardware clock (fCLK).
3. This does not include supply of the clock signal to the independent power supply RTC, frequency
measurement circuit, 12-bit interval timer, 8-bit interval timer, clock output/buzzer output, and LCD
controller/driver.
Cautions 1. After reset release, set the clock operation mode control register (CMC) before setting the CSC
register.
2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after
releasing reset. Note that if the OSTS register is being used with its default settings, the OSTS
register is not required to be set here.
3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization time of the X1
clock by using the oscillation stabilization time counter status register (OSTC).
4. Do not stop the clock selected for the CPU/peripheral hardware clock (fCLK) with the OSC register.
5. The setting of the flags of the register to stop clock oscillation (invalidate the external clock
input) and the condition before clock oscillation is to be stopped are as Table 6-2.
Before stopping the clock, check the preconditions for stopping the clock.
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Table 6-2. Stopping Clock Method
Clock Condition Before Stopping Clock Flag Settings of CSC or

(Invalidating External Clock Input) SCSC Register
X1 clock CPU and peripheral hardware clocks operate with a clock MSTOP = 1
other than the high-speed system clock.
External main system clock
(CLS = 0 and MCS = 0, or CLS = 1)
XT1 clock CPU and peripheral hardware clocks operate with a clock XTSTOP = 1
External subsystem clock other than the subsystem clock. (CLS = 0)
High-speed on-chip oscillator CPU and peripheral hardware clocks operate with a clock HIOSTOP = 1
clock other than the high-speed on-chip oscillator clock (CLS = 0
and MCS = 1, or CLS = 1) or CLS = 0, MCS = 0, and MCS1 = 1
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6.3.4 Sub clock operation mode control register (SCMC)

This register is used to set the operating mode of the XT1/P123 and XT2/EXCLKS/P124 pins, and to select the gain of
the oscillator.
After release from an RTC power-on reset or a reset from any other source, the SCMC register can be written only
once by an 8-bit memory manipulation instruction. This register can be read by an 8-bit memory manipulation instruction.
<R> The SCMC register operates on the VRTC power-supply.
Generation of the RTC power-on reset signal clears this register to 00H. This register is not reset by other reset
sources (including the power-on reset of the internal VDD power supply).
Figure 6-5. Format of Sub Clock Operation Mode Control Register (SCMC)

Symbol 7 6 5 4 3 2 1 0
SCMC 0 0 EXCLKS OSCSELS 0 AMPHS1 AMPHS0 0
EXCLKS OSCSELS Subsystem clock pin XT1/P123 pin XT2/EXCLKS/P124 pin

operation mode

0 1 XT1 oscillation mode Crystal oscillator connection
AMPHS1 AMPHS0 XT1 oscillator oscillation mode selection
0 0 Low-power consumption oscillation (default)

0 1 Normal oscillation
1 0 Ultra-low power consumption oscillation
1 1 Setting prohibited
Note The EXCLKS, OSCSELS, AMPHS1, and AMPHS0 bits are only initialized by an RTC power-on reset; they
retain their values following a reset due to another source (including the power-on reset of the internal VDD power
supply).
Cautions 1. After the CPU is released from the reset state, the SCMC register can be written only once by an
8-bit memory manipulation instruction. When using the SCMC register with its initial value (00H),
be sure to set the register to 00H after a reset ends in order to prevent malfunction due to a
program loop.
2. After the CPU is released from the reset state, set the SCMC register before XT1 oscillation is
started as set by the sub clock operation status control register (SCSC).
3. Specify the settings for the AMPHS1 and AMPHS0 bits while fIH is selected as fCLK after a reset
ends (before fCLK is switched to fMX).
4. Count the fXT oscillation stabilization time by using software.
5. After the CPU is released from the reset state following writing to the SCMC register and then a
reset other than an RTC power-on reset, set the same value as the value before the reset to
prevent incorrect operation in the case of an endless loop or runaway execution.
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Cautions 6. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
Note the following points when designing the circuit.
● Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation
evaluation using a circuit board to be actually used and confirm that there are no problems.
● When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the
mode of the XT1 oscillator, evaluate the resonators described in 6.7 Resonator and Oscillator
Constants.
● Make the wiring between the XT1 and XT2 pins and the resonators as short as possible,
and minimize the parasitic capacitance and wiring resistance. Note this particularly when the
ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
● Configure the circuit of the circuit board, using material with little parasitic capacitance and
wiring resistance.
● Place a ground pattern that has the same potential as VSS as much as possible near the
XT1 oscillator.
● Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross
with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
● The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due
to moisture absorption of the circuit board in a high-humidity environment or dew
condensation on the board. When using the circuit board in such an environment, take
measures to damp-proof the circuit board, such as by coating.
● When coating the circuit board, use material that does not cause capacitance or leakage
between the XT1 and XT2 pins.
<R> 7. The XT1 clock oscillator runs on the VRTC power-supply. It can operate after release from the
RTC power-on reset following the power supply to the VRTC pin being turned on.
8. Be sure to clear bits 7, 6, 3, and 0 to 0.
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6.3.5 Sub clock operation status control register (SCSC)

This register is used to control the operation of the sub clock.
The SCSC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
<R> The SCSC register operates on the VRTC power-supply.
Generation of the RTC power-on reset signal sets this register to 40H.
Figure 6-6. Format of Sub Clock Operation Status Control Register (SCSC)

Symbol 7 <6> 5 4 3 2 1 0
SCSC 0 XTSTOP 0 0 0 0 0 0
XTSTOPNote Control of XT1 oscillator operation
0 XT1 oscillation mode: XT1 oscillator operating

External clock input mode: External clock from EXCLKS pin is valid.
Input port mode: Input port
1 XT1 oscillation mode: XT1 oscillator stopped
External clock input mode: External clock from EXCLKS pin is invalid.
Note The XTSTOP bit is only initialized by an RTC power-on reset; it retains its value following a reset due to another
source (including the power-on reset of the internal VDD power supply).
Cautions 1. When starting XT1 oscillation by setting the XTSTOP bit, use software to wait for oscillation of
the sub clock to become stable.
2. Be sure to clear the bits 7 and 5 to 0 to 0.
6.3.6 Oscillation stabilization time counter status register (OSTC)

This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
● If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the
CPU clock.
● If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or an 8-bit memory manipulation instruction.
The generation of reset signal, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC))
= 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
● When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
● When the STOP mode is released
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Figure 6-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R

Symbol 7 6 5 4 3 2 1 0
OSTC MOST MOST MOST MOST MOST MOST MOST MOST

8 9 10 11 13 15 17 18
MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status
8 9 10 11 13 15 17 18 fX = 10 MHz fX = 20 MHz
8
0 0 0 0 0 0 0 0 2 /fX max. 25.6 µs max. 12.8 µs max.
8
1 0 0 0 0 0 0 0 2 /fX min. 25.6 µs min. 12.8 µs min.
9
1 1 0 0 0 0 0 0 2 /fX min. 51.2 µs min. 25.6 µs min.
1 1 1 0 0 0 0 0 210/fX min. 102 µs min. 51.2 µs min.
1 1 1 1 0 0 0 0 211/fX min. 204 µs min. 102 µs min.
13
1 1 1 1 1 0 0 0 2 /fX min. 819 µs min. 409 µs min.
15
1 1 1 1 1 1 0 0 2 /fX min. 3.27 ms min. 1.63 ms min.
17
18
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the
oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to the value
greater than the count value which is to be checked by the OSTC register.
● If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem
clock is being used as the CPU clock.
● If the STOP mode is entered and then released while the high-speed on-chip oscillator clock
is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS
register is set to the OSTC register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
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6.3.7 Oscillation stabilization time select register (OSTS)

This register is used to select the X1 clock oscillation stabilization wait time.
When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual
operation is automatically delayed for the time set in the OSTS register.
When switching the CPU clock from the high-speed on-chip oscillator clock or the subsystem clock to the X1 clock, and
when using the high-speed on-chip oscillator clock for switching the X1 clock from the oscillating state to STOP mode, use
the oscillation stabilization time counter status register (OSTC) to confirm that the desired oscillation stabilization time has
elapsed after release from the STOP mode. That is, use the OSTC register to check that the oscillation stabilization time
corresponding to its setting has been reached.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
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Figure 6-8. Format of Oscillation Stabilization Time Select Register (OSTS)

Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection

fX = 10 MHz fX = 20 MHz
8
0 0 0 2 /fX 25.6 µs 12.8 µs
9
0 0 1 2 /fX 51.2 µs 25.6 µs
10
0 1 0 2 /fX 102 µs 51.2 µs
11
0 1 1 2 /fX 204 µs 102 µs
13
1 0 0 2 /fX 819 µs 409 µs
1 0 1 215/fX 3.27 ms 1.63 ms
1 1 0 217/fX 13.1 ms 6.55 ms
18
1 1 1 2 /fX 26.2 ms 13.1 ms
Cautions 1. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation
status control register (CSC) to 0.
2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the
OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to the value
greater than the count value which is to be checked by the OSTC register after the oscillation
starts.
● If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem
clock is being used as the CPU clock.
● If the STOP mode is entered and then released while the high-speed on-chip oscillator clock
is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the
status up to the oscillation stabilization time set by the OSTS register is set to the OSTC
register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
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6.3.8 Subsystem clock select register (CKSEL)

The CKSEL register is used to select the sub clock or low-speed on-chip oscillator clock as the subsystem clock.
The CKSEL register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 6-9. Format of Subsystem Clock Select Register (CKSEL)

Symbol 7 6 5 4 3 2 1 <0>
CKSEL 0 0 0 0 0 0 0 SELLOSC
SELLOSC Selection of subsystem clock (fSUB)
0 Sub clock (fSX)

1 Low-speed on-chip oscillator clock (fIL)Note
Note Do not set SELLOSC to 1 when the sub clock (fSX) operates.
Caution When changing SELLOSC, be sure to set CSS to 0 (fMAIN selected) and change the value of SELLOSC
while CLS is 0.
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6.3.9 Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2)

These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use the peripheral functions below, which are controlled by these registers, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
● Timer array unit

● Serial array unit 0
● Serial array unit 1
● Serial interface IICA0
● 10-bit A/D converter
● IrDA
● 24-bit ΔΣ A/D converter
● DTC
● Frequency measurement circuit
● Independent power supply real-time clock
● 32-bit multiplier and accumulator
● Oscillation stop detection circuit
The PER0, PER1, and PER2 registers can be set by a 1-bit or an 8-bit memory manipulation instruction.
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Figure 6-10. Format of Peripheral Enable Register 0 (PER0)

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
PER0 0 IRDAEN ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
IRDAEN Control of IrDA input clock supply
0 Stops input clock supply.

● SFR used by IrDA cannot be written. The read value is 00H. However, the SFR is not initialized. Note 1
1 Enables input clock supply.
● SFR used by IrDA can be read and written.
ADCEN Control of A/D converter input clock supply

● SFR used by the A/D converter cannot be written. The read value is 00H. However, the SFR is not
initialized. Note 2
● SFR used by the A/D converter can be read and written.
IICA0EN Control of serial interface IICA0 input clock supply

● SFR used by the serial interface IICA0 cannot be written. The read value is 00H. However, the SFR is
not initialized. Note 3
● SFR used by the serial interface IICA0 can be read and written.
SAU1EN Control of serial array unit 1 input clock supply

● SFR used by the serial array unit 1 cannot be written. The read value is 00H. However, the SFR is not
initialized. Note 4
● SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply

● SFR used by the serial array unit 0 cannot be written. The read value is 00H. However, the SFR is not
initialized. Note 5
● SFR used by the serial array unit 0 can be read and written.
TAU0EN Control of timer array unit 0 input clock supply

● SFR used by the timer array unit 0 cannot be written. The read value is 00H. However, the SFR is not
initialized. Note 6
● SFR used by the timer array unit 0 can be read and written.
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Notes 1. To initialize the IrDA and the SFR used by the IrDA, use bit 6 (IRDARES) of PRR0.
2. To initialize the A/D converter and the SFR used by the A/D converter, use bit 5 (ADCRES) of PRR0.
3. To initialize the serial interface IICA0 and the SFR used by the serial interface IICA0, use bit 4 (IICA0RES)
of PRR0.
4. To initialize the serial array unit 1 and the SFR used by the serial array unit 1, use bit 3 (SAU1RES) of
PRR0.
PRR0.
6. To initialize the timer array unit 0 and the SFR used by the timer array unit 0, use bit 0 (TAU0RES) of PRR0.
Cautions 1. Be sure to clear the following bits to 0.

Bits 1 and 7
2. Do not change the target bit in the PER0 register while operation of each peripheral function is
enabled. Change the setting specified by PER0 while operation of each peripheral function
assigned to PER0 is stopped.
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Address: F00FAH After reset: 00H R/W

Symbol 7 <6> 5 4 <3> 2 1 <0>
PER1 0 FMCEN 0 0 DTCEN 0 0 DSADCEN
FMCEN Control of frequency measurement circuit input clock supply

● SFR used by the frequency measurement circuit cannot be written. The read value is 00H.
● The frequency measurement circuit is in the reset state.
● SFR used by the frequency measurement circuit can be read and written.
DTCEN Control of DTC input clock supply

● DTC cannot run.
● DTC can run.
DSADCEN Control of 24-bit ΔΣ A/D converter input clock supply

● SFR used by the 24-bit ΔΣ A/D converter cannot be written. The read value is 00H. However, the SFR
is not initialized. Note
● SFR used by the 24-bit ΔΣ A/D converter can be read and written.
Note To initialize the 24-bit ΔΣ A/D converter and the SFR used by the 24-bit ΔΣ A/D converter, use bit 0 (DSADRES)
of PRR1.

Bits 1, 2, 4, 5 and 7
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Address: F00FCH After reset: 00H R/W

Symbol <7> <6> 5 4 3 <2> 1 <0>
PER2 TMKAEN OSDCEN 0 0 0 MACEN 0 VRTCEN
TMKAEN Control of 12-bit interval timer input clock supply

● SFR used by the 12-bit interval timer cannot be written. The read value is 00H. However, the SFR is
not initialized. Note 1
● SFR used by the 12-bit interval timer can be read and written.
OSDCEN Control of oscillation stop detection circuit input clock supply

● SFR used by the oscillation stop detection circuit cannot be written. The read value is 00H. However,
the SFR is not initialized. Note 2.
● SFR used by the oscillation stop detection circuit can be read and written.
MACEN Control of 32-bit multiplier and accumulator input clock supply

● SFR used by the 32-bit multiplier and accumulator cannot be written. The read value is 00H. However,
the SFR is not initialized. Note 3
● SFR used by the 32-bit multiplier and accumulator can be read and written.
VRTCEN Control of independent power supply RTC input clock supply

● SFR used by the independent power supply RTC cannot be written. The read value is 00H. The sub
clock (fSX) clock can drive counting by the independent power supply RTC.
● SFR used by the independent power supply RTC can be read and written. Note 4
Notes 1. To initialize the 12-bit interval timer and the SFR used by the 12-bit interval timer, use bit 7 (TMKARES) of
PRR2.
2. To initialize the oscillation stop detection circuit and the SFR used by the oscillation stop detection circuit,
use bit 6 (OSDCRES) of PRR2.
3. To initialize the 32-bit multiplier and accumulator and the SFR used by the 32-bit multiplier and accumulator,
use bit 2 (MACRES) of PRR2.
4. Set the VRTCEN bit to 0 except during reading or writing of the SFRs of the independent power supply RTC.

Bits 1 and 3 to 5
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6.3.10 Subsystem clock supply option control register (OSMC)

This register is used to reduce power consumption by stopping unnecessary clock functions.
If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions,
except the independent power supply RTC, 12-bit interval timer, 8-bit interval timer, clock output/buzzer output controller,
LCD controller/driver, oscillation stop detection circuit, and frequency measurement circuit is stopped in STOP mode or
HALT mode while sub clock (fSX) is selected as CPU clock.
In addition, the OSMC register can be used to select the operating clock of the 12-bit interval timer, 8-bit interval timer,
clock output/buzzer output controller, LCD controller/driver, and frequency measurement circuit.
The OSMC register can be set by an 8-bit memory manipulation instruction or a 1-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 6-13. Format of Subsystem Clock Supply Option Control Register (OSMC)
Address: F00F3H After reset: 00H R/WNote 1

Symbol <7> 6 5 <4> 3 2 1 0
OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0
RTCLPCNote 4 Setting in STOP mode or HALT mode while sub clock (fSX) is selected as CPU clock
Enables supply of sub clock (fSX) to peripheral functions

0
(See Tables 26-1 to 26-3 for peripheral functions whose operations are enabled.)
Stops supply of sub clock (fSX) to peripheral functions other than the independent power supply RTC, 12-
1 bit interval timer, 8-bit interval timer, clock output/buzzer output controller, LCD controller/driver,
oscillation stop detection circuit, and frequency measurement circuit.
Selection of the operating clock

Selection of the count
for the 12-bit interval timer, 8-bit Selection of the output clock for
operation/stop trigger clock for
WUTMMCK0 interval timer, LCD the clock output/buzzer output
the frequency measurement
controller/driver, and frequency controller
circuit
measurement circuit
0 Sub clock (fSX) Sub clock (fSX) selected Sub clock (fSX)
Low-speed on-chip oscillator Low-speed on-chip oscillator
1 Notes 2, 3, 6, 7 Clock output is prohibited. Note 5
clock (fIL) clock (fIL) selectedNote 6
Notes 1. Be sure to set bits 0 to 3, 5, and 6 to 0.

2. Do not set the WUTMMCK0 bit to 1 while the sub clock (fSX) is oscillating.
3. Switching between the sub clock (fSX) and the low-speed on-chip oscillator clock (fIL) can be enabled by the
WUTMMCK0 bit only when all of the 12-bit interval timer, 8-bit interval timer, clock output/buzzer output
controller, LCD controller/driver, and frequency measurement circuit are stopped.
4. When the sub clock (fSX) is selected (SELLOSC = 0) by bit 0 (SELLOSC) of the CKSEL register and
RTCLPC is set to 1, the subsystem clock (fSUB) is stopped. However, when the low-speed on-chip oscillator
clock is selected (SELLOSC = 1) and RTCLPC is set to 1, the subsystem clock (fSUB) is not stopped.
5. When the WUTMMCK0 bit is set to 1, clock output from the PCLBUZn pin is prohibited.
6. When the WUTMMCK0 bit is set to 1, the low-speed on-chip oscillator clock (fIL) oscillates.
7. When the WUTMMCK0 bit is set to 1, internal voltage boosting cannot be used for the LCD drive voltage
generator of the LCD controller/driver.
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6.3.11 High-speed on-chip oscillator frequency select register (HOCODIV)

The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using
high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the
FRQSEL3 bit of the option byte (000C2H).
The HOCODIV register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to the value set by FRQSEL2 to FRQSEL0 of the option byte (000C2H).
Figure 6-14. Format of High-speed On-chip Oscillator Frequency Select Register (HOCODIV)
Address: F00A8H After reset: the value set by FRQSEL2 to FRQSEL0 of the option byte (000C2H) R/W
Symbol 7 6 5 4 3 2 1 0
HOCODIV 0 0 0 0 0 HOCODIV2 HOCODIV1 HOCODIV0
Selection of high-speed on-chip oscillator clock frequency

HOCODIV2 HOCODIV1 HOCODIV0
FRQSEL3 = 0 FRQSEL3 = 1Note 2
0 0 0 fIH = 24 MHzNote 1 Setting prohibitedNote 1

0 0 1 fIH = 12 MHz fIH = 16 MHzNote 2
1 0 0 fIH = 1.5 MHz fIH = 2 MHzNote 2
1 0 1 Setting prohibited fIH = 1 MHzNote 2
Notes 1. When 32 MHz is selected for the CPU/peripheral hardware clock (fCLK), set the high-speed on-chip oscillator
clock (fIH) to 24 MHz and select the PLL clock (32 MHz).
2. When the high-speed on-chip oscillator clock (fIH) is selected as the operating clock for the 24-bit ΔΣ A/D
converter (the DSADCK bit in the PCKC register is set to 0), the 24-bit ΔΣ A/D converter cannot be used.
Cautions 1. Set the HOCODIV register within the operable voltage range of the flash operation mode set in
the option byte (000C2H) before and after the frequency change.
Option Byte (000C2H) Value Operating Operating Voltage

Flash Operation Mode
CMODE1 CMODE0 Frequency Range Range
0 1 LP (low-power main) mode 1 MHz 1.9 to 5.5 V

0 0 LV (low-voltage main) mode 1 to 4 MHz 1.7 to 5.5 V
1 0 LS (low-speed main) mode 1 to 8 MHz 1.9 to 5.5 V
1 1 1 to 12 MHz 2.4 to 5.5 V
1 to 16 MHz 2.5 to 5.5 V
HS (high-speed main) mode
1 to 24 MHz 2.7 to 5.5 V
1 to 32 MHz 2.8 to 5.5 V
2. Set the HOCODIV register with the high-speed on-chip oscillator clock (fIH) selected as the
CPU/peripheral hardware clock (fCLK).
3. After the frequency is changed with the HOCODIV register, the frequency is switched after the
following transition time has elapsed.
● Operation for up to three clocks at the pre-change frequency
● CPU/peripheral hardware clock wait at the post-change frequency for up to three clocks
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6.3.12 Middle-speed on-chip oscillator frequency select register (MOCODIV)

The MOCODIV register is used to select the division ratio of the middle-speed on-chip oscillator.
The MOCODIV register can be set by an 8-bit memory manipulation instruction.
Figure 6-15. Format of Middle-speed On-chip Oscillator Frequency Select Register (MOCODIV)

Symbol 7 6 5 4 3 2 1 0
MOCODIV 0 0 0 0 0 0 MOCODIV1 MOCODIV0
MOCODIV1 MOCODIV0 Selection of middle-speed on-chip oscillator clock frequency
0 0 4 MHz
0 1 2 MHz
1 0 1 MHz
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6.3.13 Frequency measurement clock select register (FMCKS)

The FMCKS register is used to select the operating clock and frequency count clock to be input to the frequency
measurement circuit.
The FMCKS register can be used by a 1-bit or an 8-bit memory manipulation instruction.
Reset signal generation clears the FMCKS register to 00H.
Figure 6-16. Format of Frequency Measurement Clock Select Register (FMCKS)
Address: F007AH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
FMCKS 0 0 0 0 0 0 FMCKSEL1 FMCKSEL0
FMCKSEL1 FMCKSEL0 Selection of frequency count clock
0 0 fMX selected
0 1 fIM selected
1 × fIH selected
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6.3.14 PLL control register (DSCCTL)

This register is used to control operation of the PLL oscillator.
To select 32 MHz for the CPU/peripheral hardware clock (fCLK) while the high-speed on-chip oscillator clock (fIH) is
selected as the operating clock for the 24-bit ΔΣ A/D converter (the DSADCK bit in the PCKC register is set to 0), divide
the high-speed on-chip oscillator clock (fIH = 24 MHz) by 6 to obtain the 4-MHz PLL reference clock. After that, select
multiplication by 16 and division by 2 for the PLL (multiplication by 8) to obtain a 32-MHz clock signal from the PLL (fPLL).
The DSCCTL register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 6-17. Format of PLL Control Register (DSCCTL)
Address: F02E5H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
DSCCTL 0 0 0 0 DSFRDIV1 DSFRDIV0 DSCM DSCON
DSFRDIV1 DSFRDIV0 Control over frequency division of the PLL reference clockNotes 3, 4
1 1 Frequency division by 6 (fIH/6)

DSCM Selection of multiplication by the PLLNote 1
1 Multiplication by 16 and division by 2 (multiplication by 8)

DSCON Control of PLL oscillation and outputNote 5
0 PLL stops
1 PLL oscillates and the result is outputNote 2
Notes 1. The multiplier in parentheses “()” is because of division by 2 at the last stage of the PLL oscillator.
2. After the PLL starts operation, at least 40 µs of waiting for lock-up is required for the frequency to become
stable.
3. Do not change the division setting of the PLL reference clock while the PLL is operating. Stop the PLL
before changing the setting.
4. The only signal used as the PLL reference clock is fIH, which runs at 24 MHz.
5. When making a transition to the STOP mode, switch to the high-speed on-chip oscillator clock (fIH = 24
MHz) and stop the PLL.
Caution Be sure to clear bits 4 to 7 to 0.
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6.3.15 Main clock control register (MCKC)

This register is used to control the operation of the main clock.
The MCKC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 6-18. Format of Main Clock Control Register (MCKC)
Address: F02E6H After reset: 00H R/WNote 1

Symbol 7 6 5 4 3 2 1 0
MCKC CKSTR 0 0 0 0 0 0 CKSELR
CKSTR State of switching the main system clock (fMAIN)
0 On-chip oscillator clock (fOCO)/high-speed system clock (fMX)Note 2

1 PLL clock (fPLL)
CKSELR Selection of the main system clock (fMAIN)
0 On-chip oscillator clock (fOCO)/high-speed system clock (fMX)Note 2

1 PLL clock (fPLL)Note 3
Notes 1. Bit 7 is read only.

2. Select with the bit 4 (MCM0) of the system clock control register (CKC).
3. The high-speed on-chip oscillator clock must not be stopped while the PLL is selected.
Remark Because the MCM0 bit is given priority in the case of the conflict between MCM0 and CKSELR bits, the main
system clock is selected.
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6.3.16 Peripheral clock control register (PCKC)

This register is used to select the peripheral clock (operating clock for the 24-bit ΔΣ A/D converter or operating clock for
the PLL).
When this is used as the operating clock for the 24-bit ΔΣ A/D converter, only the 12-MHz crystal resonator can be used
as the high-speed system clock (fMX).
The PCKC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 6-19. Format of Peripheral Clock Control Register (PCKC)
Address:F0098H After reset: 00H R/W

Symbol 7 6 5 4 3 2 <1> <0>
PCKC 0 0 0 0 0 0 PLLCK DSADCK
PLLCK Control of operating clock supplied to the PLL
0 Stops supply of the high-speed on-chip oscillator clock (fIH).

1 Enables supply of the high-speed on-chip oscillator clock (fIH).
DSADCK Selection of operating clock for the 24-bit ΔΣ A/D converter
0 Enables supply of the high-speed on-chip oscillator clock (fIH)Notes 2, 3 (stops supply of fMX).
1 Enables supply of the high-speed system clock (fMX).Note 1
Notes 1. Only the 12-MHz crystal resonator can be used as the high-speed system clock (fMX).
2. When the high-speed on-chip oscillator clock (fIH) is to be selected, set fIH to 24, 12, 6, 3, or 1.5 MHz
(FRQSEL3 = 0).
3. Even when the PLL clock (fPLL) is selected as the CPU/peripheral hardware clock (fCLK), the high-speed
oscillator clock (fIH = 24 MHz) is supplied as the operating clock for the 24-bit ΔΣ A/D converter.
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6.4 System Clock Oscillator
6.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
● Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
● External clock input: EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins.
Figure 6-20 shows an example of the external circuit of the X1 oscillator.
Figure 6-20. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation (b) External clock
VSS
X1
X2 External clock EXCLK
Crystal resonator
or
ceramic resonator
Caution is listed on the next page.
6.4.2 XT1 oscillator

The XT1 oscillator oscillates with a crystal resonator (32.768 kHz (TYP.)) connected to the XT1 and XT2 pins.
<R> The XT1 clock oscillator runs on the VRTC power-supply. To use the XT1 oscillator, after turning on the power supply to
the VRTC pin and release from the RTC power-on reset, set both bit 4 (OSCSELS) of the sub clock operation mode
control register (SCMC) and bit 4 (XT1SELEN) of the clock operation mode control register (CMC) to 1.
An external clock can also be input. In this case, input the clock signal to the EXCLKS pin.
To use the XT1 oscillator, after turning on the power supply to the VRTC pin and release from the RTC power-on reset,
set bits 5 and 4 (EXCLKS, OSCSELS) of the sub clock operation mode control register (SCMC) and bit 4 (XT1SELEN) of
the clock operation mode control register (CMC) as follows.
● Crystal oscillation: EXCLKS, OSCSELS = 0, 1, XT1SELEN = 1
● External clock input: EXCLKS, OSCSELS = 1, 1, XT1SELEN = 1
When the XT1 oscillator is not used, set the input port mode (EXCLKS, OSCSELS = 0, 0).
When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins.
Figure 6-21 shows an example of the external circuit of the XT1 oscillator.
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Figure 6-21. Example of External Circuit of XT1 Oscillator
(a) Crystal oscillation (b) External clock
VSS
XT1
32.768
kHz
XT2 External clock EXCLKS
Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken
lines in the Figures 6-20 and 6-21 to avoid an adverse effect from wiring capacitance.
● Keep the wiring length as short as possible.
● Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
● Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
● Do not fetch signals from the oscillator.
The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
● Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation
using a circuit board to be actually used and confirm that there are no problems.
● When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode
of the XT1 oscillator, evaluate the resonators described in 6.7 Resonator and Oscillator Constants.
● Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and
minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultra-
low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
● Configure the circuit of the circuit board, using material with little wiring resistance.
● Place a ground pattern that has the same potential as VSS as much as possible near the XT1
oscillator.
● Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross with
the other signal lines. Do not route the wiring near a signal line through which a high fluctuating
current flows.
to moisture absorption of the circuit board in a high-humidity environment or dew condensation on
the board. When using the circuit board in such an environment, take measures to damp-proof the
circuit board, such as by coating.
● When coating the circuit board, use material that does not cause capacitance or leakage between
the XT1 and XT2 pins.
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Figure 6-22 shows examples of incorrect resonator connection.
Figure 6-22. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
PORT
VSS X1 X2 VSS X1 X2
NG
NG
NG
(c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
VSS X1 X2
VSS X1 X2
Note
Power supply/GND pattern
Note Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the
figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board.
Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics.
<R> Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
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Figure 6-22. Examples of Incorrect Resonator Connection (2/2)
(e) Wiring near high alternating current (f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
VSS X1 X2
VSS X1 X2
High current
A B C
High current
(g) Signals are fetched
VSS X1 X2
Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in
malfunctioning.
<R> Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
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6.4.3 High-speed on-chip oscillator

The high-speed on-chip oscillator is incorporated in the RL78/I1C. The frequency can be selected from among 24, 16,
12, 8, 6, 4, 3, 2, 1.5, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the
clock operation status control register (CSC).
The high-speed on-chip oscillator automatically starts oscillating after reset release.
6.4.4 Middle-speed on-chip oscillator

The middle-speed on-chip oscillator is incorporated in the RL78/I1C. Oscillation can be controlled by bit 1 (MIOEN) of
the clock operation status control register (CSC).
6.4.5 Low-speed on-chip oscillator

The low-speed on-chip oscillator is incorporated in the RL78/I1C.
<R> The low-speed on-chip oscillator runs while the watchdog timer is operating or when the setting of either or both of the
following bits is 1: bit 4 (WUTMMCK0) in the subsystem clock supply mode control register (OSMC) or bit 0 (SELLOSC) in
the subsystem clock select register (CKSEL).
The low-speed on-chip oscillator is stopped when the watchdog timer is stopped and both WUTMMCK0 and SELLOSC
are set to 0.
6.4.6 Phase-locked loop (PLL)

The RL78/I1C incorporates a PLL circuit.
The high-speed on-chip oscillator clock (fIH = 24 MHz) is divided by 6 to obtain the 4-MHz PLL reference clock and then
multiplied by 16 and divided by 2 (multiplied by 8) to obtain a 32-MHz clock signal from the PLL (fPLL).
Operation is controlled by bit 0 (DSCON) in the PLL control register (DSCCTL).
Caution When making a transition to the STOP mode, switch to the high-speed on-chip oscillator clock and
stop the PLL. Do not stop the high-speed on-chip oscillator clock while the PLL is in use.
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6.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 6-1).
CPU/peripheral hardware clock fCLK

(1) Main system clock fMAIN
(1-1) High-speed system clock fMX
● X1 clock fX
● External main system clock fEX
(1-2) Main on-chip oscillator clock fOCO
● High-speed on-chip oscillator clock fIH
● Middle-speed on-chip oscillator clock fIM
(1-3) PLL clock fPLL
(2) Subsystem clock fSUB

(2-1) Sub clock fSX
● XT1 clock fXT
● External subsystem clock fEXS
(2-2) Low-speed on-chip oscillator clock fIL
Clock for the peripheral hardware

(1) Clock for the watchdog timer
● Low-speed on-chip oscillator clock fIL
(2) Clock for the independent power supply RTC
● Sub clock fSX
(3) Clock for the 12-bit interval timer, 8-bit interval timer, LCD controller/driver, oscillation stop detection circuit,
frequency measurement circuit, and clock output/buzzer output controller
● Sub clock fSX
● Low-speed on-chip oscillator clock fIL
(4) Operating clock for the 24-bit ΔΣ A/D converter
● High-speed on-chip oscillator clock fIH
● High-speed system clock fMX
The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/I1C.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-23.
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Figure 6-23. Clock Generator Operation When Power Supply Voltage Is Turned On
10 µs or
more
Lower limit of the operating

voltage range
Power supply voltage (VDD)
VPOR
0V
<1>
Power-on-reset
RESET pin
Reset processing Switched by software

time Note 3 <3> <5> <5>
CPU clock High-speed on-chip High-speed
oscillator clock system clock Subsystem clock
<2>
High-speed on-chip
oscillator clock (fIH)
High-speed system clock Note 1

(fMX) <4>
(when X1 oscillation
selected)
X1 clock oscillation
Subsystem clock (fSUB) stabilization time Note 2
(when XT1 oscillation Starting X1 oscillation <4>
selected) is specified by software.
Starting XT1 oscillation is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit.
Note that the reset state is maintained after a reset by the voltage detection circuit or an external reset until the
voltage reaches the range of operating voltage described in 41.4 AC Characteristics (the above figure is an
example when the external reset is in use).
<2> When the reset is released, the high-speed on-chip oscillator automatically starts oscillation.
<3> The CPU starts operation on the high-speed on-chip oscillator clock after waiting for the voltage to stabilize and a
reset processing have been performed after reset release.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see 6.6.2 Example of setting X1 oscillation
clock and 6.6.3 Example of setting XT1 oscillation clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see 6.6.2 Example of setting X1 oscillation clock and 6.6.3 Example of setting XT1
oscillation clock).
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on
chip oscillator clock.
2. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3. For the reset processing time, see CHAPTER 28 POWER-ON-RESET CIRCUIT.
Cautions 1. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
2. The subsystem clock must be set after turning on the power supply to the VRTC pin and release
from the RTC power-on reset.
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6.6 Controlling Clock
6.6.1 Example of setting high-speed on-chip oscillator

After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 24, 16, 12, 8, 6, 4, 3, 2, 1.5, and
1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H). In addition, Oscillation can be changed by the high-
speed on-chip oscillator frequency select register (HOCODIV).
[Option byte setting]

Address: 000C2H
7 6 5 4 3 2 1 0
Option byte CMODE1 CMODE0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
<R> (000C2H) 0/1 0/1 1 0 0/1 0/1 0/1 0/1
CMODE1 CMODE0 Setting of flash operation mode
0 0 LV (low-voltage main) mode VDD = 1.7 V to 5.5 V @ 1 MHz to 4 MHz

1 0 LS (low-speed main) mode VDD = 1.9 V to 5.5 V @ 1 MHz to 8 MHz
1 1 HS (high-speed main) mode VDD = 2.1 V to 5.5 V @ 1 MHz to 6 MHz
VDD = 2.4 V to 5.5 V @ 1 MHz to 12 MHz
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator

fIH
0 0 0 0 24 MHz
1 0 0 1 16 MHz
0 0 0 1 12 MHz
1 0 1 0 8 MHz
0 0 1 0 6 MHz
1 0 1 1 4 MHz
0 0 1 1 3 MHz
1 1 0 0 2 MHz
0 1 0 0 1.5 MHz
1 1 0 1 1 MHz
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[High-speed on-chip oscillator frequency select register (HOCODIV) setting]

Address: F00A8H
Symbol 7 6 5 4 3 2 1 0
HOCODIV 0 0 0 0 0 HOCODIV2 HOCODIV1 HOCODIV0
HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed on-chip oscillator clock frequency

0 0 0 fIH = 24 MHzNote 1 Setting prohibitedNote 1

1 0 0 fIH =1.5 MHz fIH = 2 MHzNote 2
1 0 1 Setting prohibited fIH = 1 MHzNote 2
Notes 1. When 32 MHz is selected for the CPU/peripheral hardware clock (fCLK), set the high-speed on-chip oscillator
clock (fIH) to 24 MHz and select the PLL clock (32 MHz).
2. When the high-speed on-chip oscillator clock (fIH) is selected as the operating clock for the 24-bit ΔΣ A/D
converter (the DSADCK bit in the PCKC register is set to 0), the 24-bit ΔΣ A/D converter cannot be used.
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6.6.2 Example of setting X1 oscillation clock

After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the oscillation stabilization time select register (OSTS), clock operation mode control register (CMC), and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter
status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control
register (CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set (1) the OSCSEL bit of the CMC register, except for the cases where the fX is equal to or more than 10 MHz, in
such cases set (1) the AMPH bit, to operate the X1 oscillator.
7 6 5 4 3 2 1 0
EXCLK OSCSEL XT1SELEN AMPH

CMC
0 1 0 0 0 0 0 0/1
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP
mode.
Example: Setting values when a wait of at least 102 µs is set based on a 10 MHz resonator.
7 6 5 4 3 2 1 0
OSTS2 OSTS1 OSTS0

OSTS
0 0 0 0 0 0 1 0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7 6 5 4 3 2 1 0
MSTOP XT1SELDIS MIOEN HIOSTOP
CSC
0 1 0 0 0 0 0 0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102 µs is set based on a 10 MHz
resonator.
7 6 5 4 3 2 1 0
MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18
OSTC
1 1 1 0 0 0 0 0
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
7 6 5 4 3 2 1 0
CLS CSS MCS MCM0 MCS1 MCM1
CKC
0 0 0 1 0 0 0 0
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Caution Set the HOCODIV register within the operable voltage range of the flash operation mode set in the
option byte (000C2H) before and after the frequency change.
Option Byte (000C2H) Value Operating Operating Voltage

Flash Operation Mode
CMODE1 CMODE0 Frequency Range Range
0 1 LP (low-power main) mode 1 MHz 1.9 to 5.5 V

1 0 LS (low-speed main) mode 1 to 8 MHz 1.9 to 5.5 V
1 to 12 MHz 2.4 to 5.5 V
1 to 16 MHz 2.5 to 5.5 V
1 to 24 MHz 2.7 to 5.5 V
1 to 32 MHz 2.8 to 5.5 V
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6.6.3 Example of setting XT1 oscillation clock

After release from the reset state (except that following the RTC power-on reset), the high-speed on-chip oscillator
clock is always the initial CPU/peripheral hardware clock (fCLK).
After turning on the power supply to the VRTC pin and release from the RTC power-on reset, the XT1 oscillator and
RTC circuit can operate.
To subsequently change the CPU/peripheral hardware clock (fCLK) to the XT1 oscillation clock, set the oscillator and
start oscillation by using the subsystem clock supply option control register (OSMC), sub clock operation mode control
register (SCMC), clock operation mode control register (CMC), clock operation status control register (CSC), and sub
clock operation status control register (SCSC), set the XT1 oscillation clock to fCLK by using the system clock control
register (CKC).
<1> Turn on the power supply to the VRTC pin, and release the RTC power-on reset.
<2> To operate the frequency measurement circuit, 12-bit interval timer, 8-bit interval timer, clock output/buzzer output,
oscillation stop detection circuit, and LCD controller/driver with the sub-system clock (ultra-low current
consumption) in STOP mode or in HALT mode while CPU is operating with the sub-system clock, set the
RTCLPC bit to 1.
7 6 5 4 3 2 1 0
RTCLPC WUTMMCK0
OSMC
0/1 0 0 0 0 0 0 0
<3> Set (1) the VRTCEN bit in the PER2 register to permit access to the SFRs in the VRTC power-supply domain.
<4> Set the EXCLKS, OSCSELS, AMPHS1, and AMPHS0 bits in the SCMC register, and set the XT1 oscillation
mode and the gain for the XT1 oscillator.
7 6 5 4 3 2 1 0
EXCLKS OSCSELS AMPHS1 AMPHS0

SCMC
0 0 0 1 0 0/1 0/1 0
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
<R> <5> Set (1) the XT1SELEN bit in the CMC register to permit selection of the XT1 clock as the CPU clock.
<6> Clear (0) the XTSTOP bit of the SCSC register to start oscillation of the XT1 oscillator.
7 6 5 4 3 2 1 0
XTSTOP
SCSC
0 0 0 0 0 0 0 0
<7> Use the timer function or another function to wait for oscillation of the XT1 oscillation clock to stabilize by using
software.
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<8> Clear (0) the XT1SELDIS bit of the CSC register to permit selection of the XT1 clock as the CPU/peripheral
hardware clock.
<9> Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock
7 6 5 4 3 2 1 0
CLS CSS MCS MCM0 MCS1 MCM1
CKC
0 1 0 0 0 0 0 0
<10> After completion of setting the SFRs in the VRTC power-supply domain, clear (0) the VRTCEN bit in the PER2
register to prohibit access to SFRs in the VRTC power-supply domain.
<R> Caution Once the settings in steps <4>, <6>, and <7> are made, the values are retained except in case of an
RTC power-on reset, so making the settings again will not be necessary unless this occurs.
6.6.4 Procedure for settings when the XT1 oscillator is not to be used as the CPU/peripheral hardware clock
<1> Turn on the power supply to the VRTC pin, and release the RTC power-on reset.
<2> Set the EXCLKS, OSCSELS, AMPHS1, and AMPHS0 bits in the SCMC register, and set the XT1 oscillation
mode and the gain for the XT1 oscillator. When the XT1 clock is not to be used, set the SCMC register to 00H
and set the XT1/P123 and XT2/EXCLKS/P124 pins to the input port mode.
<3> Clear (0) the XT1SELEN bit of the CMC register to prohibit selection of the XT1 clock as the CPU clock.
<4> Set (1) the XT1SELDIS bit of the CSC register to prohibit selection of the XT1 clock as the CPU/peripheral
hardware clock.
Caution Once the settings in step <2> are made, the values are retained except in case of an RTC power-on
reset, so making the settings again will not be necessary unless this occurs.
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6.6.5 CPU clock status transition diagram

Figure 6-24 shows the CPU clock status transition diagram of this product.
Figure 6-24. CPU Clock Status Transition Diagram
Power ON
VDD  Lower limit of the operating voltage range

(A) (release from the reset state triggered by the LVD circuit or an external reset )
Reset release
(R)
CPU:
PLL clock HALT
(Q)
(G)
CPU: CPU:
Operating with PLL High-speed on-chip (H)
clock oscillator HALT
CPU:
(B) High-speed on-chip
CPU: oscillator STOP
Operating with
(E) high-speed on-chip (I)
CPU:
oscillator (F) CPU: CPU:
Operating with Operating with High-speed on-chip
XT1/EXCLK Low-speed on-chip oscillator SNOOZE
(O) inputNote oscillator
CPU: (P) CPU:
XT1/EXCLK input Low-speed on-chip
HALTNote (D) (C) oscillator HALT
CPU:
CPU:
(M) Operating with
Operating with (J)
Middle-speed on-chip
X1/EXCLK input
CPU: oscillator CPU:
X1/EXCLK input Middle-speed on-chip
HALT oscillator HALT
(L)
(N) CPU: (K)
CPU: oscillator SNOOZE CPU:
X1/EXCLK input Middle-speed on-chip
STOP oscillator STOP
: CPU clock state transitions
: CPU operation mode state transitions
Note Operation is possible after release from RTC power-on-reset.
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Table 6-3 shows show transition of the CPU clock and examples of setting the SFR registers.
Table 6-3. CPU Clock Transition and SFR Register Setting Examples (1/5)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Target state transition: (A) → (B)
Clock After Change SFR Register Setting

High-speed on-chip oscillator clock SFR registers do not have to be set (default status after reset release).
(2) Changing to high-speed on-chip oscillator clock operation (B)

Target state transition: (C) → (B), (D) → (B), (E) → (B), (F) → (B)
(Setting sequence of SFR registers)

Setting Flag of SFR Register CSC Register Waiting for CKC Register
Oscillation
HIOSTOP CSS MCM0 MCM1
Clock After Change Stabilization
High-speed on-chip oscillator clock 0 65 µs 0 0 0
Unnecessary if the CPU is

operating with the high-speed on-
chip oscillator clock
Target state transition: (Q) → (B)

Setting Flag of SFR Register MCKC Register Waiting for the clocks to be DSCCTL PCKC
switched Register Register
Clock After Change CKSELR DSCON PLLCK
High-speed on-chip oscillator 0 Confirm that the CKSTR in the 0 0

MCKC register is set to 0.
(3) Changing to middle-speed on-chip oscillator clock operation (C)

Target state transition: (B) → (C), (D) → (C), (E) → (C), (F) → (C)

Setting Flag of SFR Register CSC Register Waiting for CKC Register
MIOEN Oscillation CSS MCM0 MCM1
Clock After Change Stabilization
Middle-speed on-chip oscillator clock 1 4 µs 0 0 1
Unnecessary if the CPU is

operating with the middle-speed
on-chip oscillator clock
Remark (A) to (R) in table 6-3 correspond to (A) to (R) in Figure 6-24.
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(4) Changing to PLL clock operation (Q)

Target state transition: (B) → (Q)
Setting Flag of SFR Register DSCCTL PCKC DSCCTL

Register Register Register
Clock After Change DSFRDIV1 DSFRDIV0 DSCM PLLCK DSCON
PLL clock 1 1 1 1 1
Waiting time for MCKC Waiting for the clocks to be

lock-up Register switched
CKSELR
40 µs 1 Confirm that the CKSTR in the
MCKC register is set to 1.
Caution 24 MHz must be selected as the frequency of the high-speed on-chip oscillator clock (fIH).
Remark (A) to (R) in Table 6-3 correspond to (A) to (R) in Figure 6-24.
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(5) Changing the CPU to high-speed system clock operation (D)

Target state transition: (B) → (D), (C) → (D), (E) → (D), (F) → (D)
Setting Flag of SFR Register CMC RegisterNote 1 OSTS CSC OSTC CKC
Register Register Register Register
Clock After Change EXCLK OSCSEL AMPH MSTOP CSS MCM0
Changing to X1 clock: 1 MHz ≤ fX ≤ 10 MHz 0 1 0 Note 2 0 Must be 0 1

checked
Changing to X1 clock: 10 MHz < fX ≤ 20 0 1 1 Note 2 0 Must be 0 1
MHz checked
Changing to external main clock 1 1 × Note 2 0 Need not 0 1
be
checked
Unnecessary if these Unnecessary if the CPU is

registers are already set operating with the high-speed
system clock
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
● Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
≤ Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 41 ELECTRICAL SPECIFICATIONS).
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(6) Changing the CPU to subsystem clock operation (E)

Target state transition: (B) → (E), (C) → (E), (D) → (E)
Setting Flag of SFR Register PER2 Register SCMC RegisterNote
Clock After Change VRTCEN EXCLKS OSCSELS AMPHS1 AMPHS0
Changing to XT1 clock 1 0 1 0/1 0/1
Changing to external sub clock 1 1 1 × ×
Unnecessary if these registers are already set
SCSC CMC Waiting for CSC CKC PER2

Register Register Oscillation Register Register Register
XTSTOP XT1SELEN Stabilization XT1SELDIS CSS VRTCEN
0 1 Necessary 0 1 0
× 1 Necessary 0 1 0
Unnecessary if the CPU is operating with the subsystem

clock
Note After release from the reset state, the sub clock operation mode control register (SCMC) can be written only
once by an 8-bit memory manipulation instruction.
Operation is possible after turning on the power supply to the VRTC pin and release from the RTC power-on reset.
(7) Changing to low-speed on-chip oscillator clock operation (F)

Target state transition: (B) → (F), (C) → (F), (D) → (F)
Setting Flag of SFR Register CKSEL Oscillation accuracy CKC Register

Clock After Change stabilization time
SELLOSC CSS
Changing to low-speed on-chip oscillator 1 210 µs 1
Unnecessary
if the CPU is operating with
the low-speed on-chip
oscillator clock
Remarks 1. ×: don’t care

2. (A) to (R) in Table 6-3 correspond to (A) to (R) in Figure 6-24.
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(8) Changing from CPU operation mode (B), (C), (D), (E), (F) and (Q) to HALT mode (G), (J), (M), (O), (P) and (R)
Target state transition: (B) → (G), (C) → (J), (D) → (M), (E) → (O), (F) → (P), (Q) → (R)
Mode After Change Setting

HALT mode Executing HALT instruction
(9) Changing from CPU operation mode (B), (C), and (D) to STOP mode (H), (K), and (N)
Target state transition: (B) → (H), (C) → (K), (D) → (N)
(Setting sequence)
Mode After Change Setting

STOP mode Stopping peripheral Sets the OSTS register Executing STOP instruction
functions that cannot
operate in STOP mode
Settings are unnecessary if the CPU does not enter STOP mode
while it is operating with the high-speed system clock
(10) Changing from STOP mode (H) and (K), to SNOOZE mode (I) and (L)
For details about the setting for switching from the STOP mode to the SNOOZE mode, see 15.8 SNOOZE Mode
Function, 18.5.7 SNOOZE mode function, and 18.6.3 SNOOZE mode function.
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6.6.6 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 6-4. Changing CPU Clock (1/6)
CPU Clock Condition Before Change Processing After Change
Before Change After Change

High-speed on-chip Middle-speed on- Oscillation of middle-speed on-chip oscillator Operating current can be
oscillator clock chip oscillator clock ● MIOEN = 1 reduced by stopping the high-
speed on-chip oscillator
X1 clock Stabilization of X1 oscillation
(HIOSTOP = 1) after checking
● OSCSEL = 1, EXCLK = 0, MSTOP = 0
that the CPU clock has been
● After elapse of oscillation stabilization time
switched to the clock after
External main Enabling input of external clock from the EXCLK pin transition.
system clock ● OSCSEL = 1, EXCLK = 1, MSTOP = 0
PLL clock Oscillation of the high-speed on-chip oscillator with fIH -

at 24 MHz and supply as the operating clock for the
PLL
● FRQSEL3 to FRQSEL0 = 0000B
● HIOSTOP = 0
● PLLCK = 1
Stabilization of PLL oscillation
● DSFRDIV1 = 1, DSFRDIV0 = 1, DSCM = 1, DSCON
=1
● After waiting time for lock-up (40 μs) elapses
XT1 clock Stabilization of XT1 oscillation Operating current can be

● OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 reduced by stopping the high-
● After elapse of oscillation stabilization time speed on-chip oscillator
(HIOSTOP = 1) after checking
External subsystem Enabling input of external clock from the EXCLKS pin
that the CPU clock has been
clock ● OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
switched to the clock after
Low-speed on-chip Selection of low-speed on-chip oscillator
transition.
oscillator clock ● SELLOSC = 1
Middle-speed High-speed on-chip Oscillation of high-speed on-chip oscillator Operating current can be
on-chip oscillator oscillator clock HIOSTOP = 0 reduced by stopping the middle-
clock Stabilization of X1 oscillation speed on-chip oscillator (MIOEN
X1 clock
● OSCSEL = 1, EXCLK = 0, MSTOP = 0 = 0) after checking that the CPU
● After elapse of oscillation stabilization time clock has been switched to the
clock after transition.
PLL clock Setting prohibited (switch to the high-speed on-chip -

oscillator clock first, and then switch to the PLL clock)
External main Enabling input of external clock from the EXCLK pin Operating current can be
system clock OSCSEL = 1, EXCLK = 1, MSTOP = 0 reduced by stopping the middle-
speed on-chip oscillator (MIOEN
XT1 clock Stabilization of XT1 oscillation
= 0) after checking that the CPU
● OSCSELS = 1, EXCLKS = 0, XTSTOP = 0
clock has been switched to the
After elapse of oscillation stabilization time
External subsystem Enabling input of external clock from the EXCLKS pin
clock ● OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
Low-speed on-chip Selection of low-speed on-chip oscillator

oscillator clock ● SELLOSC = 1
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PLL clock High-speed on-chip Oscillation of the high-speed on-chip oscillator clock Operating current can be reduced
oscillator clock and selection of the high-speed on-chip oscillator as by stopping the PLL (DSCON = 0)
the main system clock after checking that the CPU clock
● HIOSTOP = 0, MCS = 0, MCS1 = 0 has been switched to the clock after
transition.
● DSCON = 0
● PLLCK = 0
Middle-speed on- Transition not possible -

chip oscillator clock
X1 clock Transition not possible -
External main Transition not possible -

system clock
XT1 clock Transition not possible -
External subsystem Transition not possible -

clock
Low-speed on-chip Transition not possible -
oscillator clock
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X1 clock High-speed on-chip Enabling oscillation of high-speed on-chip X1 oscillation can be stopped
oscillator clock oscillator (MSTOP = 1) after checking that the
● HIOSTOP = 0 CPU clock has been switched to the
● After elapse of oscillation stabilization time clock after transition.
Middle-speed on-chip Oscillation of middle-speed on-chip oscillator

oscillator clock ● MIOEN = 1
External main system Transition not possible —

clock
PLL clock Setting prohibited (switch to the high-speed

on-chip oscillator clock first, and then switch to
the PLL clock)
XT1 clock Stabilization of XT1 oscillation X1 oscillation can be stopped

● OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 (MSTOP = 1) after checking that the
● After elapse of oscillation stabilization time CPU clock has been switched to the
External subsystem Enabling input of external clock from the
clock EXCLKS pin
Low-speed on-chip Stopped XT1 oscillation
oscillator clock Selection of low-speed on-chip oscillator
● SELLOSC = 1
External main High-speed on-chip Enabling oscillation of high-speed on-chip External main system clock input
system clock oscillator clock oscillator can be disabled (MSTOP = 1) after
● HIOSTOP = 0 checking that the CPU clock has
● After elapse of oscillation stabilization time been switched to the clock after
Middle-speed on-chip Oscillation of middle-speed on-chip oscillator transition.
oscillator clock ● MIOEN = 1
PLL clock Setting prohibited (switch to the high-speed —

the PLL clock)
X1 clock Transition not possible
XT1 clock Stabilization of XT1 oscillation External main system clock input
● OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 can be disabled (MSTOP = 1) after
● After elapse of oscillation stabilization time checking that the CPU clock has
been switched to the clock after
External subsystem Enabling input of external clock from the
transition.
clock EXCLKS pin
Low-speed on-chip Stopped XT1 oscillation

oscillator clock Selection of low-speed on-chip oscillator
● SELLOSC = 1
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XT1 clock High-speed on-chip Oscillation of high-speed on-chip oscillator XT1 oscillation can be stopped
oscillator clock and selection of high-speed on-chip oscillator (XTSTOP = 1) after checking that
clock as main system clock the CPU clock has been switched to
● HIOSTOP = 0, MCS = 0, MCS1 = 0 the clock after transition.

oscillator clock and selection of middle-speed on-chip
oscillator clock as main system clock
● MIOEN = 1, MCS = 0, MCS1 = 1

the PLL clock)
X1 clock Stabilization of X1 oscillation and selection of XT1 oscillation can be stopped

high-speed system clock as main system (XTSTOP = 1) after checking that
clock the CPU clock has been switched to
● OSCSEL = 1, EXCLK = 0, MSTOP = 0 the clock after transition.
● MCS = 1
External main system Enabling input of external clock from the

clock EXCLK pin and selection of high-speed
system clock as main system clock
● MCS = 1
External subsystem Transition not possible —

clock
Low-speed on-chip Transition not possible
oscillator clock
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External subsystem High-speed on-chip Oscillation of high-speed on-chip oscillator External subsystem clock input can
clock oscillator clock and selection of high-speed on-chip oscillator be disabled (XTSTOP = 1) after
clock as main system clock checking that the CPU clock has
● HIOSTOP = 0, MCS = 0, MCS1 = 0 been switched to the clock after
transition.
oscillator clock
● MIOEN = 1, MCS = 0, MCS1 = 1

the PLL clock)
X1 clock Stabilization of X1 oscillation and selection of External subsystem clock input can
high-speed system clock as main system be disabled (XTSTOP = 1) after
clock checking that the CPU clock has
● OSCSEL = 1, EXCLK = 0, MSTOP = 0 been switched to the clock after
● After elapse of oscillation stabilization time transition.
● MCS = 1

● MCS = 1
XT1 clock Transition not possible —

External subsystem Transition not possible
clock
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Low-speed on-chip High-speed on-chip Oscillation of high-speed on-chip oscillator —
oscillator clock oscillator clock and selection of high-speed on-chip oscillator
clock as main system clock
● HIOSTOP = 0, MCS = 0, MCS1 = 0

oscillator clock
● MIOEN = 1, MCS = 0, MCS1 = 1
PLL clock Setting prohibited (switch to the high-speed

the PLL clock)
X1 clock Stabilization of X1 oscillation and selection of

high-speed system clock as main system
clock
● MCS = 1

● MCS = 1
XT1 clock Transition not possible

Low-speed on-chip Transition not possible
oscillator clock
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6.6.7 Time required for switchover of CPU clock and main system clock
By setting bits 0, 4, 6 (MCM0, MCM1, CSS) of the system clock control register (CKC), the CPU clock can be switched
(between the main system clock and the subsystem clock), main system clock can be switched (between the on-chip
oscillator clock and the high-speed system clock), and on-chip oscillator clock can be switched (between the high-speed
on-chip oscillator clock and the middle-speed on-chip oscillator clock).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Tables 6-5 to 6-8).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
the CKC register. Whether the main system clock is operating on the high-speed system clock or main on-chip oscillator
clock or PLL clock can be ascertained using bit 5 (MCS) of the CKC register. Whether the main system clock is operating
on the high-speed on-chip oscillator clock or PLL clock can be ascertained using bit 7 (CKSTR) of the MCKC register.
Whether the main on-chip oscillator clock is operating on the high-speed on-chip oscillator clock or middle-speed on-chip
oscillator clock can be ascertained using bit 1 (MCS1) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 6-5. Maximum Time Required for Main System Clock Switchover
Clock A Switching directions Clock B Remark

fOCO fMX See Table 6-6
fIH fIM See Table 6-7
fMAIN fSUB See Table 6-8
Table 6-6. Maximum Number of Clocks Required for fOCO ↔ fMX
Set Value Before Switchover Set Value After Switchover

MCM0 MCM0
0 1
(fMAIN = fOCO) (fMAIN = fMX)
0 fMX ≥ fOCO 2 clocks
(fMAIN = fOCO)
fMX < fOCO 2 fOCO/fMX clocks
1 fMX ≥ fOCO 2 fMX/fOCO clocks
(fMAIN = fMX)
fMX < fOCO 2 clocks
Table 6-7. Maximum Number of Clocks Required for fIH ↔ fIM

MCM1 MCM1
0 1
(fMAIN = fIH) (fMAIN = fIM)
0 fIM ≥ fIH 2 clocks

(fMAIN = fIH)
fIM < fIH 1 + fIH/fIM clock
1 fIM ≥ fIH 2 fIM/fIH clocks
(fMAIN = fIM)
fIM < fIH 2 clocks
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Table 6-8. Maximum Number of Clocks Required for fMAIN ↔ fSUB

CSS CSS
0 1
(fCLK = fMAIN) (fCLK = fSUB)
0 1 + 2 fMAIN/fSUB clock
(fCLK = fMAIN)
1 3 clock
(fCLK = fSUB)
Remarks 1. The number of clocks listed in Tables 6-6 to 6-8 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Tables 6-6 to 6-8 by rounding up the number after the decimal position.
Example When switching the main system clock from the high-speed on-chip oscillator clock (8 MHz) to
the high- speed system clock (@ oscillation with fIH = 8 MHz, fMX =10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
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6.6.8 Conditions before clock oscillation is stopped

The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Before stopping the clock, check the preconditions for stopping the clock.
Table 6-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Conditions Before Clock Oscillation Is Stopped

Clock Flag Settings of SFR Register
(External Clock Input Disabled)
High-speed on-chip oscillator clock MCS1 = 1, MCS = 1 or CLS = 1 HIOSTOP = 1

(The CPU is operating on a clock other than the high-speed
on-chip oscillator clock or PLL clock.)
Middle-speed on-chip oscillator clock MCS1 = 0, MCS = 1 or CLS = 1 MIOEN = 0
(The CPU is operating on a clock other than the middle-
speed on-chip oscillator clock.)
PLL clock CKSTR = 0 DSCON = 0
(The CPU is operating on a clock other than the PLL clock.)
X1 clock MCS = 0 or CLS = 1 MSTOP = 1
External main system clock (The CPU is operating on a clock other than the high-speed
system clock.)
XT1 clock CLS = 0 XTSTOP = 1
External subsystem clock (The CPU is operating on a clock other than the subsystem XT1SELEN = 0
clock.) XT1SELDIS = 1
Low-speed on-chip oscillator clock CLS = 0 SELLOSC = 0
(The CPU is operating on a clock other than the low-speed
on-chip oscillator clock.)
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6.7 Resonator and Oscillator Constants
For the resonators for which operation has been verified and their oscillator constants, see the target product page on
the Renesas Web site.
Cautions 1. The constants for these oscillator circuits are reference values based on specific environments
set up for evaluation by the manufacturers. For actual applications, request evaluation by the
manufacturer of the oscillator circuit mounted on a board. Furthermore, if you are switching
from a different product to this microcontroller, and whenever you change the board, again
request evaluation by the manufacturer of the oscillator circuit mounted on the new board.
2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the RL78 microcontroller so that the internal operation conditions are within the specifications of
the DC and AC characteristics.
Figure 6-25. Example of External Circuit
(a) X1 oscillation (b) XT1 oscillation
VSS X1 X2 VSS XT2 XT1

Rd Rd
C1 C2 C4 C3
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RL78/I1C CHAPTER 7 HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION FUNCTION
CHAPTER 7 HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION FUNCTION
7.1 High-speed On-chip Oscillator Clock Frequency Correction Function
Using the subsystem clock fSUB (32.768 kHz) as a reference, the frequency of high-speed on-chip oscillator is
measured, and the accuracy of the high-speed on-chip oscillator clock (fIH) frequency is corrected in real time.
Table 7-1 lists the operation specifications of high-speed on-chip oscillator clock frequency correction function and
Figure 7-1 shows the block diagram of high-speed on-chip oscillator clock frequency correction function.
Table 7-1. Operation Specifications of High-speed On-chip Oscillator Clock Frequency Correction Function
Item Description
Reference clock ● fSUB/29 (subsystem clock: 32.768 kHz)

Clock to be corrected ● fIH (high-speed on-chip oscillator clock)
Operating modes ● Continuous operating mode
The high-speed on-chip oscillator clock frequency is corrected continuously.
● Intermittent operating mode
The high-speed on-chip oscillator clock frequency is corrected intermittently
using a timer interrupt, etc.
Clock accuracy correction function ● Correction time: Correction cycle (31.2 ms) × (number of corrections – 0.5)Note
Interrupt ● Output when high-speed on-chip oscillator clock frequency correction is
completed (while interrupt output is enabled).
Note Correction time: Varies depending on the number of corrections.

Correction cycle: Total time of the frequency measurement phase and the frequency correction phase
Number of corrections: The number of repeated correction cycles until the frequency is adjusted to the expected
value range.
Figure 7-1. Block Diagram of High-speed On-chip Oscillator Clock Frequency Correction Function
High-speed on-chip oscillator clock frequency correction function
High-speed on-chip oscillator fIH Count clock Expected

value circuit
HOCODI V2 to HOCODIV0
19-bit High-speed on-chip
counter
Comparison oscillator clock
High- speed on-chip oscillator circuit circuit frequency correctionend
frequency select register (HOCODIV) interrupt
Increment Decrement
Sub OSC fSUB Divider fSUB/29 signal signal
32.768 kHz circuit (Count start trigger)
Correction
Count start value[6:0]
(HOCOFC register:
FCST bit)
CPU bus
Cautions 1. A subsystem clock is necessary to use the high-speed on-chip oscillator clock frequency
correction function. Connect a sub clock oscillator to XT1 and XT2.
2. Use this function as necessary to select a high-speed on-chip oscillator as the operating clock
when using a 24 bit ΔΣ type A/D converter.
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7.2 Register
Table 7-2 lists the register used for the high-speed on-chip oscillator clock frequency correction function.
Table 7-2. Register for High-speed On-chip Oscillator Clock Frequency Correction Function
Item Configuration
Control registers High-speed on-chip oscillator clock frequency correction control register (HOCOFC)
7.2.1 High-speed on-chip oscillator clock frequency correction control register (HOCOFC)
This register is used to control the high-speed on-chip oscillator clock frequency correction function.
The HOCOFC register can be set by an 8-bit memory manipulation instruction.
Figure 7-2. Format of High-Speed On-Chip Oscillator Clock Frequency Correction Control Register (HOCOFC)
Address: F02D8H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
HOCOFC FCMD FCIE 0 0 0 0 0 FCST
FCMDNote 1 High-speed on-chip oscillator clock frequency correction function operating mode
0 Continuous operating mode

1 Intermittent operating mode
FCIE Control of high-speed on-chip oscillator clock frequency correction end interrupt
0 No interrupt is generated when high-speed on-chip oscillator clock frequency correction is completed
1 An interrupt is generated when high-speed on-chip oscillator clock frequency correction is completed
FCSTNote 2 High-speed on-chip oscillator clock frequency correction circuit operation control/status
0 High-speed on-chip oscillator clock frequency correction circuit stops operating/frequency correction
is completed
1 High-speed on-chip oscillator clock frequency correction circuit starts operating/frequency correction
is operating
In continuous operating mode, operation is stopped by writing 0 to this bit by software.
In intermittent operating mode, the FCST bit is cleared by hardware after correction is completed.
Notes 1. Do not rewrite the FCMD bit when the FCST bit is 1.
2. When writing 1 to the FCST bit, confirm that the FCST bit is 0 before writing 1 to FCST. However,
when writing 1 to the FCST bit immediately after intermittent operation is completed (an interrupt is
generated when high-speed on-chip oscillator clock frequency correction is completed), wait for at
least one fIH cycle to elapse after the high-speed on-chip oscillator clock frequency correction end
interrupt is generated because clearing by hardware has priority.
After writing 0 (high-speed on-chip oscillator clock frequency correction circuit stops operating) to
the FCST bit, do not write 1 (high-speed on-chip oscillator clock frequency correction circuit starts
operating) to the FCST bit for two fIH cycles.
Caution Be sure to clear bits 5 to 1 to “0”.
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7.3 Operation
7.3.1 Operation overview

In high-speed on-chip oscillator clock frequency correction, a correction cycle is generated using the subsystem clock
(fSUB) as a reference, the frequency of the high-speed on-chip oscillator is measured, and the accuracy of the high-speed
on-chip oscillator clock frequency is corrected in real time. In clock correction, operations of the frequency measurement
and frequency correction phases are repeated. In the frequency measurement phase, correction is calculated. In the
frequency correction phase, the output of the correction value that reflects the correction calculation result is retained.
Table 7-3 lists the high-speed on-chip oscillator input frequency and correction cycle and Figure 7-3 shows the
operation timing (details) of high-speed on-chip oscillator clock frequency correction.
Table 7-3. High-Speed On-Chip Oscillator Input Frequency and Correction Cycle
fIH (MHz) FRQSEL3, HOCODIV2 to HOCODIV0Note (HOCODIV Register) Correction Cycle (ms)
24 0000 31.2
12 0001 (frequency measurement phase
6 0010 +
3 0011 frequency correction phase)
1.5 0100
16 1001
8 1010
4 1011
2 1100
1 1101
Note Be sure to change the high-speed on-chip oscillator frequency select register (HOCODIV) only when the high-
speed on-chip oscillator clock frequency correction function is not used.
The frequency measurement phase period for the correction cycle is counted using the high-speed on-chip oscillator
clock, and the high-speed on-chip oscillator frequency is corrected depending on the count result and whether it is greater
or smaller than the expected value.
Figure 7-3. Operation Timing (Details) of High-speed On-chip Oscillator Clock Frequency Correction
? Operation timing (details)
fIH = 24 MHz 31.2 ms
Reference 15.6 ms 15.6 ms

clock
(fSUB/29)
41.67 ns
fIH
(24 MHz)
Counting enabled
FCST
(operation Correction cycle
enable bit)
Measurement phase Correction phase
19-bit Count value cleared
count Counting stops
register (count value retained)
Counting starts Counting starts
Correction
value 0000000B 0000001B (previous value 0000000B + 1) 0000010B (previous value 0000001B + 1)
[6:0]
Remark Basic operation is the same in both continuous and intermittent operating modes. Only the difference
between these modes is clearing the FCST bit is controlled by either software or hardware. In addition, the
correction value is not cleared until a reset is applied to the system.
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(1) Continuous operating mode

In continuous operating mode, the high-speed on-chip oscillator clock frequency is corrected continuously. This mode
is selected by setting the FCMD bit in the HOCOFC register to 0.
Operation of high-speed on-chip oscillator clock frequency correction is started by setting the FCST bit in the
HOCOFC register to 1. Similarly, operation of high-speed on-chip oscillator clock frequency correction is stopped by
setting the FCST bit in the HOCOFC register to 0.
When operation of high-speed on-chip oscillator clock frequency correction is started, frequency counting starts at the
rising edge of the reference clock (fSUB/29) and stops at the next rising edge of the reference clock (fSUB/29) in the
frequency measurement phase.
Next, the count value and the expected value are compared, and the correction value is adjusted as follows in the
frequency correction phase:
● When the count value is greater than the expected value: Correction value – 1
● When the count value is smaller than the expected value: Correction value + 1
● When the count value is in the range of the expected value: The correction value is retained (high-speed on-chip
oscillator clock frequency correction is completed)
When the FCIE bit in the HOCOFC register is set to 1, a high-speed on-chip oscillator clock frequency correction end
interrupt is output every time high-speed on-chip oscillator clock frequency correction is completed. In continuous
operating mode, the frequency measurement phase and the frequency correction phase are repeated until the high-
speed on-chip oscillator clock frequency correction function is stopped.
Figure 7-4 shows the continuous operating mode timing.
Figure 7-4. Continuous Operating Mode Timing
? Operation timing
Continuous Operating Mode
Reference
clock
(fSUB/29)
FCMD
(operating Continuous Operating Mode 0
mode bit)
FCST
(operation
enable bit) FCST clearing: Cleared by software.
19-bit
count register Mid-count value
+1 +1 No difference retained
Correction
value 0000000B 0000001B 0000010B 0000010B
[6:0]
High-speed on-chip
oscillator clock
frequency correction Interrupt output:
end interrupt output A pulse of one fIH cycle is output on completion of correction when the FCIE bit is 1.
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(2) Intermittent operating mode

In intermittent operating mode, the high-speed on-chip oscillator clock frequency is corrected intermittently using a
timer interrupt, etc. This mode is selected by setting the FCMD bit in the HOCOFC register to 1.
Operation of high-speed on-chip oscillator clock frequency correction is started by setting the FCST bit in the
HOCOFC register to 1.
When operation of high-speed on-chip oscillator clock frequency correction is started, frequency counting starts at the
rising edge of the reference clock (fSUB/29) and stops at the next rising edge of the reference clock (fSUB/29) in the
frequency measurement phase.
Next, the count value and the expected value are compared, and the correction value is adjusted as follows in the
frequency correction phase:
● When the count value is greater than the expected value: Correction value – 1
● When the count value is smaller than the expected value: Correction value + 1
● When the count value is in the range of the expected value: The correction value is retained and the FCST bit is
cleared (high-speed on-chip oscillator clock frequency correction is completed)
While the FCIE bit in the HOCOFC register is set to 1, a high-speed on-chip oscillator clock frequency correction end
interrupt is output when high-speed on-chip oscillator clock frequency correction is completed. In intermittent
operating mode, the frequency measurement phase and the frequency correction phase are repeated, and high-
speed on-chip oscillator clock frequency correction operation is stopped after high-speed on-chip oscillator clock
frequency correction is completed.
Figure 7-5 shows the intermittent operating mode timing.
Figure 7-5. Intermittent Operating Mode Timing
• Operation timing
Intermittent Operating Mode
Reference
clock
(fSUB/29)
FCMD
(operating
mode bit)
Intermittent Operating Mode 1
FCST
(operation
enable bit) FCST clearing:
Cleared by hardware when there is no change in the correction value .
19-bit
count register Count value retained
Correction +1 +1 No difference
value
[6:0] 0000000B 0000001B “0000010B” 0000010B45
HIOTRM
[5:0]
High-speed on-chip
oscillator clock frequency Interrupt output:
correction end interrupt
output A pulse of one fIH cycle is output on completion of correction when the FCIE bit is 1.
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7.3.2 Operation procedure

The following shows the flow for starting and stopping operation when the high-speed on-chip oscillator clock frequency
correction function is used.
Figure 7-6. Example of Procedure for Setting Operating Mode
Continuous Operating Mode Intermittent Operating Mode

High-speed on-chip oscillator clock High-speed on-chip oscillator clock
Flow for starting operation frequency correction Flow for starting operation frequency correction
Continuous Operating Mode setting Intermittent Operating Mode setting
HOCOFC = 40H High-speed on-chip oscillator clock HOCOFC = C0H High-speed on-chip oscillator clock
frequency correction end interrupt frequency correction end interrupt
enabled enabled
High-speed on-chip oscillator clock High-speed on-chip oscillator clock
HOCOFC = 41H frequency correction operation HOCOFC = C1H frequency correction operation
enabled enabled
No High-speed on-chip oscillator clock No High-speed on-chip oscillator clock

frequency correction end frequency correction end
interrupt generated? interrupt generated?
Yes Yes
High-speed on-chip oscillator clock
HOCOFC = 01H frequency correction end interrupt High-speed on-chip oscillator clock
disabled frequency correction completed
Execute processing
Flow for starting intermittent operation
Timer interrupt, etc

Flow for stopping operation
HOCOFC = C1H frequency correction operation
High-speed on-chip oscillator clock enabled
HOCOFC = 00H frequency correction operation
stopped
No High-speed on-chip oscillator clock

frequency correction end
interrupt generated?
Yes
frequency correction completed
Note The high speed on-chip oscillator clock frequency correction is repeated until the high speed on-chip oscillator
clock frequency correction function is stopped.
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7.4 Usage Notes
7.4.1 SFR access

When writing 1 to FCST to control the FCST bit in intermittent operating mode, confirm that the FCST bit is 0 before
writing 1 to the FCST bit. However, when writing 1 to the FCST bit immediately after intermittent operation is completed,
wait for at least one fIH cycle after a high-speed on-chip oscillator clock frequency correction end interrupt is generated
because clearing by hardware has priority.
7.4.2 Operation during standby state

Be sure to stop operation of high-speed on-chip oscillator clock frequency correction before executing the STOP
instruction.
7.4.3 Changing high-speed on-chip oscillator frequency select register (HOCODIV)

Be sure to change the high-speed on-chip oscillator frequency select register (HOCODIV) only when the high-speed
on-chip oscillator clock frequency correction function is not used.
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RL78/I1C CHAPTER 8 TIMER ARRAY UNIT
CHAPTER 8 TIMER ARRAY UNIT
The timer array unit has eight 16-bit timers.

Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can
be used to create a high-accuracy timer.
TIMER ARRAY UNIT
channel 0 16-bit timers
channel 1
channel 2
channel 6
channel 7
For details about each function, see the table below.
Independent Channel Operation Function Simultaneous Channel Operation Function
● Interval timer (→ see 8.8.1) ● One-shot pulse output(→ see 8.9.1)

● Square wave output (→ see 8.8.1) ● PWM output(→ see 8.9.2)
● External event counter (→ see 8.8.2) ● Multiple PWM output(→ see 8.9.3)
● Input pulse interval measurement (→ see 8.8.3)
● Measurement of high-/low-level width of input
signal (→ see 8.8.4)

● Delay counter (→ see 8.8.5)
It is possible to use the 16-bit timer of channels 1 and 3 as two 8-bit timers (higher and lower). The functions that can
use channels 1 and 3 as 8-bit timers are as follows:
● Interval timer (upper or lower 8-bit timer)/square wave output (lower 8-bit timer only)
● External event counter (lower 8-bit timer only)
● Delay counter (lower 8-bit timer only)
Channel 7 can be used to realize LIN-bus communication operating in combination with UART0 of the serial array unit.
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8.1 Functions of Timer Array Unit
Timer array unit has the following functions.
8.1.1 Independent channel operation function

By operating a channel independently, it can be used for the following purposes without being affected by the operation
mode of other channels.
(1) Interval timer

Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
Compare operation Interrupt signal

Operation clock
Channel n (INTTMmn)
(2) Square wave output

A toggle operation is performed each time INTTMmn interrupt is generated and a square wave with a duty factor of
50% is output from a timer output pin (TOmn).
Operation clock Compare operation Timer output

Channel n (TOmn)
(3) External event counter

Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TImn) has reached a specific value.
Timer input Compare operation Interrupt signal

(TImn) (INTTMmn)
Edge detection Channel n
(4) Input pulse interval measurement

Counting is started by the valid edge of a pulse signal input to a timer input pin (TImn). The count value of the
timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured.
Timer input Capture operation

(TImn)
Edge detection Channel n 00H xxH
Start Capture
(Remark is listed on the next page.)
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(5) Measurement of high-/low-level width of input signal

Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is
captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Timer input Capture operation

(TImn)
Edge detection Channel n 00H xxH
Start Capture
(6) Delay counter

Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated
after any delay period.
Timer input Compare operation Interrupt signal

(TImn) (INTTMmn)
Edge detection Channel n
Start
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
8.1.2 Simultaneous channel operation function

By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels
(timers operating according to the master channel), channels can be used for the following purposes.
(1) One-shot pulse output

Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse
width.
Timer input Compare operation

Interrupt signal (INTTMmn)
(TImn)
Edge detection Channel n (master)
Output Pulse width
timing
Compare operation
Timer output
Channel p (slave) (TOmp) Set Reset
(Master) (Slave)
Start
(Master)
(2) PWM (Pulse Width Modulation) output

Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
Compare operation
Operation clock Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Timer output
Channel p (slave) (TOmp) Duty
Period
(Caution and Remark are listed on the next page.)
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(3) Multiple PWM (Pulse Width Modulation) output

By extending the PWM function and using one master channel and two or more slave channels, up to seven types
of PWM signals that have a specific period and a specified duty factor can be generated.
Compare operation Interrupt signal (INTTMmn)

Operation clock
Channel n (master)
Compare operation
Timer output
Channel p (slave) (TOmp) Duty
Period
Compare operation
Timer output
Channel q (slave) (TOmq) Duty
Period
Caution For details about the rules of simultaneous channel operation function, see 8.4.1 Basic rules of
simultaneous channel operation function.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7),

p, q: Slave channel number (n < p < q ≤ 7)
8.1.3 8-bit timer operation function (channels 1 and 3 only)

The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-
bit timer channels. This function can only be used for channels 1 and 3.
Caution There are several rules for using 8-bit timer operation function.
For details, see 8.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only).
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8.1.4 LIN-bus supporting function (channel 7 only)

Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus
communication format.
(1) Detection of wakeup signal

The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 and the
count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the low-
level width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of break field

The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 after a
wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level
width is measured. If the low-level width is greater than a specific value, it is recognized as a break field.
(3) Measurement of pulse width of sync field

After a break field is detected, the low-level width and high-level width of the signal input to the serial data input pin
(RxD0) of UART0 are measured. From the bit interval of the sync field measured in this way, a baud rate is
calculated.
Remark For details about setting up the operations used to implement the LIN-bus, see 8.3.15 Input switch control
register (ISC) and 8.8.4 Operation as input signal high-/low-level width measurement.
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8.2 Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 8-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer count register mn (TCRmn)
Register Timer data register mn (TDRmn)
Timer input TI00 to TI07, RxD0 pin (for LIN-bus)
Timer output TO00 to TO07 pins, output controller
Control registers <Registers of unit setting block>
● Peripheral enable register 0 (PER0)
● Peripheral reset control register 0 (PRR0)
● Timer clock select register m (TPSm)
● Timer channel enable status register m (TEm)
● Timer channel start register m (TSm)
● Timer channel stop register m (TTm)
● Timer input select register 0 (TIS0)
● Timer output enable register m (TOEm)
● Timer output register m (TOm)
● Timer output level register m (TOLm)
● Timer output mode register m (TOMm)
<Registers of each channel>
● Timer mode register mn (TMRmn)
● Timer status register mn (TSRmn)
● Input switch control register (ISC)
● Noise filter enable register 1 (NFEN1)
● Port mode registers (PM0, PM3, PM4, PM6, PM12)
● Port registers (P0, P3, P4, P6, P12)
Figure 8-1 shows the block diagrams of the timer array unit.
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Figure 8-1. Entire Configuration of Timer Array Unit
Timer clock select register 0 (TPS0)
PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
2 2 4 4
fCLK Prescaler
fCLK/21, fCLK/22,
fCLK/28, fCLK/210, fCLK/24,fCLK/26, fCLK/20 - fCLK/215
fCLK/212,fCLK/214,
Peripheral enable
register 0 Selector Selector
TAU0EN
(PER0)
Selector Selector
CK03
CK02
CK01
CK00
TO00
TI00
INTTM00
Selector
(Timer interrupt)
Channel 0
Event input
from ELC
TO01
INTTM01
TI01 Channel 1 INTTM01H
Selector
Event input
from ELC
TO02
TI02 INTTM02
Channel 2
TO03
INTTM03
TI03
Channel 3 INTTM03H
TO04
TI04 Channel 4 INTTM04
fIL
fSUB
Selector
fIM TO05
Event input INTTM05
from ELC Channel 5
TI05
TO06
Selector
TI06
Channel 6 INTTM06
RTCOUT
output
TO07
TI07
RTCOUT Channel 7 (LIN-bus supported) INTTM07
Selector
output
RxD0
Event input
from ELC
TIS07 TIS06 TIS05 TIS04 TIS03 TIS02 TIS01 TIS00
Timer input select register 0 (TIS0)
Remark fSUB: Subsystem clock frequency

fIM: Medium-speed on-chip oscillator clock frequency
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Figure 8-2. Internal Block Diagram of Channel 0 of Timer Array Unit
clock selection
CK00 Output
Count clock
fTCLK Timer controller
Operating
selection
fMCK controller TO00
CK01
Output latch
Mode (Pxx) PMxx
selection
Interrupt
INTTM00
controller
(Timer interrupt)
TI00
selection
Trigger
Selector
Edge
Event input detection
from ELC Timer counter register 00 (TCR00)
Timer status
register 00 (TSR00)
TIS03 OVF
Timer data register 00 (TDR00)
Overflow 00
Timer input select
register 0 (TIS0)
CKS00 CCS00 0 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001 MD000
Channel 0 Timer mode register 00 (TMR00)
Interrupt signal to slave channel
Figure 8-3. Internal Block Diagram of Channels 2, 4 of Timer Array Unit

Interrupt signal from master channel
CK00
clock selection
Output
Count clock
fTCLK Timer controller

Operating
selection
fMCK controller TO0n

CK01
Output latch
Mode (Pxx) PMxx
selection
Interrupt INTTM0n
Edge controller (Timer interrupt)
TI0n detection
selection
Trigger
Timer counter register 0n (TCR0n)

Timer status
register 0n (TSR0n)
OVF
Timer data register 0n (TDR0n)
Slave/master Overflow 0n
controller
CKS0n CCS0n MAS STS0n2 STS0n1 STS0n0 CIS0n1CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0
TER0n
Channel n Timer mode register 0n (TMR0n)
Interrupt signal to slave channel
Remark n = 2, 4
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CK00
clock selection
Count clock
Output
Operating
CK01 fTCLK Timer controller
selection
CK02
CK03 Output latch
Mode (Pxx) PMxx
selection
Interrupt
INTTM01
controller
(Timer interrupt)
selection
Trigger
TI01
Selector
Edge
detection Timer counter register 01 (TCR01)
Event input
from ELC Timer status
register 01 (TSR01)
OVF
TIS04 Overflow 01
Timer input select 8-bit timer

register 0 (TIS0) controller Interrupt
INTTM01H
Mode controller
(Timer interrupt)
selection
SPLIT
CKS01 CCS01 STS012STS011 STS010 CIS011 CIS010 MD013 MD012 MD011 MD010
01
CK00
clock selection
Count clock
Output
Operating
CK01 fTCLK Timer controller

selection

CK02
CK03 Output latch
Mode (Pxx) PMxx
selection
Interrupt
INTTM03
controller
(Timer interrupt)
selection
Trigger
Edge
TI03 Timer counter register 03 (TCR03)
detection
Timer status
register 03 (TSR03)
OVF
Overflow 03
8-bit timer
controller Interrupt
INTTM03H
Mode controller
(Timer interrupt)
selection
SPLIT
CKS03 CCS03 STS032STS031STS030 CIS031 CIS030 MD033 MD032 MD031 MD030
03
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clock selection
CK00
Count clock
Output
Operating
Timer controller
selection
fMCK fTCLK TO05
controller
CK01
Output latch
Mode (Pxx) PMxx
Timer input select selection
register 0 (TIS0) Interrupt
INTTM05
controller
(Timer interrupt)
selection
TIS02 TIS01 TIS00
Trigger
Edge
fIL Timer status
Selector
fSUB register 05 (TSR05)

fIM
Event input Timer data register 05 (TDR05) OVF
from ELC Overflow 05
TI05
CKS05 CCS05 STS052 STS051 STS050 CIS051 CIS050 MD053 MD052 MD051 MD050

clock selection
CK00
Count clock
Output
fTCLK
Operating
Timer controller
selection

CK01
Output latch
Mode (Pxx) PMxx
selection
Interrupt
INTTM06
controller
(Timer interrupt)
selection
Trigger
Selector
TI06
Edge
RTCOUT
output signal Timer status
register 06 (TSR06)
TIS05 Timer data register 06 (TDR06) OVF

Overflow 06
Timer input select 8bit Timer
register 0 (TIS0) controller
Interrupt INTTM06H
Mode
controller (Timer interrupt)
selection
MAST
CKS06 CCS06 ER06 STS062 STS061 STS060 CIS061 CIS060 MD063 MD062 MD061 MD060
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clock selection
CK00
Count clock
Output
fTCLK
Operating
selection
fMCK Timer controller TO07
controller
CK01
Output latch
Mode (Pxx) PMxx
selection
TI07 Interrupt
INTTM07
controller
RTCOUT (Timer interrupt)
Selector
selection
Trigger
output signal
Event input Edge
from ELC detection Timer counter register 07 (TCR07)
RxD0 Timer status
register 07 (TSR07)
Timer data register 07 (TDR07) OVF

TIS07 TIS06 Overflow 07
Timer input select

register 0 (TIS0)
CKS07 CCS07 STS072 STS071 STS070 CIS071CIS070 MD073 MD072 MD071 MD070
Timer mode register 07 (TMR07)

Channel 7
8.2.1 Timer count register mn (TCRmn)

The TCRmn register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to
MDmn0 bits of timer mode register mn (TMRmn) (see 8.3.4 Timer mode register mn (TMRmn)).
Figure 8-9. Format of Timer Count Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07) After reset: FFFFH R
F0181H (TCR00) F0180H (TCR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRmn
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The count value can be read by reading timer count register mn (TCRmn).
The count value is set to FFFFH in the following cases.
● When the reset signal is generated
● When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared
● When counting of the slave channel has been completed in the PWM output mode
● When counting of the slave channel has been completed in the delay count mode
● When counting of the master/slave channel has been completed in the one-shot pulse output mode
● When counting of the slave channel has been completed in the multiple PWM output mode
The count value is cleared to 0000H in the following cases.
● When the start trigger is input in the capture mode
● When capturing has been completed in the capture mode
Caution The count value is not captured to timer data register mn (TDRmn) even when the TCRmn register is
read.
The TCRmn register read value differs as follows according to operation mode changes and the operating status.
Table 8-2. Timer Count Register mn (TCRmn) Read Value in Various Operation Modes
Operation Mode Count Mode Timer count register mn (TCRmn) Read ValueNote
Value if the Value if the count Value if the operation Value when waiting
operation mode operation was paused mode was changed for a start trigger
was changed after (TTmn = 1) after count operation after one count
releasing reset paused (TTmn = 1)
Interval timer Count down FFFFH Value if stop Undefined –
mode
Capture mode Count up 0000H Value if stop Undefined –
Event counter Count down FFFFH Value if stop Undefined –
mode
One-count mode Count down FFFFH Value if stop Undefined FFFFH
Capture & one- Count up 0000H Value if stop Undefined Capture value of
count mode TDRmn register + 1
Note This indicates the value read from the TCRmn register when channel n has stopped operating as a timer (TEmn = 0)
and has been enabled to operate as a counter (TSmn = 1). The read value is held in the TCRmn register until the
count operation starts.
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8.2.2 Timer data register mn (TDRmn)

This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits
of timer mode register mn (TMRmn).
The value of the TDRmn register can be changed at any time.
This register can be read or written in 16-bit units.
In addition, for the TDRm1 and TDRm3 registers, while in the 8-bit timer mode (when the SPLIT bits of timer mode
registers m1 and m3 (TMRm1, TMRm3) are 1), it is possible to rewrite the data in 8-bit units, with TDRm1H and TDRm3H
used as the higher 8 bits, and TDRm1L and TDRm3L used as the lower 8 bits.
Figure 8-10. Format of Timer Data Register mn (TDRmn) (n = 0, 2, 4 to 7)
Address: FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02), After reset: 0000H R/W
FFF68H, FFF69H (TDR04) to FFF6EH, FFF6FH (TDR07)
FFF19H (TDR00) FFF18H (TDR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDRmn
Figure 8-11. Format of Timer Data Register mn (TDRmn) (n = 1, 3)
Address: FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03) After reset: 0000H R/W
FFF1BH (TDR01H) FFF1AH (TDR01L)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDRmn
(i) When timer data register mn (TDRmn) is used as compare register

Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an
interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten.
Caution The TDRmn register does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
(ii) When timer data register mn (TDRmn) is used as capture register

The count value of timer count register mn (TCRmn) is captured to the TDRmn register when the capture trigger is
input.
A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode register
mn (TMRmn).
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8.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.

● Timer input select register 0 (TIS0)
● Port mode registers (PM0, PM3, PM4, PM6, PM12)
● Port registers (P0, P3, P4, P6, P12)
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8.3.1 Peripheral enable register 0 (PER0)

This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
TAU0EN Control of timer array unit 0 input clock supply

● SFR used by the timer array unit 0 cannot be written. The read value is 00H. However, the SFR is
not initialized. Note
● SFR used by the timer array unit 0 can be read and written.
Note To initialize the timer array unit 0 and the SFR used by the timer array unit 0, use bit 0
(TAU0RES) of PRR0.
Cautions 1. When setting the timer array unit, be sure to set the following registers first while the
TAUmEN bit is set to 1. If TAUmEN = 0, writing to the registers which control the timer
array unit is ignored. (except for the timer input select register 0 (TIS0), input switch
control register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 3, 4, 6,
12 (PM0, PM3, PM4, PM6, PM12), and port registers 0, 3, 4, 6, 12 (P0, P3, P4, P6, P12)).
2. Be sure to clear bits 7 and 1 to “0”.
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8.3.2 Peripheral reset control register 0 (PRR0)

The PRR0 register is used to control resetting of the on-chip peripheral hardware.
Each bit in this register controls resetting and release of the reset state of the corresponding on-chip peripheral hardware.
When the timer array unit is reset, be sure to set bit 0 (TAU0RES) of this register to 1.
The PRR0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 8-13. Format of Peripheral reset control register 0 (PRR0)

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
PRR0 0 IRDARES ADCRES IICA0RES SAU1RES SAU0RES 0 TAU0RES
TAU0RES Control of timer array unit 0 reset
0 Releases the timer array unit 0 from the reset state.

1 The timer array unit 0 is in the reset state.
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8.3.3 Timer clock select register m (TPSm)

The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1,
CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register,
and CKm1 is selected by using bits 7 to 4 of the TPSm register. In addition, only for channels 1 and 3, CKm2 and CKm3
can be also selected. CKm2 is selected by using bits 9 and 8 of the TPSm register, and CKm3 is selected by using bits 13
and 12 of the TPSm register.
Rewriting of the TPSm register during timer operation is possible only in the following cases.
If the PRSm00 to PRSm03 bits can be rewritten (n = 0 to 7):

All channels for which CKm0 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 0) are stopped (TEmn = 0).
If the PRSm10 to PRSm13 bits can be rewritten (n = 0 to 7):
If the PRSm20 and PRSm21 bits can be rewritten (n = 1, 3):
If the PRSm30 and PRSm31 bits can be rewritten (n = 1, 3):
The TPSm register can be set by a 16-bit memory manipulation instruction.

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Figure 8-14. Format of Timer Clock Select register m (TPSm) (1/2)
Address: F01B6H, F01B7H After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS
m31 m30 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00
PRS PRS PRS PRS Selection of operation clock (CKmk)Note ( = 0, 1)

mk3 mk2 mk1 mk0 fCLK = 4 MHz fCLK = 8 MHz fCLK = 12 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 0 0 fCLK 4 MHz 8 MHz 12 MHz 20 MHz 24 MHz

0 0 0 1 fCLK/2 2 MHz 4 MHz 6 MHz 10 MHz 12 MHz
3
0 0 1 1 fCLK/2 500 kHz 1 MHz 1.5 MHz 2.5 MHz 3 MHz
4
0 1 0 0 fCLK/2 250 kHz 500 kHz 750 kHz 1.25 MHz 1.5 MHz
5
0 1 0 1 fCLK/2 125 kHz 250 kHz 375 kHz 625 kHz 750 kHz
6
0 1 1 0 fCLK/2 62.5 kHz 125 kHz 188 kHz 313 kHz 375 kHz
7
0 1 1 1 fCLK/2 31.3 kHz 62.5 kHz 93.8 kHz 156 kHz 188 kHz
1 0 0 0 fCLK/28 15.6 kHz 31.3 kHz 46.9 kHz 78.1 kHz 93.8 kHz
10
11
12
1 1 0 0 fCLK/2 976 Hz 1.95 kHz 2.93 kHz 4.88 kHz 5.86 kHz
13
1 1 0 1 fCLK/2 488 Hz 976 Hz 1.46 kHz 2.44 kHz 2.93 kHz
14
1 1 1 0 fCLK/2 244 Hz 488 Hz 732 Hz 1.22 kHz 1.46 kHz
15
1 1 1 1 fCLK/2 122 Hz 244 Hz 366 Hz 610 Hz 732 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
stop timer array unit (TTm = 00FFH).
Cautions 1. Be sure to clear bits 15, 14, 11, and 10 to “0”.

2. If fCLK (undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H (n =
0, m = 0 to 7), interrupt requests output from timer array units cannot be used.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency

2. The above fCLK/2r is not a signal which is simply divided fCLK by 2r, but a signal which becomes high
level for one period of fCLK from its rising edge (r = 1 to 15). For details, see 8.5.1 Count clock
(fTCLK).
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Figure 8-14. Format of Timer Clock Select register m (TPSm) (2/2)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS
m31 m30 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00
PRS PRS Selection of operation clock (CKm2)Note

m21 m20 fCLK = 4 MHz fCLK = 8 MHz fCLK = 12 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/2 2 MHz 4 MHz 6 MHz 10 MHz 12 MHz
0 1 fCLK/22 1 MHz 2 MHz 3 MHz 5 MHz 6 MHz
1 0 fCLK/24 250 kHz 500 kHz 750 kHz 1.25 MHz 1.5 MHz
6
1 1 fCLK/2 62.5 kHz 125 kHz 188 kHz 313 kHz 375 kHz
PRS PRS Selection of operation clock (CKm3)Note

m31 m30 fCLK = 4 MHz fCLK = 8 MHz fCLK = 12 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/2 8
15.6 kHz 31.3 kHz 46.9 kHz 78.1 kHz 93.8 kHz
0 1 fCLK/2 10
3.91 kHz 7.81 kHz 11.7 kHz 19.5 kHz 23.4 kHz
1 0 fCLK/2 12
976 Hz 1.95 kHz 2.93 kHz 4.88 kHz 5.86 kHz
1 1 fCLK/214 244 Hz 488 Hz 732 Hz 1.22 kHz 1.46 kHz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
stop timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock (fMCK) specified by using the CKSmn0, and
CKSmn1 bits or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK).
Caution Be sure to clear bits 15, 14, 11, 10 to “0”.
By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the
interval times shown in Table 8-3 can be achieved by using the interval timer function.
Table 8-3. Interval Times Available for Operation Clock CKSm2 or CKSm3
Clock Interval timeNote (fCLK = 20 MHz)

16 µs 160 µs 1.6 ms 16 ms
CKm2 fCLK/2 √ – – –
2
fCLK/2 √ – – –
4
fCLK/2 √ √ – –
fCLK/26 √ √ – –
8
CKm3 fCLK/2 – √ √ –
fCLK/210 – √ √ –
fCLK/212 – – √ √
fCLK/214 – – √ √
Note The margin is within 5%.

2. For details of a signal of fCLK/2j selected with the TPSm register, see 8.5.1 Count clock (fTCLK).
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8.3.4 Timer mode register mn (TMRmn)

The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK),
select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start
trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event
counter, one-count, or capture and one-count).
Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and 6
(CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1) (for details,
see 8.8 Independent Channel Operation Function of Timer Array Unit and 8.9 Simultaneous Channel Operation
Function of Timer Array Unit.
The TMRmn register can be set by a 16-bit memory manipulation instruction.
Caution The bits mounted depend on the channels in the bit 11 of TMRmn register.
TMRm2, TMRm4, TMRm6: MASTERmn bit (n = 2, 4, 6)
TMRm1, TMRm3: SPLITmn bit (n = 1, 3)
TMRm0, TMRm5, TMRm7: Fixed to 0
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Figure 8-15. Format of Timer Mode Register mn (TMRmn) (1/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKS CKS 0 CCS MAST STS STS STS CIS CIS 0 0 MD MD MD MD
(n = 2, 4, 6 ) mn1 mn0 mn ERmn mn2 mn1 mn0 mn1 mn0 mn3 mn2 mn1 mn0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 MD MD MD MD
(n = 1, 3) mn1 mn0 mn mn mn2 mn1 mn0 mn1 mn0 mn3 mn2 mn1 mn0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKS CKS 0 CCS 0Note STS STS STS CIS CIS 0 0 MD MD MD MD
(n = 0, 5, 7) mn1 mn0 mn mn2 mn1 mn0 mn1 mn0 mn3 mn2 mn1 mn0
CKS CKS Selection of operation clock (fMCK) of channel n

mn1 mn0
0 0 Operation clock CKm0 set by timer clock select register m (TPSm)

Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3.
CCS Selection of count clock (fTCLK) of channel n

mn
0 Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits

1 Valid edge of input signal input from the TImn pin
In channels 0, 1, 5, 6, and 7, valid edge of input signal selected by TIS0
Count clock (fTCLK) is used for the counter, output controller, and interrupt controller.
Note Bit 11 is fixed at 0 of read only, write is ignored.
Cautions 1. Be sure to clear bits 13, 5, and 4 to “0”.

2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed
(by changing the value of the system clock control register (CKC)), even if the operating clock
specified by using the CKSmn0 and CKSmn1 bits (fMCK) or the valid edge of the signal input
from the TImn pin is selected as the count clock (fTCLK).
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Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Bit 11 of TMRmn (n = 2, 4, 6))

MAS Selection of independent channel operation or
TER simultaneous channel operation (slave or master) of channel n
mn
0 Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.
1 Operates as master channel in simultaneous channel operation function.
Only the channel 2, 4, 6 can be set as a master channel (MASTERmn = 1).
Be sure to use channel 0, 5, 7 are fixed to 0 (Regardless of the bit setting, channel 0 operates as master, because it
is the highest channel).
Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function.
(Bit 11 of TMRmn (n = 1, 3))

SPLI Selection of 8 or 16-bit timer operation of channels 1 and 3
Tmn
0 Operates as 16-bit timer.

(Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.)
1 Operates as 8-bit timer.
STS STS STS Setting of start trigger or capture trigger of channel n

mn2 mn1 mn0
0 0 0 Only software trigger start is valid (other trigger sources are unselected).
0 0 1 Valid edge of the TImn pin input is used as both the start trigger and capture trigger.
0 1 0 Both the edges of the TImn pin input are used as a start trigger and a capture trigger.
1 0 0 Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the simultaneous channel operation function).
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Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIS CIS Selection of TImn pin input valid edge

mn1 mn0
0 0 Falling edge
0 1 Rising edge
1 0 Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
1 1 Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
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Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKS CKS 0 CCS 0Note 1 STS STS STS CIS CIS 0 0 MD MD MD MD
MD MD MD Operation mode of channel n Corresponding function Count operation of

mn3 mn2 mn1 TCR
0 0 0 Interval timer mode Interval timer/Square wave Counting down

output/PWM output (master)
0 1 0 Capture mode Input pulse interval Counting up
measurement
0 1 1 Event counter mode External event counter Counting down
1 0 0 One-count mode Delay counter/One-shot pulse Counting down
output/PWM output (slave)
1 1 0 Capture & one-count mode Measurement of high-/low-level Counting up
width of input signal
The operation of each mode varies depending on MDmn0 bit (see the table below).
Operation mode MD Setting of starting counting and interrupt

(Value set by the MDmn3 to MDmn1 bits mn0
(see table above))
● Interval timer mode 0 Timer interrupt is not generated when counting is started
(0, 0, 0) (timer output does not change, either).
● Capture mode 1 Timer interrupt is generated when counting is started
(0, 1, 0) (timer output also changes).
● Event counter mode 0 Timer interrupt is not generated when counting is started
Note 2
● One-count mode 0 Start trigger is invalid during counting operation.
(1, 0, 0) At that time, interrupt is not generated.
1 Start trigger is valid during counting operationNote 3.
At that time, interrupt is not generated.
● Capture & one-count mode 0 Timer interrupt is not generated when counting is started
Start trigger is invalid during counting operation.
At that time interrupt is not generated.
(Notes and Remark are listed on the next page.)
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Notes 1. Bit 11 is fixed at 0 of read only, write is ignored.

2. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are
not controlled.
3. If the start trigger (TSmn = 1) is issued during operation, the counter is initialized, and recounting is
started (does not occur the interrupt request).
8.3.5 Timer status register mn (TSRmn)

The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode
(MDmn3 to MDmn1 = 110B). See Table 8-4 for the operation of the OVF bit in each operation mode and set/clear
conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Figure 8-16. Format of Timer Status Register mn (TSRmn)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF
OVF Counter overflow status of channel n
0 Overflow does not occur.

1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Table 8-4. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer Operation Mode OVF Bit Set/clear Conditions
● Capture mode clear When no overflow has occurred upon capturing

● Capture & one-count mode set When an overflow has occurred upon capturing
● Interval timer mode clear
–
● Event counter mode set (Use prohibited)
● One-count mode
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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8.3.6 Timer channel enable status register m (TEm)

The TEm register is used to enable or stop the timer operation of each channel.
Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel
stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a
bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
The TEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Figure 8-17. Format of Timer Channel Enable Status register m (TEm)
Address: F01B0H, F01B1H After reset: 0000H R

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEm 0 0 0 0 TEHm 0 TEHm 0 TEm TEm TEm TEm TEm TEm TEm TEm
3 1 7 6 5 4 3 2 1 0
TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit
03 timer mode
0 Operation is stopped.
1 Operation is enabled.
TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit
01 timer mode
TEmn Indication of operation enable/stop status of channel n
This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when channel
1 or 3 is in the 8-bit timer mode.
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8.3.7 Timer channel start register m (TSm)

The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting
operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1),
because they are trigger bits.
The TSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Figure 8-18. Format of Timer Channel Start register m (TSm)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSm 0 0 0 0 TSHm 0 TSHm 0 TSm TSm TSm TSm TSm TSm TSm TSm
3 1 7 6 5 4 3 2 1 0
TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
m3
0 No trigger operation
1 The TEHm3 bit is set to 1 and the count operation becomes enabled.
The TCRm3 register count operation start in the interval timer mode in the count operation enabled state
(see Table 8-5 in 8.5.2 Start timing of counter).
TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
m1
1 The TEHm1 bit is set to 1 and the count operation becomes enabled.
The TCRm1 register count operation start in the interval timer mode in the count operation enabled state
(see Table 8-5 in 8.5.2 Start timing of counter).
TSm Operation enable (start) trigger of channel n

n
1 The TEmn bit is set to 1 and the count operation becomes enabled.
The TCRmn register count operation start in the count operation enabled state varies depending on each
operation mode (see Table 8-5 in 8.5.2 Start timing of counter).
This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TSm1 and TSm3 when
channel 1 or 3 is in the 8-bit timer mode.
Cautions 1. Be sure to clear bits 15 to 12, 10, 8 to “0”

2. When switching from a function that does not use TImn pin input to one that does, the
following wait period is required from when timer mode register mn (TMRmn) is set until the
TSmn (TSHm1, TSHm3) bit is set to 1.
When the TImn pin noise filter is enabled (TNFENnm = 1): Four cycles of the operation clock
(fMCK)
When the TImn pin noise filter is disabled (TNFENnm = 0): Two cycles of the operation clock
(fMCK)
Remarks 1. When the TSm register is read, 0 is always read.

2. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
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8.3.8 Timer channel stop register m (TTm)

The TTm register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared
to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TTHm1,
TTHm3 = 0), because they are trigger bits.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Figure 8-19. Format of Timer Channel Stop register m (TTm)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTm 0 0 0 0 TTHm 0 TTHm 0 TTm TTm TTm TTm TTm TTm TTm TTm
3 1 7 6 5 4 3 2 1 0
TTH Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
m3
1 TEHm3 bit is cleared to 0 and the count operation is stopped.
TTH Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
m1
1 TEHm1 bit is cleared to 0 and the count operation is stopped.
TTm Operation stop trigger of channel n

n
1 TEmn bit clear to 0, to be count operation stop enable status.
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in
the 8-bit timer mode.
Caution Be sure to clear bits 15 to 12, 10, 8 of the TTm register to “0”.
Remarks 1. When the TTm register is read, 0 is always read.

2. m: Unit number (m = 0),n: Channel number (n = 0 to 7)
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8.3.9 Timer input select register 0 (TIS0)

The TIS0 register is used to select the channel 0, 1, 5, 6, 7 timer input.
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Figure 8-20. Format of Timer Input Select register 0 (TIS0)

Symbol 7 6 5 4 3 2 1 0
TIS0 TIS07 TIS06 TIS05 TIS04 TIS03 TIS02 TIS01 TIS00
TIS07 TIS06 Selection of timer input used with channel 7
0 0 Input signal of timer input pin (TI07)

0 1 RTCOUT output signalNote
1 0 RXDo input pin
1 1 Event input signal from ELC
TIS05 Selection of timer input used with channel 6
0 Input signal of timer input pin (TI06)

0 RTCOUT output signalNote

1 Event input signal from ELC

TIS02 TIS01 TIS00 Selection of timer input used with channel 5
0 0 0 Input signal of timer input pin (TI05)

0 0 1 Event input signal from ELC
0 1 1 Medium-speed on-chip oscillator clock (fIM)
1 0 0 Low-speed on-chip oscillator clock (fIL)
1 0 1 Subsystem clock (fSUB)
Note When the RTCOUT output signal is selected, be sure to select it as an input source for both of channel 6
and 7.
Caution High-level width, low-level width of timer input is selected, will require more than 1/fMCK +10 ns.
Therefore, when selecting fSUB to fCLK (CSS bit of CKC register = 1), can not TIS02 bit set to 1.
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8.3.10 Timer output enable register m (TOEm)

The TOEm register is used to enable or disable timer output of each channel.
Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output
register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the
count operation is output from the timer output pin (TOmn).
The TOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TOEmL.
Figure 8-21. Format of Timer Output Enable register m (TOEm)
Address: F01BAH, F01BBH After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOEm 0 0 0 0 0 0 0 0 TOE TOE TOE TOE TOE TOE TOE TOE

m7 m6 m5 m4 m3 m2 m1 m0
TOE Timer output enable/disable of channel n

mn
0 Disable output of timer.

Without reflecting on TOmn bit timer operation, to fixed the output.
Writing to the TOmn bit is enabled and the level set in the TOmn bit is output from the TOmn pin.
1 Enable output of timer.
Reflected in the TOmn bit timer operation, to generate the output waveform.
Writing to the TOmn bit is disabled (writing is ignored).
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8.3.11 Timer output register m (TOm)

The TOm register is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When
timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only by the
timer operation.
To use the P43/TI00/TO00, P41/TI01/TO01, P07/TI02/TO02, P06/TI03/TO03, P05/TI04/TO04, P04/TI05/TO05,
P03/TI06/TO06, or P02/TI07/TO07 pin as a port function pin, set the corresponding TOmn bit to “0”.
The TOm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOm register can be set with an 8-bit memory manipulation instruction with TOmL.
Figure 8-22. Format of Timer Output register m (TOm)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOm 0 0 0 0 0 0 0 0 TOm TOm TOm TOm TOm TOm TOm TOm

7 6 5 4 3 2 1 0
TOm Timer output of channel n

n
0 Timer output value is “0”.

1 Timer output value is “1”.
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8.3.12 Timer output level register m (TOLm)

The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output
signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master
channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Figure 8-23. Format of Timer Output Level register m (TOLm)
Address: F01BCH, F01BDH After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOLm 0 0 0 0 0 0 0 0 TOL TOL TOL TOL TOL TOL TOL 0

m7 m6 m5 m4 m3 m2 m1
TOL Control of timer output level of channel n

mn
0 Positive logic output (active-high)

1 Negative logic output (active-low)
Caution Be sure to clear bits 15 to 8, and 0 to “0”.
Remarks 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when
the timer output signal changes next, instead of immediately after the register value is rewritten.
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8.3.13 Timer output mode register m (TOMm)

The TOMm register is used to control the timer output mode of each channel.
When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be
used to 0.
When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel
to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset while
the timer output is enabled (TOEmn = 1).
The TOMm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL.
Figure 8-24. Format of Timer Output Mode register m (TOMm)
Address: F01BEH, F01BFH After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOMm 0 0 0 0 0 0 0 0 TOM TOM TOM TOM TOM TOM TOM 0

m7 m6 m5 m4 m3 m2 m1
TOM Control of timer output mode of channel n

mn
0 Master channel output mode (to produce toggle output by timer interrupt request signal (INTTMmn))
1 Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of the master
channel, and reset by the timer interrupt request signal (INTTM0p) of the slave channel)
Caution Be sure to clear bits 15 to 8, and 0 to “0”.
Remark m: Unit number (m = 0)

n: Channel number
n = 0 to 7 (n = 0, 2, 4, 6 for master channel)
p: Slave channel number
n<p≤7
(For details of the relation between the master channel and slave channel, see 8.4.1 Basic rules of
simultaneous channel operation function.)
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8.3.14 Input switch control register (ISC)

The ISC register is used to select the input signal for an external interrupt (INTP0).
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 8-25. Format of Input Switch Control Register (ISC)

Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 0 ISC0
ISC0 Switching external interrupt (INTP0) input
0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1 Uses the input signal of the RXD0 pin as an external interrupt (wakeup signal detection).
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8.3.15 Noise filter enable register 1 (NFEN1)

The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is enabled, after synchronization with the operating clock (fMCK) for the target channel, whether the
signal keeps the same value for two clock cycles is detected. When the noise filter is disabled, the input signal is only
synchronized with the operating clock (fMCK) for the target channelNote.
The NFEN1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Note For details, see 8.5.1 (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1), 8.5.2
Start timing of counter, and 8.7 Timer Input (TImn) Control.
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Figure 8-26. Format of Noise Filter Enable Register 1 (NFEN1)

Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
TNFEN07 Enable/disable using noise filter of TI07 pin or RxD0 pin input signalNote
0 Noise filter OFF
1 Noise filter ON
TNFEN06 Enable/disable using noise filter of TI06 pin input signal

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON

0 Noise filter OFF
1 Noise filter ON
Note The applicable pin can be switched by setting the ISC1 bit of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of the TI07 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of the RxD0 pin can be selected.
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8.3.16 Registers controlling port functions of pins to be used for timer I/O
Using port pins for the timer array unit functions requires setting of the registers that control the port functions
multiplexed on the target pins (port mode register (PMxx) and port register (Pxx)). For details, see 4.3.1 Port mode
registers (PMxx) and 4.3.2 Port registers (Pxx).
The port mode register (PMxx) and port register (Pxx) to be set depend on the product. For details, see 4.5 Register
Settings When Using Alternate Function.
When using the ports (such as P43/TI00/TO00) to be shared with the timer output pin for timer output, set the port
mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P43/ TO00 for timer output

Set the PM43 bit of port mode register 4 to 0.
Set the P43 bit of port register 4 to 0.
When using the ports (such as P43/TI00) to be shared with the timer input pin for timer input, set the port mode register
(PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may be 0 or 1.
Example: When using P43/TO00 for timer input

Set the P43 bit of port register 4 to 0 or 1.
Remarks 1. In case of 80-pin product, in order to use a port that is shared with segment output for timer I/O function,
be sure to set the corresponding bits of LCD port function register 4 (PFSEG4) bits PFSEG32 to
PFSEG37 to “0”.
In case of 64-pin product, in order to use a port that is shared with segment output for timer I/O function,
be sure to set the corresponding bits of LCD port function register 3 (PFSEG3) bits PFSEG25 to
PFSEG24 to “0”.
2. When using the P125/(TI05)/(TO05)/VL3 pin for timer I/O, be sure to clear the ISCVL3 bit of the LCD Input
switch control register (ISCLCD) to “0”.
3. When using the P126/(TI04)/(TO04)/CAPL and P127/(TI03)/(TO03)/CAPH pins for timer I/O, be sure to
clear the ISCCAP bit of the LCD Input switch control register (ISCLCD) to “1”.
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8.4 Basic Rules of Timer Array Unit
8.4.1 Basic rules of simultaneous channel operation function

When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can be set
as a slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of
master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave channel
that operates in combination with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as
a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels
with lower channel numbers.
(9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher
master channel as a source clock.
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels
in combination must be set at the same time.
(11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating
simultaneously can be set. It cannot be applied to TSmn bits of slave channels alone.
(12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in
combination must be set at the same time.
(13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of
master channels and slave channels have to be synchronized.
(14) Timer mode register m0 (TMRm0) has no master bit (it is fixed as “0”). However, as channel 0 is the highest
channel, it can be used as a master channel during simultaneous operation.
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave
channels forming one simultaneous channel operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous
channel operation function in 8.4.1 Basic rules of simultaneous channel operation function do not apply to the
channel groups.
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Example
TAU0
CK00 Channel group 1

Channel 0: Master (Simultaneous channel operation
function)
Channel 1: Slave
Channel group 2
Channel 2: Slave (Simultaneous channel operation
function)
Channel 3: independent channel

operation function
* The operating clock of channel group 1 may

CK01 be different from that of channel group 2.
Channel 4: Master
CK00 Channel 5: independent * A channel that operates independent

channel operation channel operation function may be between
function channel group 1 and channel group 2.
Channel 6: Slave * A channel that operates independent

channel operation function may be between
a master and a slave of channel group 2.
Channel 7: independent channel Furthermore, the operating clock may be set
operation function separately.
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8.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-
bit timer channels.
This function can only be used for channels 1 and 3, and there are several rules for using it.
The basic rules for this function are as follows:
(1) The 8-bit timer operation function applies only to channels 1 and 3.
(2) When using 8-bit timers, set the SPLIT bit of timer mode register mn (TMRmn) to 1.
(3) The higher 8 bits can be operated as the interval timer function.
(4) At the start of operation, the higher 8 bits output INTTMm1H/INTTMm3H (an interrupt) (which is the same
operation performed when MDmn0 is set to 1).
(5) The operation clock of the higher 8 bits is selected according to the CKSmn1 and CKSmn0 bits of the lower-bit
TMRmn register.
(6) For the higher 8 bits, the TSHm1/TSHm3 bit is manipulated to start channel operation and the TTHm1/TTHm3 bit
is manipulated to stop channel operation. The channel status can be checked using the TEHm1/TEHm3 bit.
(7) The lower 8 bits operate according to the TMRmn register settings. The following three functions support
operation of the lower 8 bits:
● Interval timer function
● External event counter function
● Delay count function
(8) For the lower 8 bits, the TSm1/TSm3 bit is manipulated to start channel operation and the TTm1/TTm3 bit is
manipulated to stop channel operation. The channel status can be checked using the TEm1/TEm3 bit.
(9) During 16-bit operation, manipulating the TSHm1, TSHm3, TTHm1, and TTHm3 bits is invalid. The TSm1, TSm3,
TTm1, and TTm3 bits are manipulated to operate channels 1 and 3. The TEHm3 and TEHm1 bits are not changed.
(10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM)
cannot be used.
Remark m: Unit number (m = 0), n: Channel number (n = 1, 3)
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8.5 Operation of Counter
8.5.1 Count clock (fTCLK)

The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register
mn (TMRmn).
● Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits

● Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK)
are shown below.
(1) When operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
The count clock (fTCLK) is between fCLK to fCLK /215 by setting of timer clock select register m (TPSm). When a
divided fCLK is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for
one period of fCLK from its rising edge. When a fCLK is selected, fixed to high level
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at rising edge of the count clock”, as a
matter of convenience.
Figure 8-27. Timing of fCLK and count clock (fTCLK) (When CCSmn = 0)
fCLK
fCLK/2
fCLK/4
fTCLK
( = fMCK fCLK/8
= CKmn)
fCLK/16
Remarks 1. : Rising edge of the count clock

: Synchronization, increment/decrement of counter
2. fCLK: CPU/peripheral hardware clock
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(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1)
The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes
next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TImn pin
(when a noise filter is used, the delay becomes 3 to 4 clock).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at valid edge of input signal via the TImn
pin”, as a matter of convenience.
Figure 8-28. Timing of fCLK and count clock (fTCLK) (When CCSmn = 1, noise filter unused)
fMCK
TSmn (write)
<1>
TEmn
TImn input
<2>
Sampling wave
Edge detection <3> Edge detection
Rising edge
detection signal (fTCLK)
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input
signal via the TImn pin.
<2> The rise of input signal via the TImn pin is sampled by fMCK.
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remarks 1. : Rising edge of the count clock

: Synchronization, increment/decrement of counter
2. fCLK: CPU/peripheral hardware clock
fMCK: Operation clock of channel n
3. The waveform of the TImn pin input signal, which is used for input pulse interval
measurement, input signal of high/low width measurement, the delay counter, and one-
shot pulse output, is the same as that shown in above figure.
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8.5.2 Start timing of counter

Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register
m (TSm).
Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 8-5.
Table 8-5. Operations from Count Operation Enabled State to Timer Count Register mn (TCRmn) Count Start
Timer Operation Mode Operation When TSmn = 1 Is Set
● Interval timer mode No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
8.5.3 (1) Operation of interval timer mode).
● Event counter mode Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn
register.
If detect edge of TImn input. The subsequent count clock performs count down
operation (see 8.5.3 (2) Operation of event counter mode).
● Capture mode No operation is carried out from start trigger detection (TSmn = 1) until count
clock generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 8.5.3 (3) Operation of capture
mode (input pulse interval measurement)).
● One-count mode The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
8.5.3 (4) Operation of one-count mode).
● Capture & one-count mode The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 8.5.3 (5) Operation of capture &
one-count mode (high-level width measurement)).
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8.5.3 Operation of counter

The counter operation in each mode is explained.
(1) Operation of interval timer mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the
initial value until count clock generation.
<2> A start trigger is generated at the first count clock after operation is enabled.
<3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.
<4> By the first count clock after the operation enable, the value of timer data register mn (TDRmn) is loaded to the
TCRmn register and counting starts in the interval timer mode.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of
timer data register mn (TDRmn) is loaded to the TCRmn register and counting keeps on.
Figure 8-29. Operation Timing (In Interval Timer Mode)
fMCK
(fTCLK)
TSmn (write)
<1>
TEmn
<2>
Start trigger
detection signal
TCRmn Initial m m–1 0001 0000 m

value
TDRmn <3> <4> m
<5>
INTTMmn
When MDmn0 = 1 setting
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
Remark fMCK, the start trigger detection signal, and INTTMmn become active between one clock in
synchronization with fCLK.
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(2) Operation of event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the
TImn input .
Figure 8-30. Operation Timing (In Event Counter Mode)
fMCK
TSmn (write)
<1>
TEmn
<2>
TImn input
Edge detection Edge detection

Count clock
Start trigger <4>

detection signal
<1> <3>
TCRmn Initial m m–1 m–2

value
<3>
TDRmn m
Remark The timing is shown in above figure indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TImn input. The error per one period occurs be the asynchronous between the period of the
TImn input and that of the count clock (fMCK).
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(3) Operation of capture mode (input pulse interval measurement)

<2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded
to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1, INTTMmn is
generated by the start trigger.)
<4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated. However, this capture value is nomeaning. The TCRmn
register keeps on counting from 0000H.
<5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer
data register mn (TDRmn) and INTTMmn is generated.
Figure 8-31. Operation Timing (In Capture Mode: Input Pulse Interval Measurement)
fMCK
(fTCLK)
TSmn (write)
<1>
TEmn
Note
<3>
TImn input

Rising edge
Start trigger <4> <5>

detection signal
<2> <3>
TCRmn Initial value 0000 0001 0000 m–1 m 0000
TDRmn 0001Note m
INTTMmn
When MDmn0 = 1
Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is
detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse
interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval)
and so the user can ignore it.
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
cycle of TImn input. The error per one cycle occurs because the TImn input is not synchronous with the
count clock (fMCK).
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(4) Operation of one-count mode

<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and
count starts.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of
the TCRmn register becomes FFFFH and counting stops
.
Figure 8-32. Operation Timing (In One-count Mode)
fMCK
(fTCLK)
TSmn (write)
<1>
TEmn
TImn input <3>
Edge detection
Rising edge
<4>
Start trigger
detection signal
<2> <5>
TCRmn Initial value m 1 0 FFFF
INTTMmn
Start trigger input wait status
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(5) Operation of capture & one-count mode (high-level width measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
<5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated.
Figure 8-33. Operation Timing (In Capture & One-count Mode: High-level Width Measurement)
fMCK
(fTCLK)
TSmn (write)
<1>
TEmn
TImn input <3>

Rising edge
Falling edge <4> <5>
Start trigger
detection signal
<2>
TCRmn Initial value 0000 m–1 m m+1
TDRmn 0000 m
INTTMmn
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8.6 Channel Output (TOmn Pin) Control
8.6.1 TOmn pin output circuit configuration
Figure 8-34. Output Circuit Configuration
<5>
TOmn register
Interrupt signal of the master channel
(INTTMmn)
Controller
Set
Interrupt signal of the slave channel TOmn pin

(INTTMmp) Reset/toggle
<1>
<2> <3>
<4>
TOLmn
TOMmn Internal bus
TOEmn TOmn write signal
The following describes the TOmn pin output circuit.
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is
ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register m (TOm).
<2> When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and
INTTM0p (slave channel timer interrupt) are transmitted to the TOm register.
At this time, the TOLm register becomes valid and the signals are controlled as follows:
When TOLmn = 0: Positive logic output (INTTMmn → set, INTTM0p → reset)

When TOLmn = 1: Negative logic output (INTTMmn → reset, INTTM0p → set)
When INTTMmn and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal)
takes priority, and INTTMmn (set signal) is masked.
<3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTM0p (slave
channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal)
becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set timer operation is stopped (TOEmn = 0) and to
write a value to the TOm register.
<4> While timer output is disabled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal)
becomes valid. When timer output is disabled (TOEmn = 0), neither INTTMmn (master channel timer
interrupt) nor INTTM0p (slave channel timer interrupt) is transmitted to the TOm register.
<5> The TOm register can always be read, and the TOmn pin output level can be checked.
Caution Since outputs are N-ch open-drain outputs, an external pull-up resistor is required to use P60,
P61, and P62 as channel output.
Remark m: Unit number (m = 0)

n: Channel number
n<p≤7
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8.6.2 TOmn pin output setting

The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer
operation start.
Figure 8-35. Status Transition from Timer Output Setting to Operation Start
TCRmn Undefined value (FFFFH after reset)

(Counter)
Hi-Z
Timer alternate-function pin
Timer output signal
TOmn
TOEmn
Write operation enabled period to TOmn Write operation disabled period to TOmn
<1> Set TOMmn <2> Set TOmn <3> Set TOEmn <4> Set the port to <5> Timer operation start
Set TOLmn output mode
<1> The operation mode of timer output is set.
● TOMmn bit (0: Master channel output mode, 1: Slave channel output mode)
● TOLmn bit (0: Positive logic output, 1: Negative logic output)
<2> The timer output signal is set to the initial status by setting timer output register m (TOm).
<3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is disabled).
<4> The port I/O setting is set to output (see 8.3.16 Registers controlling port functions of pins to be used
for timer I/O).
<5> The timer operation is enabled (TSmn = 1).
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8.6.3 Cautions on channel output operation
(1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation
Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are
independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output
enable register m (TOEm), and timer output level register m (TOLm) does not affect the timer operation, the values can
be changed during timer operation. To output an expected waveform from the TOmn pin by timer operation, however,
set the TOm, TOEm, TOLm, and TOMm registers to the values stated in the register setting example of each operation
shown by 8.8 and 8.9.
When the values set to the TOEm, and TOMm registers (but not the TOm register) are changed close to the occurrence
of the timer interrupt (INTTMmn) of each channel, the waveform output to the TOmn pin might differ, depending on
whether the values are changed immediately before or immediately after the timer interrupt (INTTMmn) occurs.
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(2) Default level of TOmn pin and output level after timer operation start
The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is
disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port
output is enabled, is shown below.
(a) When operation starts with master channel output mode (TOMmn = 0) setting
The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0).
When the timer operation starts after setting the default level, the toggle signal is generated and the output
level of the TOmn pin is reversed.
Figure 8-36. TOmn Pin Output Status at Toggle Output (TOMmn = 0)
TOEmn
Default
Hi-Z TOmn bit = 0
status
(Default status : Low)
TOmn bit = 0
(Active high)
TOmn bit = 1
(Default status : High)
TOmn
(output) TOmn bit = 0
TOmn bit = 1
TOmn bit = 1 (Active low)
Port output is enabled
Bold : Active level
Toggle Toggle Toggle Toggle Toggle
Remarks 1. Toggle: Reverse TOmn pin output status

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(b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output))
When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m
(TOLm) setting.
Figure 8-37. TOmp Pin Output Status at PWM Output (TOMmp = 1)
TOEmp
Active Active Active
Hi -Z Default TOmp bit = 0
status
TOmp bit = 0
(Active high)
TOmp bit = 1
TOmp
(output)
TOmp bit = 0
TOmp bit = 1
(Active low)
TOmp bit = 1
Port output is enabled
Reset Reset
Set Set Set
Remarks 1. Set: The output signal of the TOmp pin changes from inactive level to active level.
Reset: The output signal of the TOmp pin changes from active level to inactive level.
2. m: Unit number (m = 0), p: Channel number (p = 1 to 7)
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(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When timer output level register m (TOLm) setting has been changed during timer operation
When the TOLm register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output
level of the TOmn pin.
The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is
operating (TEmn = 1) is shown below.
Figure 8-38. Operation When TOLm Register Has Been Changed Contents During Timer Operation
TOLm
Active Active Active Active

TOmn
(output)
Reset Reset Reset Reset

Set Set Set Set
Remarks 1. Set: The output signal of the TOmn pin changes from inactive level to active level.
Reset: The output signal of the TOmn pin changes from active level to inactive level.
(b) Set/reset timing

To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 8-39 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0

Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0
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Figure 8-39. Set/Reset Timing Operating Statuses
(1) Basic operation timing
fTCLK
INTTMmn
Master Internal reset

channel signal
TOmn pin/
TOmn Toggle Toggle
Internal set
signal
1 clock delay
INTTMmp
Slave
channel
Internal reset
signal
TOmp pin/
TOmp
Set Reset Set
(2) Operation timing when 0% duty
fTCLK
INTTMmn
Master Internal reset

channel signal
TOmn pin/
TOmn
Toggle Toggle
Internal set
signal
1 clock delay
TCRmp 0000 0001 0000 0001
INTTMmp
Slave
channel Internal reset Set
signal
Reset Set Reset

TOmp pin/
TOmp
Reset has priority. Reset has priority.
Remarks 1. Internal reset signal: TOmn pin reset/toggle signal

Internal set signal: TOmn pin set signal
2. m: Unit number (m = 0)
n: Channel number
n<p≤7
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8.6.4 Collective manipulation of TOmn bit

In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as
timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond
to the relevant bits of the channel used to perform output (TOmn).
Figure 8-40 Example of TO0n Bit Collective Manipulation
Before writing
TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00

0 0 1 0 0 0 1 0
TOE0 0 0 0 0 0 0 0 0 TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00

0 0 1 0 1 1 1 1
Data to be written
0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
After writing
O O × O × × × ×
TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
1 1 1 0 0 0 1 0
Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored.
TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is
done to the TOmn bit, it is ignored and the output change by timer operation is normally done.
Figure 8-41. TO0n Pin Statuses by Collective Manipulation of TO0n Bit
Two or more TO0n output can

be changed simultaneously
TO07
Output does not change
TO06 when value does not
change
TO05
TO04
TO03 Writing to the TO0n bit is

ignored when TOE0n
TO02 =1
TO01
TO00
Before writing Writing to the TO0n bit
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8.6.5 Timer Interrupt and TOmn pin output at operation start

In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to
generate a timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figure 8-42 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 8-42. Operation Examples of Timer Interrupt at Count Operation Start and TOmn Output
(a) When MDmn0 is set to 1
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
(b) When MDmn0 is set to 0
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle
operation.
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
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8.7 Timer Input (TImn) Control
8.7.1 TImn input circuit configuration

A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.
Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input circuit.
Figure 8-43. Input Circuit Configuration
CCSmn
fMCK
Count clock
selection
fTCLK
Timer
controller
TImn pin Noise Edge
filter detection
selection
Trigger
TNFENmn CISmn1, STSmn2 to
CISmn0 STSmn0
8.7.2 Noise filter

When the noise filter is disabled, the input signal is only synchronized with the operating clock (fMCK) for channel n.
When the noise filter is enabled, after synchronization with the operating clock (fMCK) for channel n, whether the signal
keeps the same value for two clock cycles is detected. The following shows differences in waveforms output from the
noise filter between when the noise filter is enabled and disabled.
Figure 8-44. Sampling Waveforms through TImn Input Pin with Noise Filter Enabled and Disabled
TImn pin
Noise filter disabled
Noise filter enabled
Operating clock (f MCK)
Caution The TImn pin input waveform is shown to explain the noise filter ON/OFF operation. For actual
operation, refer to the high-level width/low-level width in 41.4 AC Characteristics.
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8.7.3 Cautions on channel input operation

When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings
are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of
the channel corresponding to the timer input pin.
(1) Noise filter is disabled

When bits 12 (CCSmn), 9 (STSmn1), and 8 (STSmn0) in the timer mode register mn (TMRmn) are 0 and then one
of them is set to 1, wait for at least two cycles of the operating clock (fMCK), and then set the operation enable
trigger bit in the timer channel start register (TSm).
(2) Noise filter is enabled

When bits 12 (CCSmn), 9 (STSmn1), and 8 (STSmn0) in the timer mode register mn (TMRmn) are all 0 and then
one of them is set to 1, wait for at least four cycles of the operating clock (fMCK), and then set the operation enable
trigger bit in the timer channel start register (TSm).
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8.8 Independent Channel Operation Function of Timer Array Unit
8.8.1 Operation as interval timer/square wave output
(1) Interval timer

The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
(2) Operation as square wave output

TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions.
● Period of square wave output from TOmn = Period of count clock × (Set value of TDRmn + 1) × 2
● Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) × 2}
Timer count register mn (TCRmn) operates as a down counter in the interval timer mode.
The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel
start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of
timer mode register mn (TMRmn) is 0 at this time, INTTMmn is not output and TOmn is not toggled. If the MDmn0
bit of the TMRmn register is 1, INTTMmn is output and TOmn is toggled.
After that, the TCRmn register count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOmn is toggled at the next count clock. At the same time, the
TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the
next period.
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Figure 8-45. Block Diagram of Operation as Interval Timer/Square Wave Output
Clock selection
CKm1
Operation clockNote Timer counter
CKm0 Output TOmn pin
register mn (TCRmn) controller
Trigger selection
Timer data Interrupt
TSmn Interrupt signal
register mn(TDRmn) controller
(INTTMmn)
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 8-46. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TSmn
TEmn
TCRmn
0000H
TDRmn a b
TOmn
INTTMmn
a+1 a+1 a+1 b+1 b+1 b+1
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7)

2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
TOmn: TOmn pin output signal
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Figure 8-47. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2)
(a) Timer mode register mn (TMRmn)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKSmn1 CKSmn0 CCSmn M/S Note
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0
1/0 1/0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 1/0
Operation mode of channel n

000B: Interval timer
Setting of operation when counting is started

0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of TImn pin input edge

00B: Sets 00B because these are not used.
Start trigger selection

000B: Selects only software start.
Setting of MASTERmn bit (channels 2, 4, 6)

0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
1: 8-bit timer mode
Count clock selection

0: Selects operation clock (fMCK).
Operation clock (fMCK) selection

00B: Selects CKm0 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)

Bit n
TOm TOmn 0: Outputs 0 from TOmn.
1/0 1: Outputs 1 from TOmn.
(c) Timer output enable register m (TOEm)

Bit n
TOEm TOEmn 0: Stops the TOmn output operation by counting operation.
1/0 1: Enables the TOmn output operation by counting operation.
Note TMRm2, TMRm4, TMRm6: MASTERmn bit

TMRm1, TMRm3: SPLITmn bit
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Figure 8-47. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2)
(d) Timer output level register m (TOLm)

Bit n
TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode)
0
(e) Timer output mode register m (TOMm)

Bit n
TOMm TOMmn 0: Sets master channel output mode.
0
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Figure 8-48. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation Hardware Status

TAU Power-off status
default (Clock supply is stopped and writing to each register is
setting disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets timer mode register mn (TMRmn) (determines Channel stops operating.
default operation mode of channel). (Clock is supplied and some power is consumed.)
setting Sets interval (period) value to timer data register mn
(TDRmn).
To use the TOmn output The TOmn pin goes into Hi-Z output state.
Clears the TOMmn bit of timer output mode register m
(TOMm) to 0 (master channel output mode).
Clears the TOLmn bit to 0.
Sets the TOmn bit and determines default level of the
TOmn output. The TOmn default setting level is output when the port mode
register is in the output mode and the port register is 0.
Sets the TOEmn bit to 1 and enables operation of TOmn. TOmn does not change because channel stops operating.
Clears the port register and port mode register to 0. The TOmn pin outputs the TOmn set level.
Operation (Sets the TOEmn bit to 1 only if using TOmn output and
start resuming operation.).
Sets the TSmn (TSHm1, TSHm3) bit to 1. TEmn (TEHm1, TEHm3) = 1, and count operation starts.
The TSmn (TSHm1, TSHm3) bit automatically returns Value of the TDRmn register is loaded to timer count
to 0 because it is a trigger bit. register mn (TCRmn). INTTMmn is generated and TOmn
performs toggle operation if the MDmn0 bit of the TMRmn
Operation is resumed.
register is 1.
During Set value of the TDRmn register can be changed. Counter (TCRmn) counts down. When count value reaches
operation The TCRmn register can always be read. 0000H, the value of the TDRmn register is loaded to the
The TSRmn register is not used. TCRmn register again and the count operation is continued.
Set values of the TOm and TOEm registers can be By detecting TCRmn = 0000H, INTTMmn is generated and
changed. TOmn performs toggle operation.
Set values of the TMRmn register, TOMmn, and TOLmn After that, the above operation is repeated.
bits cannot be changed.
Operation The TTmn (TTHm1, TTHm3) bit is set to 1. TEmn (TEHm1, TEHm3), and count operation stops.
stop The TTmn (TTHm1, TTHm3) bit automatically returns The TCRmn register holds count value and stops.
to 0 because it is a trigger bit. The TOmn output is not initialized but holds current status.
The TOEmn bit is cleared to 0 and value is set to the TOmn bit. The TOmn pin outputs the TOmn bit set level.
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Figure 8-48. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)

TAU To hold the TOmn pin output level
Clears the TOmn bit to 0 after the value to
stop
be held is set to the port register. The TOmn pin output level is held by port function.
When holding the TOmn pin output level is not necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOmn bit is cleared to 0 and the TOmn pin is set to
port mode.)
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8.8.2 Operation as external event counter

The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDRmn + 1
Timer count register mn (TCRmn) operates as a down counter in the event counter mode.
The TCRmn register loads the value of timer data register mn (TDRmn) by setting any channel start trigger bit (TSmn,
TSHm1, TSHm3) of timer channel start register m (TSm) to 1.
The TCRmn register counts down each time the valid input edge of the TImn pin has been detected. When TCRmn =
0000H, the TCRmn register loads the value of the TDRmn register again, and outputs INTTMmn.
After that, the above operation is repeated.
An irregular waveform that depends on external events is output from the TOmn pin. Stop the output by setting the
TOEmn bit of timer output enable register m (TOEm) to 0.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid during the next
count period.
Figure 8-49. Block Diagram of Operation as External Event Counter
TNFENxx
Clock selection
Noise Edge
TImn pin Timer counter
filter detection
register mn (TCRmn)
Trigger selection

TSmn Interrupt signal
register mn (TDRmn) controller
(INTTMmn)
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Figure 8-50. Example of Basic Timing of Operation as External Event Counter
TSmn
TEmn
TImn
3 3
2 2 2 2
TCRmn 1 1 1 1
0000H 0 0 0
TDRmn 0003H 0002H
INTTMmn
4 events 4 events 3 events

TImn: TImn pin input signal
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Figure 8-51. Example of Set Contents of Registers in External Event Counter Mode (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/0 1/0 0 1 0/1 0 0 0 1/0 1/0 0 0 0 1 1 0

011B: Event count mode

0: Neither generates INTTMmn nor inverts
timer output when counting is started.

00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited


0: 16-bit timer mode
1: 8-bit timer mode

1: Selects the TImn pin input valid edge.


Bit n
0

Bit n
0

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Figure 8-51. Example of Set Contents of Registers in External Event Counter Mode (2/2)

Bit n
TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0

Bit n
0
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Figure 8-52. Operation Procedure When External Event Counter Function Is Used

setting disabled.)
enabled.)
Channel Sets the corresponding bit of the noise filter enable Channel stops operating.
default register 1 (NFEN1) to 0 (off) or 1 (on). (Clock is supplied and some power is consumed.)
setting Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets number of counts to timer data register mn
(TDRmn).
Clears the TOEmn bit of timer output enable register m
(TOEm) to 0.
Operation Sets the TSmn bit to 1. TEmn = 1, and count operation starts.
start The TSmn bit automatically returns to 0 because it is a Value of the TDRmn register is loaded to timer count
trigger bit. register mn (TCRmn) and detection of the TImn pin
input edge is awaited.

During Set value of the TDRmn register can be changed. Counter (TCRmn) counts down each time input edge of
operation The TCRmn register can always be read. the TImn pin has been detected. When count value
The TSRmn register is not used. reaches 0000H, the value of the TDRmn register is loaded
Set values of the TMRmn register, TOMmn, TOLmn, to the TCRmn register again, and the count operation is
TOmn, and TOEmn bits cannot be changed. continued. By detecting TCRmn = 0000H, the INTTMmn
output is generated.
Operation The TTmn bit is set to 1. TEmn = 0, and count operation stops.
stop The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops.
trigger bit.
TAU The TAUmEN bit of the PER0 register is cleared to 0. Power-off status
stop All circuits are initialized and SFR of each channel is
also initialized.
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8.8.3 Operation as input pulse interval measurement

The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured.
In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn
bit is set to 1.
The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture mode.

When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to
timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter
does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
capture trigger.
Figure 8-53. Block Diagram of Operation as Input Pulse Interval Measurement

Clock selection
CKm1
Operation clock Note Timer counter
CKm0 register mn (TCRmn)
TNFENxx
Trigger selection
Noise Edge
TImn pin
filter detection Timer data Interrupt
register mn (TDRmn) Interrupt signal
controller
TSmn (INTTMmn)
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
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Figure 8-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0)
TSmn
TEmn
TImn
FFFFH
b c d
TCRmn a
0000H
TDRmn 0000H a b c d
INTTMmn
OVF

OVF: Bit 0 of timer status register mn (TSRmn)
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Figure 8-55. Example of Set Contents of Registers to Measure Input Pulse Interval

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKSmn1 CKSmn0 CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0
1/0 0 0 0 0 0 0 1 1/0 1/0 0 0 0 1 0 1/0

010B: Capture mode

0: Does not generate INTTMmn when
counting is started.
1: Generates INTTMmn when counting is
started.

Capture trigger selection

001B: Selects the TImn pin input valid edge.

0: Independent channel operation
0: 16-bit timer mode.



Bit n
0

Bit n
TOEm TOEmn 0: Stops TOmn output operation by counting operation.
0

Bit n
0

Bit n
0

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Figure 8-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used

setting disabled.)
enabled.)
Operation Sets TSmn bit to 1. TEmn = 1, and count operation starts.
start The TSmn bit automatically returns to 0 because it is a Timer count register mn (TCRmn) is cleared to 0000H.
trigger bit. When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
During Set values of only the CISmn1 and CISmn0 bits of the Counter (TCRmn) counts up from 0000H. When the TImn
operation TMRmn register can be changed. pin input valid edge is detected or the TSmn bit is set to 1,
The TDRmn register can always be read. the count value is transferred (captured) to timer data
The TCRmn register can always be read. register mn (TDRmn). At the same time, the TCRmn
The TSRmn register can always be read. register is cleared to 0000H, and the INTTMmn signal is
Set values of the TOMmn, TOLmn, TOmn, and TOEmn generated.
bits cannot be changed. If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared.
trigger bit. The OVF bit of the TSRmn register is also held.
also initialized.
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8.8.4 Operation as input signal high-/low-level width measurement
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
register (ISC) to 1. In the following descriptions, read TImn as RxD0.
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal
width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the
following expression.
Signal width of TImn input = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1
and the TImn pin start edge detection wait status is set.
When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF
bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn
register stops at the value “value transferred to the TDRmn register + 1”, and the TImn pin start edge detection wait status
is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1
and CISmn0 bits of the TMRmn register.
Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while
the TEmn bit is 1.
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured.

CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
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Figure 8-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Clock selection
CKm1
Operation clock Note Timer counter
TNFENxx
Trigger selection
Noise Edge Timer data Interrupt
TImn pin register mn (TDRmn) Interrupt signal
filter detection controller
(INTTMmn)
Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 8-58. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TSmn
TEmn
TImn
FFFFH
a
TCRmn b
c
0000H
TDRmn 0000H a b c
INTTMmn
OVF

OVF: Bit 0 of timer status register mn (TSRmn)
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Figure 8-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/0 0 0 0 0 0 1 0 1 1/0 0 0 1 1 0 0

110B: Capture & one-count

0: Does not generate INTTMmn when
counting is started.

10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)





Bit n
0

Bit n
0

Bit n
0

Bit n
0

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Figure 8-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used

setting disabled.)
enabled.)
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation Sets the TSmn bit to 1. TEmn = 1, and the TImn pin start edge detection wait
start The TSmn bit automatically returns to 0 because it is a status is set.
trigger bit.
Detects the TImn pin input count start valid edge. Clears timer count register mn (TCRmn) to 0000H and
starts counting up.

During Set value of the TDRmn register can be changed. When the TImn pin start edge is detected, the counter
operation The TCRmn register can always be read. (TCRmn) counts up from 0000H. If a capture edge of the
The TSRmn register is not used. TImn pin is detected, the count value is transferred to
Set values of the TMRmn register, TOMmn, TOLmn, timer data register mn (TDRmn) and INTTMmn is
TOmn, and TOEmn bits cannot be changed. generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared. The TCRmn register stops
the count operation until the next TImn pin start edge is
detected.
trigger bit. The OVF bit of the TSRmn register is also held.
also initialized.
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8.8.5 Operation as delay counter

It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then
generate INTTMmn (a timer interrupt) after any specified interval.
It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count down
start during the period of TEmn = 1.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
Timer count register mn (TCRmn) operates as a down counter in the one-count mode.
When the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1, the
TEmn, TEHm1, TEHm3 bits are set to 1 and the TImn pin input valid edge detection wait status is set.
Timer count register mn (TCRmn) starts operating upon TImn pin input valid edge detection and loads the value of
timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in
synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next TImn
pin input valid edge is detected.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next
period.
Figure 8-61. Block Diagram of Operation as Delay Counter

Clock selection
CKm1
Operation clockNote Timer counter
Trigger selection
TSmn
TNFENxx
Timer data Interrupt signal
Interrupt
register mn (TDRmn) (INTTMmn)
Noise Edge controller
TImn pin
filter detection
Note For using channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
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Figure 8-62. Example of Basic Timing of Operation as Delay Counter
TSmn
TEmn
TImn
FFFFH
TCRmn
0000H
TDRmn a b
INTTMmn
a+1 b+1

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Figure 8-63. Example of Set Contents of Registers to Delay Counter (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKSmn1 CKSmn0 CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0
1/0 1/0 0 0 0/1 0 0 1 1/0 1/0 0 0 1 0 0 0

100B: One-count mode
Start trigger during operation

0: Trigger input is invalid.
1: Trigger input is valid.






Bit n
0

Bit n
0

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Figure 8-63. Example of Set Contents of Registers to Delay Counter (2/2)

Bit n
0

Bit n
0
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Figure 8-64. Operation Procedure When Delay Counter Function Is Used

setting disabled.)
enabled.)
INTTMmn output delay is set to timer data register mn
(TDRmn).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation Sets the TSmn bit to 1. TEmn = 1, and the start trigger detection (the valid edge
start The TSmn bit automatically returns to 0 because it is a of the TImn pin input is detected or the TSmn bit is set to
trigger bit. 1) wait status is set.
The counter starts counting down by the next start trigger
detection. Value of the TDRmn register is loaded to the timer count
● Detects the TImn pin input valid edge. register mn (TCRmn).

● Sets the TSmn bit to 1 by the software.
During Set value of the TDRmn register can be changed. The counter (TCRmn) counts down. When the count
operation The TCRmn register can always be read. value of TCRmn reaches 0000H, the INTTMmn output is
The TSRmn register is not used. generated, and the count operation stops until the next
start trigger detection (the valid edge of the TImn pin input
is detected or the TSmn bit is set to 1).
trigger bit.
also initialized.
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8.9 Simultaneous Channel Operation Function of Timer Array Unit
8.9.1 Operation as one-shot pulse output function

By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input
to the TImn pin.
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDRmn (master) + 2} × Count clock period

Pulse width = {Set value of TDRmp (slave)} × Count clock period
The master channel operates in the one-count mode and counts the delays. Timer count register mn (TCRmn) of the
master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn).
The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count
clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave
channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp
register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with
the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn
of the master channel) is detected. The output level of TOmp becomes active one count clock after generation of
INTTMmn from the master channel, and inactive when TCRmp = 0000H.
Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a
start trigger.
Caution The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of
the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during
count operation, therefore, an illegal waveform may be output by conflicting with load timing. Rewrite
the TDRmn register after INTTMmn is generated and the TDRmp register after INTTMmp is generated.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6)

p: Slave channel number (n < p ≤ 7)
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Figure 8-65. Block Diagram of Operation as One-Shot Pulse Output Function
Master channel
(one-count mode)
Clock selection
CKm1
Operation clock Timer counter
Trigger selection
TNFENxx
TSmn
register mn (TDRmn) Interrupt signal
Noise Edge controller
TImn pin (INTTMmn)
filter detection
Slave channel
(one-count mode) Clock selection
CKm1
Operation clock Timer counter Output
CKm0 register mp (TCRmp) TOmp pin
controller
Trigger selection

register mp (TDRmp) Interrupt signal
controller
(INTTMmp)

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Figure 8-66. Example of Basic Timing of Operation as One-Shot Pulse Output Function
TSmn
TEmn
TImn
Master
FFFFH
channel
TCRmn
0000H
TDRmn a
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave 0000H
channel
TDRmp b
TOmp
INTTMmp
a+2 b a+2 b
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6)

2. TSmn, TSmp: Bit n, p of timer channel start register m (TSm)
TEmn, TEmp: Bit n, p of timer channel enable status register m (TEm)
TImn, TImp: TImn and TImp pins input signal
TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp: TOmn and TOmp pins output signal
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Figure 8-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAS
TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0
TERmnNote
1/0 0 0 0 1 0 0 1 1/0 1/0 0 0 1 0 0 0





1: Master channel.


00B: Selects CKm0 as operation clock of channels n.
10B: Selects CKm1 as operation clock of channels n.

Bit n
0

Bit n
0

Bit n
0

Bit n
0
Note TMRm2, TMRm4, TMRm6: MASTERmn = 1

TMRm0: Fixed to 0
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Figure 8-68. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register mp (TMRmp)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmp CKSmp1 CKSmp0 CCSmp M/S Note
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
Operation mode of channel p


Selection of TImp pin input edge


100B: Selects INTTMmn of master channel.



00B: Selects CKm0 as operation clock of channel p.
* Make the same setting as master channel.

Bit p
TOm TOmp 0: Outputs 0 from TOmp.
1/0 1: Outputs 1 from TOmp.

Bit p
TOEm TOEmp 0: Stops the TOmp output operation by counting operation.
1/0 1: Enables the TOmp output operation by counting operation.

Bit p
TOLm TOLmp 0: Positive logic output (active-high)
1/0 1: Negative logic output (active-low)

Bit p
TOMm TOMmp 1: Sets the slave channel output mode.
1

TMRm1, TMRm3: SPLITmp bit
TMRm5, TMRm7: Fixed to 0

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Figure 8-69. Operation Procedure of One-Shot Pulse Output Function (1/2)

setting disabled.)
Sets the TAUmEN bit of peripheral enable registers 0
enabled.)
Determines clock frequencies of CKm0 and CKm1.
default register 1 (NFEN1) to 1 (on). (Clock is supplied and some power is consumed.)
setting Sets timer mode register mn, mp (TMRmn, TMRmp) of
two channels to be used (determines operation mode of
channels).
An output delay is set to timer data register mn (TDRmn)
of the master channel, and a pulse width is set to the
TDRmp register of the slave channel.
Sets slave channel. The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output. The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp. TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0. The TOmp pin outputs the TOmp set level.
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Figure 8-69. Operation Procedure of One-Shot Pulse Output Function (2/2)

Operation Sets the TOEmp bit (slave) to 1 (only when operation is
start resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time. The TEmn and TEmp bits are set to 1 and the master
The TSmn and TSmp bits automatically return to 0 channel enters the start trigger detection (the valid edge of
because they are trigger bits. the TImn pin input is detected or the TSmn bit of the
master channel is set to 1) wait status.
Counter stops operating.
Count operation of the master channel is started by start
trigger detection of the master channel.
● Detects the TImn pin input valid edge.
Master channel starts counting.
● Sets the TSmn bit of the master channel to 1 by
softwareNote.
Note Do not set the TSmn bit of the slave channel to 1.

During Set values of only the CISmn1 and CISmn0 bits of the Master channel loads the value of the TDRmn register to
operation TMRmn register can be changed. timer count register mn (TCRmn) by the start trigger
Set values of the TMRmp, TDRmn, TDRmp registers, detection (the valid edge of the TImn pin input is detected
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be or the TSmn bit of the master channel is set to 1), and the
changed. counter starts counting down. When the count value

The TCRmn and TCRmp registers can always be read. reaches TCRmn = 0000H, the INTTMmn output is
The TSRmn and TSRmp registers are not used. generated, and the counter stops until the next start trigger
Set values of the TOm and TOEm registers by slave detection.
channel can be changed. The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
Operation The TTmn (master) and TTmp (slave) bits are set to 1 at
stop the same time. TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0 The TCRmn and TCRmp registers hold count value and
because they are trigger bits. stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit. The TOmp pin outputs the TOmp set level.
TAU To hold the TOmp pin output level
stop Clears the TOmp bit to 0 after the value to
be held is set to the port register. The TOmp pin output level is held by port function.
When holding the TOmp pin output level is not
necessary
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)

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8.9.2 Operation as PWM function

Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period

Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output: Set value of TDRmp (slave) = 0000H
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
Remark The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it
summarizes to 100% output.
The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start
register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded
to timer count register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the
counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and
the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop
register m (TTm) is set to 1.
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the
PWM output (TOmp) cycle.
The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the
TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter
reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated.
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the
PWM output (TOmp) duty.
PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the
inactive level when the TCRmp register of the slave channel becomes 0000H.
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel, a write access is necessary two times. The timing at which the values of the TDRmn
and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of
INTTMmn of the master channel. Thus, when rewriting is performed split before and after
occurrence of INTTMmn of the master channel, the TOmp pin cannot output the expected waveform.
To rewrite both the TDRmn register of the master and the TDRmp register of the slave, therefore, be
sure to rewrite both the registers immediately after INTTMmn is generated from the master channel.

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Figure 8-70. Block Diagram of Operation as PWM Function
Master channel
(interval timer mode)
Clock selection
CKm1
Trigger selection
TSmn register mn (TDRmn) Interrupt signal
controller
(INTTMmn)
Slave channel
(one-count mode)
Clock selection
CKm1
controller
Trigger selection

controller
(INTTMmp)

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Figure 8-71. Example of Basic Timing of Operation as PWM Function
TSmn
TEmn
FFFFH
Master
TCRmn
channel 0000H
TDRmn a b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave 0000H
channel
TDRmp c d
TOmp
INTTMmp
a+1 a+1 b+1
c c d
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6)

2. TSmn, TSmp: Bit n, p of timer channel start register m (TSm)
TEmn, TEmp: Bit n, p of timer channel enable status register m (TEm)
TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp: TOmn and TOmp pins output signal
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Figure 8-72. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAS
TERmnNote
1/0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1


started.


Setting of the MASTERmn bit (channels 2, 4, 6)

1: Master channel.



Bit n
0

Bit n
0

Bit n
0

Bit n
0

TMRm0: Fixed to 0
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Figure 8-73. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
Operation mode of channel p


Selection of TImp pin input edge



0: Slave channel.
Setting of SPLITmp bit (channels 1, 3)



Bit p
TOm TOmp 0: Outputs 0 from TOmp.
1/0 1: Outputs 1 from TOmp.

Bit p
TOEm TOEmp 0: Stops the TOmp output operation by counting operation.
1/0 1: Enables the TOmp output operation by counting operation.

Bit p
TOLm TOLmp 0: Positive logic output (active-high)
1/0 1: Negative logic output (active-low)

Bit p
TOMm TOMmp 1: Sets the slave channel output mode.
1

TMRm1, TMRm3: SPLITmp bit

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Figure 8-74. Operation Procedure When PWM Function Is Used (1/2)

TAU Stops supply of timer array unit m input clock.
setting disabled.)
(PER0) to 1. Supplies timer array unit m input clock.
Each channel stops operating.
enabled.)
Channel Sets timer mode registers mn, mp (TMRmn, TMRmp) of Channel stops operating.
default two channels to be used (determines operation mode of (Clock is supplied and some power is consumed.)
setting channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp register of the slave channel.
Sets slave channel. The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output. The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp. TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0. The TOmp pin outputs the TOmp set level.
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Figure 8-74. Operation Procedure When PWM Function Is Used (2/2)

Operation Sets the TOEmp bit (slave) to 1 (only when operation is
start resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same TEmn = 1, TEmp = 1
time. When the master channel starts counting, INTTMmn is
The TSmn and TSmp bits automatically return to 0 generated. Triggered by this interrupt, the slave
because they are trigger bits. channel also starts counting.
During Set values of the TMRmn and TMRmp registers, The counter of the master channel loads the TDRmn
operation TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be register value to timer count register mn (TCRmn), and
changed. counts down. When the count value reaches TCRmn =
Set values of the TDRmn and TDRmp registers can be 0000H, INTTMmn output is generated. At the same time,
changed after INTTMmn of the master channel is the value of the TDRmn register is loaded to the TCRmn
generated. register, and the counter starts counting down again.
The TCRmn and TCRmp registers can always be read. At the slave channel, the value of the TDRmp register is
The TSRmn and TSRmp registers are not used. loaded to the TCRmp register, triggered by INTTMmn of
the master channel, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
Operation The TTmn (master) and TTmp (slave) bits are set to 1 at
stop the same time. TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0 The TCRmn and TCRmp registers hold count value and
because they are trigger bits. stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and value
is set to the TOmp bit. The TOmp pin outputs the TOmp set level.
TAU To hold the TOmp pin output level
stop Clears the TOmp bit to 0 after the value to The TOmp pin output level is held by port function.
be held is set to the port register.
When holding the TOmp pin output level is not
necessary
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)

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8.9.3 Operation as multiple PWM output function

By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values
can be output.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period

Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Remark Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
Timer count register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods.
The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM
waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of
the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and
stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp
becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp =
0000H.
In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in
one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the
value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When
TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the
master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn
from the master channel, and inactive when TCRmq = 0000H.
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same
time.
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp
registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn from the master
channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of
the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately
after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the
slave channel 2).
Remark m: Unit number (m = 0), n: Channel number (n = 0, 2, 4)

p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are integers greater than n)
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Figure 8-75. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs)
Master channel
(interval timer mode)
Clock selection
CKm1
Trigger selection
TSmn register mn (TDRmn) Interrupt signal
controller
(INTTMmn)
Slave channel 1
(one-count mode)
Clock selection
CKm1
controller
Trigger selection

controller
(INTTMmp)
Slave channel 2
(one-count mode)
Clock selection
CKm1
CKm0 register mq (TCRmq) TOmq pin
controller
Trigger selection

register mq (TDRmq) Interrupt signal
controller
(INTTMmq)

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Figure 8-76. Example of Basic Timing of Operation as Multiple PWM Output Function
(Output Two Types of PWMs)
TSmn
TEmn
FFFFH
Master
TCRmn
channel 0000H
TDRmn a b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave 0000H
channel 1
TDRmp c d
TOmp
INTTMmp
a+1 a+1 b+1
c c d d
TSmq
TEmq
FFFFH
TCRmq
Slave 0000H
channel 2
TDRmq e f
TOmq
INTTMmq
a+1 a+1 b+1
e e f f
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Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4)

2. TSmn, TSmp, TSmq: Bit n, p, q of timer channel start register m (TSm)
TEmn, TEmp, TEmq: Bit n, p, q of timer channel enable status register m (TEm)
TCRmn, TCRmp, TCRmq: Timer count registers mn, mp, mq (TCRmn, TCRmp, TCRmq)
TDRmn, TDRmp, TDRmq: Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq)
TOmn, TOmp, TOmq: TOmn, TOmp, and TOmq pins output signal
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Figure 8-77. Example of Set Contents of Registers

When Multiple PWM Output Function (Master Channel) Is Used

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAS
TERmnNote
1/0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1


started.


Setting of the MASTERmn bit (channels 2, 4, 6)

1: Master channel.



Bit n
0

Bit n
0

Bit n
0

Bit n
0

TMRm0: Fixed to 0
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Figure 8-78. Example of Set Contents of Registers

When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs)
(a) Timer mode register mp, mq (TMRmp, TMRmq)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmq CKSmq1 CKSmq0 CCSmq M/SNote STSmq2 STSmq1 STSmq0 CISmq1 CISmq0 MDmq3 MDmq2 MDmq1 MDmq0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
Operation mode of channel p, q


Selection of TImp and TImq pins input edge


Setting of MASTERmp and MASTERmq bits (channels 2, 4, 6)

0: Slave channel.
Setting of SPLITmp and SPLITmq bits (channels 1, 3)


00B: Selects CKm0 as operation clock of channel p, q.
10B: Selects CKm1 as operation clock of channel p, q.

Bit q Bit p
TOm TOmq TOmp 0: Outputs 0 from TOmp or TOmq.
1/0 1/0 1: Outputs 1 from TOmp or TOmq.

Bit q Bit p
TOEm TOEmq TOEmp 0: Stops the TOmp or TOmq output operation by counting operation.
1/0 1/0 1: Enables the TOmp or TOmq output operation by counting operation.

Bit q Bit p
TOLm TOLmq TOLmp 0: Positive logic output (active-high)
1/0 1/0 1: Negative logic output (active-low)

Bit q Bit p
TOMm TOMmq TOMmp 1: Sets the slave channel output mode.
1 1
Note TMRm2, TMRm4, TMRm6: MASTERmp, MASTERmq bit

TMRm1, TMRm3: SPLITmp, SPLIT0q bit
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Figure 8-79. Operation Procedure When Multiple PWM Output Function Is Used (1/2)

TAU Stops supply of timer array unit m input clock.
setting disabled.)
(PER0) to 1. Supplies timer array unit m input clock.
Each channel stops operating.
enabled.)
Channel Sets timer mode registers mn, mp, mq (TMRmn, Channel stops operating.
default TMRmp, TMRmq) of each channel to be used (Clock is supplied and some power is consumed.)
setting (determines operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels. The TOmp and TOmq pins go into Hi-Z output state.
The TOMmp and TOMmq bits of timer output mode
register m (TOMm) are set to 1 (slave channel output
mode).
Sets the TOLmp and TOLmq bits.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs. The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq. TOmp and TOmq do not change because channels stop
operating.
Clears the port register and port mode register to 0. The TOmp and TOmq pins output the TOmp and TOmq
set levels.
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Figure 8-79. Operation Procedure When Multiple PWM Output Function Is Used (2/2)

Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when
start resuming operation.)
The TSmn bit (master), and TSmp and TSmq (slave) bits
of timer channel start register m (TSm) are set to 1 at the
same time. TEmn = 1, TEmp, TEmq = 1
The TSmn, TSmp, and TSmq bits automatically return When the master channel starts counting, INTTMmn is
to 0 because they are trigger bits. generated. Triggered by this interrupt, the slave
channel also starts counting.
During Set values of the TMRmn, TMRmp, TMRmq registers, The counter of the master channel loads the TDRmn
operation TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq register value to timer count register mn (TCRmn) and
bits cannot be changed. counts down. When the count value reaches TCRmn =
Set values of the TDRmn, TDRmp, and TDRmq registers 0000H, INTTMmn output is generated. At the same time,
can be changed after INTTMmn of the master channel is the value of the TDRmn register is loaded to the TCRmn
generated. register, and the counter starts counting down again.
The TCRmn, TCRmp, and TCRmq registers can always At the slave channel 1, the values of the TDRmp register
be read. are transferred to the TCRmp register, triggered by
The TSRmn, TSRmp, and TSR0q registers are not used. INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmp become active
one count clock after generation of the INTTMmn output
from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq register, triggered by INTTMmn
of the master channel, and the counter starts counting
down. The output levels of TOmq become active one
count clock after generation of the INTTMmn output from
the master channel. It becomes inactive when TCRmq =
0000H, and the counting operation is stopped.
Operation The TTmn bit (master), TTmp, and TTmq (slave) bits are
stop set to 1 at the same time. TEmn, TEmp, TEmq = 0, and count operation stops.
The TTmn, TTmp, and TTmq bits automatically return
The TCRmn, TCRmp, and TCRmq registers hold count
to 0 because they are trigger bits.
value and stop.
The TOmp and TOmq output are not initialized but hold
current status.
The TOEmp and TOEmq bits of slave channels are
cleared to 0 and value is set to the TOmp and TOmq bits. The TOmp and TOmq pins output the TOmp and TOmq
set levels.
TAU To hold the TOmp and TOmq pin output levels
stop Clears the TOmp and TOmq bits to 0 after
the value to be held is set to the port register. The TOmp and TOmq pin output levels are held by port
When holding the TOmp and TOmq pin output levels are function.
not necessary
Setting not required
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
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8.10 Cautions When Using Timer Array Unit
8.10.1 Cautions when using timer output

Depends on products, a pin is assigned a timer output and other alternate functions. In this case, outputs of the other
alternate functions must be set in initial status.
For details, see 4.5 Register Settings When Using Alternate Function.
(a) Using TO02 to TO07 outputs (80-pin products only)

In addition to clearing the port mode register (the PMxx bit) and the port register (the Pxx bit) to 0, be sure to
clear the corresponding bit of LCD port function register 4 (PFSEG37 to PFSEG32) to “0”.
(b) Using TO01, TO06 and TO07 outputs (64-pin products only)
In addition to clearing the port mode register (the PMxx bit) and the port register (the Pxx bit) to 0, be sure to
clear the corresponding bit of LCD port function register 2 (PFSEG18) and LCD port function register 3
(PFSEG24 to PFSEG25) to “0”.
(c) Using TO00 and TO01 outputs assigned to the P43 and P41
So that the alternated PCLBUZ1 and PCLBUZ0 outputs become 0, not only set the port mode register (the
PM43 and PM41 bits) and the port register (the P43 and P41 bits) to 0, but also use the bit 7 of the clock
output select register n (CKSn) with the same setting as the initial status.
(d) Using TO02 to TO07 outputs assigned to the P07 to P02

So that the alternated P07/SO00/TxD0, P06/SDA00, P05/SCK00/SCL00, P04/TxD1, P03/SDA10 and
P02/SCL10 outputs become 1, not only set the port mode register (the PM07 to PM02 bits) and the port
register (the P07 to P02 bits) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status.
(e) Using TO06 outputs assigned to the P31

So that the alternated P06/TxD2/IrTxD outputs become 1, not only set the port mode register (the PM06 bit)
and the port register (the P06 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial
output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status.
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RL78/I1C CHAPTER 9 REALTIME CLOCK WITH INDEPENDENT POWER SUPPLY
CHAPTER 9 REALTIME CLOCK WITH INDEPENDENT POWER SUPPLY
9.1 Overview
The RTC has two types of counting modes: calendar count mode and binary count mode. They are used by switching
the register settings.
For calendar count mode, the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates for leap
years.
For binary count mode, the RTC does not count in terms of years, months, dates, day-of-week, hours, or minutes; it
counts seconds, and retains the information as a serial value. This mode can be used for calendars other than the
Gregorian calendar.
The RTC uses the 128-Hz clock which is acquired by the count source divided by the prescaler as the basic clock.
Year, month, date, day-of-week, a.m./p.m. (in 12-hour mode), hour, minute, second, or 32-bit binary is counted in 1/128
second units.
Table 9-1 lists the specifications of the RTC, shows a block diagram of the RTC, and Table 9-2 shows the pin
configuration of the RTC.
Table 9-1. RTC Specifications
Item Description
Count mode Calendar count mode/binary count mode
Count source Sub-clock (fSX) Note
Clock and calendar ● Calendar count mode
functions Year, month, date, day-of-week, hour, minute, second are counted, BCD display
12 hours/24 hours mode switching function
30 seconds adjustment function (a number less than 30 is rounded down to 00 seconds, and 30 seconds
or more are rounded up to one minute)
Automatic adjustment function for leap years
● Binary count mode
Count seconds in 32 bits, binary display
● Common to both modes
Start/stop function
The sub-second digit is displayed in binary units (1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, or 64 Hz).
Clock error correction function
Clock (1-Hz/64-Hz) output
Interrupts ● Alarm interrupt (ALM)
As an alarm interrupt condition, selectable which of the below is compared with:
Calendar count mode: Year, month, date, day-of-week, hour, minute, or second can be selected
Binary count mode: Each bit of the 32-bit binary counter
● Periodic interrupt (PRD)
2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32 second, 1/64 second, or
1/256 second can be selected as an interrupt period.
● Recovery from standby mode can be performed by an alarm interrupt or periodic interrupt
Time capture function ● Times can be captured when the edge of the time capture event input pin is detected.
For every event input, month, date, hour, minute, and second are captured or 32-bit binary counter value is
captured.
Event link function Periodic event output
<R> Note The XT1 clock oscillator runs on the VRTC power-supply. It can operate after release from the RTC power-on
reset following the power supply to the VRTC pin being turned on. If the VRTC power-supply stops, an RTC
power-on reset is generated and the XT1 clock oscillator stops.
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Figure 9-1. Block Diagram of RTC
Internal peripheral bus

Realtime clock (RTC)
Bus interface
SCSC SCMC
To each
RCR2 function
RTCOUT
Time counter 1-Hz/64-Hz output Alarm function
Prescaler
XT1 Crystal 128 Hz RSECAR/ RMINAR/
32.768 kHz RSECCNT/
XT2 oscillation Selec 128-Hz generation R64CNT BCNT0AR BCNT1AR
tor Sub-clock BCNT0
EXCLKS RHRAR/ RWKAR/
(fSX)
RADJ RHRCNT/ RMINCNT/ BCNT2AR BCNT3AR
BCNT2 BCNT1 RDAYAR/ RMONAR/
RCR4 BCNT0AER BCNT1AER
RCR3 RYRAR RYRAREN/
RWKCNT/
RDAYCNT BCNT2AER BCNT3AER
BCNT3
RMONCNT RYRCNT Alarm comparison
Interrupt control
RSR INTRTCALM
INTRTCPRD
RCR1
Time capture control
RSECCPn/ RMINCPn/
Time capture BCNT0CPn BCNT1CPn
event input pins Noise RHRCPn/ RDAYCPn/
RTCICn filter BCNT2CPn BCNT3CPn
RMONCPn
RTCCRn
RTCICNFEN
R64CNT: 64-Hz counter RSECAR/BCNT0AR: Second alarm register/Binary counter 0 alarm register
RSECCNT/BCNT0: Second counter/Binary counter 0 RMINAR/BCNT1AR: Minute alarm register/Binary counter 1 alarm register
RMINCNT/BCNT1: Minute counter/Binary counter 1 RHRAR/BCNT2AR: Hour alarm register/Binary counter 2 alarm register
RHRCNT/BCNT2: Hour counter/Binary counter 2 RWKAR/BCNT3AR: Day-of-week alarm register/Binary counter 3 alarm register
RWKCNT/BCNT3: Day-of-week counter/Binary counter 3 RDAYAR/BCNT0AER: Date alarm register/Binary counter 0 alarm enable register
RDAYCNT: Date counter RMONAR/BCNT1AER: Month alarm register/Binary counter 1 alarm enable register
RMONCNT: Month counter RYRAR/BCNT2AER: Year alarm register/Binary counter 2 alarm enable register
RYRCNT: Year counter RYRAREN/BCNT3AER: Year alarm enable register/Binary counter 3 alarm enable register
RSR: Status register
RCR1: RTC control register 1
RCR5GD: RCR5 guard register
RADJ: Time error adjustment register
RTCCRn: Time capture control register n
RSECCPn/BCNT0CPn: Second capture register n/BCNT0 capture register n
RMINCPn/BCNT1CPn: Minute capture register n/BCNT1 capture register n
RHRCPn/BCNT2CPn: Hour capture register n/BCNT2 capture register n
RDAYCPn/BCNT3CPn: Date capture register n/BCNT3 capture register n
RMONCPn: Month capture register n
Remark n = 0 to 2
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Table 9-2. Pin Configuration of RTC
Pin Name I/O Function

XT1 Input Connecting a 32.768-kHz crystal vibrator.
XT2 Input
EXCLKS Input Connecting a 32.768-kHz external clock input.
RTCOUT Output 1 or 64-Hz waveform output pin.
RTCIC0 Input Time capture event input pins
RTCIC1 Input
RTCIC2 Input
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<R> 9.2 Register Descriptions
When writing to or reading from RTC registers, do so in accordance with 9.6.4 Notes when writing to and reading
from registers.
If the value in an RTC register after a reset is given as undefined in the list, it is not initialized by a reset. When RTC
enters the reset state during counting operations (i.e. while the RCR2.START bit is 1), the year, month, day of the week,
date, hours, minutes, seconds, and 64-Hz counters continue to operate. Note that a reset generated during writing to or
updating of a register might destroy the register value.
Table 9-3 shows the power domains, the values after different types of reset, and the R/W properties of the registers
that control the RTC.
<R> Table 9-3. Registers that Control the RTC (1/3)

After MCU Reset R/W Property
RTC RTC
Special Function Bit Name Power Reset
Power-on Power-on Software
Register (SFR) Name Domain other than VRTCEN = 0 VRTCEN = 1
Reset Reset Reset
Note 2
RTCPOR
PER2 VRTCEN VDDNote 1 – 0 0 – Readable and Readable and
writable writableNote 6
R64CNT – VRTC Undefined – – 00H Not readable ReadableNote 4
RSECCNT/BCNT0 – VRTC Undefined – – – Not readable, Readable and

not writable writableNotes 4, 7, 9
RMINCNT/BCNT1 – VRTC Undefined – – – Not readable, Readable and

RHRCNT/BCNT2 – VRTC Undefined – – – Not readable, Readable and

RWKCNT/BCNT3 – VRTC Undefined – – – Not readable, Readable and

RDAYCNT – VRTC Undefined – – – Not readable, Readable and

RMONCNT – VRTC Undefined – – – Not readable, Readable and

RYRCNT – VRTC Undefined – – – Not readable, Readable and

RSECAR/BCNT0AR – VRTC Undefined – – 00H Not readable, Readable and

not writable writableNote 7
RMINAR/BCNT1AR – VRTC Undefined – – 00H Not readable, Readable and

RHRAR/BCNT2AR – VRTC Undefined – – 00H Not readable, Readable and

RWKAR/BCNT3AR – VRTC Undefined – – 00H Not readable, Readable and

RDAYAR/BCNT0AER – VRTC Undefined – – 00H Not readable, Readable and

RMONAR/BCNT1AER – VRTC Undefined – – 00H Not readable, Readable and

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RTC RTC
Reset Reset Reset
RTCPOR Note 2
RYRAR/BCNT2AER – VRTC Undefined – – 0000H Not readable, Readable and
RYRAREN/BCNT3AER – VRTC Undefined – – 00H Not readable, Readable and

RCR1 AIE VRTC Undefined – – – Not readable, Readable and

PIE VRTC Undefined – – – Not readable, Readable and

RTCOS VDDNote 1 – 0 – – Not readable, Readable and

not writable writableNotes 6, 9
PES VRTC Undefined – – – Not readable, Readable and

RCR2 START VRTC Undefined – – – Not readable, Readable and

RESET VDDNote 1 – 0 – – Not readable, Readable and

ADJ30 VDDNote 1 – 0 – 0 Not readable, Readable and

RTCOE VDDNote 1 – 0 – – Not readable, Readable and

AADJE VRTC Undefined – – 0 Not readable, Readable and

AADJP VRTC Undefined – – 0 Not readable, Readable and

HR24 VRTC Undefined – – – Not readable, Readable and

CNTMD VRTC Undefined – – – Not readable, Readable and

RCR3 RTCICEN VRTC Undefined – – – Not readable, Readable and

RCR4 RCKSEL VRTC Undefined – – – Not readable, Readable and

RCR5 – VRTC Undefined – – – Not readable, Readable and

RCR5GD – VDDNote 1 – 00H – – Not writable Writable
RADJ – VRTC Undefined – – 00H Not readable, Readable and

RTCCRy (y = 0 to 2) – VRTC Undefined – – 00H Not readable, Readable and

RSECCPy/BCNT0CPy – VRTC Undefined – – 00H Not readable Readable

(y = 0 to 2)
RMINCPy/BCNT1CPy – VRTC Undefined – – 00H Not readable Readable

(y = 0 to 2)
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RTC RTC
Reset Reset Reset
RTCPOR Note 2
RHRCPy/BCNT2CPy – VRTC Undefined – – 00H Not readable Readable
(y = 0 to 2)
RDAYCPy/BCNT3CPy – VRTC Undefined – – 00H Not readable Readable

(y = 0 to 2)
RMONCPy (y = 0 to 2) – VRTC Undefined – – 00H Not readable Readable
RSR AF VDDNote 1 – 0Note 3 – 0 Not readable, Readable and

CF VDDNote 1 – 0Note 3 – 0 Not readable, Readable and

PF VDDNote 1 – 0Note 3
– 0 Not readable, Readable and
SCMC – VRTC 00H – – – Not readable, Readable and

SCSC – VRTC 40H – – – Not readable, Readable and

RTCPORSR – VRTC 00H – – – Not readable, Readable and

RTCICNFEN – VRTC 00H – – – Not readable, Readable and

Notes 1. VDD or VBAT is selected by the battery backup function.

2. Refer to (1) to (7) in CHAPTER 27 RESET FUNCTION according to the reset factors.
3. The value read after release from the reset state may be undefined.
4. In the case of reading the time in any of the following situations, wait for 1/128 of a second while the time
counter is operating (RCR2.START bit = “1”) before reading the time.
– After return from a reset state other than the RTC power-on reset and RTC software reset states
– After return from the power-on reset state
– After return from STOP mode
– After return from HALT mode while the RTCLPC bit is 1 and the CPU is being driven by the subsystem
clock (fSUB)
– After changing the setting of the VRTCEN bit from 0 to 1
5. Wait for 2 cycles of the CPU clock (fCLK) before reading this register after changing the setting of the
VRTCEN bit from 0 to 1.
6. Values written can be read immediately after writing to the register.
7. Values written will be read correctly from the 4th cycle of the CPU clock (fCLK) after writing.
8. The value in the register is updated in synchronization with the source for counting. If the value in the
register is overwritten, confirm that the value has actually been updated before proceeding with further
processing.
9. Do not write to the register during counting (RCR2.START = 1). Stop the counter before writing.
10. After a reset is generated, only write to this RTC register after 6 clock cycles of the source for counting have
elapsed. Setting the registers that control the RTC while the power supply from the VRTC pin is stopped is
prohibited.
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This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware
that is not used is also stopped so as to decrease the power consumption and noise.
To manipulate of the registers of the independent power supply real-time clock, set (1) the bit 0 (VRTCEN). Other than
time when read/write accessing, clear (0) the bit 0 (VRTCEN).
The PER2 register can be set by a 1-bit or an 8-bit memory manipulation instruction.
<R> Address: F00FCH After reset: 00H R/W

Symbol <7> <6> 5 4 3 <2> 1 <0>
VRTCEN Control of independent power supply RTC input clock supply

● SFR used by the independent power supply RTC cannot be written. The read value is 00H. The sub
clock (fSX) clock can drive counting by the independent power supply RTC.
● SFR used by the independent power supply RTC can be read and written.
Cautions 1. If the battery back-up function isn’t used, leak current may be generated via the VRTC pin when
the VDD pin power supply voltage is less than 1.9 V. Therefore, set the VRTCEN bit to 0 except
during reading or writing of the SFRs of the independent power supply RTC.
2. If the battery back-up function is used, leak current may be generated via the VRTC pin when the
VBAT pin power supply voltage is less than 1.9 V. Therefore, set the VRTCEN bit to 0 except
during reading or writing of the SFRs of the independent power supply RTC.
3. When the power of the VRTC pin is not supplied, set the VRTCEN bit to 0.
4. Be sure to clear the following bits to 0.
Bits 1 and 3 to 5
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9.2.2 64-Hz counter (R64CNT)

The R64CNT counter is used in both calendar count mode and in binary count mode.
The 64-Hz counter (R64CNT) generates the period for a second by counting up periods of the 128-Hz clock.
The state in the sub-second range can be confirmed by reading this counter.
This counter is set to 00h by an RTC software reset or executing 30-second adjustment.
To read this counter, follow the procedure in 9.3.6 Reading 64-Hz counter and time.
Figure 9-3. Format of 64-Hz Counter (R64CNT)
Address: F0581H After reset: Undefined R

Symbol 7 6 5 4 3 2 1 0
R64CNT 0 F1HZ F2HZ F4HZ F8HZ F16HZ F32HZ F64HZ
F1HZ 1 Hz
Indicate the state for 1 Hz of the sub-second digit.
F2HZ 2 Hz
F4HZ 4 Hz
F8HZ 8 Hz
F16HZ 16 Hz
F32HZ 32 Hz
F64HZ 64 Hz
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9.2.3 Second counter (RSECCNT)/binary counter 0 (BCNT0)
(1) In calendar count mode:

The RSECCNT counter is used for setting and counting the BCD-coded second value. It counts carries generated
once per second in the 64-Hz counter.
The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Before writing to
this register, be sure to stop the count operation through the setting of the START bit in RCR2.
Figure 9-4. Format of Second Counter (RSECCNT)
Address: F0583H After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RSECCNT 0 SEC10 SEC1
SEC10 10-Second Count
Counts from 0 to 5 for 60-second counting.
SEC1 1-Second Count
Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place.
(2) In binary count mode:

The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0.
The 32-bit binary counter performs count operation by a carry generating for each second of the 64-Hz counter.
Before writing to this register, be sure to stop the count operation through the setting of the START bit in RCR2.
Figure 9-5. Format of Binary Counter 0 (BCNT0)
Address: F0583H After reset: Undefined

Symbol 7 6 5 4 3 2 1 0
BCNT0 BCNT[7:0]
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9.2.4 Minute counter (RMINCNT)/binary counter 1 (BCNT1)

The RMINCNT counter is used for setting and counting the BCD-coded minute value. It counts carries generated
once per minute in the second counter.
A value from 00 through 59 (in BCD) can be specified; if a value outside of this range is specified, the RTC does
not operate correctly. Before writing to this register, be sure to stop the count operation through the setting of the
START bit in RCR2.
Figure 9-6. Format of Minute Counter (RMINCNT)

Symbol 7 6 5 4 3 2 1 0
RMINCNT 0 MIN10 MIN1
MIN10 10-Minute Count
Counts from 0 to 5 for 60-minute counting.
MIN1 1-Minute Count
Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place.


Symbol 7 6 5 4 3 2 1 0
BCNT1 BCNT[15:8]
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9.2.5 Hour counter (RHRCNT)/binary counter 2 (BCNT2)

The RHRCNT counter is used for setting and counting the BCD-coded hour value. It counts carries generated
once per hour in the minute counter.
The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24).
When the RCR2.HR24 bit is 0: From 00 to 11 (in BCD)
If a value outside of this range is specified, the RTC does not operate correctly. Before writing to this register, be
sure to stop the count operation through the setting of the START bit in RCR2.
The PM bit is only enabled when the RCR2.HR24 bit is 0. Otherwise, the setting in the PM bit has no effect.
Figure 9-8. Format of Hour Counter (RHRCNT)

Symbol 7 6 5 4 3 2 1 0
RHRCNT 0 PM HR10 HR1
PM PM
0 a.m.
1 p.m.
Time Counter Setting for a.m./p.m.
HR10 10-Hour Count
Counts from 0 to 2 once per carry from the ones place.
HR1 1-Hour Count
Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place.


Symbol 7 6 5 4 3 2 1 0
BCNT2 BCNT[23:16]
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9.2.6 Day-of-week counter (RWKCNT)/binary counter 3 (BCNT3)

The RWKCNT counter is used for setting and counting in the coded day-of-week value. It counts carries generated
once per day in the hour counter.
A value from 0 through 6 can be specified; if a value outside of this range is specified, the RTC does not operate
correctly.
Figure 9-10. Format of Day-of-Week Counter (RWKCNT)

Symbol 7 6 5 4 3 2 1 0
RWKCNT 0 0 0 0 0 DAYW
DAYW2 DAYW1 DAYW0 Day-of-Week Counting
0 0 0 Sunday
0 0 1 Monday
0 1 0 Tuesday
0 1 1 Wednesday
1 0 0 Thursday
1 0 1 Friday
1 1 0 Saturday
1 1 1 Setting Prohibited


Symbol 7 6 5 4 3 2 1 0
BCNT3 BCNT[31:24]
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9.2.7 Date counter (RDAYCNT)

The RDAYCNT counter is used in calendar count mode.
RDAYCNT is used for setting and counting the BCD-coded date value. It counts carries generated once per day in the
hour counter. The count operation depends on the month and whether the year is a leap year.
Leap years are determined according to whether the year counter (RYRCNT) value is divisible by 400, 100, and 4.
A value from 01 through 31 (in BCD) can be specified; if a value outside of this range is specified, the RTC does not
operate correctly. (When specifying a value, note that the range of specifiable days depends on the month and whether
the year is a leap year.) Before writing to this register, be sure to stop the count operation through the setting of the
START bit in RCR2.
Figure 9-12. Format of Date Counter (RDAYCNT)
Address: F058BH After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RDAYCNT 0 0 DATE10 DATE1
DATE10 10-Day Count
DATE1 1-Day Count
Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.
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9.2.8 Month counter (RMONCNT)

The RMONCNT counter is used in calendar count mode.
RMONCNT is used for setting and counting the BCD-coded month value. It counts carries generated once per month
in the date counter.
operate correctly. Before writing to this register, be sure to stop the count operation through the setting of the START bit in
RCR2.
Figure 9-13. Format of Month Counter (RMONCNT)
Address: F058DH After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RMONCNT 0 0 0 MON10 MON1
MON10 10-Month Count
MON1 1-Month Count
Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.
9.2.9 Year counter (RYRCNT)

The RYRCNT counter is used in calendar count mode.
RYRCNT is used for setting and counting the BCD-coded year value. It counts carries generated once per year in the
month counter.
operate correctly. Before writing to this register, be sure to stop the count operation through the setting of the START bit in
RCR2.
RYRCNT can only be accessed with a 16-bit memory manipulation instruction.
Figure 9-14. Format of Year Counter (RYRCNT)
Address: F058EH After reset: Undefined R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RYRCNT 0 0 0 0 0 0 0 0 YR10 YR1
YR10 10-Year Count

Counts from 0 to 9 once per carry from ones place.
YR1 1-Year Count
Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place.
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9.2.10 Second alarm register (RSECAR)/binary counter 0 alarm register (BCNT0AR)

RSECAR is an alarm register corresponding to the BCD-coded second counter RSECCNT. When the ENB bit is
set to 1, the RSECAR value is compared with the RSECCNT value. From among the alarm registers (RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1
are compared with the corresponding counters. When the respective values all match, the alarm flag (AF) of the
RTC status register (RSR) is set to 1.
RSECAR values from 00 through 59 (in BCD) can be specified; if a value outside of this range is specified, the
RTC does not operate correctly.
This register is set to 00h by an RTC software reset.
Figure 9-15. Format of Second Alarm Register (RSECAR)

Symbol 7 6 5 4 3 2 1 0
RSECAR ENB SEC10 SEC1
ENB ENB
0 The register value is not compared with the RSECCNT counter value.
1 The register value is compared with the RSECCNT counter value.
SEC10 10 Seconds
Setting value for the tens place of seconds
SEC1 1 Seconds
Setting value for the ones place of seconds

The BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0.
Figure 9-16. Binary Counter 0 Alarm Register (BCNT0AR)

Symbol 7 6 5 4 3 2 1 0
BCNT0AR BCNTAR[7:0]
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9.2.11 Minute alarm register (RMINAR)/binary counter 1 alarm register (BCNT1AR)

RMINAR is an alarm register corresponding to the BCD-coded minute counter RMINCNT. When the ENB bit is set
to 1, the RMINAR value is compared with the RMINCNT value. From among the alarm registers (RSECAR,
RMINAR values from 00 through 59 (in BCD) can be specified; if a value outside of this range is specified, the RTC
does not operate correctly.
Figure 9-17. Format of Minute Alarm Register (RMINAR)

Symbol 7 6 5 4 3 2 1 0
RMINAR ENB MIN10 MIN1
ENB ENB
0 The register value is not compared with the RMINCNT counter value.
1 The register value is compared with the RMINCNT counter value.
MIN10 10 Minutes
Setting value for the tens place of minutes
MIN1 1 Minute
Setting value for the ones place of minutes

Figure 9-18. Format of Binary Counter 1 Alarm Register (BCNT1AR)

Symbol 7 6 5 4 3 2 1 0
BCNT1AR BCNTAR[15:8]
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9.2.12 Hour alarm register (RHRAR)/binary counter 2 alarm register (BCNT2AR)

RHRAR is an alarm register corresponding to the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1,
the RHRAR value is compared with the RHRCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are
compared with the corresponding counters. When the respective values all match, the alarm flag (AF) of the RTC
status register (RSR) is set to 1.
The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24).
If a value outside of this range is specified, the RTC does not operate correctly.
When the RCR2.HR24 bit is 0, be sure to set the PM bit.
When the RCR2.HR24 bit is 1, the setting in the PM bit has no effect.
Figure 9-19. Format of Hour Alarm Register (RHRAR)

Symbol 7 6 5 4 3 2 1 0
RHRAR ENB PM HR10 HR1
ENB ENB
0 The register value is not compared with the RHRCNT counter value.
1 The register value is compared with the RHRCNT counter value.
PM PM
0 a.m.
1 p.m.
Time Alarm Setting for a.m. or p.m..
HR10 10 Hours
Setting value for the tens place of hours
HR1 1 Hour
Setting value for the ones place of hours


Symbol 7 6 5 4 3 2 1 0
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9.2.13 Day-of-week alarm register (RWKAR)/binary counter 3 alarm register (BCNT3AR)

RWKAR is an alarm register corresponding to the coded day-of-week counter RWKCNT. When the ENB bit is set
to 1, the RWKAR value is compared with the RWKCNT value. From among the alarm registers (RSECAR,
RWKAR values from 0 through 6 (in BCD) can be specified; if a value outside of this range is specified, the RTC
Figure 9-21. Format of Day-of-Week Alarm Register (RWKAR)

Symbol 7 6 5 4 3 2 1 0
RWKAR ENB 0 0 0 0 DAYW
ENB ENB
0 The register value is not compared with the RWKCNT counter value.
1 The register value is compared with the RWKCNT counter value.
DAYW2 DAYW1 DAYW0 Day-of-Week Counting

0 0 0 Sunday
0 0 1 Monday
0 1 0 Tuesday
0 1 1 Wednesday
1 0 0 Thursday
1 0 1 Friday
1 1 0 Saturday
1 1 1 Setting Prohibited


Symbol 7 6 5 4 3 2 1 0
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9.2.14 Date alarm register (RDAYAR)/binary counter 0 alarm enable register (BCNT0AER)

RDAYAR is an alarm register corresponding to the BCD-coded date counter RDAYCNT. When the ENB bit is set to
1, the RDAYAR value is compared with the RDAYCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are
compared with the corresponding counters. When the respective values all match, the alarm flag (AF) of the RTC
status register (RSR) is set to 1.
RDAYAR values from 01 through 31 (in BCD) can be specified; if a value outside of this range is specified, the RTC
Figure 9-23. Format of Date Alarm Register (RDAYAR)

Symbol 7 6 5 4 3 2 1 0
RDAYAR ENB 0 DATE10 DATE1
ENB ENB
0 The register value is not compared with the RDAYCNT counter value.
1 The register value is compared with the RDAYCNT counter value.
DATE10 10 Days
Setting value for the tens place of days
DATE1 1 Days
Setting value for the ones place of days

The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b7 to b0. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are
set to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the alarm flag (AF) of
the RTC status register (RSR) is set to 1.
Figure 9-24. Format of Binary Counter 0 Alarm Enable Register (BCNT0AER)

Symbol 7 6 5 4 3 2 1 0
BCNT0AER ENB[7:0]
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9.2.15 Month alarm register (RMONAR)/binary counter 1 alarm enable register (BCNT1AER)

RMONAR is an alarm register corresponding to the BCD-coded month counter RMONCNT. When the ENB bit is
set to 1, the RMONAR value is compared with the RMONCNT value. From among the alarm registers (RSECAR,
RMONAR values from 01 through 12 (in BCD) can be specified; if a value outside of this range is specified, the
RTC does not operate correctly.
Figure 9-25. Format of Month Alarm Register (RMONAR)
Address: F059BH After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RMONAR ENB 0 0 MON10 MON1
ENB ENB
0 The register value is not compared with the RMONCNT counter value.
1 The register value is compared with the RMONCNT counter value.
MON10 10 Months
MON1 1 Month

Figure 9-26. Binary Counter 1 Alarm Enable Register (BCNT1AER)
Address: F059BH After reset: Undefined

Symbol 7 6 5 4 3 2 1 0
BCNT1AER ENB[15:8]
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9.2.16 Year alarm register (RYRAR)/binary counter 2 alarm enable register (BCNT2AER)

RYRAR is an alarm register corresponding to the BCD-coded year counter RYRCNT.
RYRAR values from 00 through 99 (in BCD) can be specified; if a value outside of this range is specified, the RTC
RYRAR can only be accessed with a 16-bit memory manipulation instruction.
Figure 9-27. Format of Year Alarm Register (RYRAR)
Address: F059CH After reset: Undefined R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RYRAR 0 0 0 0 0 0 0 0 YR10 YR1
YR10 10 Years
Setting value for the tens place of years
YR1 1 Year
Setting value for the ones place of years

counter b23 to b16. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which
are set to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the alarm flag (AF)
of the RTC status register (RSR) is set to 1.
BCNT2AER can only be accessed with a 16-bit memory manipulation instruction.
Address: F059CH After reset: Undefined

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCNT2AER 0 0 0 0 0 0 0 0 ENB[23:16]
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9.2.17 Year alarm enable register (RYRAREN)/binary counter 3 alarm enable register (BCNT3AER)

When the ENB bit in RYRAREN is set to 1, the RYRAR value is compared with the RYRCNT value. From among
the alarm registers (RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those
selected with the ENB bits set to 1 are compared with the corresponding counters. When the respective values all
match, the alarm flag (AF) of the RTC status register (RSR) is set to 1.
Figure 9-29. Format of Year Alarm Enable Register (RYRAREN)
Address: F059FH After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RYRAREN ENB 0 0 0 0 0 0 0
ENB ENB
0 The register value is not compared with the RYRCNT counter value.
1 The register value is compared with the RYRCNT counter value.

Address: F059FH After reset: Undefined

Symbol 7 6 5 4 3 2 1 0
BCNT3AER ENB[31:24]
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9.2.18 RTC control register 1 (RCR1)

The RCR1 register is used in both calendar count mode and in binary count mode.
Bits AIE, PIE, and PES are updated synchronously with the count source. When the RCR1 register is modified, check
that all the bits have been updated before proceeding to the next processing.
Figure 9-31. Format of RTC Control Register 1 (RCR1)
Address: F05A3H After reset: UndefinedNote R/W

Symbol 7 6 5 4 3 2 1 0
RCR1 PES RTCOS PIE 0 AIE
PES Periodic Interrupt Select
0110 A periodic interrupt is generated every 1/256 second.

1110 A periodic interrupt is generated every 1 second.
1111 A periodic interrupt is generated every 2 seconds.
Other than No periodic interrupts are generated.
above
These bits specify the period for the periodic interrupt. A periodic interrupt is generated with the period specified by
these bits.
RTCOS RTCOUT Output Select
0 RTCOUT outputs 1 Hz.

1 RTCOUT outputs 64 Hz.
This bit selects the RTCOUT output period. The RTCOS bit must be rewritten while count operation is stopped (the
RCR2.START bit is 0) and RTCOUT output is disabled (the RCR2.RTCOE bit is 0). When the RTCOUT is output to an
external pin, the RCR2.RTCOE bit must be enabled. About I/O ports, refer to CHAPTER 4 PORT FUNCTIONS.
PIE Periodic Interrupt Control

0 A periodic interrupt request is disabled.
1 A periodic interrupt request is enabled.
This bit enables or disabled a periodic interrupt.
AIE Alarm Interrupt Control
0 An alarm interrupt request is disabled.

1 An alarm interrupt request is enabled.
This bit enables or disables alarm interrupt requests.
<R> Note The setting of the RTCOS bit following the generation of a power-on reset signal is 0.
<R> Caution Be sure to set bit 1 to 0.

This register can only be accessed with an 8-bit memory manipulation instruction.
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The RCR2 register is related to hours mode, automatic adjustment function, enabling the RTCOUT output, 30-
second adjustment, RTC software reset, and controlling count operation.
Figure 9-32. Format of RTC Control Register 2 (RCR2) (In Calendar Count Mode) (1/3)

Symbol 7 6 5 4 3 2 1 0
RCR2 CNTMD HR24 AADJP AADJE RTCOE ADJ30 RESET START
CNTMD Count Mode Select
0 The calendar count mode.

1 The binary count mode.
This bit specifies whether the RTC count mode is operated in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings.
This bit is updated synchronously with the count source, and its value is fixed before the RTC software reset is
completed.
For details on initial settings, refer to 9.3.1 Outline of initial settings of registers after power on.
HR24 Hours Mode

0 The RTC operates in 12-hour mode.
1 The RTC operates in 24-hour mode.
This bit specifies whether the RTC will operate in 12- or 24-hour mode.
Use the START bit to stop counting by the counters before changing the value of the HR24 bit. Do not stop counting
(write 0 to the START bit) and change the value of the HR24 bit at the same time.
AADJP Automatic Adjustment Period Select
0 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute.
1 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds.
This bit selects the automatic-adjustment period.

Set the plus–minus bits (RADJ.PMADJ) to 00b (adjustment is not performed) before changing the value of the AADJP
bit.
The AADJP bit is set to 0 by an RTC software reset.
AADJE Automatic Adjustment Control
0 Automatic adjustment is disabled.

1 Automatic adjustment is enabled.
This bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ) to 00b (adjustment is not performed) before changing the value of the AADJE
bit.
The AADJE bit is set to 0 by an RTC software reset.
<R> Note The setting of the RESET, ADJ30, and RTCOE bits following the generation of a power-on reset signal is 0.
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Address: F05A5H After reset: UndefinedNote 1 R/W

Symbol 7 6 5 4 3 2 1 0
RTCOE RTCOUT Output Control
0 RTCOUT output disabled.

1 RTCOUT output enabled.
This bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting by the counters before changing the value of the RTCOE bit. Do not stop counting
(write 0 to the START bit) and change the value of the RTCOE bit at the same time.
When RTCOUT is to be output from an external pin, enable the RTCOE bit and set up the port control for the pin.
ADJ30 30-Second Adjustment Control
In writing
0 Writing is invalid.
1 30-second adjustment is executed.
In reading
0 In normal time operation, or 30-second adjustment has completed.
1 During 30-second adjustment
This bit is for 30-second adjustment.
When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the
value of 30 seconds or more is rounded up to 1 minute.
The 30-second adjustment is performed in synchronization with the count source. When 1 is written to this bit, the
ADJ30 bit is automatically set to 0 after the 30-second adjustment is completed. In case when 1 is written to the ADJ30
<R> bit, check that the bit is set to 0, and then make next settings. Additionally, be sure to maintain the value of the VRTCEN
bit as 1 until the 30-second adjustment is completed.
When the 30-second adjustment is performed, the prescaler and R64CNT are also reset.
The ADJ30 bit is set to 0 by an RTC software reset.
RESET RTC Software Reset Control
In writing
1 The prescaler and the target registers for RTC software resetNote 2 are initialized
In reading
0 In normal time operation, or an RTC software reset has completed.
1 During an RTC software reset
This bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, the initialization starts in synchronization with the count source. When the
initialization is completed, the RESET bit is automatically set to 0.
<R> When 1 is written to the RESET bit, check that the bit is set to 0, and then make next settings. Additionally, be sure to
maintain the value of the VRTCEN bit as 1 until the initialization is completed.
<R> Notes 1. The setting of the RESET, ADJ30, and RTCOE bits following the generation of a power-on reset signal is 0.
<R> 2. R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/
BCNT0AER, RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy,
RSECCPy/BCNT0CPy, RMINCPy/BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy,
RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP, RSR
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Symbol 7 6 5 4 3 2 1 0
START Prescaler and time counter operation control
0 Prescaler and time counter are stopped.

1 Prescaler and time counter operate normally.
This bit stops or restarts the prescaler or time counter operation.

The START bit is updated in synchronization with the next count source. When the START bit is modified, check that the bit
<R> has been updated before proceeding to the next processing. Additionally, be sure to maintain the value of the VRTCEN
bit as 1 until the bit is updated.
<R> Note The setting of the RESET, ADJ30, and RTCOE bits following the generation of a power-on reset signal is 0.
Caution This register can only be accessed with an 8-bit memory manipulation instruction.
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Figure 9-33. Format of RTC Control Register 2 (RCR2) (In Binary Count Mode) (1/2)

Symbol 7 6 5 4 3 2 1 0
RCR2 CNTMD 0 AADJP AADJE RTCOE 0 RESET START
CNTMD Count Mode Select

0 The calendar count mode.
1 The binary count mode.
This bit specifies whether the RTC count mode is operated in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings.
This bit is updated synchronously with the count source, and its value is fixed before the RTC software reset is
completed.
For details on initial settings, refer to 9.3.1 Outline of initial settings of registers after power on.
AADJP Automatic Adjustment Period Select

0 Adds or subtracts the RADJ.ADJ[5:0] bits from the prescaler count value every 32 seconds
1 Adds or subtracts the RADJ.ADJ[5:0] bits from the prescaler count value every 8 seconds
This bit selects the automatic-adjustment period.
Correction period can be selected from 32 second units or 8 second units in binary count mode.
Set the plus–minus bits (RADJ.PMADJ) to 00b (adjustment is not performed) before changing the value of the AADJP
bit.
The AADJP bit is set to 0 by an RTC software reset.
AADJE Automatic Adjustment Control

0 Automatic adjustment is disabled.
1 Automatic adjustment is enabled.
This bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ) to 00b (adjustment is not performed) before changing the value of the AADJE
bit.
The AADJE bit is set to 0 by an RTC software reset.
RTCOE RTCOUT Output Control

0 RTCOUT output disabled.
1 RTCOUT output enabled.
This bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting by the counters before changing the value of the RTCOE bit. Do not stop counting
(write 0 to the START bit) and change the value of the RTCOE bit at the same time.
When an RTCOUT signal is to be output from an external pin, enable the port control as well as setting this bit.
<R> Note The setting of the RESET and RTCOE bits following the generation of a power-on reset signal is 0.
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Figure 9-33. Format of RTC Control Register 2 (RCR2) (In Binary Count Mode) (2/2)
Address: F05A5H After reset: UndefinedNote 1 R/W

Symbol 7 6 5 4 3 2 1 0
RCR2 CNTMD 0 AADJP AADJE RTCOE 0 RESET START
RESET RTC Software Reset Control
In writing
1 The prescaler and the target registers for RTC software resetNote 2 are initialized
In reading
0 In normal time operation, or an RTC software reset has completed.
1 During an RTC software reset
This bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, the initialization starts in synchronization with the count source. When the
initialization is completed, the RESET bit is automatically set to 0.
<R> When 1 is written to the RESET bit, check that the bit is set to 0, and then make next settings. Additionally, be sure to
maintain the value of the VRTCEN bit as 1 until the initialization is completed.
START 32-bit binary counter, 64-Hz counter, and prescaler operation control
0 The 32-bit binary counter, 64-Hz counter, and prescaler are stopped.
1 The 32-bit binary counter, 64-Hz counter, and prescaler are in normal operation.
This bit stops or restarts the prescaler or counter (clock) operation.

The START bit is updated in synchronization with the count source. When the START bit is modified, check that the bit
<R> is updated, and then make next settings. Additionally, be sure to maintain the value of the VRTCEN bit as 1 until the bit
is updated.
<R> Notes 1. The setting of the RESET and RTCOE bits following the generation of a power-on reset signal is 0.
2. R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/
BCNT0AER, RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy,
RSECCPy/BCNT0CPy, RMINCPy/BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy,
<R> RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP, RSR
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The RCR3 register is used to select the time capture event input (RTCICn) pins enable/disable.
Address: F05A7H After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RCR3 0 0 0 0 0 0 0 RTCICEN
RCR3 RTCCRn
register register Time capture event input (RTCICn) enable/disable
RTCICEN TCEN
0 0 RTCICn input is disabled.

0 1 Setting prohibitedNote
1 0 RTCICn input is disabled.
1 1 RTCICn input is enabled.
RTCICEN bit (Time capture event input (RTCICn) control bit)

This bit is used to select the time capture event input (RTCICn) pins enable/disable.
When using the time capture event input function, be sure to set the TCEN bit to 1 after setting the RTCICEN bit to 1.
When not using the time capture event input function, set the RTCICEN bit to 0. However, the external interrupt function
of the RTCICn pin can be used, even when setting the RTCICEN bit to 0.
Note Setting the TCEN bit to 1 is prohibited when setting the RTCICEN to 0. When using the RTCICn pin, be sure to
set the TCEN bit to 1 after setting the RTCICEN bit to 1.
Caution Be sure to set bits 7 to 0 to “0”. This register can only be accessed with an 8-bit memory
manipulation instruction.
Remark n = 0 to 2
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The RCR4 register is used to select the count source clock. This register is a common function with the calendar count
mode and the binary count mode.
When the RCKSEL bit of the RCR4 register is set to “0”, the clock performs counting operation with the sub-clock (fSX).
Address: F05A9H After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 <0>
RCR4 0 0 0 0 0 0 0 RCKSEL
RCKSEL Selection of count source clock

0 Sub-clock (fSX)
1 Setting prohibited
Sub-clock (fSX) is selected as the count source. The count source can be selected only once before initial setting of the
registers for independent power supply RTC after power-on.
Caution Be sure to set the RCKSEL bit to 0. This register can only be accessed with an 8-bit memory

The RCR5 register is used to select the count source clock. This register is a common function with the calendar count
mode and the binary count mode.
Address: F05B3H After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RCR5 0 0 0 0 RCR5[3:0]
RCR5[3:0] Selection of realtime clock count source
0000 Select the sub clock (fSX) as a realtime clock count source
Other than Setting prohibited
above
The count source can be selected only once before initial setting of the registers for independent power supply RTC after
power-on. This register can be accessed only after register guard release with the RCR5GD register.
For details, refer to Figure 9-54 Outline of Initial Settings after Power On.
Caution Be sure to set the RCR5[3:0] bits to 0. This register can only be accessed with an 8-bit memory
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9.2.23 RCR5 guard register (RCR5GD)

The RCR5GD register is used to control the guard function for RTC control register 5 (RCR5).
Figure 9-37. Format of RCR5 Guard Register 5 (RCR5GD)
Address: F05B9H After reset: 00H W

Symbol 7 6 5 4 3 2 1 0
RCR5GD RCR5GD
RCR5GD Control of guard function for RTC control register 5 (RCR5)

When writing consecutively in order to 00H, 72H, 64H, RTC control register 5 (RCR5) can be accessed.
To activate the guard function, write 00H once.
And, this register is a write-only register. When this register is read, the read value is always 0.
9.2.24 Time error adjustment register (RADJ)

The RADJ register is used both in calendar count mode and in binary count mode.
Adjustment is performed by the addition to or subtraction from the prescaler.
In case when the automatic adjustment enable (RCR2.AADJE) bit is 0, adjustment is performed when writing to the
RADJ.
In case when the RCR2.AADJE bit is 1, adjustment is performed in the interval specified by the automatic adjustment
period select (RCR2.AADJP) bit.
The current adjustment by software (disabling automatic adjustment) may be invalid if the following adjustment value is
specified within 320 cycles of the count source after the register setting. To perform adjustment consecutively, wait for 320
cycles or more of the count source after the register setting and then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits have been
updated before continuing with further processing.
Figure 9-38. Format of Time Error Adjustment Register (RADJ)
Address: F05AFH After reset: Undefined R/W

Symbol 7 6 5 4 3 2 1 0
RADJ PMADJ ADJ
PMADJ Time Error Adjustment Operation Control
00 Adjustment is not performed.

01 Adjustment is performed by the addition to the prescaler.
10 Adjustment is performed by the subtraction from the prescaler.
These bits select whether the clock is set ahead or back depending on the error-adjustment value set in the ADJ bits.
ADJ Time Error Adjustment Value Setting
These bits specify the adjustment value (the number of sub-clock cycles) from the prescaler.
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9.2.25 Time capture control register y (RTCCRy) (y = 0 to 2)

The RTCCRy register is used both in calendar count mode and in binary count mode.
RTCCR0, RTCCR1, and RTCCR2 control the RTCIC0, RTCIC1, and RTCIC2 pins, respectively.
RTCCRy is updated in synchronization with the count source. When RTCCRy is modified, check that all the bits except
for the TCST bit have been updated before continuing with further processing.
Caution When the internal power supply voltage that VDD pin or VBAT pin was chosen by a battery backup
function is stopped, the RTC time capture becomes unusable even if the power is supplied from the
VRTC pin.
Figure 9-39. Format of Time Capture Control Register y (RTCCRy) (y = 0 to 2) (1/2)
Address: RTCCR0 F05C1H, RTCCR1 F05C3H, RTCCR2 F05C5H After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
RTCCRy TCEN 0 TCNF 0 TCST TCCT
TCEN Time Capture Event Input Pin Control
0 The RTCICn pin is disabled as the time capture event input.

1 The RTCICn pin is enabled as the time capture event input.
This bit enables or disables the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2).
When the sub-clock is selected (RCR4.RSCSRL bit = 0 and RCR3.RTCICEN bit = 0), the time capture event input pins
(RTCIC0, RTCIC1, and RTCIC2) are disabled regardless of the value of the TCEN bit.
When the functions of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2) are multiplexed, set the port
control and enable this bit. In this case, the port control should be set first. If the TCEN bit is set to 0, set also the TCCT
bits to 00b.
TCNF Time Capture Noise Filter Control
00 The noise filter is off.

10 The noise filter is on (count source).
11 The noise filter is on (count source by divided by 32).
These bits control the noise filter of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2).
When the noise filter is on, the count source divided by 1 or 32 is selectable by the combination with the RTCICNFEN
register. In this case, when the input level on the time capture event input pin matches three consecutive times at the set
sampling period, the input level is determined.
Set the TCNF bits while the TCCT bits are 00b (no event is detected). When the noise filter is used, set the TCNF[1:0]
bits, wait for three cycles of the specified sampling period, and then set the TCCT bits. Set the TCNF[1:0] bits when the
TCEN bit is 1.
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Figure 9-39. Format of Time Capture Control Register y (RTCCRy) (y = 0 to 2) (2/2)
Address: RTCCR0 F05C1H, RTCCR1 F05C3H, RTCCR2 F05C5H After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
RTCCRy TCEN 0 TCNF 0 TCST TCCT
TCST Time Capture Status
0 No event is detected.
1 An event is detected.
This bit indicates that an event of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2) has been detected.
When the TCST bit is 0, no event is detected.
When the TCST bit is 1, this bit indicates that an event of the corresponding pin has been detected and the capture
register is valid. When multiple events have been detected, the capture time for the first event is retained.
If an event is detected while the count operation is stopped (the RCR2.START bit is 0), the captured value is not
guaranteed. In this case, set the TCST bit to 0 for deleting the captured value.
Writing 0 sets the TCST bit to 0. In addition, writing any other value except 0 has no effect.
Set the TCST bit while the TCCT bits are 00b (no event is detected).
The TCST bit is set to 0 in synchronization with the count source. When the TCST bit is set to 0, check that the bit has
been updated before continuing with further processing.
TCCT Time Capture Control
00 No event is detected.
01 Rising edge is detected.
10 Falling edge is detected.
11 Both edges are detected.
These bits control the edge detection of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2). The
detection edge is selectable. The TCCT bits should be set while the TCEN bit is 1.
Note Indicates that an event has been detected. Writing 1 to this bit has no effect. Writing 0 sets this bit to 0.
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9.2.26 Second capture register y (RSECCPy) (y = 0 to 2)/BCNT0 capture register y (BCNT0CPy) (y = 0 to 2)

RSECCPy is a read-only register that captures the RSECCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RSECCP0,
RSECCP1, and RSECCP2 registers, respectively.
Before reading from this register, be sure to stop the time capture event detection through the setting of the
RTCCRy.TCCT[1:0] bits.
Figure 9-40. Format of Second Capture Register y (RSECCPy) (y = 0 to 2)
Address: RSECCP0 F05D3H, RSECCP1 F05E3H, RSECCP2 F05F3H After reset: Undefined R
Symbol 7 6 5 4 3 2 1 0
RSECCPy 0 SEC10 SEC1
SEC10 10-Second Capture
Capture value for the tens place of seconds
SEC1 1-Second Capture
Capture value for the ones place of seconds

BCNT0CPy is a read-only register that captures the BCNT0 value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT0CP0,
BCNT0CP1, and BCNT0CP2 registers, respectively.
Figure 9-41. Format of BCNT0 Capture Register y (BCNT0CPy) (y = 0 to 2)
Address: BCNT0CP0 F05D3H,BCNT0CP1 F05E3H, BCNT0CP2 F05F3H After reset: Undefined

Symbol 7 6 5 4 3 2 1 0
BCNT0CPy BCNTCPy
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9.2.27 Minute capture register y (RMINCPy) (y = 0 to 2)/BCNT1 capture register y (BCNT1CPy) (y = 0 to 2)

RMINCPy is a read-only register that captures the RMINCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMINCP0,
RMINCP1, and RMINCP2 registers, respectively.
Figure 9-42. Format of Minute Capture Register y (RMINCPy) (y = 0 to 2)
Address: RMINCP0 F05D5H, RMINCP1 F05E5H, RMINCP2 F05F5H After reset: Undefined R
Symbol 7 6 5 4 3 2 1 0
RMINCPy 0 MIN10 MIN1
MIN10 10-Minute Capture
Capture value for the tens place of minutes
MIN1 1-Minute Capture
Capture value for the ones place of minutes

Address: BCNT1CP0 F05D5H, BCNT1CP1 F05E5H, BCNT1CP2 F05F5H After reset: Undefined
Symbol 7 6 5 4 3 2 1 0
BCNT1CPy BCNTCPy
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9.2.28 Hour capture register y (RHRCPy) (y = 0 to 2)/BCNT2 capture register y (BCNT2CPy) (y = 0 to 2)

RHRCPy is a read-only register that captures the RHRCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RHRCP0,
RHRCP1, and RHRCP2 registers, respectively.
The PM bit is only enabled when the RCR2.HR24 bit is 0 (in 12-hour mode).
Figure 9-44. Format of Hour Capture Register y (RHRCPy) (y = 0 to 2)
Address: RHRCP0 F05D7H, RHRCP1 F05E7H, RHRCP2 F05F7H After reset: Undefined R
Symbol 7 6 5 4 3 2 1 0
RHRCPy 0 PM HR10 HR1
PM PM
0 a.m.
1 p.m.
HR10 10-Hour Capture
Capture value for the tens place of hours
HR1 1-Hour Capture
Capture value for the ones place of hours

Address: BCNT2CP0 F05D7H, BCNT2CP1 F05E7H, BCNT2CP2 F05F7H After reset: Undefined
Symbol 7 6 5 4 3 2 1 0
BCNT2CPy BCNTCPy
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9.2.29 Date capture register y (RDAYCPy) (y = 0 to 2)/BCNT3 capture register y (BCNT3CPy) (y = 0 to 2)

RDAYCPy is a read-only register that captures the RDAYCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RDAYCP0,
RDAYCP1, and RDAYCP2 registers, respectively.
Figure 9-46. Format of Date Capture Register y (RDAYCPy) (y = 0 to 2)
Address: RDAYCP0 F05DBH, RDAYCP1 F05EBH, RDAYCP2 F05FBH After reset: Undefined R
Symbol 7 6 5 4 3 2 1 0
RDAYCPy 0 0 DATE10 DATE1
DATE10 10-Day Capture
Capture value for the tens place of days
DATE1 1-Day Capture
Capture value for the ones place of days

The event detection times detected by the RTCTC0, RTCTC1, and RTCTC2 pins are stored in the BCNT3CP0,
Address: BCNT3CP0 F05DBH, BCNT3CP1 F05EBH, BCNT3CP2 F05FBH After reset: Undefined
Symbol 7 6 5 4 3 2 1 0
BCNT3CPy BCNTCPy
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9.2.30 Month capture register y (RMONCPy) (y = 0 to 2)

RMONCPy is a read-only register that captures the RMONCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMONCP0,
RMONCP1, and RMONCP2 registers, respectively.
Figure 9-48. Format of Month Capture Register y (RMONCPy) (y = 0 to 2)
Address: RMONCP0 F05DDH, RMONCP1 F05EDH, RMONCP2 F05FDH After reset: Undefined R
Symbol 7 6 5 4 3 2 1 0
RMONCPy 0 0 0 MON10 MON1
MON10 10-Month Capture
Capture value for the tens place of months
MON1 1-Month Capture
Capture value for the ones place of months
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9.2.31 RTC status register (RSR)

RSR is a flag register of the periodic interrupt, carry, and alarm. This register is a common function with the calendar
count mode and the binary count mode.
Each flag is set to 1 when the prescaler or the clock counter matches each interrupt setting condition. The prescaler,
clock counter, and the setting register of each interrupt are not reset, so each flag may be set before it is read.
Figure 9-49. Format of RTC Status Register (RSR)
Address:F05A1H After reset: 00HNote 1 R/W
Symbol 7 6 5 4 3 2 1 0
RSR 0 0 0 0 0 PF CF AF
PF Periodic interrupt flag
0 No interrupt occurs at a period that is set with RCR1.PES[3:0] bits

1 Interrupt occurs at a period that is set with RCR1.PES[3:0] bits Note 2
This flag indicates that the interrupt occurs at a period that is set with RCR1.PES[3:0] bits.
<R> This flag is set to “1” when the interrupt occurs.
<Clear condition>
● 0 is written to the PF flag.
<Set condition>
● Interrupt occurs at a period that is set with RCR1.PES[3:0] bits.
CF Carry flag
0 No carry of second counter/binary counter 0, and no carry of the 64 Hz counter when the 64 Hz counter
is reading
1 Carry of second counter/binary counter 0, or carry of the 64 Hz counter when the 64 Hz counter is
reading
During CF = 1, be sure to read again because the value which is read from the count register is not guaranteed.
<Clear conditions>
● 0 is written to the CF flag.
<Set condition>
● Carry of second counter/binary counter 0, or carry of the 64 Hz counter when the 64 Hz counter is reading
● 1 is written to the CF flag.
AF Alarm flag
0 The counter does not match the alarm registers

1 The counter matches the alarm registers Note 2
● This bit is set to 1 when the counter matches the alarm time set with the alarm registers (calendar count mode:
RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, RYRAR; binary count mode: BCNT0AR, BCNT1AR,
BCNT2AR, BCNT3AR) (only registers that the ENB bit is set to 1).
<Clear conditions>
● 0 is written to the AF flag.
<Set condition>
● The counter matches the alarm registers (only registers that the ENB bit is set to 1).
Notes 1. After reset is released, read value may be undefined.

2. Writing “1” to this bit is invalid.
(Cautions are listed on the next page.)
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<R> Cautions 1. Exclusively use either the alarm interrupt or periodic interrupt. Use the AIE and PIE bits of RTC
control register 1 (RCR1) instead of the AF and PF bits to judge whether the interrupt is an alarm
interrupt or periodic interrupt from within the interrupt processing routine.
<R> 2. In the case where only the alarm interrupt is in use, use the RTCAIF flag of the flag register (IF1H)
instead of the AF bit to generate the alarm interrupt.
<R> 3. In the case where only the periodic interrupt is in use, use the RTCRIF flag of the flag register
(IF1H) instead of the PF bit to generate the periodic interrupt.
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<R> 9.2.32 Sub clock operation mode control register (SCMC)

This register is used to set the operating mode of the XT1/P123 and XT2/EXCLKS/P124 pins, and to select the gain of
the oscillator.
After release from an RTC power-on reset or a reset from any other source, the SCMC register can be written only
once by an 8-bit memory manipulation instruction. This register can be read by an 8-bit memory manipulation instruction.
The SCMC register operates on the VRTC power-supply. Generation of the RTC power-on reset signal clears this
register to 00H. This register is not reset by other reset sources (including the power-on reset of the internal VDD power
supply).
Figure 9-50. Format of Sub Clock Operation Mode Control Register (SCMC)
Address: F0384H After reset: 00HNote R/W

Symbol 7 6 5 4 3 2 1 0
SCMC 0 0 EXCLKS OSCSELS 0 AMPHS1 AMPHS0 0
Subsystem clock pin

EXCLKS OSCSELS XT1/P123 pin XT2/EXCLKS/P124 pin
operation mode

0 1 XT1 oscillation mode Crystal oscillator connection
AMPHS1 AMPHS0 XT1 oscillator oscillation mode selection
0 0 Low-power consumption oscillation (default)

0 1 Normal oscillation
1 0 Ultra-low power consumption oscillation
Note The EXCLKS, OSCSELS, AMPHS1, and AMPHS0 bits are only initialized by an RTC power-on reset; they
retain their values following a reset due to another source (including the power-on reset of the internal VDD
power supply).
Cautions 1. After the CPU is released from the reset state, the SCMC register can be written only once by an
8-bit memory manipulation instruction. When using the SCMC register with its initial value (00H),
be sure to set the register to 00H after a reset ends in order to prevent malfunction due to a
program loop.
2. After the CPU is released from the reset state, set the SCMC register before XT1 oscillation is
started as set by the sub clock operation status control register (SCSC).
3. Specify the settings for the AMPHS1 and AMPHS0 bits while fIH is selected as fCLK after a reset
ends (before fCLK is switched to fMX).
4. Count the fXT oscillation stabilization time by using software.
5. After the CPU is released from the reset state following writing to the SCMC register and then a
reset other than an RTC power-on reset, set the same value as the value before the reset to
prevent incorrect operation in the case of an endless loop or runaway execution.
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Cautions 6. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
● Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation
evaluation using a circuit board to be actually used and confirm that there are no problems.
● When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the
mode of the XT1 oscillator, evaluate the resonators described in 6.7 Resonator and Oscillator
Constants.
● Make the wiring between the XT1 and XT2 pins and the resonators as short as possible,
and minimize the parasitic capacitance and wiring resistance. Note this particularly when the
ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
● Configure the circuit of the circuit board, using material with little parasitic capacitance and
wiring resistance.
● Place a ground pattern that has the same potential as VSS as much as possible near the
XT1 oscillator.
● Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross
with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
to moisture absorption of the circuit board in a high-humidity environment or dew
condensation on the board. When using the circuit board in such an environment, take
measures to damp-proof the circuit board, such as by coating.
● When coating the circuit board, use material that does not cause capacitance or leakage
between the XT1 and XT2 pins.
7. Be sure to clear bits 7, 6, 3, and 0 to 0.
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<R> 9.2.33 Sub clock operation status control register (SCSC)

This register is used to control the operation of the sub clock.
The SCSC register can be set by a 1-bit or an 8-bit memory manipulation instruction.
The SCSC register operates on the VRTC power-supply.
Generation of the RTC power-on reset signal sets this register to 40H.
Figure 9-51. Format of Sub Clock Operation Status Control Register (SCSC)

Symbol 7 <6> 5 4 3 2 1 0
SCSC 0 XTSTOP 0 0 0 0 0 0
XTSTOPNote Control of XT1 oscillator operation
XT1 oscillation mode: XT1 oscillator operating

0 External clock input mode: External clock from EXCLKS pin is valid.
XT1 oscillation mode: XT1 oscillator stopped
1 External clock input mode: External clock from EXCLKS pin is invalid.
Note The XTSTOP bit is only initialized by an RTC power-on reset; it retains its value following a reset due to another
source (including the power-on reset of the internal VDD power supply).
Cautions 1. When starting XT1 oscillation by setting the XTSTOP bit, use software to wait for oscillation of
the sub clock to become stable.
2. Be sure to clear the bits 7 and 5 to 0 to 0.
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9.2.34 RTC power-on-reset status register (RTCPORSR)

The RTCPORSR register is used to check the occurrence of an RTC Power-on reset.
Writing 1 to bit 0 (RTCPORF) of the RTCPORSR register enables this function. Writing 0 disables this function.
Write 1 to the RTCPORF bit in advance to enable checking of the occurrence of an RTC power-on reset.
The RTCPORSR register can be set by an 8-bit memory manipulation instruction.
<R> The RTCPORSR register operates on the VRTC power-supply.
Generation of the RTC power-on reset signal clears this register to 00H.
Cautions 1. The RTCPORSR register is reset only by an RTC power-on reset; it retains the value when a reset
caused by another source occurs.
<R> 2. The RTCPORSR register is readable and writable while the VRTCEN bit is “1”.
Figure 9-52. Format of RTC Power-on-reset Status Register (RTCPORSR)

Symbol 7 6 5 4 3 2 1 0
RTCPORSR 0 0 0 0 0 0 0 RTCPORF
RTCPORF Checking occurrence of RTC Power-on reset
0 RTC power-on reset has occurred.

1 No RTC power-on reset has occurred.
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9.2.35 Time capture event input noise filter enable register (RTCICNFEN)
The RTCICNFEN register is used to set the noise filter can be used for the input signal from the RTCICn (n = 0 to 2)
pins.
When the noise filter is enabled, after selection of whether RTC count source (fXT) divided by 212 or 213 performed with
the operation clock (fMCK) of the target channel, 3-clock match detection is performed.
The RTCICNFEN register can be set by an 8-bit memory manipulation instruction.
Caution The RTCICNFEN register is reset only by an RTC power-on reset; it retains the value when a reset
Figure 9-53. Format of Time Capture Event Input Noise Filter Enable Register (RTCICNFEN)

Symbol 7 6 5 4 3 2 1 0
RTCICNFEN 0 RTCIC2NF1 RTCIC1NF1 RTCIC0NF1 0 RTCIC2NF0 RTCIC1NF0 RTCIC0NF0
RTCIC2NF1 RTCIC2NF0 Use of noise filter of RTCIC2 pin
0 0 Noise filter OFF
0 1
1 0 Noise filter ON (RTC count source (fSX) divided by 212 = 250 ms)
0 1
0 1
Cautions 1. Be sure to clear bits 7 and 3 to 0.

2. Set the RTCICNFEN register while the TCCT bits are 00b (no event is detected). When the noise
filter is used, set the RTCICNFEN register, wait for three cycles of the specified sampling period,
and then set the TCCT bits. Set the RTCICNFEN register when the TCEN bit is 1.
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9.3 Operation
9.3.1 Outline of initial settings of registers after power on

After the power is turned on, the initial settings for the clock setting, count mode setting, time error adjustment, time
setting, alarm, interrupt, and time capture control register should be performed.
Figure 9-54. Outline of Initial Settings after Power On
Power on
Initialization Initialization of setting registers
Clock and count mode settings Clock supply setting and count mode setting
Time setting in the clock counter and initial

Set the time setting of the time error adjustment register
Set the alarm Initial setting of the alarm register
Set the interrupt Initial setting of the interrupt control register
Remark The minimum operating voltage of VDD is 1.7 V or 1.9 V, although the minimum operating voltage of VRTC is
1.6 V.
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9.3.2 Initialization procedure

Figure 9-55 shows an initialization procedure.
Figure 9-55. Initialization Procedure
VRTCEN=1 setting
(PER2 register) Enables to supply clock to RTC
Initialization of all registers for RTC
Releases guard function of RCR5 register

Writing 00h, 72h, and 64h, to RCR5GD register
Writing 00h to RCR5 register Selects sub-clock (fsx) as count source of RTC
Writing 00h to RCR5GD register Activates guard function of RCR5 register
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9.3.3 Clock and count mode setting procedure

Figure 9-56 shows how to set the clock and the count mode.
Figure 9-56. Clock and Count Mode Setting Procedure
Select the count source (fSX) Set the RCR4.RCKSEL bit Note 3
Set the RTCICn input (n = 0 to 2) Set the RCR3.RTCICEN bit
Supply 6 clocks of the count source
Set the START bit to 0
No
START = 0 Note 4 Wait for the RCR2.START bit to become 0
Yes
Select count mode RCR2.CNTMD bit setting Notes 1, 2
Execute RTC software reset Write 1 to the RCR2.RESET bit Note 2
No
RESET = 0 Note 4 Wait for the RCR2.RESET bit to become 0
Yes
Notes 1. This step is not necessary if the count mode has been set concurrently with setting the START bit to 0.
2. Rewriting the RCR2 register with a way of read-modify-writing is prohibited.
3. Be sure to clear the RCR4.RCKSEL bit to 0.
<R> Z 4. Be sure to maintain the value of the VRTCEN bit as 1.
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9.3.4 Setting the time procedure

Figure 9-57 shows how to set the time.
Figure 9-57. Setting the Time
Set the START bit to 0 Write 0 to the RCR2.START bit
No Wait for the RCR2.START bit to become 0

START = 0 Note 2
Yes
Execute the prescaler and R64CNT Write 1 to the RCR2.RESET bit Note 1
reset
No Wait for the RCR2.RESET bit to become 0

RESET = 0 Note 2
Yes
Set the year, month, day of the week,

date, hour, minute, and second/ Settings in arbitrary order is possible
binary counters 3 to 0
Set clock error adjustment values Set clock error adjustment values
Set the START bit to 1 Write 1 to the RCR2.START bit
No
START = 1 Note 2 Wait for the RCR2.START bit to become 1
Yes
Notes 1. This step is not necessary for the time-setting procedure because an RTC software reset
is executed in the clock setting procedure of the initial settings for the power supply.
<R> 2. Be sure to maintain the value of the VRTCEN bit as 1.
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9.3.5 30-second adjustment procedure

Figure 9-58 shows how to execute 30-second adjustment.
Figure 9-58. 30-Second Adjustment Procedure
Execute 30-second adjustment while the clock is in operation

Clock is in operation
(the RCR2.START bit is 1)
Set the RCR2.ADJ30 bit to 1 Write 1 to the RCR2.ADJ30 bit
No
ADJ30 = 0 Note Wait for the RCR2.ADJ30 bit to become 0
Yes
<R> Note Be sure to maintain the value of the VRTCEN bit as 1 until the 30-second adjustment is completed.
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9.3.6 Reading 64-Hz counter and time

Figure 9-59 shows how to read the 64-Hz counter and time.
Figure 9-59. Reading Time
To read the time without using interrupt
Clear the carry flag to 0 Write 0 to the RSR.CF bit
Read the Counter register Read all of the necessary counter register
Yes
Carry flag = 1? Note Read and check the RSR.CF bit
No
<R> Note The carry flag (CF) will not be set to 1 while the VRTCEN bit is 0. The VRTCEN bit must be 1 for the carry
flag (CF) to be read.
If a carry occurs while the 64-Hz counter and time are being read, the correct time will not be obtained, so they must be
read again. The procedure for reading the time without using interrupts is shown in Figure 9-59.
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9.3.7 Alarm function

Figure 9-60 shows how to use the alarm function.
Figure 9-60. Using Alarm Function
Clock running Check that the count is in operation

(the RCR2.START bit is 1)
Write 0 to the AIE bit of RCR1 register for avoiding

Disable the alarm interrupt request wrong interrupt.
Set alarm enable at the same time as or after the

Set alarm time alarm time setting
Set the RCR1.PES[3:0] bits to 1000b to wait for periodic

Wait for the completion of the alarm time
interrupts twice
setting
Clear the alarm flag, since the AF bit of RSR may have
Clear the alarm flag been set while the alarm time was being set.
Enable the alarm interrupt request Write 1 to the AIE bit of RCR1 register
Monitor alarm time Wait for alarm interrupt or set the AF bit of RSR to 1.
(wait for interrupt or check alarm flag)
In calendar count mode, an alarm can be generated by any one of year, month, date, day-of-week, hour, minute or
second, or any combination of those. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set
the alarm time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting.
In binary count mode, an alarm can be generated in any bit combination of 32 bits. Write 1 to the ENB bit of the alarm
enable register corresponding to the target bit of the alarm, and set the alarm time to the alarm register. For bits that are
not target of the alarm, write 0 to the ENB bit of the alarm enable register.
When the counter and the alarm time match, the alarm flag (AF) of the RTC status register (RSR) is set to 1. Alarm
detection can be confirmed by reading this bit, but an interrupt should be used in most cases. If 1 has been set in the
interrupt request enable bit corresponding to the ALM interrupt, an alarm interrupt is generated in the event of alarm,
enabling the alarm to be detected.
Writing 0 clear the alarm flag (AF) of the RTC status register (RSR).
<R> When the counter and the alarm time match in standby mode, the MCU returns from standby mode.
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9.3.8 Procedure for disabling alarm interrupt

Figure 9-61 shows the procedure for disabling the enabled alarm interrupt request.
Figure 9-61. Procedure for Disabling Alarm Interrupt Request
Enable the alarm interrupt The RCR1.AIE bit register has been set to 1
Disable the alarm interrupt Write 1 to the interrupt mask flag (RTCAMK)
Disable the alarm interrupt request of

Write 0 to the RCR1.AIE bit
the RTC
No
AIE bit = 0 Wait for the RCR1.AIE bit to be cleared to 0
Yes
Until the RCR1.AIE bit becomes 0, set the alarm flag

Set the alarm flag to 0 to 0 after confirming that the alarm flag (AF) of the
RTC status register (RSR) has become 1
Clear the alarm interrupt request to 0 Write 0 to the alarm interrupt request (RTCAIF)
9.3.9 Time error adjustment function

The time error adjustment function is used to correct errors (running fast or slow) in the time due to the precision of
oscillation by the sub-clock. Since 32,768 cycles of the sub-clock constitute 1 second of operation when the sub-clock is
selected, the clock runs fast if the sub-clock frequency is high and slow if the sub-clock frequency is low. This function can
be used to correct errors due to the clock running fast or slow.
Two types of time error adjustment functions are provided: automatic adjustment and adjustment by software.
Use the RCR2.AADJE bit to select automatic adjustment or adjustment by software.
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9.3.9.1 Automatic adjustment

Enable automatic adjustment by setting the RCR2.AADJE bit to 1.
Automatic adjustment is the addition or subtraction of the value counted by the prescaler to or from the value in the
RADJ register every time the adjustment period selected by the RCR2.AADJE bit elapses.
Examples are shown below.
[Example 1] Sub-clock running at 32.769 kHz

Adjustment procedure:
When the sub-clock is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant to run at
32,768 clock cycles, so the clock runs fast by one clock cycle every second. The time on the clock is fast by 60 clock
cycles per minute, so adjustment can take the form of setting the clock back by 60 cycles every minute.
Register settings: (when RCR2.CNTMD = 0)

● RCR2.AADJP = 0 (adjustment every minute)
● RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler.)
● RADJ.ADJ[5:0] = 60 (3Ch)

32,768 clock cycles, so the clock runs slow by two clock cycles every second. The time on the clock is slow by 20
clock cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10
seconds.
Register settings: (when RCR2.CNTMD = 0)

● RCR2.AADJP = 1 (adjustment every 10 seconds)
● RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler.)
● RADJ.ADJ[5:0] = 20 (14h)

At 32.764 kHz, 1 second elapses on 32,764 clock cycles. Since the RTC operates for 32,768 clock cycles as 1 second,
the clock is delayed for four clock cycles per second. In 8 seconds, the delay is 32 clock cycles, so correction can be
made by proceeding the clock for 32 clock cycles every 8 seconds.
Register settings when the RCR2.CNTMD bit is 1

● RCR2.AADJP = 1 (adjustment every 8 seconds)
● RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler.)
● RADJ.ADJ[5:0] = 32 (20h)
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9.3.9.2 Adjustment by software

Enable adjustment by software by setting the RCR2.AADJE bit to 0.
Adjustment by software is the addition or subtraction of the value counted by the prescaler to or from the value in the
RADJ register at the time of execution of an instruction for writing to the RADJ register.
An example is shown below.

32,768 clock cycles, so the clock runs fast by one clock cycle every second. The time on the clock is fast by one clock
cycle per second, so adjustment can take the form of setting the clock back by one cycle every second.
Register settings:
● RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler.)
● RADJ.ADJ[5:0] = 1 (01h)
This is written to the RADJ register once per 1-second interrupt.
9.3.9.3 Procedure for changing the mode of adjustment

When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the
RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
Changing from adjustment by software to automatic adjustment:

(1) Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
(2) Set the RCR2.AADJE bit to 1 (automatic adjustment is enabled).
(3) Use the RCR2.AADJP bit to select the period of adjustment.
(4) In RADJ, set the PMADJ[1:0] bits for addition or subtraction and the ADJ[5:0] bits to the value for use in time error
adjustment.
Changing from adjustment by software to automatic adjustment:

(1) Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
(2) Set the RCR2.AADJE bit to 0 (adjustment by software is enabled).
(3) Proceed with adjustment by setting the RADJ.PMADJ[1:0] bits for addition or subtraction and the RADJ.ADJ[5:0]
bits to the value for use in time error adjustment at the desired time. After that, the time is adjusted every time a
value is written to the RADJ register.
9.3.9.4 Procedure for stopping adjustment

Stop adjustment by setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
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9.3.9.5 Time capture function

The RTC is capable of storing the month, date, hour, minute and second/binary counters 3 to 0 by detecting an edge of
a signal on a time capture event input pin.
A noise filter can also be used on a time capture event input pin. If the noise filter is enabled, the TCST bit is set to 1
when the input level on the pin matches three times.
The noise filter can be switched on or off for each of the time capture event input pins. Operation when the noise filter
is off is shown in and operation when the noise filter is on is shown in Figure 9-63.
Figure 9-62. Timing of a Time Capture Function Operation (with the Filter Off)
Count source
RTCICn (n = 0 to 2)
Internal event-input signal
Time counters AAAA BBBB
Capture register 0 AAAA
TCST
Detection of the No capturing when

rising edge TCST = 1
Figure 9-63. Timing of a Time Capture Function Operation (with the Filter On)
Count source
RTCICn (n = 0 to 2)
Internal event-input signal (1) (2) (1) (2) (1) (2) (3)
Since the level has matched three
Since the level has only matched times, it is conveyed to the internal
twice, it is not conveyed to the circuits.
internal circuits.
Internal event-detection signal
Time counters AAAA BBBB
Capture register 0 BBBB
TCST
Detection of the rising edge
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9.3.10 Noise filter operation for RTCICn pin (n = 0 to 2)

The RTCICn pin (n = 0 to 2) can be used as the RTC time capture event input. A noise filter for the RTCICn pin is
incorporated to prevent an unnecessary time capturing caused by chattering of the RTCICn pin. A sampling clock is
selected with the RTCICnNF0 bit of the RTCICNFEN register. The RTCICn pin input signal is sampled, and it can pass
when matching with the detection level three times continuously.
Example of noise filter operation is shown in Figure 9-64.
Figure 9-64. Noise Filter Operation
250 ms or 500 ms
RTCICn
(Noise filter input)
Sampling timing
(fXT/212 or fXT/213)
When three times of high levels are not detected
consecutively, the input signal is considered to be
a noise.
RTCICn
(Noise filter output)
When three times of low levels are not detected
consecutively, the input signal is considered to be
(n = 0 to 2) a noise.
When three times of low levels are detected When three times of high levels are detected
consecutively, the low level is passed. consecutively, the high level is passed.
Setting of the noise filter for the RTCICn pin can be selected with two registers (RTCICNFEN and RTCCRn.TCNF1-0).
A setting list is shown in the following table.
Table 9-4. Noise Filter Operation for RTCICn Pin (n = 0 to 2)
RCR3 RTCCRn RTCICNFEN

Noise filter setting for RTCICn pin
RTCICEN TCNF1 TCNF0 RTCICnNF1 RTCICnNF0
0 0 0 0 x RTCICn pin input is invalid.

0 x Noise filter OFF
0 0 1 0 Noise filter ON (RTC count source divided by 212)
0 1 1 Noise filter ON (RTC count source divided by 213)
1 0 0 0 Noise filter ON (RTC count source)
1 1 0 0 Noise filter ON (RTC count source divided by 32)
Remark n = 0 to 2
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9.4 Interrupt Sources
There are three interrupt sources in the realtime clock. Table 9-5 lists interrupt sources for the RTC.
Table 9-5. RTC Interrupt Sources
Name Interrupt Sources
INTRTCALM Alarm interrupt (ALM)

INTRTCPRD Periodic interrupt (PRD)
(1) Alarm interrupt (ALM)

This interrupt is generated according to the result of comparison between the alarm registers and realtime clock
counters (for details, refer to 9.3.7 Alarm function).
Since there is a possibility that the interrupt flag may be set to 1 when the settings of the alarm registers match the
clock counters, wait for the alarm time settings to be confirmed and clear the alarm flag (AF) of the RTC status
register (RSR) to 0 again after modifying values of the alarm registers. Once the interrupt flag for the alarm
interrupt has been set to 1 and the state has returned to non-matching of the alarm registers and clock counters,
the flag will not be set again until there is a further match or the values of the alarm registers are modified again.
Figure 9-65. Timing Chart for the Alarm Interrupt (ALM)
Sequence for setting the alarm
Alarm-register settings Wait until the alarm

in progress time setting is
confirmed
Alarm registers
Clock counters
Match while settings are being made
Alarm flag
Flag clearing by Alarm interrupt

software accepted
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(2) Periodic interrupt (PRD)

This interrupt is generated at intervals of 2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second,
1/32 second, 1/64 second, 1/128 second, or 1/256 second. The interrupt interval can be selected through the
RCR1.PES[3:0] bits.
<R> 2. In the case where only the periodic interrupt is in use, use the RTCRIF flag of the flag register
(IF1H) instead of the PF bit to generate the periodic interrupt.
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9.5 Event Link Output
The RTC outputs the following event signals for the event link controller (ELC), and these can be used to initiate
operations by other modules selected in advance.
(1) Periodic event output

The periodic event signal is output at the interval selected from among 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2,
1, and 2 seconds by the setting of the RCR1.PES[3:0] bits.
The event generation period immediately after the event generation is selected is not guaranteed.
Caution If event linking from the RTC is to be used, only make the ELC settings after making the RTC
settings (initialization, time settings, etc.). Making the RTC settings after the ELC settings can
lead to the output of unexpected event signals.
9.5.1 Interrupt handling and event linking

The RTC has a bit to enable or disable periodic interrupts. An interrupt request signal is output for the CPU when an
interrupt source is generated while the corresponding enable bit is enabled.
In contrast, an event link output signal is sent to other modules as an event signal via the ELC when an interrupt source
is generated, regardless of the setting of the corresponding interrupt enable bit.
Caution Although alarm and periodic interrupts can still be output during STOP mode, the periodic event
signals for the ELC are not output.
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9.6 Usage Notes
9.6.1 Register writing during counting

The following registers should not be written to during counting (while the RCR2.START bit = 1).
RSECCNT/BCNT0, RMINCNT/BCNT1, RHRCNT/BCNT2, RDAYCNT, RWKCNT/BCNT3, RMONCNT, RYRCNT,

RCR1.RTCOS, RCR2.RTCOE, RCR2.HR24
The counter must be stopped before writing to any of the above registers.
9.6.2 Use of periodic interrupts

The procedure for using periodic interrupts is shown in Figure 9-66.
The generation and period of the periodic interrupt can be changed by the setting of the RCR1.PES[3:0] bits. However,
since the prescaler, R64CNT, and RSECCNT/BCNT0 are used to generate interrupts, the interrupt period is not
guaranteed immediately after setting of the RCR1.PES[3:0] bits.
Furthermore, stopping/restarting or resetting counter operation, reset by RTC software, and the 30-second adjustment
by changing the RCR2 value affects the interrupt period. When the time error adjustment function is used, the interrupt
generation period after adjustment is added or subtracted according to the adjustment value.
Figure 9-66. Using Periodic Interrupt Function
Set the RCR1.PES[3:0] bits and

Set the period and enable interrupt requests
write 1 to the RCR1.PIE bit
The period
is not
guaranteed.
The first interrupt is generated Confirm generation of the first periodic interrupt Note
Interrupts
are The set period elapses
generated
with the
specified
period. An interrupt is generated Confirm generation of a periodic interrupt
Note When a interrupt generation period is changed while the periodic interrupt is used, an interrupt
may be generated at the completion of the setting. If the interrupt is generated immediately after
the setting, the period is not guaranteed for two interrupts including the current interrupt.
9.6.3 RTCOUT (1-Hz/64-Hz) clock output

Stopping/restarting or resetting counter operation, reset by RTC software, and the 30-second adjustment by changing
the RCR2 value affects the period of RTCOUT (1-Hz/64-Hz) output. When the time error adjustment function is used, the
period of RTCOUT (1-Hz/64-Hz) output after adjustment is added or subtracted according to the adjustment value.
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<R>
<R> 9.6.4 Notes when writing to and reading from registers
● When reading a counter register such as the second counter after having written to the counter register, follow the
procedure in 9.3.6 Reading 64-Hz counter and time.
● Values written to the count registers, alarm registers, year alarm enable register, AADJE, AADJP, and HR24 bits of
the RCR2 register, RCR3 register, RCR4 register, or RCR5 register will be read correctly from the 4th cycle of the
CPU clock (fCLK) after writing.
● Values written to the SCMC, SCSC, RTCPORSR, RTCICNFEN, and RSR registers, RCR1.RTCOS and
RCR2.RTCOE bits can be read immediately after writing.
● In the case of reading the time from the time counters (R64CNT, RxxxCNT/BCNTn) in any of the following situations,
wait for 1/128 of a second while the time counter is operating (RCR2.START bit = “1”) before reading the time.
- After return from a reset state other than the RTC power-on reset and RTC software reset states
- After return from the power-on reset state
- After return from STOP mode
- After return from HALT mode while the RTCLPC bit is 1 and the CPU is being driven by the subsystem clock (fSUB)
- After changing the setting of the VRTCEN bit from 0 to 1
● After a reset is generated, write to the RTC register when six cycles of the count source clock have elapsed.
When the power supply from the VRTC pin is stopped, setting an RTC related register is prohibited.
9.6.5 Changing the count mode

When changing the count mode (calendar/binary), set the RCR2.START bit to 0, stop counting operation, then start
again from the initial setting. For details on initial setting, refer to 9.3.1 Outline of initial settings of registers after
power on.
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9.6.6 Stop procedure

<R> The operation of the realtime clock with independent power supply is undefined immediately after release from the RTC
power-on reset state.
When it is not used, stop it according to following procedure shown in Figure 9-67.
Figure 9-67. Stop Setting Procedure
Select the count source (fSX) Set the RCR4.RCKSEL bit Note 3
Set the RTCICn input (n = 0 to 2) Set the RCR3.RTCICEN bit
Set the START bit to 0 Note 2
No
START = 0 Wait for the RCR2.START bit to become 0
Yes
Select count mode RCR2.CNTMD bit setting Notes 1, 2
Execute RTC software reset Write 1 to the RCR2.RESET bit Note 2
No
RESET = 0 Wait for the RCR2.RESET bit to become 0
Yes
<R> Disable interrupt request Set the AIE and PIE bits of the RCR1 to 0.
Notes 1. This step is not necessary if the count mode has been set concurrently with setting the START bit to 0.
2. Rewriting the RCR2 register with a way of read-modify-writing is prohibited.
3. Be sure to clear the RCR4.RCKSEL bit to 0.
9.6.7 Caution of shortwave detection function

When supply voltage from the VDD or VBAT type supply voltage pins is shut off, the shortwave detection (RTCICn)
function cannot be used.
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RL78/I1C CHAPTER 10 FREQUENCY MEASURE CIRCUIT
CHAPTER 10 FREQUENCY MEASURE CIRCUIT
10.1 Frequency Measurement Circuit
The frequency measurement circuit is used to measure the frequency of the sub clock (fSX) or low-speed on-chip
oscillator clock (fIL), by inputting the high-accuracy reference clock externally.
10.2 Configuration of Frequency Measurement Circuit
The frequency measurement circuit includes the following hardware.
Table 10-1. Configuration of Frequency Measurement Circuit
Item Configuration
Counter Counter (32-bit)

Control registers Peripheral enable register 1 (PER1)
Frequency measurement count register L (FMCRL)
Frequency measurement count register H (FMCRH)
Frequency measurement control register (FMCTL)
Frequency measurement clock select register (FMCKS)
Figure 10-1 shows the frequency measurement circuit diagram.
Figure 10-1. Frequency Measurement Circuit Diagram
Bus
FMS
28/fSX or 28/fIL Selector
Frequency
to measurement FMCRH FMCRL INTFM
circuit
215/fSX or 215/fIL
fMX, fIH, or fIM
FMDIV2 to
FMDIV0
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10.3 Registers Controlling Frequency Measurement Circuit
The frequency measurement circuit is controlled by the following registers.

● Frequency measurement count register L (FMCRL)
● Frequency measurement count register H (FMCRH)
● Frequency measurement control register (FMCTL)
● Frequency measurement clock select register (FMCKS)
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This register is used to enable or disable supplying the clock to the register used for the frequency measurement circuit.
Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Of the registers that are used to control the frequency measurement circuit can be set by setting bit 6 (FMCEN) of this
register to 1.

Symbol 7 <6> 5 4 <3> 2 1 <0>
FMCEN Control of frequency measurement circuit input clock supply

● SFR used by the frequency measurement circuit cannot be written. The read value is 00H.
● The frequency measurement circuit and SFR are in the reset state.
● SFR used by the frequency measurement circuit can be read and written.

Bits 7, 5, 4, 2, and 1
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The OSMC register can be set by a 1-bit or 8-bit memory manipulation instruction.

Symbol <7> 6 5 <4> 3 2 1 0

circuit
measurement circuit
1 Low-speed on-chip oscillator Low-speed on-chip oscillator
Clock output is prohibited. Note 4
clock (fIL)Notes 2, 3, 5, 6 clock (fIL) selectedNote 5
Notes 1. Be sure to clear bits 6, 5, and 3 to 0 to 0.

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10.3.3 Frequency measurement count register L (FMCRL)

This register represents the lower 16 bits of the frequency measurement count register (FMCR) in the frequency
The FMCRL register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears the FMCRL register to 0000H.
Figure 10-4. Format of Frequency Measurement Count Register L (FMCRL)
Address:F0312H After reset: 0000H R

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCRL
Cautions 1. Do not read the value of FMCRL when FMS = 1.

2. Read the value of FMCRL after the frequency measurement complete interrupt is generated.
10.3.4 Frequency measurement count register H (FMCRH)

This register represents the upper 16 bits of the frequency measurement count register (FMCR) in the frequency
The FMCRH register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears the FMCRH register to 0000H.
Figure 10-5. Format of Frequency Measurement Count Register H (FMCRH)
Address: F0314H After reset: 0000H R

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCRH
Cautions 1. Do not read the value of FMCRH when FMS = 1.

2. Read the value of FMCRH after the frequency measurement complete interrupt is generated.
Figure 10-6. Frequency Measurement Count Register (FMCRH, FMCRL)
31 16 15 0
FMCR FMCRH FMCRL
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10.3.5 Frequency measurement control register (FMCTL)

The FMCTL register is used to set the operation of the frequency measurement circuit. This register is used to start
operation and set the period of frequency measurement.
The FMCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the FMCTL register to 00H.
Figure 10-7. Format of Frequency Measurement Control Register (FMCTL)

Symbol <7> 6 5 4 3 2 1 0
FMCT FMS 0 0 0 0 FMDIV2 FMDIV1 FMDIV0
FMS Frequency measurement circuit operation enable
0 Stops the frequency measurement circuit.

1 Operates the frequency measurement circuit.
Starts counting on the rising edge of the operating clock and stops counting on the next rising edge of the
operating clock.
FMDIV2 FMDIV1 FMDIV0 Frequency measurement period setting

0 0 0 28/fSX or 28/fIL (7.8125 ms)
0 0 1 29/fSX or 29/fIL (15.625 ms)
0 1 0 210/fSX or 210/fIL (31.25 ms)
0 1 1 211/fSX or 211/fIL (62.5 ms)
1 0 0 212/fSX or 212/fIL (0.125 s)
1 0 1 213/fSX or 213/fIL (0.25 s)
1 1 0 214/fSX or 214/fIL (0.5 s)
1 1 1 215/fSX or 215/fIL (1s)
Caution Do not read the value of the FMDIV2 to FMDIV0 bits when FMS = 1.
Remark The frequency measurement resolution can be calculated by the formula below.
● Frequency measurement resolution = 106/(frequency measurement period × reference clock frequency
(fMX) [Hz]) [ppm]
Example 1) When FMDIV2 to FMDIV0 = 000B and fMX = 20 MHz, measurement resolution = 6.4 ppm
Example 2) When FMDIV2 to FMDIV0 = 111B and fMX = 1 MHz, measurement resolution = 1 ppm
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10.3.6 Frequency measurement clock select register (FMCKS)

The FMCKS register is used to select the operating clock and frequency count clock to be input to the frequency
The FMCKS register can be used by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the FMCKS register to 00H.
Figure 10-8. Format of Frequency Measurement Clock Select Register (FMCKS)
Address: F007AH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
FMCKS 0 0 0 0 0 0 FMCKSEL1 FMCKSEL0
FMCKSEL1 FMCKSEL0 Selection of frequency count clock

0 0 fMX selected
0 1 fIM selected
1 × fIH selected
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10.4 Frequency Measurement Circuit Operation
10.4.1 Setting frequency measurement circuit

Set frequency measurement circuit after setting 0 to FMS first.
Figure 10-9. Procedure for Setting Frequency Measurement Circuit Using Reference Clock
Start
High-speed system clock

oscillator operating
FMCEN = 1 Enables writing to registers.
FMS = 0 Stops frequency measurement circuit.
Setting FMDIV2 to FMDIV0 Measures frequency measurement period.
Enables operation of frequency

FMS = 1
No
INTFM = 1 ?
Reading counters Reads frequency measurement count register (L/H).
FMCEN = 0 Disables writing to registers.
Frequency calculation
Caution After the frequency measurement count register (L/H) is read, be sure to set FMCEN to 0.
The fSX or fIL oscillation frequency is calculated by using the following expression.
Reference clock frequency [Hz] × operation trigger division ratio

fSX or fIL oscillation frequency = [Hz]
Frequency measurement count register value (FMCR)
For example, when the frequency is measured under the following conditions
● Count clock frequency: fMX = 10 MHz
● Frequency measurement period setting register: FMDIV2 to FMDIV0 = 111B (operation trigger division ratio: 215)
and the measurement result is as follows,

● Frequency measurement count register: FMCR = 10000160D
the fSX or fIL oscillation frequency is obtained as below.
(10 × 106) × 215

fSX or fIL oscillation frequency = = 32767.47572 [Hz]
10000160
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10.4.2 Frequency measurement circuit operation timing

The operation timing of the frequency measurement circuit is shown in Figure 10-10.
After the frequency measurement circuit operation enable bit (FMS) is set to 1, counting is started by the count start
trigger set with the frequency measurement period setting bits (FMDIV2 to FMDIV0) and stopped by the next trigger. After
counting is stopped, the count value is retained, and the frequency measurement circuit operation enable bit (FMS) is
reset to 0. An interrupt is also generated for one clock of fSX or fIL. After the operation of the frequency measurement
circuit is completed (FMS = 0) and the frequency measurement count register (L/H) is read, be sure to set bit 6 (FMCEN)
of peripheral enable register 1 to 0.
Figure 10-10. Frequency Measurement Circuit Operation Timing
Write Write
Bit 6 (FMCEN) of
peripheral enable register 1
Frequency Write
measurement circuit
operation enable bit
(FMS)
fSX or fIL
Count start/stop trigger

(About 0.5 to 128 Hz)
Count start Count stop
Reference clock
(fMX, fIH, fIM: 1 to 32 MHz)
Frequency
measurement count 0 1 2 3 4 5 6 7 00989720H 00000000H
register (FMCR)
Interrupt (INTFM)
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RL78/I1C CHAPTER 11 12-BIT INTERVAL TIMER
CHAPTER 11 12-BIT INTERVAL TIMER
11.1 Functions of 12-bit Interval Timer
An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP
mode and triggering an A/D converter’s SNOOZE mode.
11.2 Configuration of 12-bit Interval Timer
The 12-bit interval timer includes the following hardware.
Table 11-1. Configuration of 12-bit Interval Timer
Item Configuration
Counter 12-bit counter

Peripheral reset control register 2 (PRR2)
12-bit interval timer control register (ITMC)
Figure 11-1. Block Diagram of 12-bit Interval Timer
Clear
Count
Selector
fSX clock Count operation

12-bit counter
control circuit
fIL
Interrupt request signal

Match signal (INTIT)
WUTMM
RINTE ITMCMP11 to ITMCMP0
CK0
Subsystem clock supply 12-bit interval timer control
option control register
(OSMC) register (ITMC)
Internal bus
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11.3 Registers Controlling 12-bit Interval Timer
The 12-bit interval timer is controlled by the following registers.

● 12-bit interval timer control register (ITMC)

This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
When the 12-bit interval timer is used, be sure to set bit 7 (TMKAEN) of this register to 1.

Symbol <7> <6> 5 4 3 <2> 1 <0>
TMKAEN Control of 12-bit interval timer input clock supply

● SFR used by the 12-bit interval timer cannot be written. The read value is 00H. However, the SFR is
not initialized. Note
● SFR used by the 12-bit interval timer can be read and written.
Note To initialize the 12-bit interval timer and the SFR used by the 12-bit interval timer, use bit 7 (TMKARES) of PRR2.

Bits 5 to 3 and 1
assigned to PER2 is stopped (except for FMCEN).
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This register is used for individual reset control of each peripheral hardware.
This MCU controls reset and reset release of each peripheral hardware supported by the PRR2 register.
To reset the 12-bit interval timer, be sure to set bit 7 (TMKARES) to 1.
Figure 11-3. Format of Peripheral Reset Control Register 2 (PRR2)
Address: F00FDH After reset: 00H R/W

Symbol <7> <6> 5 4 3 <2> 1 0
PRR2 TMKARES OSDCRES 0 0 0 MACRES 0 0
TMKARES Reset control of 12-bit interval timer

0 12-bit interval timer reset release
1 12-bit interval timer reset state
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The WUTMMCK0 bit can be used to select the 12-bit interval timer operation clock.
The OSMC register can be set by an 8-bit memory manipulation instruction.

Symbol <7> 6 5 <4> 3 2 1 0

circuit
measurement circuit
Low-speed on-chip oscillator Low-speed on-chip oscillator
1 Clock output is prohibited. Note 4
clock (fIL)Notes 2, 3, 5, 6 clock (fIL) selectedNote 5
Notes 1. Be sure to clear bits 6, 5, and 3 to 0 to 0.

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11.3.4 12-bit interval timer control register (ITMC)

This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer
compare value.
The ITMC register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0FFFH.
Figure 11-5. Format of 12-bit Interval Timer Control Register (ITMC)
Address: FFF90H After reset: 0FFFH R/W

Symbol 15 14 13 12 11 to 0
ITMC RINTE 0 0 0 ITCMP11 to ITCMP0
RINTE 12-bit interval timer operation control

0 Count operation stopped (count clear)
1 Count operation started
ITCMP11 to ITCMP0 Specification of the 12-bit interval timer compare value

001H These bits generate a fixed-cycle interrupt (count clock cycles × (ITCMP setting + 1)).
●
●
●
FFFH
000H Setting prohibit
Example interrupt cycles when 001H or FFFH is specified for ITCMP11 to ITCMP0
● ITCMP11 to ITCMP0 = 001H, count clock: when fSUB = 32.768 kHz
1/32.768 [kHz] × (1 + 1) = 0.06103515625 [ms]  61.03 [µs]
● ITCMP11 to ITCMP0 = FFFH, count clock: when fSUB = 32.768 kHz
1/32.768 [kHz] × (4095 + 1) = 125 [ms]
Cautions 1. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the
INTIT interrupt servicing. When the operation starts (from 0 to 1) again, clear the TMKAIF flag,
and then enable the interrupt servicing.
2. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit.
3. When setting the RINTE bit after returned from standby mode and entering standby mode again,
confirm that the written value of the RINTE bit is reflected, or wait that more than one clock of the
count clock has elapsed after returned from standby mode. Then enter standby mode.
4. Only change the setting of the ITCMP11 to ITCMP0 bits when RINTE = 0.
However, it is possible to change the settings of the ITCMP11 to ITCMP0 bits at the same time as
when changing RINTE from 0 to 1 or 1 to 0.
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11.4 12-bit Interval Timer Operation
11.4.1 12-bit interval timer operation timing

The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate a 12-bit interval timer that
repeatedly generates interrupt requests (INTIT).
When the RINTE bit is set to 1, the 12-bit counter starts counting.
When the 12-bit counter value matches the value specified for the ITCMP11 to ITCMP0 bits, the 12-bit counter value is
cleared to 0, counting continues, and an interrupt request signal (INTIT) is generated at the same time.
The basic operation of the 12-bit interval timer is as follows.
Figure 11-6. 12-bit Interval Timer Operation Timing (ITCMP11 to ITCMP0 = 0FFH, count clock: fSUB = 32.768 kHz)
Count clock
RINTE
Counting starts at the rising edge of the first cycle of
the count clock signal after the RINTE bit is set to 1.
0FFH
12-bit counter
000H
The 12-bit counter is cleared
asynchronously with the count
clock signal when the RINTE bit is
cleared to 0
ITCMP11 to ITCMP0 0FFH
INTIT
Period (7.81 ms)
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11.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode
When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1
to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Then, enter HALT or STOP mode.
● After setting RINTE to 1, confirm by polling that the RINTE bit has become 1, and then enter HALT or STOP mode
(see Example 1 in Figure 11-7).
● After setting RINTE to 1, wait for at least one cycle of the count clock and then enter HALT or STOP mode (see
Example 2 in Figure 11-7).
Figure 11-7. Procedure of Entering to HALT or STOP Mode after Setting RINTE to 1
Example 1 Example 2
Return from HALT mode Return from HALT mode

Return from STOP mode Return from STOP mode
RINTE = 1 Count operation is started. RINTE = 1

At least one cycle of the
count clock after returned
from HALT or STOP
Confirm count operation Wait for at least one cycle
RINTE = 1? mode
No is started. of the count clock
Yes
HALT instruction executed Enter HALT or HALT instruction executed Enter HALT or
STOP instruction executed STOP mode STOP instruction executed STOP mode
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CHAPTER 12 8-BIT INTERVAL TIMER
The 8-bit interval timer has two 8-bit timers (channel 0 and channel 1) which operate independently. These timers can
be connected to operate as a 16-bit timer.
The 8-bit interval timer contains two units, 8-bit interval timer_0 and 8-bit interval timer_1, which have the same function.
This chapter describes these units as the 8-bit interval timer unless there are differences among them.
12.1 Overview
The 8-bit interval timer is an 8-bit timer that operates using the fSX or fIL clock that is asynchronous with the CPU. Table
12-1 lists the 8-bit interval timer specifications and Figure 12-1 shows the 8-bit interval timer block diagram.
Table 12-1. 8-Bit Interval Timer Specifications
Item Description
Count source ● fSX, fSX/2, fSX/4, fSX/8, fSX/16, fSX/32, fSX/64, fSX/128
(operating clock) ● fIL, fIL/2, fIL/4, fIL/8, fIL/16, fIL/32, fIL/64, fIL/128
Operating mode ● 8-bit counter mode
Channel 0 and channel 1 operate independently as an 8-bit counter
● 16-bit counter mode
Channel 0 and channel 1 are connected to operate as a 16-bit counter
Interrupt ● Output when the counter matches the compare value
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Figure 12-1. 8-Bit Interval Timer Block Diagram
Channel 0
Data bus
Channel 0
Compare register (8-bit) Interrupt signal
(INTITn0)
TSTARTn0 Clear
fSX, fSX/m or Counter source

Counter register (8-bit)
fIL, fIL/m
Channel 1
Data bus
Channel 1
TSTARTn1
1 Counter source Interrupt signal
fSX, fSX/m or Compare register (8-bit) (INTITn1)
fIL, fIL/m 0
Clear
TCSMDn
Counter register (8-bit)
TCKn0 [2:0]
Division register (8-bit)
TCKn1 [2:0]
TSTARTni (i = 0, 1), TCSMDn, TCLKENn: Bits in TRTCRn register

TCKni [2:0]: Bit in TRTMDn register
Remark m = 2, 4, 8, 16, 32, 64, 128
n = 0, 1
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12.2 I/O Pins
The 8-bit interval timer does not have an I/O pin.
12.3 Registers
Table 12-2 lists the 8-bit interval timer register configuration.
Table 12-2. Registers
Item Configuration
Control registers 8-bit interval timer counter register 00 (TRT00)Note 1
8-bit interval timer counter register 01 (TRT01)Note 1
8-bit interval timer compare register 00 (TRTCMP00)Note 1
8-bit interval timer control register 0 (TRTCR0)
8-bit interval timer division register 0 (TRTMD0)
8-bit interval timer control register 1 (TRTCR1)
8-bit interval timer division register 1 (TRTMD1)
Notes 1. Can be accessed only when the TCSMDn bit in the TRTCRn register = 0.
2. Can be accessed only when the TCSMDn bit in the TRTCRn register = 1.
Remark n = 0, 1
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12.3.1 8-bit interval timer counter register ni (TRTni) (n = 0, 1, i = 0, 1)

This is the 8-bit interval timer counter register. It is used as a counter that counts up based on the count clock.
The TRTni register can be set by an 8-bit memory manipulation instruction.
Figure 12-2. Format of 8-bit Interval Timer Counter Register ni (TRTni)
Address: F0540H (TRT00), F0541H (TRT01), F0548H (TRT10), F0549H (TRT11) After reset: 00H RNotes 1, 2
Symbol 7 6 5 4 3 2 1 0
TRTni
Notes 1. The TRTni register is set to 00H two cycles of the count clock after the compare register TRTCMPni is
write-accessed. Refer to 12.4.4 Timing for updating compare register values.
2. Can be accessed only when the mode select bit (TCSMDn) in the 8-bit interval timer control register n
(TRTCRn) is 0.
12.3.2 8-bit interval timer counter register n (TRTn) (n = 0, 1)

This is a 16-bit counter register when the 8-bit interval timer is used in 16-bit interval timer mode.
The TRTn register can be set by a 16-bit memory manipulation instruction.
Figure 12-3. Format of 8-bit Interval Timer Counter Register n (TRTn)
Address: F0540H (TRT0), F0548H (TRT1) After reset: 0000H RNotes 1, 2
F0541H (TRT01) F0540H (TRT00)

F0549H (TRT11) F0548H (TRT10)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRTn
Notes 1. The TRTn register is set to 0000H two cycles of the count clock after the compare register TRTCMPn is
write-accessed. Refer to 12.4.4 Timing for updating compare register values.
(TRTCRn) is 0.
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12.3.3 8-bit interval timer compare register ni (TRTCMPni) (n = 0, 1, i = 0, 1)

This is the 8-bit interval timer compare value register.
The TRTCMPni register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
The setting range is 01H to FFHNote 1.
This register is used to store the compare value of registers TRTn0 and TRTn1 (counters).
Write-access clears the count value (TRTn0, TRTn1) to 00H.
Refer to 12.4.4 Timing for updating compare register values for the timing of rewriting the compare value.
Figure 12-4. Format of 8-bit Interval Timer Compare Register ni (TRTCMPni)
Address: F0350H (TRTCMP00), F0351H (TRTCMP01), After reset: FFH R/WNotes 1, 2

F0358H (TRTCMP10), F0359H (TRTCMP11)
Symbol 7 6 5 4 3 2 1 0
TRTCMPni
Notes 1. The TRTCMPni register must not be set to 00H.

(TRTCRn) is 0.
12.3.4 8-bit interval timer compare register n (TRTCMPn) (n = 0, 1)

This is a compare value register when the 8-bit interval timer is used in 16-bit interval timer mode. The TRTCMPn
register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to FFFFH. The setting is 0001H to FFFFHNote 1.
This register is used to store the compare value of the TRTn register (counter).
Write-access clears the count value (TRTn) to 0000H.
Refer to 12.4.4 Timing for updating compare register values for the timing of rewriting the compare value.
Figure 12-5. Format of 8-bit Interval Timer Compare Register n (TRTCMPn)
Address: F0350H (TRTCMP0), F0358H (TRTCMP1) After reset: FFFFH R/WNote 2
F0351H (TRTCMP01) F0350H (TRTCMP00)

F0359H (TRTCMP11) F0358H (TRTCMP10)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRTCMPn
Notes 1. The TRTCMPn register must not be set to 0000H.

(TRTCRn) is 1.
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12.3.5 8-bit interval timer control register n (TRTCRn) (n = 0, 1)

This register is used to start and stop counting by the 8-bit interval timer and to switch between using the 8-bit interval
timer as an 8-bit counter or a 16-bit counter.
The TRTCRn register can be set by a 1-bit or 8-bit manipulation instruction.
Reset signal generation resets this register to 00H.
Figure 12-6. Format of 8-bit Interval Timer Control Register n (TRTCRn)
Address: F0352H (TRTCR0), F035AH (TRTCR1) After reset: 00H R/WNote 3

Symbol 7 6 5 4 3 <2> 1 <0>
TRTCRn TCSMDn 0 0 TCLKENn 0 TSTARTn1 0 TSTARTn0
TCSMDn Mode select
0 Operates as 8-bit counter

1 Operates as 16-bit counter (channel 0 and channel 1 are connected)
Refer to 12.4 Operation for details.
TCLKENn 8-bit interval timer clock enableNote 1
0 Clock is stopped
1 Clock is supplied
TSTARTn1 8-bit interval timer 1 count startNotes 1, 2

0 Count stops
1 Count starts
In 8-bit interval timer mode, writing 1 to the TSTARTn1 bit starts the TRTn1 count and writing 0 stops the count.
In 16-bit interval timer mode, this bit is invalid because it is not used. Refer to 12.4 Operation for details.
TSTARTn0 8-bit interval timer 0 count startNotes 1, 2
0 Count stops
1 Count starts
In 8-bit interval timer mode, writing 1 to the TSTARTn0 bit starts the TRTn0 count and writing 0 stops the count.
In 16-bit interval timer mode, writing 1 to the TSTARTn0 bit starts the TRTn count and writing 0 stops the count.
Refer to 12.4 Operation for details.
Notes 1. Be sure to set the TCLKENn bit to 1 before setting the 8-bit interval timer. To stop the clock, set TSTARTn0
and TSTARTn1 to 0 and then set the TCLKENn bit to 0 after one or more cycles of the operating clock (fSX
or fIL) have elapsed. Refer to 12.5.3 8-bit interval timer setting procedure for details.
2. Refer to 12.5.1 Changing settings of operating mode for the notes on using bits TSTARTn0, TSTARTn1,
and TCSMDn.
3. Bits 6, 5, 3, and 1 are read-only. When writing, write 0. When reading, 0 is read.
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12.3.6 8-bit interval timer division register n (TRTMDn) (n = 0, 1)

This register is used to select the division ratio of the count source used by the 8-bit interval timer.
The TRTMDn register can be set by an 8-bit memory manipulation instruction.
Figure 12-7. Format of 8-bit Interval Timer Division Register n (TRTMDn)
Address: F0353H (TRTMD0), F035BH (TRTMD1) After reset: 00H R/WNote 4

Symbol 7 6 5 4 3 2 1 0
TRTMDn — TCKn1 — TCKn0
TCKn1
8-bit interval timer 1 division selectNotes 1, 2, 3
Bit 6 Bit 5 Bit 4
0 0 0 fSX or fIL
0 0 1 fSX/2 or fIL/2
1 0 0 fSX/16 or fIL/16
1 0 1 fSX/32 or fIL/32
1 1 0 fSX/64 or fIL/64
1 1 1 fSX/128 or fIL/128
In 8-bit interval timer mode, TRTn1 counts using the count source set in TCKn1.
In 16-bit interval timer mode, set these bits to 000 because they are not used. Refer to 12.4 Operation for details.
TCKn0
8-bit interval timer 0 division selectNotes 1, 2, 3
Bit 2 Bit 1 Bit 0
0 0 0 fSX or fIL
1 0 0 fSX/16 or fIL/16
1 0 1 fSX/32 or fIL/32
1 1 0 fSX/64 or fIL/64
1 1 1 fSX/128 or fIL/128
In 8-bit interval timer mode, TRTn0 counts using the count source set in TCKn0.
In 16-bit interval timer mode, TRTn counts using the count source set in TCKn0. Refer to 12.4 Operation for details.
Notes 1. Do not switch the count source during count operation. When switching the count source, set these bits
while the TSTARTni bit in the TRTCRn register is 0 (count stops).
2. Set TCKni of the unused channel to 000B.
3. Be sure to set the TCKni (i = 0, 1) bit before setting the TRTCMPni register.
4. Bits 7 and 3 are read-only. When writing, write 0. When reading, 0 is read.
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12.4 Operation
12.4.1 Count mode

The following two modes are supported: 8-bit counter mode and 16-bit counter mode. Table 12-3 lists the registers and
settings used in 8-bit counter mode and Table 12-4 lists the registers and settings used in 16-bit counter mode.
Table 12-3. Registers and Settings Used in 8-Bit Counter Mode
Register Name (Symbol) Bit Function
8-bit interval timer counter register n0 (TRTn0) b7 to b0 8-bit counter of channel 0.

The count value can be read.
8-bit interval timer counter register n1 (TRTn1) b7 to b0 8-bit counter of channel 1.
8-bit interval timer compare register n0 b7 to b0 8-bit compare value of channel 0.
(TRTCMPn0) Set the compare value.
8-bit interval timer compare register n1 b7 to b0 8-bit compare value of channel 1.
(TRTCMPn1) Set the compare value.
8-bit interval timer control register n (TRTCRn) TSTARTn0 Select whether to start/stop the count of channel 0.
TSTARTn1 Select whether to start/stop the count of channel 1.
TCLKENn Set to 1.
TCSMDn Set to 0.
8-bit interval timer division register n TCKn0 Select the count clock of channel 0.
(TRTMDn)
TCKn1 Select the count clock of channel 1.
Remark n = 0, 1
Table 12-4. Registers and Settings Used in 16-Bit Counter Mode
Register Name (Symbol) Bit Function
8-bit interval timer counter register n (TRTn) b15 to b0 16-bit counter.

8-bit interval timer compare register n b15 to b0 16-bit compare value.
(TRTCMPn) Set the compare value.
8-bit interval timer control register n TSTARTn0 Select whether to control starting/stopping the count.
(TRTCRn) TSTARTn1 Set to 0.
TCLKENn Set to 1.
TCSMDn Set to 1.
8-bit interval timer division register n TCKn0 Select the count clock.
(TRTMDn)
TCKn1 Set to 000B.
Remark n = 0, 1
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12.4.2 Timer operation

The counter is incremented by the count source selected by the TCKni (n = 0, 1, i = 0, 1) bit in the division register
(TRTMDn). The count value is decremented each time the count source is input. After the count value is set to the
compare value, the value is compared and matched when the next count source is input, and then an interrupt is
generated. The interrupt request is output with a single pulse that is synchronized with the count source. Note that the
interrupt request continues to be generated when the TSTARTni bit in the TRTCRn register is set to 0 and counting is
stopped at 00h.
When operation is stopped, the counter continues retaining the count value immediately before operation is stopped.
To clear the count value, set the compare value in the TRTCMPni register again. After the TRTCMPni register is written,
the count value is cleared after two cycles of the count source.
Figure 12-8. Example of Timer Operation
Count source
Value in TRTni register
The compare value is rewritten
m
Time
Count Count
stops restarts
TSTARTni bit
in TRTCRn register m+1 p+1
Initialization
Compare match
interrupt request
Compare register m p
Remark n = 0, 1 i = 0, 1 m, p: Values set in TRTCMPni register
However, the initial 00H count interval when starting count varies as follows according to the timing 1 is written in the
TSTARTni (i = 0, 1) bit of the TRTCR register.
● When the count source (fSX or fIL) is selected

Maximum: Two cycles of the count source
Minimum: One cycle of the count source
● When the count source (fSX/2m or fIL/2m) is selected
Maximum: One cycle of the count source
Minimum: One cycle of the selected clock (fSX or fIL)
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When the count value matches the compare value, the count value is cleared by the next count source. When the
compare value in the TRTCMPni register is rewritten, the count value is also cleared two cycles of the count source after
writing.
Table 12-5 lists the interrupt sources in 8-bit/16-bit count mode.
Table 12-5. Interrupt Sources in 8-Bit/16-Bit Count Mode
Interrupt Name 8-Bit Count Mode Source 16-Bit Count Mode Source
Rising edge of the next count source after compare Rising edge of the next count source after compare
INTITn0
match of channel 0 match
Rising edge of the next count source after compare Not generated
INTITn1
match of channel 1
Remark n = 0, 1
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12.4.3 Start/stop timing
12.4.3.1 When count source (fSX) is selected

After 1 is written to the TSTARTni (n = 0, 1, i = 0, 1) bit in the TRTCRn register, the count is started by the next sub
clock (fSX), and then the counter is incremented from 00H to 01H by the next count source (fSX). Likewise, after 0 is written
to the TSTARTni bit, the count is stopped after the counter is incremented by the sub clock (fSX). Figure 12-9 shows the
timing for starting/stopping count operation, and Figure 12-10 shows the timing of count stop → compare setting (count
clearing) → count start. Figure 12-9 and Figure 12-10 show the update timing in 8-bit counter mode, but operation is
performed at the same timing even in 16-bit counter mode.
Figure 12-9. Example of Count Start/Stop Operation (fSX Selected)
Write 01H (TSTARTni = 1) Write 56H to Write 00H (TSTARTni = 0) Write 01H (TSTARTni = 1)
to the TRTCRni register the TRTCMPni register to the TRTCRn register to the TRTCRn register
by a program by a program by a program by a program
Count source
Register write clock
TSTARTni bit
in TRTCRn register Count stops Count restarts
TRTCMPni register 34H 56H
Compare register (chi) 34H 56H
Counter (chi) 00H 01H ... 33H 34H 00H 01H ... 33H 34H 00H 01H 02H 03H 00H 01H ... 23H 24H 25H 26H 27H
Compare match
interrupt (chi)
The TCSMDn bit in the TRTCRn register is set to 0 (8-bit counter operation)
Remark n = 0, 1 i = 0, 1
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Figure 12-10. Example of Count Stop → Count Clearing → Count Start Operation (fSX Selected)
Write 01H (TSTARTni = 1) Write 00H (TSTARTni = 0) Write 56H to the Write 01H (TSTARTni = 1)
to the TRTCRni register to the TRTCRn register TRTCMPni register to the TRTCRn register
Count source
(fSX)
TSTARTni bit
Count starts Count stops Count clears Count starts
in TRTCRn register
Counter (chi) 00H 01H 33H 34H 00H 01H 20H 21H 22H 00H 01H 55H 56H 00H 01H
Compare match
interrupt (chi)
Remark n = 0, 1 i = 0, 1
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12.4.3.2 When count source (fSX/2m) is selected

After 1 is written to the TSTARTni (n = 0, 1, i = 0, 1) bit in the TRTCRn register, the count is started with the next sub
clock (fSX), and then the counter is incremented from 00H to 01H by the next count source (fSX/2m). Likewise, after 0 is
written to the TSTARTni bit, the count is stopped with the sub clock (fSX).
However, the first period to count 00H when the timer starts counting is shorter than one cycle of the count source as
below, depending on the timing for writing to the TSTARTni bit and the timing of the next count source.
Minimum: One cycle of the sub clock (fSX)
Maximum: One cycle of the count source
Figure 12-11 shows the timing for starting/stopping count operation, and Figure 12-12 shows the timing of count stop
→ compare setting (count clearing) → count start. Figure 12-11 and Figure 12-12 show the update timing in 8-bit counter
mode, but operation is performed at the same timing even in 16-bit counter mode.
Figure 12-11. Example of Count Start/Stop Operation (fSX/2m Selected)
Write 01H (TSTARTni = 1) Write 56H to the Write 00H (TSTARTni = 0) Write 01H (TSTARTni = 1)
to the TRTCRni register TRTCMPni register to the TRTCRn register to the TRTCRn register
fSX
Count source
(fSX/24)
TSTARTni bit
in TRTCRn register Count stops Count restarts
Counter (chi) 00H 01H 02H 33H 34H 00H 01H 33H 34H 00H 01H 02H 03H 00H 01H 23H 24H 25H 26H 27H
Compare match
interrupt (chi)
Remark n = 0, 1 i = 0, 1
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Figure 12-12. Example of Count Stop → Count Clearing → Count Start Operation (fSX/2m Selected)
Write 01H (TSTARTni = 1) Write 00H (TSTARTni = 0) Write 56H to the Write 01H (TSTARTni = 1)
to the TRTCRni register to the TRTCRn register TRTCMPni register to the TRTCRn register
fSX
Count source
(fSX/24)
TSTARTni bit
Count starts Count stops Count clears Count starts
in TRTCRn register
Counter (chi) 00H 01H 02H 33H 34H 00H 01H 02H 03H 00H 01H 55H 56H 00H 01H
Compare match
interrupt (chi)
Remark n = 0, 1 i = 0, 1
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12.4.4 Timing for updating compare register values

The timing for updating the value of the TRTCMPni (n = 0, 1, i = 0, 1) register is the same, regardless of the value of
the TSTARTni bit in the TRTCRn register. After TRTCMPni is write-accessed, the value is stored in the compare register
after two cycles of the count source. When stored in the compare register, the count value is cleared and set (8-bit count
mode: 00H, 16-bit count mode: 0000H).
Figure 12-13 shows the timing of rewrite operation. This figure shows the update timing in 8-bit count mode, but
operation is performed at the same timing in 16-bit count mode.
Figure 12-13. Timing of Compare Value Rewrite Operation
Write 34H to the TRTCMPni register

by a program
TRTCMPni register FFH 34H
Count source
Compare register FFH 34H
Counter F7H F8H 00H 01H 02H
Remark n = 0, 1 i = 0, 1
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12.5 Notes on 8-Bit Interval Timer
12.5.1 Changing settings of operating mode

The settings of bits TCSMDn and TCKni (n = 0, 1, i = 0, 1) must be changed while the TSTARTni bit in the TRTCRn
register is 0 (count stops). After the value of the TSTARTni bit is rewritten from 1 to 0 (count stops), allow at least one
cycle of fSX or fIL to elapse before accessing the registers (TRTCRn and TRTMDn) associated with the 8-bit interval timer.
12.5.2 Accessing compare registers

Do not write to the same compare registers (TRTCMPn0, TRTCMPn1, and TRTCMPn) successively. When writing
successively, allow at least two cycles of the count source between writes.
Writing to the compare register (TRTCMPn0, TRTCMPn1, TRTCMPn) must proceed while the source to drive counting
is made to oscillate by setting the 8-bit interval timer clock enable bit (TCLKENn) to 1.
12.5.3 8-bit interval timer setting procedure

To supply the clock, set the 8-bit interval timer clock enable bit (TCLKENn) in the 8-bit interval timer control register
(TRTCRn) to 1 and then set the TSTARTni bit. Do not set bits TCLKENn and TSTARTni at the same time.
To stop the clock, set TSTARTni to 0 and then allow at least one cycle of fSX or fIL to elapse before setting the TCLKENn
bit to 0.
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RL78/I1C CHAPTER 13 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CHAPTER 13 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
13.1 Functions of Clock Output/Buzzer Output Controller
The clock output controller is intended for clock output for supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
The PCLBUZn pin outputs a clock selected by clock output select register n (CKSn).
Figure 13-1 shows the block diagram of clock output/buzzer output controller.
Remark n = 0, 1
Figure 13-1. Block Diagram of Clock Output/Buzzer Output Controller
Internal bus
Clock output select register 1 (CKS1)
PCLOE1 0 0 0 CSEL1 CCS12 CCS11 CCS10
fMAIN Prescaler
PCLOE1
5 3 fMAIN/211 to fMAIN/213
Selector
Clock/buzzer
fMAIN to fMAIN/24 controller PCLBUZ1 Note 1/P41 Note 2
fSX to fSX/27
Output latch PM41
fMAIN/211 to fMAIN/213 (P41 Note 2) Note 2
Selector
fMAIN to fMAIN/24
Clock/buzzer
controller PCLBUZ0 Note 1/P43 Note 2
fSX to fSX/27
8 8
PCLOE0 Output latch PM43
fSX Prescaler Note 2
(P43) Note 2
PCLOE0 0 0 0 CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Notes 1. For output frequencies available from PCLBUZ0 and PCLBUZ1, refer to 41.4 AC Characteristics.
2. The port mode register (PMxx) and port register (Pxx) to be set depend on the product and the setting of the
peripheral I/O redirection register 0 (PIOR0).
For details, see 4.5 Register Settings When Using Alternate Function.
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13.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 13-1. Configuration of Clock Output/Buzzer Output Controller
Item Configuration
Control registers Clock output select registers n (CKSn)
Port mode registers 3, 4 (PM3, PM4)
Port registers 3, 4 (P3, P4)
13.3 Registers Controlling Clock Output/Buzzer Output Controller
The following register is used to control the clock output/buzzer output controller.
● Clock output select registers n (CKSn)
● Port mode registers 3, 4 (PM3, PM4)
● Port registers 3, 4 (P3, P4)
13.3.1 Clock output select registers n (CKSn)

This register set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and set the
output clock.
Select the clock to be output from the PCLBUZn pin by using the CKSn register.
The CKSn register is set by a 1-bit or 8-bit memory manipulation instruction.
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Figure 13-2. Format of Clock Output Select Registers n (CKSn)
Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H R/W

Symbol <7> 6 5 4 3 2 1 0
CKSn PCLOEn 0 0 0 CSELn CCSn2 CCSn1 CCSn0
PCLOEn PCLBUZn pin output enable/disable specification
0 Output disable (default)

1 Output enable
CSELn CCSn2 CCSn1 CCSn0 PCLBUZn pin output clock selection

fMAIN = fMAIN = fMAIN = fMAIN =
5 MHz 10 MHz 20 MHz 24 MHz
0 0 0 0 fMAIN 5 MHz 10 MHz Setting Setting

Note
prohibited prohibited
Note Note
0 0 0 1 fMAIN/2 2.5 MHz 5 MHz 10 MHz Setting

Note
prohibited
Note
0 0 1 0 fMAIN/22 1.25 MHz 2.5 MHz 5 MHz 6 MHz

3
0 0 1 1 fMAIN/2 625 kHz 1.25 MHz 2.5 MHz 3 MHz
4
0 1 0 0 fMAIN/2 312.5 kHz 625 kHz 1.25 MHz 1.5 MHz
11
0 1 0 1 fMAIN/2 2.44 kHz 4.88 kHz 9.77 kHz 11.7 kHz
12
0 1 1 0 fMAIN/2 1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
0 1 1 1 fMAIN/213 610 Hz 1.22 kHz 2.44 kHz 2.93 kHz
1 0 0 0 fSX 32.768 kHz
1 0 0 1 fSX/2 16.384 kHz
2
1 0 1 0 fSX/2 8.192 kHz
3
1 0 1 1 fSX/2 4.096 kHz
4
1 1 0 0 fSX/2 2.048 kHz
5
1 1 0 1 fSX/2 1.024 kHz
6
1 1 1 0 fSX/2 512 Hz
1 1 1 1 fSX/27 256 Hz
Note Use the output clock within a range of 16 MHz. See 41.4 AC Characteristics for details.
Caution Change the output clock after disabling clock output (PCLOEn = 0).
Remarks 1. n = 0, 1
2. fMAIN: Main system clock frequency
fSX: Sub clock
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13.3.2 Registers controlling port functions of pins to be used for clock or buzzer output
Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on
the target pin (port mode register (PMxx), port register (Pxx)). For details, see 4.3.1 Port mode registers (PMxx) and
4.3.2 Port registers (Pxx).
Specifically, using a port pin with a multiplexed clock or buzzer output function (e.g. P43/TI00/TO00/PCLBUZ0,
P41/INTP6/TI01/TO01/PCLBUZ1) for clock or buzzer output, requires setting the corresponding bits in the port mode
register (PMxx) and port register (Pxx) to 0.
Example: When P43/TI00/TO00/PCLBUZ0 is to be used for clock or buzzer output

Set the P43 bit of port register 4 to 0.
Make the setting for channel 0 of the timer array unit to not be in use.
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13.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.

The PCLBUZ0 pin outputs a clock/buzzer selected by clock output select register 0 (CKS0).
The PCLBUZ1 pin outputs a clock/buzzer selected by clock output select register 1 (CKS1).
13.4.1 Operation as output pin

The PCLBUZn pin is output as the following procedures.
<1> Set 0 in the bit of the port mode register (PMxx) and port register (Px) which correspond to the port which has a
pin used as the PCLBUZ0 pin.
<2> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
of the PCLBUZn pin (output in disabled status).
<3> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output.
Figure 13-3 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the
clock.
2. n = 0, 1
Figure 13-3. Timing of Outputting Clock from PCLBUZn Pin
PCLOEn
1 clock elapsed
Clock output
Narrow pulses are not recognized
13.5 Cautions of Clock Output/buzzer Output Controller
● When the main system clock is selected for the PCLBUZn output (CSELn = 0), if STOP mode is entered within 1.5
clock cycles output from the PCLBUZn pin after the output is disabled (PCLOEn = 0), the PCLBUZn output width
becomes shorter.
● Setting the WUTMMCK0 bit in the subsystem clock supply option control register (OSMC) to 1 disables operation of
the clock output/buzzer output controller.
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RL78/I1C CHAPTER 14 WATCHDOG TIMER
CHAPTER 14 WATCHDOG TIMER
14.1 Functions of Watchdog Timer
The counting operation of the watchdog timer is set by the option byte (000C0H).
The watchdog timer operates on the low-speed on-chip oscillator clock (fIL).
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
● If the watchdog timer counter overflows

● If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
● If data other than “ACH” is written to the WDTE register
● If data is written to the WDTE register during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of the RESF register, see CHAPTER 27 RESET FUNCTION.
When 75% + 1/2 fIL of the overflow time is reached, an interval interrupt can be generated.
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14.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 14-1. Configuration of Watchdog Timer
Item Configuration
Counter Internal counter (17 bits)
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Table 14-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (000C0H)
Watchdog timer interval interrupt Bit 7 (WDTINT)

Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer (in HALT/STOP Bit 0 (WDSTBYON)
mode)
Remark For the option byte, see CHAPTER 35 OPTION BYTE.
Figure 14-1. Block Diagram of Watchdog Timer
WDTINT of option byte Interval time controller

(000C0H)
Interval time interrupt
(Count value overflow time × 3/4) + 1/2 fIL)
WDCS2 to WDCS0 of
option byte (000C0H)
6 16
Clock Internal fIL/2 to fIL/2
Overflow signal
fIL input counter Selector
(17 bits) Reset
controller
output Internal reset signal
controller
Count clear
signal Window size
decision signal
WINDOW1 and WINDOW0 of
option byte (000C0H)
Window size check
WDTON of option byte Watchdog timer enable Write detector to

(000C0H) register (WDTE) WDTE except ACH
Internal bus
Remark fIL: Low-speed on-chip oscillator clock
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14.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
14.3.1 Watchdog timer enable register (WDTE)

Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AH Note.
Figure 14-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FFFABH After reset: 1AH/9AH Note R/W

Symbol 7 6 5 4 3 2 1 0
WDTE
Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte
(000C0H). To operate watchdog timer, set the WDTON bit to 1.
WDTON Bit Setting Value WDTE Register Reset Value

0 (watchdog timer count operation disabled) 1AH
1 (watchdog timer count operation enabled) 9AH
Cautions 1. If a value other than “ACH” is written to the WDTE register, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset
signal is generated.
3. The value read from the WDTE register is 9AH/1AH (this differs from the written value (ACH)).
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14.4 Operation of Watchdog Timer
14.4.1 Controlling operation of watchdog timer
1. When the watchdog timer is used, its operation is specified by the option byte (000C0H).
● Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 35 OPTION BYTE).
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
● Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see
14.4.2 Setting overflow time of watchdog timer and CHAPTER 35 OPTION BYTE).
● Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 14.4.3 Setting window open period of watchdog timer and CHAPTER 35 OPTION BYTE).
2. After a reset release, the watchdog timer starts counting.

3. By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and
before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
4. After that, write the WDTE register the second time or later after a reset release during the window open period.
If the WDTE register is written during a window close period, an internal reset signal is generated.
5. If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
● If a 1-bit manipulation instruction is executed on the WDTE register

● If data other than “ACH” is written to the WDTE register
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer starts counting again.
2. After “ACH” is written to the WDTE register, an error of up to 2 clocks (fIL) may occur before the
watchdog timer is cleared.
3. The watchdog timer can be cleared immediately before the count value overflows.
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Caution 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending
on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0 WDSTBYON = 1
In HALT mode Watchdog timer operation stops. Watchdog timer operation continues.
In STOP mode
In SNOOZE mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
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14.4.2 Setting overflow time of watchdog timer

Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
Table 14-3. Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer

(fIL = 17.25 kHz (MAX.))
0 0 0 26/fIL (3.71 ms)
0 0 1 27/fIL (7.42 ms)
0 1 0 28/fIL (14.84 ms)
0 1 1 29/fIL (29.68 ms)
1 0 0 211/fIL (118.72 ms)
1 0 1 213/fIL (474.89 ms) Note
1 1 0 214/fIL (949.79 ms) Note
1 1 1 216/fIL (3799.18 ms) Note
<R> Note Using the watchdog timer under the following conditions may lead to the generation of an interval interrupt
(INTWDTI) after one cycle of the watchdog timer clock once the watchdog timer counter has been cleared.
Usage conditions that may lead to the generation of an interval interrupt:

- The overflow time of the watchdog timer is set to 213/fIL, 214/fIL, or 216/fIL,
- the interval interrupt is in use (the setting of the WDTINT bit of the relevant option byte is 1), and
- ACH is written to the WDTE register (FFFABH) when the watchdog timer counter has reached or exceeded
75% of the overflow time.
This interrupt can be masked by clearing the watchdog timer counter through steps 1 to 5 below.
1. Set the WDTIMK bit of the interrupt mask flag register 0 (MK0L) to 1 before clearing the watchdog timer
counter.
2. Clear the watchdog timer counter.
3. Wait for at least 80 µs.
4. Clear the WDTIIF bit of the interrupt request flag register (IF0L) to 0.
5. Clear the WDTIMK bit of the interrupt mask flag register 0 (MK0L) to 0.
Remark fIL: Low-speed on-chip oscillator clock frequency
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14.4.3 Setting window open period of watchdog timer

Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
● If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
is cleared and starts counting again.
● Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an
internal reset signal is generated.
Example: If the window open period is 50%
Counting Overflow
starts time
Window close period (50%) Window open period (50%)
Internal reset signal is generated Counting starts again when

if “ACH” is written to WDTE. “ACH” is written to WDTE.
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
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The window open period can be set is as follows.
Table 14-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 1 50%
1 0 75% Note
1 1 100%
<R> Note When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to WDTE)
must proceed outside the corresponding period from among those listed below, over which clearing of the
counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of the
watchdog timer is set).
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time Period over which clearing the
(fIL = 17.25 kHz (MAX.)) counter is prohibited when the
window open period is set to 75%
0 0 0 26/fIL (3.71 ms) 1.85 ms to 2.51 ms
7
0 0 1 2 /fIL (7.42 ms) 3.71 ms to 5.02 ms
8
0 1 0 2 /fIL (14.84 ms) 7.42 ms to 10.04 ms
9
0 1 1 2 /fIL (29.68 ms) 14.84 ms to 20.08 ms
11
1 0 0 2 /fIL (118.72 ms) 56.36 ms to 80.32 ms
13
1 0 1 2 /fIL (474.89 ms) 237.44 ms to 321.26 ms
14
1 1 0 2 /fIL (949.79 ms) 474.89 ms to 642.51 ms
1 1 1 216/fIL (3799.18 ms) 1899.59 ms to 2570.04 ms
Caution When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless
of the values of the WINDOW1 and WINDOW0 bits.
Remark If the overflow time is set to 29/fIL, the window close time and open time are as follows.
Setting of Window Open Period
50% 75% 100%
Window close time 0 to 20.08 ms 0 to 10.04 ms None

Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms
<When window open period is 50%>

● Overflow time:
29/fIL (MAX.) = 29/17.25 kHz (MAX.) = 29.68 ms
● Window close time:
0 to 29/fIL (MIN.) × (1 – 0.5) = 0 to 29/12.75 kHz × 0.5 = 0 to 20.08 ms
● Window open time:
29/fIL (MIN.) × (1 – 0.5) to 29/fIL (MAX.) = 29/12.75 kHz × 0.5 to 29/17.25 kHz = 20.08 to 29.68 ms
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14.4.4 Setting watchdog timer interval interrupt

Setting bit 7 (WDTINT) of an option byte (000C0H) can generate an interval interrupt (INTWDTI) when 75% + 1/2 fIL of
the overflow time is reached.
Table 14-5. Setting of Watchdog Timer Interval Interrupt
WDTINT Use of Watchdog Timer Interval Interrupt

0 Interval interrupt is not used.
1 Interval interrupt is generated when 75% + 1/2 fIL of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
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RL78/I1C CHAPTER 15 A/D CONVERTER
CHAPTER 15 A/D CONVERTER
The number of analog input channels of the A/D converter differs, depending on the product.
64, 80-pin 100-pin

Analog input channels 4 ch 6 ch
(ANI0 to ANI3) (ANI0 to ANI5)
15.1 Function of A/D Converter
The A/D converter is used to convert analog input signals into digital values, and is configured to control analog inputs,
including up to 6 channels of A/D converter analog inputs (ANI0 to ANI5). 10-bit or 8-bit resolution can be selected by the
ADTYP bit of the A/D converter mode register 2 (ADM2).
The A/D converter has the following function.
● 10-bit/8-bit resolution A/D conversion

10-bit or 8-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to
ANI5. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated (when in the select
mode).
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Various A/D conversion modes can be specified by using the mode combinations below.
Trigger mode Software trigger Conversion is started by software.

Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger.
Hardware trigger wait mode The power is turned on by detecting a hardware trigger while the
system is off and in the conversion standby state, and
conversion is then started automatically after the stabilization
wait time passes.
When using the SNOOZE mode function, specify the hardware
trigger wait mode.
Channel selection Select mode A/D conversion is performed on the analog input of one selected
mode channel.
Scan mode A/D conversion is performed on the analog input of four channels
in order. Four consecutive channels can be selected from ANI0
to ANI5 as analog input channels.
Conversion operation One-shot conversion mode A/D conversion is performed on the selected channel once.
mode Sequential conversion mode A/D conversion is sequentially performed on the selected
channels until it is stopped by software.
Operation voltage Standard 1 or standard 2 mode Conversion is done in the operation voltage range of 2.7 V ≤ VDD
mode ≤ 5.5 V.
Low voltage 1 or low voltage 2 Conversion is done in the operation voltage range of 1.9 V ≤ VDD
mode ≤ 5.5 V.
Select this mode for conversion at a low voltage. Because the
operation voltage is low, it is internally boosted during
conversion.
Sampling time selection Sampling clock cycles: The sampling time in standard 1 or low voltage 1 mode is seven
7 fAD cycles of the conversion clock (fAD). Select this mode when the
output impedance of the analog input source is high and the
sampling time should be long.
Sampling clock cycles: The sampling time in standard 2 or low voltage 2 mode is five
5 fAD cycles of the conversion clock (fAD). Select this mode when
enough sampling time is ensured (for example, when the output
impedance of the analog input source is low).
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Figure 15-1. Block Diagram of A/D Converter
Internal bus
RL78/I1C
A/D port configuration A/D test register
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register (ADPC) (ADTES)
ADPC2 ADPC1 ADPC0 ADTES1 ADTES0 Conversion result Conversion result

comparison upper limit comparison lower limit ADREFP1 and ADREFP0 bits
setting register (ADUL) setting register (ADLL)
3
Note
Internal reference voltage (1.45 V)
2
VDD
AV REFP /ANI0/P20
Selector
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ADCS bit
ANI0/AV REFP /P20
ANI1/AV REFM /P21
Digital Sample & hold circuit
P22/ANI2/EXLVD port
control A/D voltage comparator
P23/ANI3
P24/ANI4 Comparison
P25/ANI5 voltage
generator ADREFM bit
VSS
Selector
Successive
approximation register AV REFM /ANI1/P21
(SAR)
Selector
VSS
Timer trigger signal (INTRTCALM, INTRTCPRD)
Temperature sensor Timer trigger signal (INTIT)
Controller Timer trigger signal (INTTM01)
Internal reference voltage (1.45 V) Note
A/D conversion
result upper INTAD
limit/lower limit
6 comparator
ADREFP1 ADREFP0 ADREFPM ADRCK AWC ADTYP
A/D converter mode 6

register 2 (ADM2)
ADISS ADS4 ADS3 ADS2 ADS1 ADS0 A/D conversion result
ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 ADCS ADMD FR2 FR1 FR0 LV1 LV0 ADCE
register (ADCR)
Analog input channel A/D converter mode A/D converter mode
specification register (ADS) register 1 (ADM1) register 0 (ADM0)
Internal bus
Note When using an internal reference voltage, it must be used in HS mode.

The minimum operating voltage in HS mode is 2.4 V.
Use an external reference voltage if you need to operate at 2.4 V or less.
Remark Analog input pin for figure 15-1 when a 100-pin product is used.
432
CHAPTER 15 A/D CONVERTER
15.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI5 pins

These are the analog input pins of the 6 channels of the A/D converter. They input analog signals to be converted
into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit

The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(3) A/D voltage comparator

This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage
generator with the analog input voltage. If the analog input voltage is found to be greater than the reference voltage
(1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register
(SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is
reset.
After that, bit 8 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the
comparison voltage generator is selected by the value of bit 9, to which the result has been already set.
Bit 9 = 0: (1/4 AVREF)

Bit 9 = 1: (3/4 AVREF)
The voltage tap of the comparison voltage generator and the analog input voltage are compared and bit 8 of the SAR
register is manipulated according to the result of the comparison.
Analog input voltage ≥ Voltage tap of comparison voltage generator: Bit 8 = 1

Analog input voltage ≤ Voltage tap of comparison voltage generator: Bit 8 = 0
Comparison is continued like this to bit 0 of the SAR register.

When performing A/D conversion at a resolution of 8 bits, the comparison continues until bit 2 of the SAR register.
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
(4) Comparison voltage generator

The comparison voltage generator generates the comparison voltage input from an analog input pin.
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(5) Successive approximation register (SAR)

The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match
the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified
A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated.
(6) 10-bit A/D conversion result register (ADCR)

The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits
are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)

The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates INTAD through the A/D conversion result upper limit/lower limit comparator.
(9) AVREFP pin

This pin inputs an external reference voltage (AVREFP).
If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D
converter mode register 2 (ADM2) to 0 and 1, respectively.
The analog signals input to ANI2 to ANI5 are converted to digital signals based on the voltage applied between
AVREFP and the – side reference voltage (AVREFM/VSS).
In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference
voltage of the A/D converter.
(10) AVREFM pin

This pin inputs an external reference voltage (AVREFM). If using AVREFM as the – side reference voltage of the A/D
converter, set the ADREFM bit of the ADM2 register to 1.
In addition to AVREFM, it is possible to select VSS as the – side reference voltage of the A/D converter.
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15.3 Registers Controlling A/D Converter
The A/D converter is controlled by the following registers.

● A/D converter mode register 0 (ADM0)
● 10-bit A/D conversion result register (ADCR)
● 8-bit A/D conversion result register (ADCRH)
● Analog input channel specification register (ADS)
● Conversion result comparison upper limit setting register (ADUL)
● Conversion result comparison lower limit setting register (ADLL)
● A/D test register (ADTES)
● A/D port configuration register (ADPC)
● Port mode register 2 (PM2)
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When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
ADCEN Control of A/D converter input clock supply

● SFR used by the A/D converter cannot be written. The read value is 00H. However, the SFR is not
initialized. Note
● SFR used by the A/D converter can be read and written.
Note To initialize the A/D converter and the SFR used by the A/D converter, use bit 5 (ADCRES) of PRR0.
Cautions 1. When setting the A/D converter, be sure to set the following registers first while the ADCEN
bit is set to 1. If ADCEN = 0, writing to the control registers of A/D converter is ignored.
(except for port mode register 2 (PM2) and A/D port configuration register (ADPC)).
● 10-bit A/D conversion result register (ADCR)
● 8-bit A/D conversion result register (ADCRH)
● Analog input channel specification register (ADS)
● Conversion result comparison upper limit setting register (ADUL)
● Conversion result comparison lower limit setting register (ADLL)
● A/D test register (ADTES).
2. Be sure to clear bits 7 and 1 to 0.
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The PRR0 register is used to control resetting of the on-chip peripheral modules.
Each bit in this register controls resetting and release of the reset state of the corresponding on-chip peripheral module.
To reset the A/D converter, be sure to set bit 5 (ADCRES) to 1.
The PRR0 register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 15-3. Format of Peripheral reset control Register 0 (PRR0)

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
ADCRES Control resetting of the A/D converter and temperature sensor 2
0 Releases the A/D converter and temperature sensor 2 from the reset state.
1 The A/D converter and temperature sensor 2 are in the reset state.
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15.3.3 A/D converter mode register 0 (ADM0)

This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 15-4. Format of A/D Converter Mode Register 0 (ADM0)
Address: FFF30H After reset: 00H R/W

Symbol <7> 6 5 4 3 2 1 <0>
ADM0 ADCS ADMD FR2Note 1 FR1Note 1 FR0Note 1 LV1Note 1 LV0Note 1 ADCE
ADCS A/D conversion operation control

0 Stops conversion operation
[When read]
Conversion stopped/standby status
1 Enables conversion operation

[When read]
While in the software trigger mode: Conversion operation status
While in the hardware trigger wait mode: A/D power supply stabilization wait status
+ conversion operation status
ADMD Specification of the A/D conversion channel selection mode

0 Select mode
1 Scan mode
ADCE A/D voltage comparator operation controlNote 2

0 Stops A/D voltage comparator operation
1 Enables A/D voltage comparator operation
Notes 1. For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 15-3 A/D Conversion Time
Selection.
2. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage
comparator is controlled by the ADCS and ADCE bits, and it takes 1 µs from the start of operation for the
operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1 µs or more has elapsed from the
time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result.
Otherwise, ignore data of the first conversion.
Cautions 1. Change the ADMD, FR2 to FR0, LV1, LV0, and ADCE bits while conversion is stopped (ADCS =
0, ADCE = 0).
2. Do not set ADCS = 1 and ADCE = 0.
3. Do not change the ADCE and ADCS bits from 0 to 1 at the same time by using an 8-bit
manipulation instruction. Be sure to set these bits in the order described in 15.7 A/D
Converter Setup Flowchart.
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Table 15-1. Settings of ADCS and ADCE Bits
ADCS ADCE A/D Conversion Operation
0 0 Conversion stopped state

0 1 Conversion standby state
1 1 Conversion-in-progress state
Table 15-2. Setting and Clearing Conditions for ADCS Bit
A/D Conversion Mode Set Conditions Clear Conditions
Software Select mode Sequential conversion When 1 is When 0 is written to ADCS

trigger mode written to ADCS
One-shot conversion ● When 0 is written to ADCS
mode ● The bit is automatically cleared to 0 when
A/D conversion ends.
Scan mode Sequential conversion When 0 is written to ADCS
mode
conversion ends on the specified four
channels.
Hardware Select mode Sequential conversion When 0 is written to ADCS
trigger no-wait mode
mode One-shot conversion When 0 is written to ADCS
mode
mode
One-shot conversion When 0 is written to ADCS
mode
Hardware Select mode Sequential conversion When a When 0 is written to ADCS
trigger wait mode hardware trigger
mode One-shot conversion is input ● When 0 is written to ADCS
A/D conversion ends.
mode
conversion ends on the specified four
channels.
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Figure 15-5. Timing Chart When A/D Voltage Comparator Is Used
A/D voltage comparator: enables operation
ADCE
A/D voltage comparator

Conversion start timeNote 2
Conversion Conversion Conversion Conversion
standby operation standby stopped
Software
ADCS Note 1
trigger mode
1 is written 0 is written to ADCS.

Cleared automatically upon completion of A/D conversion.
to ADCS.
Conversion Trigger Conversion Conversion Conversion
standby standby operation standby stopped
Hardware trigger
ADCS Note 1
no-wait mode Hardware
trigger detection
1 is written 0 is written to ADCS.
to ADCS.
A/D power supply stabilization wait time
Conversion Conversion Conversion Conversion
standby operation standby stopped
Hardware trigger Trigger Trigger
ADCS standby
wait mode standby
Hardware trigger 0 is written to ADCS.

Cleared automatically upon completion of A/D conversion.
detection
Notes 1. While in the software trigger mode or hardware trigger no-wait mode, the time from the rising of the ADCE
bit to the falling of the ADCS bit must be 1 µs or longer to stabilize the internal circuit.
2. In starting conversion, the longer will take up to following time
ADM0 Conversion Clock Conversion Start Time (Number of fCLK Clock)
FR2 FR1 FR0 (fAD) Software Trigger Mode/ Hardware Trigger Wait Mode
Hardware Trigger No-wait Mode
0 0 0 fCLK/64 63 1
0 0 1 fCLK/32 31
0 1 0 fCLK/16 15
0 1 1 fCLK/8 7
1 0 0 fCLK/6 5
1 0 1 fCLK/5 4
1 1 0 fCLK/4 3
1 1 1 fCLK/2 1
However, for the second and subsequent conversion in sequential conversion mode, the conversion start
time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected.
Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is
automatically switched to 1 when the hardware trigger signal is detected). However, it is possible
to clear the ADCS bit to 0 to specify the A/D conversion standby status.
2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is
not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
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Cautions 3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion
stopped/conversion standby status).
4. To complete A/D conversion, specify at least the following time as the hardware trigger interval:
Hardware trigger no wait mode: 2 fCLK clock + conversion start time + A/D conversion time
Hardware trigger wait mode: 2 fCLK clock + conversion start time + A/D power supply
stabilization wait time + A/D conversion time
Remark fCLK: CPU/peripheral hardware clock frequency
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Table 15-3. A/D Conversion Time Selection (1/4)
(1) When there is no A/D power supply stabilization wait time

Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0 Mode Conversion Number of Conversion Conversion Time Selection at 10-Bit Resolution
(ADM0) Clock (fAD) Conversion Time 2.7 V ≤ VDD ≤ 5.5 V
Note
FR2 FR1 FR0 LV1 LV0 Clock fCLK = fCLK = fCLK = fCLK = fCLK =
1 MHz 4 MHz 8 MHz 16 MHz 24 MHz
0 0 0 0 0 Normal 1 fCLK/64 19 fAD 1216/fCLK Setting Setting Setting Setting prohibited
0 0 1 fCLK/32 (number of 608/fCLK prohibited prohibited prohibited 38 µs 25.3333 µs
0 1 0 fCLK/16 sampling 304/fCLK 38 µs 19 µs 12.6667 µs
0 1 1 fCLK/8 clock: 152/fCLK 38 µs 19 µs 9.5 µs 6.3333 µs
1 0 0 fCLK/6 7 fAD) 114/fCLK 28.5 µs 14.25 µs 7.125 µs 4.75 µs
1 0 1 fCLK/5 95/fCLK 23.75 µs 11.875 µs 5.938 µs 3.9583 µs
1 1 0 fCLK/4 76/fCLK 19 µs 9.5 µs 4.75 µs 3.1667 µs
1 1 1 fCLK/2 38/fCLK 38 µs 9.5 µs 4.75 µs 2.375 µs Setting
prohibited
0 0 0 0 1 Normal 2 fCLK/64 17 fAD 1088/fCLK Setting Setting Setting Setting prohibited
prohibited
Note These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (fAD).
Cautions 1. The A/D conversion time must also be within the relevant range of conversion time (tCONV) described
in 41.6.1 A/D converter characteristics.
2. Rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data while conversion is
stopped (ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion start time. Conversion start time add in the
first conversion. Select conversion time, taking clock frequency errors into consideration.
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(2) When there is no A/D power supply stabilization wait time

Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0 Mode Conversion Number of Conversion Conversion Time Selection at 10-Bit Resolution
(ADM0) Clock (fAD) Conversion Time 1.9 V ≤ VDD ≤ 5.5 V Note 2 Note 3
Note 1
FR2 FR1 FR0 LV1 LV0 Clock fCLK = fCLK = fCLK = fCLK = fCLK =
1 MHz 4 MHz 8 MHz 16 MHz 24 MHz
0 0 0 1 0 Low- fCLK/64 19 fAD 1216/fCLK Setting Setting Setting Setting prohibited
voltage 1
prohibited
0 0 0 1 1 Low- fCLK/64 17 fAD 1088/fCLK Setting Setting Setting Setting prohibited
voltage 2
0 1 1 fCLK/8 clock: 5 136/fCLK 34 µs 17 µs 8.5 µs 5.6667 µs
1 0 0 fCLK/6 fAD) 102/fCLK 25.5 µs 12.75 µs 6.375 µs 4.25 µs
prohibited
Notes 1. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
2. 2.4 V ≤ VDD ≤ 5.5 V
3. 2.7 V ≤ VDD ≤ 5.5 V
in 41.6.1 A/D converter characteristics.
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(3) When there is A/D power supply stabilization wait time

Normal mode 1, 2 (hardware trigger wait modeNote 1)
A/D Converter Mode Mode Conversion Number of Number of A/D Power A/D Power Supply Stabilization Wait Cock +
Register 0 (ADM0) Clock (fAD) A/D Power Conversion Supply Conversion Time at 10-Bit Resolution
Note 2
Supply Clock Stabilization 2.7 V ≤ VDD ≤ 5.5 V
FR2 FR1 FR0 LV1 LV0 Stabilization Wait Cock + fCLK = fCLK = fCLK = fCLK = fCLK =
Wait Cock Conversion 1 MHz 4 MHz 8 MHz 16 MHz 24 MHz
Time
0 0 0 0 0 Normal fCLK/64 8 fAD 19 fAD 1728/fCLK Setting Setting Setting Setting prohibited
0 0 1 1 fCLK/32 (number of 864/fCLK prohibited prohibited prohibited 54 µs 36 µs
0 1 0 fCLK/16 sampling 432/fCLK 54 µs 27 µs 18 µs
clock:
0 1 1 fCLK/8 216/fCLK 54 µs 27 µs 13.5 µs 9 µs
7 fAD)
prohibited
0 0 0 0 1 Normal fCLK/64 8 fAD 17 fAD 1600/fCLK Setting Setting Setting Setting prohibited
0 0 1 2 fCLK/32 (number of 800/fCLK prohibited prohibited prohibited 50 µs 33.3333 µs
prohibited
Notes 1. For the second and subsequent conversion in sequential conversion mode, the conversion start time and
stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see Table 15-3
(1/4)).
2. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
in 41.6.1 A/D converter characteristics. Note that the conversion time (tCONV) does not include the
A/D power supply stabilization wait time.
4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply
stabilization wait time from the hardware trigger detection.
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(4) When there is A/D power supply stabilization wait time

Low-voltage mode 1, 2 (hardware trigger wait modeNote 1)
A/D Converter Mode Register 0 Mode Conversion Number of Number of A/D power A/D Power Supply Stabilization Wait Cock +
(ADM0) Clock (fAD) A/D power Conversion Supply Conversion Time at 10-Bit Resolution
Note 2
supply Clock Stabilization 1.9 V ≤ VDD ≤ 5.5 V Note 3 Note 4
FR2 FR1 FR0 LV1 LV0 Stabilization Wait Cock + fCLK = fCLK = fCLK = fCLK = fCLK =
Wait Cock Conversion 1 MHz 4 MHz 8 MHz 16 MHz 24 MHz
Time
0 0 0 1 0 Low- fCLK/64 2 fAD 19 fAD 1344/fCLK Setting Setting Setting Setting prohibited
0 0 1 voltage fCLK/32 (number of 672/fCLK prohibited prohibited prohibited 42 µs 28 µs
0 1 0 1 fCLK/16 sampling 336/fCLK 42 µs 21 µs 14 µs
0 1 1 fCLK/8 clock: 168/fCLK 42 µs 21 µs 10.5 µs 7 µs
prohibited
0 0 0 1 1 Low- fCLK/64 2 fAD 17 fAD 1216/fCLK Setting Setting Setting Setting prohibited
0 0 1 voltage fCLK/32 (number of 608/fCLK prohibited prohibited prohibited 38 µs 25.3333 µs
0 1 0 2 fCLK/16 sampling 304/fCLK 38 µs 19 µs 12.6667 µs
prohibited
Notes 1. For the second and subsequent conversion in sequential conversion mode, the conversion start time and
stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see Table 15-3 (2/4)).
2. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
3. 2.4 V ≤ VDD ≤ 5.5 V
4. 2.7 V ≤ VDD ≤ 5.5 V
in 41.6.1 A/D converter characteristics. Note that the conversion time (tCONV) does not include the
A/D power supply stabilization wait time.
4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply
stabilization wait time from the hardware trigger detection.
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Figure 15-6. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode)
1 is written to ADCS or ADS is rewritten.
ADCS
Sampling
timing
INTAD
Conversion Sampling Successive conversion Sampling Successive

start conversion
Conversion Conversion time Conversion time

start time
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This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal.

Symbol 7 6 5 4 3 2 1 0
ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0
ADTMD1 ADTMD0 Selection of the A/D conversion trigger mode
0 × Software trigger mode

1 0 Hardware trigger no-wait mode
1 1 Hardware trigger wait mode
ADSCM Specification of the A/D conversion mode
0 Sequential conversion mode

1 One-shot conversion mode
ADTRS1 ADTRS0 Selection of the hardware trigger signal
0 0 End of timer channel 01 count or capture interrupt signal (INTTM01)

0 1 Event signal selected by ELC
1 0 Independent power supply RTC alarm interrupt signal (INTRTCALM), independent power
supply RTC fixed-cycle interrupt signal (INTRTCPRD)
1 1 12-bit interval timer interrupt signal (INTIT)
Cautions 1. Rewrite the value of the ADM1 register while conversion is stopped (ADCS = 0, ADCE = 0).
2. To complete A/D conversion, specify at least the following time as the hardware trigger interval:
Hardware trigger no wait mode: 2 fCLK clock + conversion start time + A/D conversion time
Hardware trigger wait mode: 2 fCLK clock + conversion start time + A/D power supply
stabilization wait time + A/D conversion time
3. In modes other than SNOOZE mode, input of the next INTRTCALM/INTRTCPRD or INTIT will not
be recognized as a valid hardware trigger for up to four fCLK cycles after the first
INTRTCALM/INTRTCPRD or INTIT is input.

2. fCLK: CPU/peripheral hardware clock frequency
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This register is used to select the + side or – side reference voltage of the A/D converter, check the upper limit and
lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
Figure 15-8. Format of A/D Converter Mode Register 2 (ADM2) (1/2)

Symbol 7 6 5 4 <3> <2> 1 <0>
ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP
ADREFP1 ADREFP0 Selection of the + side reference voltage of the A/D converter
0 0 Supplied from VDDNote 2
0 1 Supplied from P20/AVREFP/ANI0

1 0 Supplied from the internal reference voltage (1.45 V)Note 1
● When ADREFP1 or ADREFP0 bit is rewritten, this must be configured in accordance with the following procedures.
(1) Set ADCE = 0
(2) Change the values of ADREFP1 and ADREFP0
(3) Reference voltage stabilization wait time (A)
(4) Set ADCE = 1
(5) Reference voltage stabilization wait time (B)
When ADREFP1 and ADREFP0 are set to 1 and 0, the setting is changed to A = 5 µs, B = 1 µs.
When ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1, A needs no wait and B = 1 µs.
After (5) stabilization time, start the A/D conversion.
● When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the
temperature sensor output voltage and internal reference voltage (1.45 V).
Be sure to perform A/D conversion while ADISS = 0.
ADREFM Selection of the – side reference voltage source of the A/D converter
0 Supplied from VSS

1 Supplied from P21/AVREFM/ANI1
Notes 1. This setting can be used only in HS (high-speed main) mode.

When using a temperature sensor, be sure to use an internal reference voltage.
2. When using reference voltage (+) = VDD, take into account the voltage drop due to the effect of the power
switching circuit of the battery backup function and use the A/D conversion result. In addition, enter HALT
mode during A/D conversion and set VDD port to input.
Cautions 1. Only rewrite the value of the ADM2 register while conversion is stopped (ADCS = 0, ADCE = 0).
2. Do not set the ADREFP1 bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is
operating on the subsystem clock. When the internal reference voltage is selected (ADREFP1,
ADREFP0 = 1, 0), the A/D converter reference voltage current (IADREF) indicated in 41.3.2 Supply
current characteristics will be added.
3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify
input mode by using the port mode register.
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Figure 15-8. Format of A/D Converter Mode Register 2 (ADM2) (2/2)

Symbol 7 6 5 4 <3> <2> 1 <0>
ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP
ADRCK Checking the upper limit and lower limit conversion result values
0 The interrupt signal (INTAD) is output when the ADLL register ≤ the ADCR register ≤ the ADUL register
(AREA 1).
1 The interrupt signal (INTAD) is output when the ADCR register < the ADLL register (AREA 2) or the
ADUL register < the ADCR register (AREA 3).
Figure 15-9 shows the generation range of the interrupt signal (INTAD) for AREA 1 to AREA 3.
AWC Specification of the SNOOZE mode

0 Do not use the SNOOZE mode function.
1 Use the SNOOZE mode function.
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed
without operating the CPU (the SNOOZE mode).
● The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the
CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
● Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited.
● Using the SNOOZE mode function in the sequential conversion mode is prohibited.
● When using the SNOOZE mode function, specify a hardware trigger interval of at least “shift time to SNOOZE
modeNote + conversion start time + A/D power supply stabilization wait time + A/D conversion time +2 fCLK clock”
● Even when using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation and change it to 1 just before
shifting to STOP mode.
Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation.
If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal
operation.
ADTYP Selection of the A/D conversion resolution

0 10-bit resolution
1 8-bit resolution
Note Refer to “Transition time from STOP mode to SNOOZE mode” in 26.3.3 SNOOZE mode
Caution Only rewrite the value of the ADM2 register while conversion is stopped (ADCS = 0, ADCE = 0).
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Figure 15-9. ADRCK Bit Interrupt Signal Generation Range
ADCR register value

(A/D conversion result)
1111111111
AREA 3
INTAD is generated
(ADUL < ADCR)
when ADRCK = 1.
ADUL register setting
AREA 1
(ADLL ≤ ADCR ≤ ADUL) INTAD is generated
when ADRCK = 0.
ADLL register setting
AREA 2 INTAD is generated

(ADCR < ADLL) when ADRCK = 1.
0000000000
Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register.
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15.3.6 10-bit A/D conversion result register (ADCR)

This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of
the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EHNote.
The ADCR register can be read by a 16-bit memory manipulation instruction.
Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the
value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 15-9), the result is
not stored.
Figure 15-10. Format of 10-bit A/D Conversion Result Register (ADCR)
Address: FFF1FH, FFF1EH After reset: 0000H R
FFF1FH FFF1EH
Symbol
ADCR 0 0 0 0 0 0
Cautions 1. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode
register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (bits 7 and
6 of the ADCR register).
2. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result
are read in order starting at bit 15 of the ADCR register.
15.3.7 8-bit A/D conversion result register (ADCRH)

This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
storedNote.
The ADCRH register can be read by an 8-bit memory manipulation instruction.
Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the
value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 15-9), the result is
not stored.
Figure 15-11. Format of 8-bit A/D Conversion Result Register (ADCRH)
Address: FFF1FH After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ADCRH
Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may
become undefined. Read the conversion result following conversion completion before writing to
the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect
conversion result to be read.
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15.3.8 Analog input channel specification register (ADS)

This register specifies the input channel of the analog voltage to be A/D converted.
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 15-12. Format of Analog Input Channel Specification Register (ADS)

Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0
Օ Select mode (ADMD = 0)

ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input Input source
channel
0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin

0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin
0 0 0 0 1 0 ANI2 P22/ANI2/EXLVD pin
0 0 0 0 1 1 ANI3 P23/ANI3 pin
0 0 0 1 0 0 ANI4 P24/ANI4 pin
0 0 0 1 0 1 ANI5 P25/ANI5 pin
0 1 1 1 0 1 – Temperature sensor output
voltageNote
1 0 0 0 0 1 – Internal reference voltage
(1.45 V)Note
Օ Scan mode (ADMD = 1)

ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel
Scan 0 Scan 1 Scan 2 Scan 3
0 0 0 0 0 ANI0 ANI1 ANI2 ANI3

Note This setting can be used only in HS (high-speed main) mode.

When using a temperature sensor, be sure to use an internal reference voltage.

2. Set a channel to be set the analog input by ADPC register in the input mode by using port mode
register 2 (PM2).
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the
ADS register.
4. Rewrite the value of the ADISS bit while conversion is stopped (ADCS = 0, ADCE = 0).
5. If using AVREFP as the + side reference voltage of the A/D converter, do not select ANI0 as an
A/D conversion channel.
6. If using AVREFM as the – side reference voltage of the A/D converter, do not select ANI1 as an
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Cautions 7. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side
reference voltage. After the ADISS bit is set to 1, the initial conversion result cannot be used.
For the setting flow, see 15.7.4 Setup when temperature sensor output voltage/internal
reference voltage is selected.
8. Do not set the ADISS bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is
operating on the subsystem clock. Also, if the ADREFP1 bit is set to 1, the A/D converter
reference voltage current (IADREF) indicated in 41.3.2 Supply current characteristics will be
added to the current consumption when shifting to HALT mode while the CPU is operating on
the main system clock.
9. Ignore the conversion result if the corresponding ANI pin does not exist in the product used.
15.3.9 Conversion result comparison upper limit setting register (ADUL)

This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 15-9).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Figure 15-13. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)

Symbol 7 6 5 4 3 2 1 0
ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0
15.3.10 Conversion result comparison lower limit setting register (ADLL)

This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 15-9).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Figure 15-14. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)

Symbol 7 6 5 4 3 2 1 0
ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0
Cautions 1. When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D
conversion result register (ADCR) are compared with the values in the ADUL and ADLL
registers.
2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS = 0,
ADCE = 0).
3. The setting of the ADUL registers must be greater than that of the ADLL register.
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15.3.11 A/D test register (ADTES)

This register is used to select the + side reference voltage or – side reference voltage of the A/D converter, or the
analog input channel (ANIxx) as the target for A/D conversion. When using this register to test the converter, set as
follows.
● For zero-scale measurement, select the – side reference voltage as the target for conversion.
● For full-scale measurement, select the + side reference voltage as the target for conversion.
The ADTES register can be set by an 8-bit memory manipulation instruction.
Figure 15-15. Format of A/D Test Register (ADTES)

Symbol 7 6 5 4 3 2 1 0
ADTES 0 0 0 0 0 0 ADTES1 ADTES0
ADTES1 ADTES0 A/D conversion target
0 0 ANIxx/temperature sensor output voltageNote/internal reference voltage (1.45 V)Note (This

is specified using the analog input channel specification register (ADS).)
1 0 The – side reference voltage (selected by the ADREFM bit of the ADM2 register)
1 1 The + side reference voltage (selected by the ADREFP1 or ADREFP0 bit of the ADM2
register)
Note The temperature sensor output voltage and internal reference voltage (1.45 V) can be selected only in
the HS (high-speed main) mode.
Caution For details of the A/D test function, see CHAPTER 32 SAFETY FUNCTIONS.
15.3.12 Registers controlling port function of analog input pins

Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port
mode registers (PMxx) and A/D port configuration register (ADPC)).
For details, see 4.3.1 Port mode registers (PMxx) and 4.3.6 A/D port configuration register (ADPC).
When using the ANI0 to ANI5 pins for analog input of the A/D converter, set the port mode register (PMxx) bit
corresponding to each port to 1 and select analog input through the A/D port configuration register (ADPC).
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15.4 A/D Converter Conversion Operations
The A/D converter conversion operations are described below.
<1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<3> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AVREF by the tap selector.
<4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set
to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0.
<5> Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 9, as described below.
● Bit 9 = 1: (3/4) AVREF
● Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows.
● Sampled voltage ≥ Voltage tap: Bit 8 = 1
● Sampled voltage < Voltage tap: Bit 8 = 0
<6> Comparison is continued in this way up to bit 0 of the SAR register.
<7> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latchedNote 1.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generatedNote 1.
<8> Repeat steps <1> to <7>, until the ADCS bit is cleared to 0Note 2.
To stop the A/D converter, clear the ADCS bit to 0.
Notes 1. If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the
ADUL and ADLL registers (see Figure 15-9), the A/D conversion result interrupt request signal is not
generated and no A/D conversion results are stored in the ADCR and ADCRH registers.
2. While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not
automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode,
either. Instead, 1 is retained.
Remarks 1. Two types of the A/D conversion result registers are available.
● ADCR register (16 bits): Store 10-bit A/D conversion value
● ADCRH register (8 bits): Store 8-bit A/D conversion value
2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
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Figure 15-16. Conversion Operation of A/D Converter (Software Trigger Mode)
Write ADCS to 1
ADCS
Conversion time
Conversion Sampling time
start time
A/D converter Conversion Conversion

Conversion start Sampling A/D conversion
operation standby standby
Conversion
SAR Undefined result
ADCR Conversion
result
INTAD
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7 (ADCS)
of the A/D converter mode register 0 (ADM0) to 0.
When the value of the analog input channel specification register (ADS) is rewritten or overwritten during conversion,
the current A/D conversion is interrupted, and A/D conversion is performed on the analog input newly specified in the ADS
register. The partially converted data is discarded.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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15.5 Input Voltage and Conversion Results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI5) and the theoretical A/D
conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
VAIN
SAR = INT ( × 1024 + 0.5)
AVREF
ADCR = SAR × 64
or
ADCR AVREF ADCR AVREF

( – 0.5) × ≤ VAIN < ( + 0.5) ×
64 1024 64 1024
where, INT( ): Function which returns integer part of value in parentheses

VAIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 15-17 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 15-17. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR ADCR
1023 FFC0H
1022 FF80H
1021 FF40H
A/D conversion result
3 00C0H
2 0080H
1 0040H
0 0000H
1 1 3 2 5 3 2043 1022 2045 1023 2047 1
2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048
Input voltage/AVREF
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
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15.6 A/D Converter Operation Modes
The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is
described in 15.7 A/D Converter Setup Flowchart.
15.6.1 Software trigger mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1 µs), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 15-18. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1. ADCE is cleared to 0. <8>
ADCE ADCS is overwritten A hardware trigger ADCS is cleared to

<2> ADCS is set to 1 while in the <4> <6> <7>
with 1 during A/D is generated 0 during A/D
conversion standby status.
conversion operation. (and ignored). conversion operation.
ADCS ADS is rewritten during
<5> A/D conversion operation
(from ANI0 to ANI1).
ADS Data 0 Data 1
(ANI0) (ANI1)
Conversion is <3> Conversion is
<3> A/D conversion <3> <3> <3>
interrupted.
ends and the next interrupted
conversion starts. and restarts.
A/D
conversion Conversion Conversion Data 0 Data 0 Data 0 Data 0 Data 0 Data 1 Data 1 Data 1 Conversion Conversion
stopped standby (ANI0) (ANI0) (ANI0) (ANI0) (ANI0) (ANI1) (ANI1) (ANI1) standby stopped
status
Conversion start
ADCR, Data 0 Data 0 Data 0 Data 1 Data 1
ADCRH (ANI0) (ANI0) (ANI0) (ANI1) (ANI1)
INTAD
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15.6.2 Software trigger mode (select mode, one-shot conversion mode)
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion
standby status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 15-19. Example of Software Trigger Mode (Select Mode, One-shot Conversion Mode) Operation Timing
ADCE ADCS is set to ADCS is ADCS is overwritten ADCS is

<2> 1 while in the <4> automatically<2> <5> <4> <2> <4> <2> <7> cleared to
cleared to with 1 during A/D
conversion 0 during A/D
standby status. 0 after conversion operation.
conversion conversion
ADCS ends. <6> ADS is rewritten during
operation.
A/D conversion operation
Data 0 Data 1
ADS (ANI0) (ANI1)
A/D Conversion is Conversion is
<3> conversion interrupted <3> <3>
ends. and restarts. interrupted.
A/D
Conversion Conversion Data 0 Conversion Data 0 Data 0 Conversion Data 0 Data 1 Conversion Data 1 Conversion Conversion
conversion stopped standby standby standby standby standby stopped
(ANI0) (ANI0) (ANI0) (ANI0) (ANI1) (ANI1)
status
Conversion start Conversion start Conversion start Conversion start
ADCR, Data 0 Data 0 Data 1
ADCRH (ANI0) (ANI0) (ANI1)
INTAD
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15.6.3 Software trigger mode (scan mode, sequential conversion mode)
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts (until all four channels are finished).
conversion restarts at the first channel. The partially converted data is discarded.
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start.
Figure 15-20. Example of Software Trigger Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
ADCE ADCS is overwritten A hardware trigger is <6> ADCS is cleared <7>

<2> ADCS is set to 1 while in the <4>
conversion standby status. with 1 during A/D generated (and ignored). to 0 during A/D
conversion operation. conversion operation.
ADCS
<5> ADS is rewritten during

A/D conversion operation.
ADS ANI0 to ANI3 ANI4 to ANI7

Conversion is
A/D conversion ends and the <3> Conversion is <3> Conversion is <3> interrupted.
next conversion starts. interrupted and restarts. interrupted and restarts.
A/D
conversion Conversion Conversion Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Conversion Conversion
stopped standby (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) standby stopped
status
Conversion start
ADCR, Data 0 Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6 Data 7 Data 4
(ANI0) (ANI1) (ANI2) (ANI3) Data 0 (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4)
ADCRH
INTAD
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
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15.6.4 Software trigger mode (scan mode, one-shot conversion mode)
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
interrupt request signal (INTAD) is generated.
<4> After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters
the A/D conversion standby status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 15-21. Example of Software Trigger Mode (Scan Mode, One-shot Conversion Mode) Operation Timing
ADCE <4> ADCS is ADCS is cleared<7>

<2> ADCS is set to 1 while automatically<2> <5> ADCS is overwritten <4> <2>
in the conversion cleared to with 1 during A/D to 0 during A/D
standby status. 0 after conversion operation. conversion operation.
conversion
ADCS ends.

<3> A/D conversion Conversion is Conversion is Conversion is

<3> interrupted and restarts.
ends. interrupted and restarts. interrupted.
A/D
conversion Conversion Conversion Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Conversion Conversion
stopped standby (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) standby stopped
status
Conversion start Conversion start Conversion start
ADCR, Data 0 Data 1 Data 2 Data 3 Data 0 (ANI0) Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6
ADCRH (ANI0) (ANI1) (ANI2) (ANI3) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6)
INTAD
The interrupt is generated four times. The interrupt is generated four times.
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15.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
A/D conversion immediately starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
system enters the A/D conversion standby status. However, the A/D converter does not stop in this status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 15-22. Example of Hardware Trigger No-wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE <2> ADCS is set to 1.

<5> A hardware trigger is
<3> A hardware trigger generated during A/D
is generated. conversion operation.
Hardware
trigger
Trigger ADCS is overwritten <7> ADCS is cleared<8>
The trigger is not standby with 1 during A/D to 0 during A/D The trigger is not
acknowledged. status conversion operation. conversion operation. acknowledged.
ADCS <6> ADS is rewritten during
ADS Data 0 Data 1
(ANI0) (ANI1)
<4> A/D conversion Conversion is
ends and the next Conversion is Conversion is interrupted and Conversion
conversion<4> interrupted <4> interrupted <4> restarts. <4> is interrupted.
starts. and restarts. and restarts.
A/D
conversion Conversion Conversion Data 0 Data 0 Data 0 Data 0 Data 0 Data 1 Data 1 Data 1 Data 1 Conversion Conversion
stopped standby (ANI0) (ANI0) (ANI0) (ANI0) (ANI0) (ANI1) (ANI1) (ANI1) (ANI1) standby stopped
status
Conversion start
INTAD
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15.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode)
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
<5> After A/D conversion ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby
status.
Figure 15-23. Example of Hardware Trigger No-wait Mode (Select Mode, One-shot Conversion Mode) Operation
Timing
<1> ADCE is set to 1. ADCE is cleared to 0.<10>

<3>A hardware trigger <3> generated during A/D <3> <3> <3>
is generated. conversion operation.
Hardware
trigger
The trigger is not Trigger ADCS retains<5> ADCS is overwritten with 1 during <8> <5> <9> ADCS is cleared to 0 during
acknowledged. standby the value 1. <5>
<5>
A/D conversion A/D conversion operation.
status operation.
Trigger standby status
ADCS <7>ADS is rewritten during
Data 0 Data 1
ADS (ANI0) (ANI1)
<4> A/D conversion Conversion is Conversion is Conversion is Conversion is
ends. interrupted interrupted interrupted interrupted.
and restarts. <4> and restarts. <4> and restarts.<4>
A/D
Conversion Conversion Data 0 Conversion Data 0 Data 0 Conversion Data 0 Data 1 Conversion Data 1 Data 1 Data 1 Conversion Conversion
conversion stopped standby (ANI0) standby (ANI0) (ANI0) standby (ANI0) (ANI1) standby (ANI1) (ANI1) (ANI1) standby stopped
status
Conversion start Conversion standby
ADCR, Data 0 Data 0 Data 1 Data 1

ADCRH (ANI0) (ANI0) (ANI1) (ANI1)
INTAD
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15.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
conversion of the channel following the specified channel automatically starts.
Figure 15-24. Example of Hardware Trigger No-wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
<1> ADCE is set to 1.

ADCE is cleared to 0. <9>

is generated. conversion operation. ADCS is cleared to 0 <8>
Hardware during A/D conversion
trigger operation.
The trigger is not Trigger ADCS is overwritten <7>
standby The trigger is not
acknowledged. status with 1 during A/D acknowledged.
conversion operation.
ADCS


A/D conversion <4> Conversion is <4> Conversion is <4> Conversion is <4> Conversion is
ends and the next interrupted interrupted interrupted interrupted.
A/D conversion starts. and restarts. and restarts. and restarts.
Conversion Conversion Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Data 6 Data 4 Data 5 Data 6 Data 7 Data 4 Conversion Conversion
conversion stopped standby (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) (ANI6) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) standby stopped
status
Conversion start
ADCR, Data 0 Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Data 4 Data 5 Data 6 Data 7
(ANI0) (ANI1) (ANI2) (ANI3) Data 0 (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) (ANI4) (ANI5) (ANI6) (ANI7)
ADCRH
INTAD
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
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15.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D
conversion standby status.
Figure 15-25. Example of Hardware Trigger No-wait Mode (Scan Mode, One-shot Conversion Mode) Operation
Timing

<3> A hardware trigger <3> generated during A/D <3> <3>
is generated. conversion operation. <9> ADCS is cleared to 0
trigger operation.
The trigger is not Trigger ADCS retains <5> <5> <5> <8>ADCS is overwritten The trigger is not
acknowledged. standby
status the value 1.
with 1 during A/D acknowledged.
ADCS ADS is rewritten
<7> during A/D
<4> A/D Conversion is Conversion is Conversion is Conversion is
conversion interrupted <4> interrupted <4> interrupted interrupted.
ends. and restarts. and restarts. and restarts.
A/D
Conversion Conversion Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Conversion Data 4 Data 5 Data 4 Data 5 Data 6 Conversion Conversion
conversion stopped standby (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) standby (ANI4) (ANI5) (ANI4) (ANI5) (ANI6) standby stopped
status
Conversion start
ADCR, Data 0 Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6 Data 7 Data 5
Data 0 (ANI0) Data 4 (ANI4)
ADCRH (ANI0) (ANI1) (ANI2) (ANI3) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7) (ANI5)
INTAD
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15.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)
hardware trigger standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 15-26. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE
Hardware is generated. conversion operation.
trigger
ADCS is overwritten <6> ADCS is cleared <7>
The trigger Trigger Trigger The trigger
is not with 1 during A/D to 0 during A/D
standby conversion operation. conversion operation. standby is not
acknowledged. status status acknowledged.
ADCS <5> ADS is rewritten during
Data 0 Data 1
ADS (ANI0) (ANI1)
<3> A/D conversion ends Conversion is Conversion is
and the next Conversion is interrupted and Conversion is
conversion<3> interrupted restarts. interrupted.
and restarts.<3> interrupted <3> <3>
starts. and restarts.
A/D
Conversion Conversion Data 0 Data 0 Data 0 Data 0 Data 0 Data 1 Data 1 Data 1 Data 1 Conversion Conversion
conversion stopped standby (ANI0) (ANI0) (ANI0) (ANI0) (ANI0) (ANI1) (ANI1) (ANI1) (ANI1) standby stopped
status
Conversion start
INTAD
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15.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)
hardware trigger standby status.
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
conversion restarts. The partially converted data is initialized.
Figure 15-27. Example of Hardware Trigger Wait Mode (Select Mode, One-shot Conversion Mode) Operation
Timing
ADCE
<2>A hardware trigger <2> <5> A hardware trigger is <2> <8> ADCS is cleared
generated during A/D <2> <2>
is generated. to 0 during A/D
Hardware conversion operation. conversion
trigger operation.
Trigger ADCS is automatically
The trigger is not standby Trigger Trigger Trigger <7> ADCS is overwritten <4>Trigger Trigger The trigger is not
<4>standby <4> standby <4>standby standby standby acknowledged.
acknowledged. status cleared to 0 after status status status
with 1 during A/D
status status
conversion ends. conversion operation.
ADCS <6> ADS is rewritten

during A/D conversion
operation (from ANI0
to ANI1).
Data 0 Data 1
ADS (ANI0) (ANI1)
<3> A/D conversion Conversion is Conversion is Conversion is Conversion is
ends. interrupted <3> interrupted interrupted interrupted.
and restarts. and restarts.<3> and restarts. <3>
A/D
conversion
Conversion Conversion Data 0 Conversion Data 0 Data 0 Conversion Data 0 Data 1 Conversion Data 1 Data 1 Conversion Data 1 Conversion Conversion
stopped standby (ANI0) stopped (ANI0) (ANI0) stopped (ANI0) (ANI1) stopped (ANI1) (ANI1) stopped (ANI1) standby stopped
status
Conversion start Conversion start Conversion start Conversion start Conversion start

ADCRH (ANI0) (ANI0) (ANI1) (ANI1)
INTAD
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15.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
conversion of the channel following the specified channel automatically starts.
Figure 15-28. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE
is generated.
Hardware conversion operation.
trigger
The trigger is not Trigger ADCS is overwritten <6> ADCS is cleared <7>Trigger standby The trigger is not
acknowledged. standby status with 1 during A/D to 0 during A/D status acknowledged.
conversion operation. conversion operation.
ADCS


A/D conversion <3> <3> <3> <3> Conversion is
Conversion is Conversion is Conversion is interrupted.
ends and the next interrupted and restarts. interrupted and restarts. interrupted and restarts.
A/D conversion starts.
Conversion Conversion Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Data 6 Data 4 Data 5 Data 6 Data 7 Data 4 Conversion Conversion
conversion stopped standby (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) (ANI6) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) stopped
standby
status
Conversion start
ADCR, Data 0 Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Data 4 Data 5 Data 6 Data 7
Data 0 (ANI0)
ADCRH (ANI0) (ANI1) (ANI2) (ANI3) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) (ANI4) (ANI5) (ANI6) (ANI7)
INTAD
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
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15.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
Figure 15-29. Example of Hardware Trigger Wait Mode (Scan Mode, One-shot Conversion Mode) Operation
Timing
ADCE <5> A hardware trigger is

<2> A hardware trigger <2> generated during A/D <2> <2>
is generated. conversion operation. <8> ADCS is cleared to 0
trigger operation.
ADCS is automatically <4> <4> <4> <7>ADCS is overwritten
cleared to 0 after with 1 during A/D
The trigger is not Trigger Trigger
conversion ends. standby Trigger Trigger conversion operation. Conversion The trigger
acknowledged. standby standby standby standby is not
ADCS status status status ADS is rewritten status status acknowledged.
<6> during A/D
<3> A/D Conversion is Conversion is Conversion is Conversion is

conversion interrupted <3> interrupted <3> interrupted interrupted.
ends. and restarts. and restarts. and restarts.
A/D
Conversion Conversion Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Conversion Data 4 Data 5 Data 4 Data 5 Data 6 Conversion Conversion
conversion stopped standby (ANI0) (ANI1) (ANI2) (ANI3) stopped (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) stopped (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) stopped (ANI4) (ANI5) (ANI4) (ANI5) (ANI6) standby stopped
status Conversion Conversion Conversion Conversion
start start start start
Data 0 (ANI0)
Data 1 Data 2 Data 3 Data 0 Data 4 Data 5 Data 6 Data 7 Data 5
Data 4 (ANI4)
ADCRH (ANI0) (ANI1) (ANI2) (ANI3) (ANI1) (ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7) (ANI5)
INTAD
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15.7 A/D Converter Setup Flowchart
The A/D converter setup flowchart in each operation mode is described below.
15.7.1 Setting up software trigger mode
Figure 15-30. Setting up Software Trigger Mode
Start of setup
PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.

ADPC register settings
ANI0 to ANI5 pins: Set using the ADPC register
PM register setting The ports are set to the input mode.
● ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
● ADM2 register
● ADM0 register setting ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
● ADM1 register setting voltage.
● ADM2 register setting ADRCK bit: This is used to select the range for the A/D conversion result comparison
● ADUL/ADLL register setting value generated by the interrupt signal from AREA1, AREA3, and
AREA2.
● ADS register setting
ADTYP bit: 8-bit/10-bit resolution
(The order of the settings is
● ADUL/ADLL register
irrelevant.)
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
● ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time count A below may be required if the
Reference voltage stabilization values of the ADREFP1 and ADREFP0 bits are changed.
wait time count A If change the ADREFP1 and ADREFP0 = 1, 0: A = 5 µs
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait
ADCE bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
Reference voltage stabilization

The reference voltage stabilization wait time count B (1 µs) is counted by the software.
wait time count B
After counting up to the reference voltage stabilization wait time count B ends, the
ADCS bit setting
ADCS bit of the ADM0 register is set (1), and A/D conversion starts.
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion The A/D conversion end interrupt (INTAD) is generated.Note
Storage of conversion results in

The conversion results are stored in the ADCR and ADCRH registers.
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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15.7.2 Setting up hardware trigger no-wait mode
Figure 15-31. Setting up Hardware Trigger No-wait Mode
Start of setup

ADPC register settings
ANI0 to ANI5 pins: Set using the ADPC register
● ADM0 register
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait
mode.
● ADM2 register
● ADM0 register setting ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
● ADM2 register setting ADRCK bit: This is used to select the range for the A/D conversion result comparison
● ADUL/ADLL register setting value generated by the interrupt signal from AREA1, AREA3, and AREA2.
● ADS register setting ADTYP bit: 8-bit/10-bit resolution
(The order of the settings is

irrelevant.) ● ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
● ADS register
The reference voltage stabilization wait time count A below may be required if the values
of the ADREFP1 and ADREFP0 bits are changed.
Reference voltage stabilization
If change the ADREFP1 and ADREFP0 = 1, 0: A = 5 µs
wait time count A If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait
standby status.
Reference voltage stabilization The reference voltage stabilization wait time count B (1 µs) is counted by the software.
wait time count B
After counting up to the reference voltage stabilization wait time count B ends, the ADCS
ADCS bit setting bit of the ADM0 register is set (1), and the system enters the hardware trigger standby
status.
Hardware trigger standby status
Start of A/D conversion by

generating a hardware trigger


the ADCR and ADCRH registers The conversion results are stored in the ADCR and ADCRH registers.
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15.7.3 Setting up hardware trigger wait mode
Figure 15-32. Setting up Hardware Trigger Wait Mode
Start of setup

ADPC register settings ANI0 to ANI5 pins: Set using the ADPC register
● ADM0 register
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
● ADM0 register setting
● ADM1 register setting ● ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
● ADM2 register setting
voltage.
● ADUL/ADLL register setting ADRCK bit: This is used to select the range for the A/D conversion result comparison
● ADS register setting value generated by the interrupt signal from AREA1, AREA3, and AREA2.
(The order of the settings is AWC bit: This is used to set up the SNOOZE mode function.
irrelevant.) ADTYP bit: 8-bit/10-bit resolution
These are used to specify the upper limit and lower limit A/D conversion result comparison
values.
● ADS register
Reference voltage The reference voltage stabilization wait time count A below may be required if the
values of the ADREFP1 and ADREFP0 bits are changed.
stabilization wait time count A
standby status.
Hardware trigger generation
Stabilization wait time for A/D The system automatically counts up to the stabilization wait time for A/D power supply.
power supply
Start of A/D conversion After counting up to the reference voltage stabilization wait time ends, A/D conversion starts.

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15.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software
trigger mode and one-shot conversion mode)
Figure 15-33. Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
Start of setup
The ADCEN bit of the PER0 register is set (1), and supplying the clock
PER0 register setting
starts.
● ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D
conversion time.
ADMD bit: This is used to specify the select mode.
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software
trigger mode.
ADSCM bit: One-shot conversion mode

ADREFP1, ADREFP0, and ADREFM bits: These are used to select the
● ADM1 register setting reference voltage.
● ADM2 register setting ADRCK bit: This is used to select the range for the A/D conversion result
comparison value generated by the interrupt signal from
● ADUL/ADLL register setting AREA1, AREA3, and AREA2.
● ADS register setting ADTYP bit: 8-bit/10-bit resolution
These are used to specify the upper limit and lower limit A/D conversion
result comparison values.
● ADS register
ADISS and ADS4 to ADS0 bits: These are used to select temperature
sensor output voltage or internal
reference voltage.
The reference voltage stabilization wait time count A may be required if

Reference voltage the values of the ADREFP1 and ADREFP0 bits are changed.
stabilization wait time count A If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait
If change the ADREFP1 and ADREFP0 = 1, 0: Setting prohibited
The ADCE bit of the ADM0 register is set (1), and the system enters the
ADCE bit setting
Reference voltage The reference voltage stabilization wait time count B (1 µs) is counted by
the software.
First A/D conversion time
stabilization wait time count B
After counting up to the reference voltage stabilization wait time count B

ADCS bit setting
ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion
starts
End of A/D conversion The A/D conversion end interrupt (INTAD) will be generated.
After ADISS is set (1), the initial conversion result cannot be used.
Second A/D conversion time
ADCS bit setting The ADCS bit of the ADM0 register is set (1), and A/D conversion starts.

being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
Caution This setting can be used only in HS (high-speed main) mode.
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15.7.5 Setting up test mode
Figure 15-34. Setting up Test Mode
Start of setup
● ADM0 register
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: This is used to specify the one-shot conversion mode.
● ADM1 register setting ADREFP1, ADREFP0, and ADREFM bits: These are used to select for the reference
● ADUL/ADLL register setting ADRCK bit: This is used to set the range for the A/D conversion result comparison
value generated by the interrupt signal to AREA2.
● ADS register setting
ADTYP bit: This is used to specify 10-bit resolution.
● ADTES register setting
(The order of the settings is ● ADUL/ADLL register
irrelevant.) These set ADUL to FFH and ADLL to 00H (initial values).
● ADS register
ADS4 to ADS0 bits: These are used to set to ANI0.
● ADTES register
ADTES1, ADTES0 bits: AVREFM/AVREFP
Reference voltage stabilization The reference voltage stabilization wait time count A may be required if the values of
the ADREFP1 and ADREFP0 bits are changed.
wait time count A
standby status.
Reference voltage stabilization The reference voltage stabilization wait time count B (1 µs) is counted by the software.
wait time count B
ADCS bit setting After counting up to the reference voltage stabilization wait time count B ends, the ADCS
bit of the ADM0 register is set (1), and A/D conversion starts.

the ADCR and ADCRH registers The conversion results are stored in the ADCR and ADCRH registers.
Caution For the procedure for testing the A/D converter, see 32.3.8 A/D test function.
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15.8 SNOOZE Mode Function
In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D
conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed
without operating the CPU. This is effective for reducing the operation current.
If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be
judged at a certain interval of time in SNOOZE mode. Using this function enables power supply voltage monitoring and
input key judgment based on A/D inputs.
In the SNOOZE mode, only the following conversion modes can be used:
● Hardware trigger wait mode (select mode, one-shot conversion mode)
● Hardware trigger wait mode (scan mode, one-shot conversion mode)
Caution That the SNOOZE mode can only be specified when the high-speed on-chip oscillator clock (fIH) or
the medium-speed on-chip oscillator clock (fIM) is selected for fCLK.
Figure 15-35. Block Diagram When Using SNOOZE Mode Function
Hardware trigger Clock request signal

Independent power supply RTC, input (internal signal)
A/D converter Clock generator
A/D conversion end
interrupt request
High-speed on-chip
signalNote 1 (INTAD)
oscillator clock
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP
mode (for details about these settings, see 15.7.3 Setting up hardware trigger wait modeNote 2). Just before move to
STOP mode, bit 2 (AWC) of A/D converter mode register 2 (ADM2) is set to 1. After the initial settings are specified, bit 0
(ADCE) of A/D converter mode register 0 (ADM0) is set to 1.
If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to
the A/D converter. After supplying this clock, the system automatically counts up to the A/D power supply stabilization
wait time, and then A/D conversion starts.
The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt signal is
generatedNote 1.
Notes 1. Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL
register), there is a possibility of no interrupt signal being generated.
2. Be sure to set the ADM1 register to E2H or E3H.
Remark The hardware trigger is INTRTCALM/INTRTCPRD or INTIT.

Specify the hardware trigger by using the A/D Converter Mode Register 1 (ADM1).
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(1) If an interrupt is generated after A/D conversion ends

If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request
signal (INTAD) is generated.
● While in the select mode

When A/D conversion ends and an A/D conversion end interrupt request signal (INTAD) is generated, the A/D
converter returns to normal operation mode from SNOOZE mode. At this time, be sure to clear bit 2 (AWC = 0:
SNOOZE mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D
conversion will not start normally in the subsequent SNOOZE or normal operation mode.
● While in the scan mode

If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four
channels, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE
mode to the normal operation mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of A/D
converter mode register 2 (ADM2) to 0. If the AWC bit is left set to 1, A/D conversion will not start normally in the
subsequent SNOOZE or normal operation mode.
Figure 15-36. Operation Example When Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode)
INTIT
Clock request signal

(internal signal) The clock request signal
remains at the high level.
ADCS
Conversion
Channel 1 Channel 2 Channel 3 Channel 4
channels
Interrupt signal
(INTAD)
An interrupt is generated
when conversion on one
of the channels ends.
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(2) If no interrupt is generated after A/D conversion ends

If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request
signal (INTAD) is not generated.
● While in the select mode

If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock
request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip
oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE
mode.
● While in the scan mode

If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the
four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion
of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input
later, A/D conversion work is again performed in the SNOOZE mode.
Figure 15-37. Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan
Mode)
INTIT

(internal signal)
The clock request signal

ADCS is set to the low level.
Conversion
Channel 1 Channel 2 Channel 3 Channel 4
channels
Interrupt signal
(INTAD)
No interrupt is generated when

conversion ends for any channel.
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Figure 15-38. Flowchart for Setting up SNOOZE Mode
Start of setup

ADPC register setting
ANI0 to ANI5 pins: Set using theADPC register
PMx register setting The ports are set to the input mode.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify theA/D conversion time.
• ADM0 register setting • ADM1 register
Normal ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
operation • ADM1 register setting ADSCM bit: One-shot conversion mode
ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
• ADM2 register setting
• ADM2 register
• ADUL/ADLL register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage.
setting ADRCK bit: This is used to select the range for theA/D conversion result comparison value
generated by the interrupt signal fromAREA1, AREA3, and AREA2.
• ADS register setting ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
(The order of the settings
These are used to specify the upper limit and lower limitA/D conversion result comparison values.
is irrelevant.)
• ADS register
The reference voltage stabilization wait time countA may be required if the values of theADREFP1
Reference voltage and ADREFP0 bits are changed.
stabilization wait time count A If change theADREFP1 and ADREFP0 = 1, 0: A = 5 µs
If change theADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait
Immediately before entering the STOP mode, enable the SNOOZE mode by setting theAWC bit of
AWC = 1 the ADM2 register to 1.
The ADCE bit of the ADM0 register is set (1), and the system enters theA/D conversion
ADCE bit setting standby status.
Enter the STOP mode
STOP
mode
Hardware trigger After hardware trigger is generated, the system automatically counts up to the stabilization
generation wait time for A/D power supply andA/D conversion is started in the SNOOZE mode.
The A/D conversion

operations are performed.
End of A/D conversion The A/D conversion end interrupt (INTAD) is generated.Note 1
SNOOZE
mode
The clock request signal
(an internal signal) is No INTAD
automatically set to the low generation
level in the SNOOZE mode.
Yes
Storage of conversion The conversion results are stored in theADCR and ADCRH registers.
results in the ADCR and
ADCRH registers
Normal
operation AWC = 0 Release the SNOOZE mode by clearing theAWC bit of the ADM2 register to 0.Note 2
Normal operation
Notes 1. If the A/D conversion end interrupt request signal (INTAD) is not generated by setting ADRCK bit and
ADUL/ADLL register, the result is not stored in the ADCR and ADCRH registers.
The system enters the STOP mode again. If a hardware trigger is input later, A/D conversion operation is
again performed in the SNOOZE mode.
2. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or
normal operation mode. Be sure to clear the AWC bit to 0.
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15.9 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage
per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is
expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024

= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error

This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these
express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error

When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog
input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity
error, and differential linearity error in the characteristics table.
Figure 15-39. Overall Error Figure 15-40. Quantization Error
1......1 1......1
Ideal line
Digital output
Digital output
Overall
error 1/2LSB Quantization error
1/2LSB
0......0 0......0
0 AVREF 0 AVREF
Analog input Analog input
(4) Zero-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes
from 0……001 to 0……010.
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(5) Full-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale – 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error

This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses
the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-
scale error and full-scale error are 0.
(7) Differential linearity error

While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and
the ideal value.
Figure 15-41. Zero-Scale Error Figure 15-42. Full-Scale Error
111
Digital output (Lower 3 bits)
Full-scale error
Digital output (Lower 3 bits)

Ideal line
111
011
110
010
101 Ideal line

001
Zero-scale error
000
000 0 1021/1024 1022/1024 1023/1024 AVREF
0 1/1024 AV REF 2/1024 AV REF 3/1024 AV REF AVREF AVREF AVREF AVREF
Analog input (V) Analog input (V)
Figure 15-43. Integral Linearity Error Figure 15-44. Differential Linearity Error
1......1
1......1
Ideal 1LSB width
Ideal line
Digital output
Digital output
Differential
Integral linearity linearity error
error
0......0 0......0
0 AVREF 0 AVREF
Analog input Analog input
(8) Conversion time

This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time

This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
Conversion time
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15.10 Cautions for A/D Converter
(1) Operating current in STOP mode

Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0
(ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same
time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start
operation.
(2) Input range of ANI0 to ANI5 pins

Observe the rated range of the ANI0 to ANI5 pins input voltage. If a voltage exceeding VDD and AVREFP or below VSS
and AVREFM (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value
of that channel becomes undefined. In addition, the converted values of the other channels may also be affected.
When internal reference voltage (1.45 V) is selected reference voltage for the + side of the A/D converter, do not input
voltage exceeding internal reference voltage (1.45 V) to a pin selected by the ADS register. However, the input of
voltages exceeding the internal reference voltage (1.45 V) to pins not selected by the ADS register does not create a
problem.
Caution Internal reference voltage (1.45 V) can be used only in HS (high-speed main) mode.
(3) Conflicting operations
<1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register
read by instruction upon the end of conversion
The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to
the ADCR or ADCRH registers.
<2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register 0 (ADM0) write, the
analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end
of conversion
The ADM0, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed,
nor is the conversion end interrupt signal (INTAD) generated.
(4) Noise countermeasures

To maintain the 10-bit resolution, attention must be paid to noise input to the AVREFP, VDD, ANI0 to ANI5 pins.
<1> Connect a capacitor with a low equivalent resistance and a good frequency response (capacitance of about
0.01 µF) via the shortest possible run of relatively thick wiring to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
connecting an external capacitor as shown in Figure 15-45 is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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Figure 15-45. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREFP and

VDD or equal to or lower than AVREFM and VSS may enter, clamp with
a diode with a small VF value (0.3 V or lower).
Reference
voltage AVREFP or VDD
input
ANI0 to ANI5
C = 10 pF to 0.1 µF
(5) Analog input (ANIn) pins
<1> The analog input pins (ANI0 to ANI5) are also used as input port pins (P20 to P25).
When A/D conversion is performed with any of the ANI0 to ANI5 pins selected, do not change to output value
P20 to P25 while conversion is in progress; otherwise the conversion resolution may be degraded.
<2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result
might differ from the expected value due to a coupling noise. Be sure to avoid the input or output of digital
signals and signals with similarly sharp transitions during A/D conversion.
(6) Input impedance of analog input (ANIn) pins

This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress,
and on the other states.
To make sure that sampling is effective, however, we recommend using the converter with analog input sources that
have output impedances no greater than 1 kΩ. If a source has a higher output impedance, lengthen the sampling
time or connect a larger capacitor (with a value of about 0.1 µF) to the pin from among ANI0 to ANI5 which the source
is connected (see Figure 15-45). The sampling capacitor may be being charged while the setting of the ADCS bit is 0
and immediately after sampling is restarted and so is not defined at these times. Accordingly, the state of conversion
is undefined after charging starts in the next round of conversion after the value of the ADCS bit has been 1 or when
conversion is repeated. Thus, to secure full charging regardless of the size of fluctuations in the analog signal,
ensure that the output impedances of the sources of analog inputs are low or secure sufficient time for the completion
of conversion.
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(7) Interrupt request flag (ADIF)

The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
Figure 15-46. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite ADS rewrite ADIF is set but ANIm conversion

(start of ANIn conversion) (start of ANIm conversion) has not ended.
A/D conversion ANIn ANIn ANIm ANIm
ADCR ANIn ANIn ANIm ANIm
ADIF
(8) Conversion results just after A/D conversion start

While in the software trigger mode or hardware trigger no-wait mode, the first A/D conversion value immediately after
A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 µs after the ADCE bit was
set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation

When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR and ADCRH registers may
become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, or
ADPC register. Using a timing other than the above may cause an incorrect conversion result to be read.
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(10) Internal equivalent circuit

The equivalent circuit of the analog input block is shown below.
Figure 15-47. Internal Equivalent Circuit of ANIn Pin
R1
ANIn
C1 C2
Table 15-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREFP, VDD ANIn Pins R1 [kΩ] C1 [pF] C2 [pF]
3.6 V ≤ VDD ≤ 5.5 V ANI0 to ANI5 14 8 2.5
2.7 V ≤ VDD ≤ 3.6 V ANI0 to ANI5 39 8 2.5
1.9 V ≤ VDD < 2.7 V ANI0 to ANI5 231 8 2.5
Remark The resistance and capacitance values shown in Table 15-4 are not guaranteed values.
(11) Starting the A/D converter

Start the A/D converter after the AVREFP and VDD voltages stabilize.
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RL78/I1C CHAPTER 16 TEMPERATURE SENSOR 2
CHAPTER 16 TEMPERATURE SENSOR 2
16.1 Functions of Temperature Sensor
The RL78/I1C has an on-chip temperature sensor. Temperature can be measured by measuring the output voltage
from the temperature sensor using the 10-bit A/D converter. The mode of the temperature sensor can be switched to one
of the following three modes by setting the temperature control register.
● High-temperature range mode: Mode 1, 0°C to 90°C (Output Image Diagram Mode 1)
● Normal-temperature range mode: Mode 2, –20°C to 70°C (Output Image Diagram Mode 2)
● Low-temperature range mode: Mode 3, –40°C to 50°C (Output Image Diagram Mode 3)
Temperature sensor may be used in HS (high-speed main) mode.
Figure 16-1 shows a block diagram of temperature sensor.
Figure 16-1. Block Diagram
10-bit
Temperature sensor A/D converter
Temperature sensor control TMPEN TMPSEL1 TMPSEL0

test register (TMPCTL)
Internal bus
Figure 16-2. Output Image Diagram
Temperature sensor output voltage (V)
1.25
Mode 3 Mode 2 Mode 1
0.1
0
TJ = -40 TJ = -10 TJ = 25 TJ = 55 TJ = 90 Temp. (°C)
: Area where linearity can be secured
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16.2 Registers
Table 16-1 shows the register used for the temperature sensor.
Table 16-1. Register
Item Configuration
Control registers Temperature sensor control test register (TMPCTL)

Peripheral enable register 0 (PER0)

The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the temperature sensor 2 is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 16-3. Format of Peripheral enable register 0 (PER0)

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
ADCEN Control of input clock supply to A/D converter and temperature sensor 2

● SFR used by the A/D converter and temperature sensor 2 cannot be written. The read value is
00H. However, the SFR is not initialized. Note
● SFR used by the A/D converter and temperature sensor 2 can be read and written.
Note To initialize the A/D converter and the SFR used by the A/D converter and temperature sensor 2, use bit 5
(ADCRES) of PRR0.
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16.2.2 Temperature sensor control test register (TMPCTL)

The TMPCTL register is used to stop or start operation of the temperature sensor, and select the mode of the
temperature sensor.
The TMPCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset generation clears this register to 00H.
Figure 16-4. Format of Temperature sensor control test register (TMPCTL)
Address: F03B0H After reset: 00H R/W

Symbol <7> 6 5 4 3 2 1 0
Note 1 Note 2
TMPCTL TMPEN 0 0 0 0 0 TMPSEL1 TMPSEL0Note 2
TMPEN Temperature sensor operation control
0 Temperature sensor stops operation

1 Temperature sensor starts operation
TMPSEL1 TMPSEL0 Temperature sensor operation selection
0 0 Normal-temperature range (Mode 2)
0 1 High-temperature range (Mode 1)

1 0 Low-temperature range (Mode 3)
Notes 1. After setting the TMPEN bit to 1, a 50 µs operation stabilization wait time is necessary.
2. After changing bits TMPSEL1-TMPSEL0, a 15 µs mode switch stabilization wait time is necessary.
Cautions 1. Be sure to clear bits 6 to 2 to “0”.

2. When using a temperature sensor, use a 10-bit A/D converter at internal reference voltage. If you
select VDD as reference voltage, operation will not be normal.

To reset the temperature sensor, be sure to set bit 5 (ADCRES) to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
ADCRES Control resetting of the A/D converter and temperature sensor 2
0 Releases the A/D converter and temperature sensor 2 from the reset state.
1 The A/D converter and temperature sensor 2 are in the reset state.
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16.3 Setting Procedures
The procedures for setting the temperature sensor are shown below.
16.3.1 Starting operation of the temperature sensor

Figure 16-6 shows the setting flowchart when starting operation of temperature sensor.
Figure 16-6. Setting Flowchart When Starting Operation of Temperature Sensor
Start settings State after the reset is released
Set the PER0 register • Set ADCEN = 1
Set the TMPSEL1 to TMPSEL0 bits • Set the mode of the temperature sensor
Set the TMPEN bit • Set TMPEN = 1 (temperature sensor starts operation)
Operation stabilization wait timeNote

(50 µs)
Set the 10-bit A/D converter

• Set ADTES1 = 1, ADTES0 = 0 (AVREFM)
initialization processing

to start dummy conversion

• Set ADTES1 = 0, ADTES0 = 0 (ADISS, ADS)
normalization processing
Set the ADM2 register • ADREFP1, ADREFP0: Select internal reference

voltage (1.45 V)
Set the ADS register • Bits ADS4 to ADS0: Select temperature sensor output

to start conversion
Note Operation stabilization wait time is required until the A/D converter starts conversion.
Caution Select internal reference voltage for 10-bit A/D converter.
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16.3.2 Switching modes

Figure 16-7 shows the setting flowchart when switching mode of temperature sensor.
Figure 16-7. Setting Flowchart When Switching Mode of Temperature Sensor
Start settings ADCEN = 1, TMPEN = 1
Set the TMPSEL1 to TMPSEL0 bits • Set these bits according to the range to be measured
Note
Mode switch stabilization wait time
(15 µs)

to start conversion
Note Mode switch stabilization wait time is required until the A/D converter starts conversion.
Caution Select internal reference voltage for 10-bit A/D converter.
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RL78/I1C CHAPTER 17 24-BIT ΔΣ A/D CONVERTER
CHAPTER 17 24-BIT ΔΣ A/D CONVERTER
The 24-bit ΔΣ A/D converter has a 24-bit resolution when converting an analog input signal to digital values.
17.1 Functions of 24-bit ΔΣ A/D Converter
The 24-bit ΔΣ A/D converter has the following functions:
Օ S/N+D ratio: 80 dB min. (when pre-amplifier gain of ×1 is selected)

Օ 24-bit resolution (conversion result register: 24 bits)
Օ 3 channels (current channel: 2 channels voltage channel: 1 channel) (80-pin products)
Օ 4 channels (current channel: 2 channels voltage channel: 2 channels) (64-pin products, 100-pin products)
Օ Analog input: 8 (positive, negative input/channel)
Օ ΔΣ conversion mode
Օ Pre-amplifier gain selectable: ×1, ×2, ×4, ×8, ×16, or ×32Note (channels 0, 1, 2, and 3)
Օ Operating voltage: VDD or VBAT = 2.4 to 5.5 V, AVSS = 0 V
Օ Analog input voltage: ±0.500 V (when pre-amplifier gain of ×1 is selected)
±0.250 V (when pre-amplifier gain of ×2 is selected)
±0.125 V (when pre-amplifier gain of ×4 is selected)
±62.5 mV (when pre-amplifier gain of ×8 is selected)
±31.25 mV (when pre-amplifier gain of ×16 is selected)
±15.625 mV (when pre-amplifier gain of ×32Note is selected)
Օ Reference voltage generation (0.8 V (TYP.) can be output)
Օ Sampling frequency: 3906.25 Hz (4 kHz sampling mode)/1953.125 Hz (2 kHz sampling mode)
Օ HPF cutoff frequency: 0.607 Hz, 1.214 Hz, 2.429 Hz, or 4.857 Hz can be selected
Օ Operating clock: High-speed system clock (fMX) (only 12 MHz crystal resonator can be used)
High-speed on-chip oscillator (fIH)
Note The gain is multiplied by 2 by the digital filter.
Cautions 1. When using the high-speed system clock (fMX) by setting DSADCK in the PCKC register to 1,
supply 12 MHz.
2. The 24-bit ΔΣ A/D converter cannot be used in the LP (low-power main) or LV (low-voltage main)
mode.
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Table 17-1 lists the configuration of 24-bit ΔΣ A/D converter. Figures 17-1 and 17-2 show the block diagram of 24-bit
ΔΣ A/D converter, respectively.
Table 17-1. Configuration of 24-bit ΔΣ A/D Converter
Item Configuration
Analog input 3 channels and 6 inputs (80-pin products)

4 channels and 8 inputs (64-pin products, 100-pin products)
Internal units Pre-amplifier block
ΔΣ A/D converter
Reference voltage generation
<R> Phase adjustment circuit (PHC0, PHC1, PHC2, PHC3)

Digital filter (DF)
High-pass filter (HPF)
Zero-cross detection
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Figure 17-1. Block Diagram of 24-bit ΔΣ A/D Converter (64-pin Products, 100-pin Products)
Analog block Digital block
Zero-cross detection Interrupt

INTDSADZC0
Digital
adjustment
INTDSADZC1
(PHC0)
ANIN0 -x1 to x16  A/D converter
Phase
filter
ANIP0 + Channel 0
(DF0)
Digital
adjustment
(PHC1)
Phase
filter
ANIP1 + Channel 1 High-
(DF1)
pass filter
Digital
adjustment
(HPF)
(PHC2)
Phase
filter
ANIP2 + Channel 2
(DF2)
DSADCR0
Digital DSADCR1
adjustment
Interrupt
(PHC3)
Phase
DSADCR2
filter INTDSAD
ANIP3 + Channel 3 DSADCR3
(DF3)
Internal
AREGC
bus
AVCM
AVRT
0.1 µF to 4.7 µF
PCKC
VDD
10 µF + 0.1 µF
VBAT Regulator for  A/D DCLK Operation clock (12 MHz) High-speed on-chip oscillator/2
converter
High-speed system clock (12 MHz)
generator
10 µF + 0.1 µF
DSADCEN
AVSS
Figure 17-2. Block Diagram of 24-bit ΔΣ A/D Converter (80-pin Products)
Analog block Digital block
Zero-cross detection Interrupt

INTDSADZC0
Digital
adjustment
INTDSADZC1
(PHC0)

Phase
filter
ANIP0 + Channel 0
(DF0)
Digital
adjustment
(PHC1)

Phase
filter
ANIP1 + Channel 1 High-
(DF1)
pass filter
Digital
adjustment
(HPF)
(PHC2)

Phase
filter
ANIP2 + Channel 2
(DF2)
DSADCR0
DSADCR1
DSADCR2
Interrupt
INTDSAD
Internal
AREGC
bus
AVCM
AVRT
0.1 µF to 4.7 µF
PCKC
VDD
10 µF + 0.1 µF VBAT Regulator for  A/D DCLK Operation clock (12 MHz) High-speed on-chip oscillator/2
converter
High-speed system clock (12 MHz)
generator
10 µF + 0.1 µF
DSADCEN
AVSS
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17.1.1 I/O pins

Table 17-2 lists the I/O pins for the 24-bit ΔΣ A/D converter.
Table 17-2. Pin Configuration
Name Symbol I/O Function
Analog input positive pin 0 to analog input ANIPn Input Analog input pin for ΔΣ A/D converter (positive input)Notes 1, 3
positive pin 3
Analog input negative pin 0 to analog input ANINn Input Analog input pin for ΔΣ A/D converter (negative input)Notes 1, 3
negative pin 3
ΔΣ A/D converter power supply voltage pin AREGC – ΔΣ A/D converter power supply voltage
Common voltage pin AVCM – Common voltage
Reference voltage pin AVRT – Reference voltage
Analog power supply pin 1 VDD – Analog power supplyNote 2
Analog power supply pin 2 VBAT – Analog power supplyNote 2
Analog GND AVSS – Analog GND pin
Notes 1. One channel inputs two signals. The ANINn pin is the negative input, while the ANIPn pin is the positive
input.
2. Connect capacitors of 10 µF + 0.1 µF as stabilization capacitance between the VDD/VBAT and AVSS pins.
3. Consider the sensor delay when selecting the pin for a single phase two-wire meter.
Remark n = 0 to 3 for 64- and 100-pin products, n = 0 to 2 for 80-pin products
17.1.2 Pre-amplifier
This unit amplifies an analog input signal to be input to the ANINn and ANIPn pins.
The gain can be set to ×1, ×2, ×4, ×8, ×16, or ×32Note using the register settings.
17.1.3 ΔΣ A/D converter

Four ΔΣ A/D converter circuits are provided so that a total of four channels of analog inputs can be converted into 2-bit
digital signals. These four ΔΣ A/D converter circuits operate synchronously. Each 2-bit digital value is passed through the
phase adjustment circuit, the digital filter, and the high-pass filter, and then stored into the conversion result registers
(DSADCR0 to DSADCR3) as the conversion result of each channel. Each time conversion of all four channels is
completed, the interrupt request signal is generated to inform the CPU that the conversion result can be read. The
sampling frequency (fs) can be selected as 3906.25 Hz or 1953.125 Hz. The maximum pending time and over-sampling
frequency vary as follows depending on the sampling frequency. Complete reading of the ΔΣ A/D conversion result
register before the maximum pending time.
Sampling Frequency (fs) Maximum Pending Time Over-sampling Frequency
3906.25 Hz (4 kHz sampling mode) 192 µs 1.5 MHz

1953.125 Hz (2 kHz sampling mode) 384 µs 750 kHz
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17.1.4 Reference voltage generator

An internal reference voltage source (band-gap reference circuit) is provided and a reference voltage is output from the
reference voltage output pin AVRT. Connect a capacitor of 0.47 µF as external capacitance.
17.1.5 Phase adjustment circuits (PHCn)

This circuit adjusts the phase of input analog signals. The phase between analog signals is adjusted in steps (one step
= 384 fs) up to 1151 steps.
Phase shifts between input analog signals occur due to external components (such as current sensors). Use the
DSADPHCn register to correct such phase shifts in advance, because these shifts can decrease the precision of power
calculations.
A step for correcting phase shifts can be adjusted in 0.0144° units if the line frequency is 60 Hz, or in 0.0120° units if
the line frequency is 50 Hz.
Four phase adjustment circuits (PHC0 to PHC3) are provided in the RL78/I1C and each phase can be adjusted for
input signals.
17.1.6 Digital filter (DF)

This unit eliminates high harmonic signal included in the ΔΣ A/D converter and thins out the data rate to 1/384.
17.1.7 Zero-cross detection

Interrupt is generated when any timing for reversing signs is detected in the operation result of the digital filter.
17.1.8 High-pass filter (HPF)

This unit eliminates the DC component included in the input signal and the DC offset generated by the analog circuit.
Whether the high-pass filter is inserted or not can be selected for each channel.
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17.2 Registers
Table 17-3 lists the registers used for the 24-bit ΔΣ A/D converter.
Item Configuration
Control registers ΔΣ A/D converter mode register (DSADMR)
ΔΣ A/D converter gain control register 0 (DSADGCR0)
ΔΣ A/D converter gain control register 1 (DSADGCR1)
ΔΣ A/D converter interrupt control register (DSADICR)
ΔΣ A/D converter interrupt clear register (DSADICLR)
ΔΣ A/D converter interrupt status register (DSADISR)
ΔΣ A/D converter HPF control register (DSADHPFCR)
ΔΣ A/D converter phase control register 0 (DSADPHCR0)
Registers ΔΣ A/D converter conversion result register 0L (DSADCR0L)
ΔΣ A/D converter conversion result register 0M (DSADCR0M)
ΔΣ A/D converter conversion result register 0H (DSADCR0H)
ΔΣ A/D converter conversion result register 1L (DSADCR1L)
ΔΣ A/D converter conversion result register 0 (DSADCR0)
Peripheral clock control register (PCKC)
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17.2.1 ΔΣ A/D converter mode register (DSADMR)

The DSADMR register is used to set the operating mode of the ΔΣ A/D converter. This register is used to select the
sampling period and the resolution of the ΔΣ A/D converter, and control powering on each channel and enabling its
operation.
The DSADMR register can be set by a 16-bit memory manipulation instruction.
Figure 17-3. Format of ΔΣ A/D Converter Mode Register (DSADMR)
Address: F03C0H After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSADMR DSAD DSAD 0 0 DSAD DSAD DSAD DSAD 0 0 0 0 DSAD DSAD DSAD DSAD
FR TYP PON3 PON2 PON1 PON0 CE3 CE2 CE1 CE0
DSADFR Sampling frequency selection

0 3906.25 Hz
1 1953.125 Hz
This bit is used to select the sampling frequency.
DSADTYP Resolution selection when reading ΔΣ A/D converter conversion result register
0 24-bit resolution
1 16-bit resolution
When DSADTYP = 0:
The lower 16 bits in the ΔΣ A/D converter conversion result register can be read by reading the ΔΣ A/D converter conversion
result register (DSADCRn). Read DSADCRnH as the higher 8 bits.
When DSADTYP = 1:
The higher 16 bits in the ΔΣ A/D converter conversion result register can be read by reading the ΔΣ A/D converter conversion
result register (DSADCRn).
DSADPONn ΔΣ A/D converter power-on control (analog block) of channel n
0 Power down
1 Power on
DSADCEn ΔΣ A/D converter operation enable (analog and digital blocks) of channel n
0 Electric charge reset
1 Normal operation
This bit is used to enable conversion operation of the ΔΣ A/D converter. The charge of the analog block and the conversion result
of the digital block are reset. To reset the charge of the ΔΣ A/D converter normally, first set the DSADCEn bit from 1 to 0, and
then wait for at least 1.4 µs before performing conversion again.
(Caution and Remark are listed on the next page.)
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Cautions 1. When a clock faster than 12 MHz is selected as the CPU clock (fCLK), do not write to the DSADMR
register successively. When writing to this register successively, allow at least one cycle of fCLK
between writes. Three cycles is required until the ΔΣ A/D converter is powered down after the
DSADPONn bit is set to 0. When setting the DSADPONn bit to 1 again, be sure to allow at least three
cycles of fCLK before powering on the ΔΣ A/D converter.
2. Be sure to clear bits 13, 12, and 7 to 4 to “0”.
Remark n = 0 to 3
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17.2.2 ΔΣ A/D converter gain control register 0 (DSADGCR0)

The DSADGCR0 register is used to select the gain of the programmable gain amplifier of channels 0 and 1.
DSADGCR0 can be set by an 8-bit memory manipulation instruction.
Figure 17-4. Format of ΔΣ A/D Converter Gain Control Register 0 (DSADGCR0)

Symbol 7 6 5 4 3 2 1 0
DSADGCR0 0 DSADGAIN12 DSADGAIN11 DSADGAIN10 0 DSADGAIN02 DSADGAIN01 DSADGAIN00
DSADGAIN12 DSADGAIN11 DSADGAIN10

Selection of programmable amplifier gain of channel 1
Bit 6 Bit 5 Bit 4
0 0 0 PGA gain: ×1
0 0 1 PGA gain: ×2
0 1 0 PGA gain: ×4
0 1 1 PGA gain: ×8
1 0 0 PGA gain: ×16
1 0 1 PGA gain: ×32Note
These bits are used to control the PGA gain. The gain can be set in the range of ×1 to ×32.

Bit 2 Bit 1 Bit 0
0 0 0 PGA gain: ×1
0 0 1 PGA gain: ×2
0 1 0 PGA gain: ×4
0 1 1 PGA gain: ×8
1 0 0 PGA gain: ×16
Caution Be sure to clear bits 7 and 3 to “0”.
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17.2.3 ΔΣ A/D converter gain control register 1 (DSADGCR1)

The DSADGCR1 register is used to select the gain of the programmable gain amplifier of channels 2 and 3.
DSADGCR1 can be set by an 8-bit memory manipulation instruction.
Figure 17-5. Format of ΔΣ A/D Converter Gain Control Register 1 (DSADGCR1)

Symbol 7 6 5 4 3 2 1 0
DSADGCR1 0 DSADGAIN32 DSADGAIN31 DSADGAIN30 0 DSADGAIN22 DSADGAIN21 DSADGAIN20

Bit 6 Bit 5 Bit 4
0 0 0 PGA gain: ×1
0 0 1 PGA gain: ×2
0 1 0 PGA gain: ×4
0 1 1 PGA gain: ×8
1 0 0 PGA gain: ×16

Bit 2 Bit 1 Bit 0
0 0 0 PGA gain: ×1
0 0 1 PGA gain: ×2
0 1 0 PGA gain: ×4
0 1 1 PGA gain: ×8
1 0 0 PGA gain: ×16
Caution Be sure to clear bits 7 and 3 to “0”.
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17.2.4 ΔΣ A/D converter HPF control register (DSADHPFCR)

The DSADHPFCR register is used to select the cutoff frequency of the high pass filter and disable or enable the high-
pass filter for each channel.
DSADHPFCR can be set by an 8-bit memory manipulation instruction.
Figure 17-6. Format of ΔΣ A/D Converter HPF Control Register (DSADHPFCR)

Symbol 7 6 5 4 3 2 1 0
DSADHPFCR DSADCOF1 DSADCOF0 0 0 DSADTHR3 DSADTHR2 DSADTHR1 DSADTHR0
DSADCOF1 DSADCOF0
Selection of cutoff frequency of high-pass filter
Bit 7 Bit 6
0 0 0.607 Hz
0 1 1.214 Hz
1 0 2.429 Hz
1 1 4.857 Hz
DSADTHR3 High-pass filter disable of channel 3

0 High-pass filter used
1 High-pass filter not used



Cautions 1. Be sure to clear bits 5 and 4 to “0”.

2. Writing to the DSADTHRn bit shall be completed when any of the following conditions is satisfied:
● DSADCEn = 0 (Conversion is being stopped)
● Within 21 µs from the zero-cross detection interrupt
Remark The high-pass filter convergence time can be changed by changing the high-pass filter cut-off frequency. The
convergence time decreases as the cut-off frequency increases.
To initialize the high-pass filter, use the DSADRES bit of the peripheral reset control register (PRR1).
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17.2.5 ΔΣ A/D converter interrupt control register (DSADICR)

The DSADICR register is used to control the zero-cross detection interrupt.
DSADICR can be set by an 8-bit memory manipulation instruction.
Figure 17-7. Format of ΔΣ A/D Converter Interrupt Control Register (DSADICR)

Symbol 7 6 5 4 3 2 1 0
DSADICR DSADZC DSADZC DSADZC DSADZC DSADZC DSADZC DSADZC DSADZC
EGP1 EGN1 MD1 CTL1 EGP0 EGN0 MD0 CTL0
DSADZC DSADZC
Selection of zero-cross detection edge of DF output
EGPn EGNn
0 0 Zero-cross detection disabled

0 1 Falling edge of DSADZCn
1 0 Rising edge of DSADZCn
1 1 Both rising and falling edges of DSADZCn
DSADZC
Zero-cross detection mode selection
MDn
0 Pulse output mode

1 Level output mode
DSADZC
Zero-cross detection channel selection bit 1
CTL1
0 Channel 3
1 Channel 0
DSADZC
Zero-cross detection channel selection bit 0
CTL0
0 Channel 2
1 Channel 1
Caution Since 3 cycles are required for the synchronization at the sampling frequency (3906.25 Hz/1953.125 Hz)
for this register, the operation after 4 cycles at sampling frequency is reflected when the setting value is
rewritten. After reflecting, the next write instruction can be accepted.
Remark n = 0, 1
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DSADZCEGNn bit, DSADZCEGPn bit (n = 0, 1)

These bits are used to set the valid edges that generate a zero-cross detection interrupt to the DF output. The DF
output zero-cross detection conditions and relationships between waveforms of the DF output and the DSADZCn
bit are shown in the Figures 17-8 to 17-11.
Table 17-4. Zero-cross Detection Conditions for the DF Output
DSADZC DSADZC
Detection Edge Selection
EGPn EGNn
0 0 Zero-cross detection disabled

0 1 Falling edge of DSADZCn
1 0 Rising edge of DSADZCn
1 1 Both rising and falling edges of DSADZCn
Figure 17-8. INTDSADZCn Interrupt Generation Timing

(Pulse output: DSADZCMDn = 0, DSADZCEGNn = 0, DSADZCEGPn = 0)
DF output n 0
DSADZCn
Zero-cross detection interrupt n

DF output n 0
DSADZCn
Sampling frequency
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DF output n 0
DSADZCn
Sampling frequency

DF output n 0
DSADZCn
Sampling frequency
DSADZCMDn bit (n = 0, 1)
This bit is used to select the output type of zero-cross detection interrupt.
Interrupts may be generated for several times in the proximity of a zero cross when the DF output includes
harmonic signals in the case of setting “0” (pulse output mode). Set “1” (level output mode) to prevent the interrupt
from generating for several times.
It is necessary to clear the assertion by software when the zero-cross detection interrupt is asserted once in the
case of setting a level output mode.
For more information on the operation, see Figures 17-23 and 17-25 in 17.3.3.1 Zero-cross detection interrupt
operation.
DSADZCCTLn bit (n = 0, 1)
This bit is used to select a target channel for detecting a zero-cross.
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17.2.6 ΔΣ A/D converter interrupt clear register (DSADICLR)

The DSADICLR register is used to clear the zero-cross detection interrupt.
DSADICLR is set by an 8-bit memory manipulation instruction.
Figure 17-12. ΔΣ A/D Converter Interrupt Clear Register (DSADICLR) Format
Address: F03C9H After reset: 00H W

Symbol 7 6 5 4 3 2 1 0
DSADICLR 0 0 0 DSADICL1 0 0 0 DSADICL0
DSADICL1 Zero-cross detection interrupt 1 clear bit
0 Does not clear zero-cross detection interrupt 1 (INTDSADZC1).

1 Clears zero-cross detection interrupt 1 (INTDSADZC1).
DSADICL0 Zero-cross detection interrupt 0 clear bit
0 Does not clear zero-cross detection interrupt 0 (INTDSADZC0).

1 Clears zero-cross detection interrupt 0 (INTDSADZC0).
DSADICLn bit (n = 0, 1)
Writing 1 to this bit clears the zero-cross detection interrupt n (INTDSADZCn). Writing 0 to this bit does not operate
the register. Reading value of this bit is 0 regardless of the writing value. The clear operation of the zero-cross
detection interrupt by the software is prioritized when the timings of zero-cross detection interrupt and writing 1 to
this bit simultaneously occur. This register is cleared after 3 cycles at the sampling frequency when 1 is written to
this bit. Next clear instruction can be accepted after the clear.
Figure 17-13. INTDSADZCn Interrupt Generation Clear Timing
Sampling frequency (1) (2) (3) (1) (2) (3) (1) (2) (3)
Conversion
completion interrupt
Zero-cross interrupt n
*
Writing 1 to the
DSADICLn bit
Invalid (1) (2) (3) Next clear acceptance enabled
instruction
* Conflict of set and clear
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17.2.7 ΔΣ A/D converter interrupt status register (DSADISR)

<R> The DSADISR register indicates the zero-cross detection interrupt status.
DSADISR is set by an 8-bit memory manipulation instruction.
Figure 17-14. ΔΣ A/D Converter Interrupt Status Register (DSADISR) Format
Address: F03CAH After reset: 22H R

Symbol 7 6 5 4 3 2 1 0
DSADISR 0 0 DSADZC1 DSADZCI1 0 0 DSADZC0 DSADZCI0
DSADZCn DF output status bit n
0 DF output n is in the negative status

1 DF output n is in the positive status
This bit is used to indicate the status of DF output in the target channel, which is selected by the DSADZCCTLn bit.
DSADZCIn Zero-cross detection interrupt status bit n
0 Zero-cross detection interrupt n (INTDSADZCn) is 0.

1 Zero-cross detection interrupt n (INTDSADZCn) is 1.
This bit is used to monitor the zero-cross detection interrupt (INTDSADZCn).
<Setting conditions>
● When detecting the zero-cross by the valid edge that is set by the DSADZCEGNn and DSADZCEGPn bits in the DSADICR
register.
<Clear conditions>
● Automatically clears after the elapse of one sampling time when in the pulse output mode (DSADZCMDn = 0 in the DSADICR
register.)
● Cleared by software when in the level output mode (DSADZCMDn = 1 in the DSADICR register)
Caution The zero-cross detection interrupt may be generated for several times in the proximity of a zero cross
due to the harmonic signals included in DF output. Therefore, clear the interrupts by writing 1 to the
DSADICLn bit by using software after a certain period of time. Interrupts may possibly be generated
again due to the harmonic signals when they are cleared immediately after the generation of the zero-
cross detection interrupt.
Remark n = 0, 1
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17.2.8 ΔΣ A/D converter phase control register n (DSADPHCRn) (n = 0, 1, 2, 3)

The DSADPHCRn register is used to select the channel for input to the phase adjustment n circuit and set the
adjustment step.
DSADPHCRn can be set by a 16-bit memory manipulation instruction.
Figure 17-15. Format of ΔΣ A/D Converter Phase Control Register n (DSADPHCRn) (n = 0, 1, 2, 3)
Address: F03D0H (DSADPHCR0), F03D2H (DSADPHCR1), F03D4H (DSADPHCR2), F03D6H (DSADPHCR3)

After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSADPHCRn DSAD DSAD DSAD DSAD DSAD DSAD DSAD DSAD DSAD DSAD DSAD
0 0 0 0 0 PHCn PHCn PHCn PHCn PHCn PHCn PHCn PHCn PHCn PHCn PHCn
10 9 8 7 6 5 4 3 2 1 0
DSADPHCn10 to
ΔΣ A/D converter channel n phase adjustment
DSADPHCn0Note
000H Through (no phase adjustment)

001H One step
... ...
47EH 1150 steps
47FH 1151 steps
These bits are used to adjust the phase of 2-bit ΔΣ A/D conversion data input from the analog block.
The DSADPHCn10 to DSADPHCn0 bits are used to specify the phase adjustment (one step = 384 fs).
Since the sampling frequency (3906.25 Hz) is included in the calculation of the adjustment value, the phase that can be adjusted
by correcting one step is 1 [s]/(384 [fs] × 3906.25 [Hz]) = 0.6667 [µs].
Example: To adjust the phase by 100 µs for 2-bit signal input from the analog block, the register set value will be 96H since
100/0.6667 = 150 [steps].
Note These bits cannot be set to a value of 480H or greater.
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17.2.9 ΔΣ A/D converter conversion result register n (DSADCRnL, DSADCRnM, DSADCRnH) (n = 0, 1, 2, 3)

The DSADCRn (H/M/L) registers are 24-bit registers used to retain the conversion results of the ΔΣ A/D converter of
each channel.
The DSADCRnL, DSADCRnM, and DSADCRnH registers can be read individually by an 8-bit manipulation instruction.
Reading of the conversion result of the ΔΣ A/D converter differs depending on the setting of the DSADTYP bit in the ΔΣ
A/D converter mode register (DSADMR).
Setting the DSADCEn bit in the ΔΣ A/D converter mode register (DSADMR) to 0 or reset signal generation clears the
DSADCRnL, DSADCRnM, and DSADCRnH registers to 00H.
Figure 17-16. Format of ΔΣ A/D Converter Conversion Result Register n

(DSADCRnL, DSADCRnM, DSADCRnH) (n = 0, 1, 2, 3)
Address: F03E0H (DSADCR0L) F03E1H (DSADCR0M) F03E2H (DSADCR0H)

F03E4H (DSADCR1L) F03E5H (DSADCR1M) F03E6H (DSADCR1H)
F03E8H (DSADCR2L) F03E9H (DSADCR2M) F03EAH (DSADCR2H)
F03ECH (DSADCR3L) F03EDH (DSADCR3M) F03EEH (DSADCR3H)
After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
DSADCRnH DSADCRnH[7:0]
Symbol 7 6 5 4 3 2 1 0
DSADCRnM DSADCRnM[7:0]
Symbol 7 6 5 4 3 2 1 0
DSADCRnL DSADCRnL[7:0]
● When 24-bit resolution is set (DSADTYP in the DSADMR register = 0)
DSADCRnH DSADCRnM DSADCRnL
Bit b23 b16 b15 b8 b7 b0
ΔΣ A/D conversion result n [23:16] ΔΣ A/D conversion result n [15:8] ΔΣ A/D conversion result n [7:0]
Bit Symbol Conversion result of channel n
b7 to b0 DSADCRnL[7:0] Conversion result bits 7 to 0 of channel n

b15 to b8 DSADCRnM[7:0] Conversion result bits 15 to 8 of channel n
b23 to b16 DSADCRnH[7:0] Conversion result bits 23 to 16 of channel n
(Caution is listed on the next page.)
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● When 16-bit resolution is set (DSADTYP in the DSADMR register = 1)
DSADCRnH DSADCRnM DSADCRnL
Bit b23 b16 b15 b8 b7 b0
ΔΣ A/D conversion result n [23:16] ΔΣ A/D conversion result n [23:16] ΔΣ A/D conversion result n [15:8]
b7 to b0 DSADCRnL[7:0] Conversion result bits 15 to 8 of channel n

b15 to b8 DSADCRnM[7:0] Conversion result bits 23 to 16 of channel n
b23 to b16 DSADCRnH[7:0] Conversion result bits 23 to 16 of channel n
Caution Be sure to read the ΔΣ A/D converter conversion result register within its maximum pending
time after the ΔΣ A/D conversion end interrupt is generated.
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17.2.10 ΔΣ A/D converter conversion result register n (DSADCRn) (n = 0, 1, 2, 3)

The DSADCRn register is used to access the conversion result of each channel using a 16-bit memory manipulation
instruction.
The DSADCRn register can be read by a 16-bit memory manipulation instruction. Reading of the conversion result of
the ΔΣ A/D converter differs depending on the setting of the DSADTYP bit in the ΔΣ A/D converter mode register
(DSADMR).
Setting the DSADCEn bit in the ΔΣ A/D converter mode register (DSADMR) to 0 or reset signal generation clears the
DSADCRn register to 0000H.
Figure 17-17. Format of ΔΣ A/D Converter Conversion Result Register n (DSADCRn) (n = 0, 1, 2, 3)
Address: F03E0H (DSADCR0) F03E4H (DSADCR1) F03E8H (DSADCR2)

F03ECH (DSADCR3)
After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSADCRn DSADCRn[15:0]
● When 24-bit resolution is set (DSADTYP in the DSADMR register = 0)Note

b15 to b0 DSADCRn[15:0] Conversion result bits 15 to 0 of channel n
● When 16-bit resolution is set (DSADTYP in the DSADMR register = 1)Note

b15 to b0 DSADCRn[15:0] Conversion result bits 23 to 8 of channel n
Note Access to the ΔΣ A/D converter conversion result changes depending on the setting of the DSADTYP bit in the
DSADMR register.
● DSADTYP = 0: The lower 16 bits can be read.
Read DSADCRnH as the higher 8 bits.
● DSADTYP = 1: The higher 16 bits can be read.
Caution Be sure to read the ΔΣ A/D converter conversion result register within its maximum pending time
after the ΔΣ A/D conversion end interrupt is generated.
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The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
To use the 24-bit ΔΣ A/D converter, be sure to set bit 0 (DSADCEN) to 1.

Symbol 7 <6> 5 4 <3> 2 1 <0>
DSADCEN Control of 24-bit ΔΣ A/D converter input clock supply

● SFR used by the 24-bit ΔΣ A/D converter cannot be written. The read value is 00H. However, the SFR is not
initialized. Note
Enables input clock supply.
1
● SFR used by the 24-bit ΔΣ A/D converter can be read and written.
Note To initialize the 24-bit ΔΣ A/D converter and the SFR used by the 24-bit ΔΣ A/D converter, use bit 0 (DSADRES) of
PRR1.
Cautions 1. When setting the 24-bit ΔΣ A/D converter, be sure to set the DSADCEN bit to 1 first.
If DSADCEN = 0, writing to a control register of the ΔΣ A/D converter is ignored.
2. Be sure to clear bits 7, 5, 4, 2, and 1 to “0”.
3. When a high-speed on-chip oscillator is selected as the input clock, be sure to run the high-speed
on-chip oscillator clock frequency correction function to input clock with high frequency precision.
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The PRR1 register is used to independently control resetting each of the peripheral hardware.
Each bit in this register controls resetting and release of the reset state of the corresponding peripheral hardware.
To reset the 24-bit ΔΣ A/D converter, be sure to set bits 0 (DSADRES) to 1.
Reset signal generation clears the PRR1 register to 00H.
Address: F00FBH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>
PRR1 0 0 0 0 0 0 0 DSADRES
DSADRES Control resetting of the 24-bit ΔΣ A/D converter
0 Release of the reset state of the 24-bit ΔΣ A/D converter

1 The 24-bit ΔΣ A/D converter is in the reset state.
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17.2.13 Peripheral clock control register (PCKC)

The PCKC register is used to control peripheral clocks. Set bit 0 to select a clock for the 24-bit ΔΣ A/D converter.
The PCKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 17-20. Format of Peripheral Clock Control Register (PCKC)

Symbol 7 6 5 4 3 2 <1> <0>
PCKC 0 0 0 0 0 0 PLLCK DSADCK
DSADCK Selection of operation clock for 24-bit ΔΣ A/D converter
0 Supply high-speed on-chip oscillator clock (fIH). (Stop fMX supply)Note 1

1 Supply high-speed system clock (fMX)Note 2
Notes 1. When selecting the high-speed on-chip oscillator clock, be sure to run the high-speed on-chip oscillator clock
frequency correction function.
2. Only a 12 MHz crystal oscillator can be used as the high-speed system clock frequency (fMX).
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17.3 Operation
The 24-bit ΔΣ A/D converter has the digital signal input pins for four ΔΣ A/D converter conversion results. By passing
2-bit values obtained from these ΔΣ A/D converter conversion results through the digital filter, the value is converted into
24-bit digital values.
The mode setting of the ΔΣ A/D converter of the analog block depends on the values of the DSADMR, DSADGCR0,
and DSADGCR1 register. Table 17-5 lists the mode settings.
Table 17-5. Mode Settings
Signal/Mode <1> Normal <2> ΔΣ A/D Conversion Stop <3> Power-down
DSADGAINn2 to DSADGAINn0 Any value Any value Any value

DSADPONn 1 1 0
DSADCEn 1 0 0
Remark n = 0 to 3
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17.3.1 Operation of 24-bit ΔΣ A/D converter

When selecting the high-speed on-chip oscillator clock (fIH), be sure to run the high-speed on-chip oscillator clock
frequency correction function according to 7.3.2 Operation procedure before running the ΔΣ A/D converter.
When selecting the high-speed system clock (fMX), allow at least two cycles of fCLK after switching to the selected clock.
The 24-bit ΔΣ A/D converter starts operating when the DSADPONn bit (n = 0 to 3) and the DSADCEn bit in the
DSADMR register are set to 1. The setup time of the analog block and digital filter block is required after power on and
start of conversion. Perform initialization in accordance with the flowchart below.
Figure 17-21. Initialization Flowchart
Start  A/D converter

(hardware reset)
Cancel system reset

RESET L → H

frequency correction function operating
privilegeNote 1
HOCOFC = 41H
Select  A/D converter input clock • High-speed system clock (fMX) selected (DSADCK = 1)
(DSADCK in PCKC register) Allow at least two cycles of fCLK after switching to the selected clock.
Enable  A/D converter input clock • Set bit 0 (DSADCEN) in peripheral enable register 1 (PER1) to 1,
DSADCEN in PER1 register = 1 and start the input clock to the  A/D converter.
Set sampling frequencyNote 2

• Sampling frequency selected (DSADFR bit)
DSADMR = 0000H/8000H
• Programmable gain amplifier selected (DSADGAINn2 to DSADGAINn0 bits)

Set gain, HPF, and phase adjustment
• Insertion of high-pass filter specified (DSADTHRn bit)
step
• Phase adjustment, phase adjustment step selected (DSADPHCRm register)
Set  A/D to power onNote 3

•  A/D converter power on controlled (DSADPONn bit)
Enable  A/D conversion operationNote 4
•  A/D converter operation enabled (DSADCEn bit)
DSADMR = 0F0FH/8F0FH
Wait for setup time

Number of times
INTDSAD is
generated = 80Note 3 Number of times INTDSAD
is generated > 80

frequency correction complete interrupt
disabledNote 5
HOCOFC = 01H
Execute processing
using  A/D conversion result
(Note and Remark are listed on the next page.)
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Notes 1. When selecting the high-speed on-chip oscillator clock, be sure to run the high-speed on-chip oscillator
clock frequency correction function before running the ΔΣ A/D converter.
2. Set the sampling frequency while the ΔΣ A/D converter is powered down.
3. The setup time (the number of times INTDSAD is to be generated) when DSADPONn is set to 0 and then 1
will be officially determined after evaluation.
4. If the ΔΣ A/D converter is temporarily stopped for initialization (DSADCEn = 0 with DSADPONn = 1) and
then restarted, it is necessary to wait for a certain setup time. In this case, since stabilization time is
necessary for the converter, wait for one INTDSAD to be generated as the setup time.
To initialize the ΔΣ A/D converter, make sure that DSADCEn remains 0 for at least 1.4 µs.
5. Perform only when selecting the high-speed on-chip oscillator clock.
Remark n = 0 to 3; m = 0, 1
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17.3.2 Procedure for switching from normal operation mode to neutral missing mode
Figure 17-22 shows the procedure for switching from normal operation (with anti-tamper) (a total of three: current
channel 0, voltage channel 1, and current channel 2 operate) to neutral missing mode (only current channel 0 operates), in
single-phase two-wire mode.
In neutral missing mode, there are cases when only current channel 0 operates and only current channel 2 operates.
Use the same procedure when switching the mode.
Figure 17-22. Procedure for Switching from Normal Operation Mode to Neutral Missing Mode
Enable  A/D conversion operation

(DSADCE3 to DSADCE0 = 0111B) •  A/D converter operation enable bits
DSADMR = 0707H (DSADCE3 to DSADCE0 = 0111B)
Normal operation mode
Detect tamper state

(Detect neutral missing state)
Disable voltage channel 1 and current channel 2

Stop  A/D conversion operation •  A/D converter operation enable bits
(DSADCE3 to DSADCE0 = 0001B) (DSADCE3 to DSADCE0 = 0001B)
Set  A/D to power down •  A/D converter power-on control bits
(DSADPON3 to DSADPON0 = 0001B) (DSADPON3 to DSADPON0 = 0001B)
DSADMR = 0101H
Neutral missing mode
Clear tamper state

(Clear neutral missing state)
Re-enable voltage channel 1 and current channel 2

Set  A/D to power on •  A/D converter power-on control bits
(DSADPON3 to DSADPON0 = 0111B) (DSADPON3 to DSADPON0 = 0111B)
Enable  A/D conversion operation •  A/D converter operation enable bits
(DSADCE3 to DSADCE0 = 0111B) (DSADCE3 to DSADCE0 = 0111B)
DSADMR = 0707H
Wait for setup time

Number of times
INTDSAD is Number of times INTDSAD
generated  80 is generated > 80
Execute processing using  A/D conversion result
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17.3.3 Interrupt operation

This section shows two interrupt functions that are included by the RL78/I1C 24-bit ΔΣ A/D converter.
17.3.3.1 Zero-cross detection interrupt operation

The 24-bit ΔΣ A/D converter includes two zero-cross detection interrupts.
The target channel of the zero-cross detection interrupt can be controlled by the DSADZCCTLn bit. Therefore, zero-
cross detection interrupt 0 is performed with the target of channel 2 and channel 1 when DSADZCCTL0 = 0 and
DSADZCCTL0 = 1, respectively. In the same manner, the zero-cross detection interrupt 1 is performed with the target of
channel 3 and channel 0 when DSADZCCTL1 = 0 and DSADZCCTL1 = 1, respectively.
The zero-cross detection interrupt is detected in synchronization with the rising edge of the ΔΣ A/D conversion
completion interrupt (INTDSAD). Zero-cross detection interrupt timings are shown in Figures 17-23 and 17-24. The valid
edge setting of the zero-cross detection can be controlled by the DSADZCEGNn and DSADZCEGPn bits.
Figure 17-23. INTDSADZCn Interrupt Generation Timing (Pulse Output: DSADZCMDn = 0)
DF output n 0
DSADZCn
INTDSADZCn/DSADZCIn
Detection stop
INTDSADZCn/DSADZCIn
Falling edge detection
INTDSADZCn/DSADZCIn
Rising edge detection
INTDSADZCn/DSADZCIn
Both-edge detection
* Interrupts can be cleared by software in the same

Sampling frequency Sampling frequency manner as in the level output mode.
Remark The zero-cross detection interrupt is High for 2 cycles when a series of detection conditions are generated at
the timing of both-edge detection.
Figure 17-24. INTDSADZCn Interrupt Generation Timing When the Harmonic Signals Are Included in the DF
Output (Pulse Output: DSADZCMDn = 0)
DF operation result n 0
DSADZCn
INTDSADZCn/DSADZCIn
Detection stop
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
Both-edge detection
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Interrupt may be generated for several times in proximity of a zero cross when the ΔΣ A/D converter DF output includes
the harmonic signals. The interrupt output is in the level output mode as shown in Figure 17-25 when setting
DSADZCMD0 = 1 if you want to refrain the number of interrupt generations to 1.
Figure 17-25. INTDSADZCn Interrupt Generation Timing (Level Output: DSADZCMDn = 1)
DSADZCn
INTDSADZCn/DSADZCIn
Detection stop
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
Both-edge detection
Software clear (writing 1 to the DSADCL bit)
In the case of level output mode, clear the zero-cross detection interrupt signal n (INTDSADZCn) by using software by
writing 1 to the DSADICLn bit until the next zero-cross detection interrupt n generation. The zero-cross detection interrupt
n must be cleared by using software at the timing when the harmonic signals do not impact because the interrupt may be
generated for several times due to the harmonic signals.
Zero-cross detection interrupt n can be cleared by writing 1 to the DSADICLn bit. In addition, zero-cross detection
interrupt n may not be generated at the clear timing by the software because the clear operation is prioritized.
Figure 17-26. Zero-cross Detection Interrupt Clear Procedure

(with Selection of channel 2, When Detecting Both Edges)
• Zero-cross detection channel selection bit 0

(DSADZCCTL0 = 0B)
Zero-cross interrupt clear • Zero-cross detection mode 0
procedure start (DSADZCMD0 = 1B)
(Level output: DSADZCMD0 = 1) • Zero-cross detection falling edge enable bit 0
(DSADZCEGN0 = 1B)
• Zero-cross detection rising edge enable bit 0
Zero-cross detection interrupt
(INTDSADZC0) generation (DSADZCEGP0 = 1B)
Wait
Clear timing does not elapse
Clear timing elapses
• Zero-cross detection interrupt 0 clear bitNote

Channel n zero-cross detection
interrupt clear (DSADICL0 = 1B)
(DSADICL0 = 1B) Note Zero-cross detection interrupt 0 must be
cleared after writing 1 to this bit and after
3 cycles at the sampling frequency.
Zero-cross detection interrupt clear
procedure completion
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17.3.3.2 ΔΣ A/D conversion end interrupt operation

When ΔΣ A/D conversion is enabled, conversion of the signals on the four channels of analog input pins (ANINn and
ANIPn) is started. Four sets of ΔΣ A/D converter circuits are provided, and each of which independently executes
conversion. Each time conversion of all four channels is completed, the interrupt request signal (INTDSAD) is generated
to inform the CPU that the conversion result can be read.
The generation cycle of INTDSAD (tINTDSAD) differs depending on the sampling frequency specified by the DSADFR bit
in the DSADMR register. The maximum pending time for reading the ΔΣ A/D converter conversion result register n
(DSADCRn) by interrupt servicing is as shown in Figure 17-27. Complete reading of the DSADCRn register within this
time.
Figure 17-27. Timing of Generation of INTDSAD Signal and Storing in DSADCRn Register
21.34 µs tINTDSAD tRDLIM

INTDSAD
DSADCR0 D0 (n - 1) D0 (n) D0 (n + 1)
DSADCR1 D1 (n - 1) D1 (n) D1 (n + 1)
DSADCR2 D2 (n - 1) D2 (n) D2 (n + 1)
DSADCR3 D3 (n - 1) D3 (n) D3 (n + 1)
tINTDSAD: Interrupt generation cycle: 256 µs (DSADFR = 0)

512 µs (DSADFR = 1)
tRDLIM: DSADCR read pending time (max): 192 µs (DSADFR = 0)
384 µs (DSADFR = 1)
Remark n = 0 to 3
17.3.4 Operation in standby state

In STOP operation mode, the ΔΣ A/D converter and the digital filter do not operate. To reduce current consumption,
stop operation of the ΔΣ A/D converter (DSADCEn in the DSADMR register = 0000B) and power down the ΔΣ A/D
converter (DSADPONn in the DSADMR register = 0000B) before executing the STOP instruction.
Remark n = 0 to 3
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17.4 Notes on Using 24-Bit ΔΣ A/D Converter
17.4.1 External pins

The VDD and VBAT pins are the analog power supply pin of the ΔΣ A/D converter.
The AVSS pin is the ground power supply pin of the ΔΣ A/D converter. Always keep the voltage on this pin the same as
that on the VSS pin even when the ΔΣ A/D converter is not used.
17.4.2 SFR access
(1) Read the DSADCRn register by ΔΣ A/D conversion end interrupt (INTDSAD) servicing. If the DSADCRn register is
read before a ΔΣ A/D conversion end interrupt is generated, an illegal value may be read because of a conflict
between storing the conversion value in the DSADCRn register and reading the register.
The period of the INTDSAD processing during which the DSADCRn register is read is 192 µs (when DSADFR is
set to 0) or 384 µs (when DSADFR is set to 1), so complete reading of the register within this time.
Reading the DSADCRnL, DSADCRnM, and DSADCRnH registers are performed in the same conditions as those
described above.
(2) After powering on the ΔΣ A/D converter (DSADPONn in the DSADMR register = 1), internal setup time is
necessary. Consequently, the data of the first 80 conversions is invalid.
(3) Setup time is also necessary when the ΔΣ A/D converter has been temporarily stopped for initialization (by clearing
the DSADCEn bit in the DSADMR register to 0 with DSADPONn = 1) and then restarted. In this case, since
stabilization time is necessary for the converter, wait for one INTDSAD to be generated as the setup time. To
initialize the ΔΣ A/D converter, make sure that DSADCEn remains 0 for at least 1.4 µs.
(4) The time required for the correct data to be output after the conversion operation has been enabled (by setting the
DSADCEn bit to 1) differs depending on the analog input status at that time. This is because the stabilization time
of the high-pass filter changes depending on the analog input status.
(5) Set the sampling frequency (DSADFR bit in the DSADMR register) while the DSADPONn bit in the DSADMR
register is 0.
Be sure to set the DSADGCR1 and DSADGCR0 registers, DSADCOF[1:0] bits in the DSADHPFCR register,
DSADZCCTL1 and DSADZCCTL0 bits in the DSADICR register, and DSADPHCRn register while the ΔΣ A/D
converter is stopped (DSADCEn = 0).
(6) Since the DSADCRn register is initialized when the DSADCEn bit is 0, read the DSADCRn register when the
DSADCEn bit is 1.
(7) Clear the DSADPONn bit in the DSADMR register to 0 before shifting to software STOP mode. If software STOP
mode is entered with the DSADPONn bit set to 1, a current will flow.
(8) Latency is required to allow 3 times of ΔΣ A/D conversion completion interrupt generation in order to reflect new
setting to the internal logic when the DSADICR register is rewrote. Rewriting the DSADICR register is prohibited
during the latency for reflection.
It is required to wait for a total of 3 times of ΔΣ A/D conversion completion interrupt generation before the
conversion stop and after the restart of the A/D conversion because the reflection into the internal logic from the
DSADICR register stops if the A/D conversion in all channels stops (DSADCEn = 0).
(9) Latency is required to allow 3 times of ΔΣ A/D conversion completion interrupt generation until the zero-cross
detection interrupt is cleared when 1 is written to the DSADICL0 or DSADICL1 bit in the DSADICLR register.
Writing 1 to the same bit described above during the latency of clear is invalid.
A total of 3 times of ΔΣ A/D conversion completion interrupts are generated before the conversion stop and after
the restart of the A/D conversion because the reflection into the internal logic from the DSADICL0 or DSADICL1 bit
stops if the A/D conversion in all channels stops (DSADCEn = 0).
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(10) Writing to the DSADTHRn bit in the DSADHPFCR register shall be completed when any of the following conditions
is satisfied:
● DSADCEn = 0 (Conversion is being stopped)
● Within 21 µs from the zero-cross detection interrupt
(11) For the zero-cross detection interrupt status bit (DSADZCIn) and DF output status bit (DSADZCn) corresponding to
the interrupted channel in the DSADISR register, values become undefined when the A/D conversion for the
channel performing the zero-cross detection was stopped. Therefore, do not use the value of corresponding bits
after the stop. After the restart of the A/D conversion, the values for the bits described above are corrected when
the ΔΣ A/D conversion completion interrupt is generated once.
Remark n = 0 to 3
17.4.3 Setting operating clock

When selecting two frequency division of the high-speed on-chip oscillator clock (fHOCO) as an operation clock for the
24-bit ΔΣ A/D converter, set FRQSEL3 of the user option byte to “0” to make base oscillator clock frequency of the high-
speed on-chip oscillator clock (fHOCO) 24 MHz.
When using the high-speed system clock (fMX) by setting DSADCK in the PCKC register to 1, supply 12 MHz.
Also, when selecting the high-speed on-chip oscillator clock (fHOCO/2), be sure to run the high-speed on-chip oscillator
frequency correction function.
Cautions 1. Count the INTDSAD signal 80 times after the ΔΣ A/D converter is started and then load the
converted data when the next INTDSAD signal is generated.
2. Thoroughly evaluate the stabilization time in the environment in which the ΔΣ A/D converter is
used.
To stop the 24-bit ΔΣ A/D converter while it is operating, set the DSADPON3 to DSADPON0 bits in the DSADMR
register to 0000B, and then set the DSADCEN bit in the PER1 register to 0.
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17.4.4 Cycle measurement of the zero-cross detection interrupt by using ELC

Be sure to clear the register by using software by writing 1 to the DSADICLn bit when measuring the cycle of the zero-
cross detection interrupt by using event link controller (ELC) by setting the output destination of the INTDSADZCn interrupt
to the timer.
In addition, software clear must be performed at the timing when harmonic signals do not impact from the
INTDSADZCn interrupt at all.
For more information on the zero-cross detection interrupt, see 17.3.3.1 Zero-cross detection interrupt operation.
Figure 17-28. INTDSADZC Interrupt Generation Timing (Level Output: DSADZCMD = 1)
DSADZCn
INTDSADZCn/DSADZCIn
Detection stop
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
INTDSADZCn/DSADZCIn
Both-edge detection
Software clear (writing 1 to the DSADCL bit)
17.4.5 Zero-cross detection interrupt software-clear

Be sure to clear the zero-cross detection interrupt registers (INTDSADZC0, INTDSADZC1) by writing 1 to the
DSADICLn bit when the zero-cross detection is stopped once and then it is restarted with the setting of the zero-cross
detection interrupt in the level output mode (DSADZCMD = 1).
For more information on the zero-cross detection interrupt, see 17.3.3.1 Zero-cross detection interrupt operation.
<R> 17.4.6 Input range

The 24-bit ΔΣ A/D converter must be used with input within the range stated in 41.6.2 24-bit ΔΣ A/D converter
characteristics. The input of a signal exceeding the input voltage range and at a frequency of 20 kHz or higher may result
in a conversion error. Such cases may necessitate a measure in the form of an external circuit etc.
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RL78/I1C CHAPTER 18 SERIAL ARRAY UNIT
CHAPTER 18 SERIAL ARRAY UNIT
Serial array unit has up to four serial channels. Each channel can achieve 3-wire serial (CSI), UART, and simplified I2C
communication.
Function assignment of each channel supported by the RL78/I1C is as shown below.
64, 80-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 0 CSI00 UART0 IIC00

1 – (supporting LIN-bus) –
2 CSI10 UART1 IIC10
3 – –
1 0 – UART2 –
1 – (supporting IrDA) –
2 – – –
3 – – –
100-pin products

1 – (supporting LIN-bus) –
2 CSI10 UART1 IIC10
3 – –
1 0 – UART2 –
2 CSI30 UART3 IIC30
3 – –
When “UART0” is used for channels 0 and 1 of the unit 0, CSI00 and IIC00 cannot be used, but UART1 or IIC10 can be
used.
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18.1 Functions of Serial Array Unit
Each serial interface supported by the RL78/I1C has the following features.
18.1.1 3-wire serial I/O (CSI00, CSI10, CSI30)

Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
3-wire serial communication is clocked communication performed by using three communication lines: one for the serial
clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
For details about the settings, see 18.5 Operation of 3-Wire Serial I/O (CSI00, CSI10, CSI30) Communication.
[Data transmission/reception]
● Data length of 7 or 8 bits
● Phase control of transmit/receive data
● MSB/LSB first selectable
[Clock control]
● Master/slave selection
● Phase control of I/O clock
● Setting of transfer period by prescaler and internal counter of each channel
● Maximum transfer rateNote
During master communication: Max. fMCK/2
During slave communication: Max. fMCK/6
[Interrupt function]
● Transfer end interrupt/buffer empty interrupt
[Error detection flag]
● Overrun error
In addition, CSI00 supports the SNOOZE mode. When SCK input is detected while in the STOP mode, the SNOOZE
mode makes data reception that does not require the CPU possible.
Note Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics. For details, see CHAPTER
41 ELECTRICAL SPECIFICATIONS.
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18.1.2 UART (UART0 to UART3)

This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be
implemented by using timer array unit with an external interrupt (INTP0).
For details about the settings, see 18.6 Operation of UART (UART0 to UART3) Communication.
● Data length of 7, 8, or 9 bitsNote
● Select the MSB/LSB first
● Level setting of transmit/receive data and select of reverse
● Parity bit appending and parity check functions
● Stop bit appending
● Error interrupt in case of framing error, parity error, or overrun error
● Framing error, parity error, or overrun error
In addition, UART0 reception supports the SNOOZE mode. When RxD input is detected while in the STOP mode, the
SNOOZE mode makes data reception that does not require the CPU possible.
The LIN-bus is accepted in UART0 (0 and 1 channels of unit 0).

[LIN-bus functions]
● Wakeup signal detection
Using the external interrupt (INTP0) and
● Break field (BF) detection
timer array unit
● Sync field measurement, baud rate calculation
Note Only UART0 can be specified for the 9-bit data length.
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18.1.3 Simplified I2C (IIC00, IIC10, IIC30)

This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions only as a master.
Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop
conditions are observed.
For details about the settings, see 18.8 Operation of Simplified I2C (IIC00, IIC10, IIC30) Communication.
● Master transmission, master reception (only master function with a single master)
● ACK output functionNote and ACK detection function
● Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least
significant bit is used for R/W control.)
● Manual generation of start condition and stop condition
● Transfer end interrupt
● ACK error, or overrun error
* [Functions not supported by simplified I2C]

● Slave transmission, slave reception
● Arbitration loss detection function
● Wait detection functions
Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn bit (serial output enable register
m (SOEm)) and serial communication data output is stopped. See the processing flow in 18.8.3 (2) for details.
Remarks 1. To use an I2C bus of full function, see CHAPTER 19 SERIAL INTERFACE IICA.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
18.1.4 IrDA
By combining UART2 of the serial array unit and the IrDA module, IrDA communication waveforms can be transmitted
or received based on IrDA (Infrared Data Association) standard 1.0. For details, see CHAPTER 20 IrDA.
● Transfer rate: 115.2 kbps/57.6 kbps/38.4 kbps/19.2 kbps/9600 bps/2400 bps
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18.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Table 18-1. Configuration of Serial Array Unit
Item Configuration
Note 1
Shift register 8 bits or 9 bits
Buffer register Lower 8 bits or 9 bits of serial data register mn (SDRmn)Notes 1, 2
Serial clock I/O SCK00, SCK10, SCK30 pins (for 3-wire serial I/O), SCL00, SCL10, SCL30 pins (for simplified
I2C)
Serial data input SI00, SI10, SI30 pins (for 3-wire serial I/O), RxD1 to RxD3 pins (for UART), RXD0 pin (for UART
supporting LIN-bus)
Serial data output SO00, SO10, SO30 pins (for 3-wire serial I/O), TxD1 to TxD3 pins (for UART), TXD0 pin (for
UART supporting LIN-bus)
Serial data I/O SDA00, SDA10, SDA30 pins (for simplified I2C)
Control registers <Registers of unit setting block>
● Serial clock select register m (SPSm)
● Serial channel enable status register m (SEm)
● Serial channel start register m (SSm)
● Serial channel stop register m (STm)
● Serial output enable register m (SOEm)
● Serial output register m (SOm)
● Serial output level register m (SOLm)
● Serial standby control register 0 (SSC0)
<Registers of each channel>
● Serial data register mn (SDRmn)
● Serial mode register mn (SMRmn)
● Serial communication operation setting register mn (SCRmn)
● Serial status register mn (SSRmn)
● Serial flag clear trigger register mn (SIRmn)
● Port input mode registers 0, 1, 8 (PIM0, PIM1, PIM8)
● Port output mode registers 0, 1, 8 (POM0, POM1, POM8)
● Port mode registers 0, 1, 8 (PM0, PM1, PM8)
● Port registers 0, 1, 8 (P0, P1, P8)
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Notes 1. The number of bits used as the shift register and buffer register differs depending on the unit and channel.
● mn = 00, 01: lower 9 bits
● Other than above: lower 8 bits
2. The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending
on the communication mode.
● CSIp communication … SIOp (CSIp data register)
● UARTq reception … RXDq (UARTq receive data register)
● UARTq transmission … TXDq (UARTq transmit data register)
● IICr communication … SIOr (IICr data register)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 10, 30),
q: UART number (q = 0 to 3), r: IIC number (r = 00, 10, 30), mn = 00 to 03, 10 to 13
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Figure 18-1 shows the block diagram of the serial array unit 0.
Figure 18-1. Block Diagram of Serial Array Unit 0
Noise filter enable

Serial output register 0 (SO0) register 0 (NFEN0)
0 0 0 0 1 CKO02 1 CKO00 0 0 0 0 1 SO02 1 SO00 SNFEN SNFEN

10 00
Peripheral enable Serial channel
register 0 (PER0) Serial clock select register 0 (SPS0) Serial standby
SE03 SE02 SE01 SE00 enable status
register 0 (SE0) control register 0
PRS PRS PRS PRS PRS PRS PRS PRS (SSC0)
SAU0EN
013 012 011 010 003 002 001 000 Serial channel
SS03 SS02 SS01 SS00 start register 0 SSEC0 SWC0
(SS0)
4 4 Serial channel
ST03 ST02 ST01 ST00 stop register 0
(ST0)
Serial output
0 SOE02 0 SOE00 enable register 0
fCLK Prescaler (SOE0)
fCLK/20 to fCLK/215 fCLK/20 to fCLK/215 0 Serial output level

SOL02 0 SOL00
register 0 (SOL0)
Selector Selector
CK01 CK00 Serial data register 00 (SDR00)

Channel 0 Output latch PM06 or P07
(LIN-bus supported) (Clock division setting block) (Buffer register block) (P06 or P07)
Serial data output pin

Selector
fMCK (when CSI00: SO00)

Clock controller
(when IIC00: SDA00)

Selector
fTCLK (when UART0: TXD0)

Shift register
Output
Serial clock I/O pin Synchro- Edge fSCK controller
nous
(when CSI00: SCK00) circuit detection
(when IIC00: SCL00)
Interrupt Serial transfer end interrupt
Communication controller controller (when CSI00: INTCSI00)
(when IIC00: INTIIC00)
Output latch Mode selection (when UART0: INTST0)
Serial flag clear trigger
PM05 (P05) CSI00 or IIC00
register 00 (SIR00)
or UART0
(for transmission) PECT OVCT
Serial data input pin 00 00
Synchro- Noise
(when CSI00: SI00) nous elimination Edge/level
enabled/
(when IIC00: SDA00) circuit disabled detection Clear
Communication
status
(when UART0: RxD0)
SNFEN00 Error controller

CKS00 CCS00 STS00 SIS00 MD002 MD001 MD000
Serial mode register 00 (SMR00) Error

information
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS TSF BFF PEF OVF
00 00 00 00 00 001 000 00 001 000 001 000 00 00 00 00
When UART0
Serial communication operation setting register 00 (SCR00) Serial status register 00 (SSR00)
CK01 CK00
Channel 1
(LIN-bus supported) Communication controller
Serial transfer end interrupt
Mode selection (when UART0: INTSR0)
UART0
Edge/level (for reception)
detection Error controller Serial transfer error interrupt
(INTSRE0)
CK01 CK00
Output latch PM03

Serial clock I/O pin
(when IIC10: SCL10) Channel 2 (P03)
Communication controller Serial data output pin
(when CSI10: SCK10)
(when IIC10: SDA10)
Mode selection (when UART1: TXD1)
CSI10 or IIC10 (when CSI10: SO10)
Output latch or UART1 Serial transfer end interrupt
PM02 (P02) (when IIC10: INTIIC10)
(for transmission)
Serial data input pin Noise (when UART1: INTST1)
Synchro-
(when IIC10: SDA10) nous elimination Edge/level (when CSI10: INTCSI10)
circuit enabled/
(when UART1: RXD1) disabled detection
SNFEN10
CK01 CK00
When UART1
Channel 3
Communication controller
UART1
Error controller Serial transfer error interrupt
detection
(INTSRE1)
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Figure 18-2 shows the block diagram of the serial array unit 1.
Figure 18-2. Block Diagram of Serial Array Unit 1
Noise filter enable

Serial output register 1 (SO1) register 0 (NFEN0)
0 0 SNFEN SNFEN
0 0 0 1 CKO12 1 CKO10 0 0 0 1 SO12 1 SO10
30 20
Peripheral enable
register 1 (PER1) Serial clock select register 1 (SPS1) Serial channel
SE13 SE12 SE11 SE10 enable status
PRS PRS PRS PRS PRS PRS PRS PRS register 1 (SE1)
SAU1EN
113 112 111 110 103 102 101 100 Serial channel
SS13 SS12 SS11 SS10 start register 1
(SS1)
4 4 Serial channel
ST13 ST12 ST11 ST10 stop register 1
(ST1)
Serial output
0 SOE12 0 SOE10 enable register 1
fCLK Prescaler
(SOE1)
fCLK/20 to fCLK/215 fCLK/20 to fCLK/215 Serial output
0 SOL12 0 SOL10 level register 1
(SOL1)
Selector Selector
Serial data register 10 (SDR10)

Channel 0 Output latch PM56 or PM31
CK11 CK10 (Clock division setting block) (Buffer register block)
(P56 or P31)
IrDA
Selector
fMCK
(when UART2: TxD2)
Clock controller (when IrDA: IrTxD)
Selector
fTCLK
Shift register
Output
controller
Interrupt
controller Serial transfer end interrupt
Communication controller (when UART2: INTST2)
Mode selection Serial flag clear trigger

UART2 register 10 (SIR10)
(for transmission)
PECT OVCT
Serial data input pin Noise
10 10
Edge/level
IrDA
Synchro- elimination
(when UART2: RxD2) nous enabled/
(when IrDA: IrRxD) circuit disabled detection
Communication
status
SNFEN20 Error controller
CKS10 CCS10 STS10 SIS10 MD102 MD101 MD100
Serial mode register 10 (SMR10) Error

information
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS TSF BFF PEF OVF
10 10 10 10 10 101 100 10 101 100 101 100 10 10 10 10
When UART2
Serial communication operation setting register 10 (SCR10) Serial status register 10 (SSR10)
CK11 CK10
Channel 1
Communication controller
(when UART2: INTSR2)
Mode selection
UART2
detection
(INTSRE2)
CK11 CK10
Output latch PM84

Serial clock I/O pin Channel 2 (P84)
(when IIC30: SCL30) Communication controller
Mode selection (when CSI30: SO30)
CSI30 or IIC30 (when IIC30: SDA30)
Output latch or UART3
PM57 (P57) Serial transfer end interrupt (when UART3: TxD3)
(for transmission) (when CSI30: INTCSI30)
Serial data input pin Synchro- Noise
Edge/level (when IIC30: INTIIC30)
nous elimination
(when IC30: SDA30) circuit enabled/ detection (when UART3: INTST3)
disabled
(when UART3: RxD3)
SNFEN30
CK11 CK10
When UART3
Channel 3 Communication controller

UART3
detection
(INTSRE3)
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18.2.1 Shift register

This is a 9-bit register that converts parallel data into serial data or vice versa.
In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are usedNote.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8/9 bits of serial data register mn (SDRmn).
8 7 6 5 4 3 2 1 0
Shift register
18.2.2 Lower 8/9 bits of the serial data register mn (SDRmn)

The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits)Note 1 or bits 7 to
0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division
ratio of the operation clock (fMCK).
When data is received, parallel data converted by the shift register is stored in the lower 8/9 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8/9 bits.
The data stored in the lower 8/9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0,
DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data.
● 7-bit data length (stored in bits 0 to 6 of SDRmn register)
● 8-bit data length (stored in bits 0 to 7 of SDRmn register)
● 9-bit data length (stored in bits 0 to 8 of SDRmn register)Note 1
The SDRmn register can be read or written in 16-bit units.

The lower 8/9 bits of the SDRmn register can be read or writtenNote 2 as the following SFR, depending on the
communication mode.
● CSIp communication … SIOp (CSIp data register)
● UARTq reception … RXDq (UARTq receive data register)
● UARTq transmission … TXDq (UARTq transmit data register)
● IICr communication … SIOr (IICr data register)
Reset signal generation clears the SDRmn register to 0000H.
Notes 1. Only UART0 can be specified for the 9-bit data length.
2. Rewriting SDRmn[7:0] by 8-bit memory manipulation instruction is prohibited when the operation is stopped
(SEmn = 0) (all of SDRmn[15:9] are cleared (0)).
Remarks 1. After data is received, “0” is stored in bits 0 to 8 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 10, 30),
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Figure 18-3. Format of Serial Data Register mn (SDRmn) (mn = 00, 01, 10, 11)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01), After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
FFF11H (SDR00) FFF10H (SDR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
8 7 6 5 4 3 2 1 0
Shift register
Remark For the function of the higher 7 bits of the SDRmn register, see 18.3 Registers Controlling Serial
Array Unit.
Figure 18-4. Format of Serial Data Register mn (SDRmn) (mn = 02, 03, 12, 13)
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), After reset: 0000H R/W
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
8 7 6 5 4 3 2 1 0
Shift register
Caution Be sure to clear bit 8 to “0”.
Remark For the function of the higher 7 bits of the SDRmn register, see 18.3 Registers Controlling Serial
Array Unit.
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18.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.

● Serial standby control register 0 (SSC0)
● Port input mode registers 0, 1, 8 (PIM0, PIM1, PIM8)
● Port output mode registers 0, 1, 8 (POM0, POM1, POM8)
● Port mode registers 0, 1, 8 (PM0, PM1, PM8)
● Port registers 0, 1, 8 (P0, P1, P8)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
Reset signal generation clears the PER0 register to 00H.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
SAUmEN Control of serial array unit m input clock supply
0 Stops supply of input clock.

● SFR used by the serial array unit m cannot be written. The read value is 00H. However, the SFR is
not initialized. Notes 1, 2
● SFR used by serial array unit m can be read/written.
Notes 1. To initialize the serial array unit 1 and the SFR used by the serial array unit 1, use bit 3 (SAU1RES) of
PRR0.
PRR0.
Cautions 1. When setting serial array unit m, be sure to first set the following registers with the SAUmEN
bit set to 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for the input switch control
register (ISC), noise filter enable register 0 (NFEN0), port input mode registers 0, 1, 3, 5, 8
(PIM0, PIM1, PIM3, PIM5, PIM8), port output mode registers 0, 1, 3, 5, 8 (POM0, POM1, POM3,
POM5, POM8), port mode registers 0, 1, 3, 5, 8 (PM0, PM1, PM3, PM5, PM8), and port registers
0, 1, 3, 5, 8 (P0, P1, P3, P5, P8)).
● Serial standby control register m (SSCm)
Remark m: Unit number (m = 0, 1), n:Channel number (n = 0 to 3)
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18.3.2 Serial clock select register m (SPSm)

The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits
3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
Figure 18-6. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm 0 0 0 0 0 0 0 0 PRS PRS PRS PRS PRS PRS PRS PRS

m13 m12 m11 m10 m03 m02 m01 m00
PRS PRS PRS PRS Selection of operation clock (CKmk)Note

mk3 mk2 mk1 mk0 fCLK = 4 MHz fCLK = 8 MHz fCLK = 12 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 0 0 fCLK 4 MHz 8 MHz 12 MHz 20 MHz 24 MHz

2
3
0 0 1 1 fCLK/2 500 kHz 1 MHz 1.5 MHz 2.5 MHz 3 MHz
0 1 0 0 fCLK/24 250 kHz 500 kHz 750 kHz 1.25 MHz 1.5 MHz
0 1 0 1 fCLK/25 125 kHz 250 kHz 375 kHz 625 kHz 750 KHz
0 1 1 0 fCLK/26 62.5 kHz 125 kHz 187.5 kHz 313 kHz 375 kHz
7
0 1 1 1 fCLK/2 31.25 kHz 62.5 kHz 93.8 kHz 156 kHz 187.5 kHz
8
9
10
11
1 1 0 0 fCLK/212 976 Hz 1.95 kHz 2.93 kHz 4.88 kHz 5.86 kHz
1 1 0 1 fCLK/213 488 Hz 976 Hz 1.46 kHz 2.44 kHz 2.93 kHz
14
1 1 1 0 fCLK/2 244 Hz 488 Hz 732 Hz 1.22 kHz 1.46 kHz
15
1 1 1 1 fCLK/2 122 Hz 244 Hz 366 Hz 610 Hz 732 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU).

2. m: Unit number (m = 0, 1)
3. k = 0, 1
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18.3.3 Serial mode register mn (SMRmn)

The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock
(fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or
simplified I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART
mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0
bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Figure 18-7. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS CCS 0 0 0 0 0 STS 0 SIS 1 0 0 MD MD MD

mn mn mnNote mn0Note mn2 mn1 mn0
CKS Selection of operation clock (fMCK) of channel n

mn
0 Operation clock CKm0 set by the SPSm register

1 Operation clock CKm1 set by the SPSm register
Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated.
CCS Selection of transfer clock (fTCLK) of channel n

mn
0 Divided operation clock fMCK specified by the CKSmn bit

1 Clock input fSCK from the SCKp pin (slave transfer in CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and
error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the
SDRmn register.
STS Selection of start trigger source

mn
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I2C).
1 Valid edge of the RXDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note The SMR01, SMR03, SMR11, and SMR13 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or
SMR12 register) to “0”. Be sure to set bit 5 to “1”.
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Figure 18-7. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS CCS 0 0 0 0 0 STS 0 SIS 1 0 0 MD MD MD

mn mn mnNote mn0Note mn2 mn1 mn0
SIS Controls inversion of level of receive data of channel n in UART mode

mn0
0 Falling edge is detected as the start bit.

The input communication data is captured as is.
1 Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD MD Setting of operation mode of channel n

mn2 mn1
0 0 CSI mode
0 1 UART mode
1 0 Simplified I2C mode
MD Selection of interrupt source of channel n

mn0
0 Transfer end interrupt

1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
Note The SMR01, SMR03, SMR11, and SMR13 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or
SMR12 register) to “0”. Be sure to set bit 5 to “1”.
18.3.4 Serial communication operation setting register mn (SCRmn)

The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit,
stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
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Figure 18-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 SLCm SLC 0 1 DLSm DLS
mn mn mn mn mn mn1 mn0 mn n1Note 1 mn0 n1Note 2 mn0
TXE RXE Setting of operation mode of channel n

mn mn
0 0 Disable communication.
0 1 Reception only
1 0 Transmission only
1 1 Transmission/reception
DAP CKP Selection of data and clock phase in CSI mode Type
mn mn
0 0 SCKp 1
SOp D7 D6 D5 D4 D3 D2 D1 D0
SIp input timing
0 1 SCKp 2
SIp input timing
1 0 SCKp 3
SIp input timing
1 1 SCKp 4
SIp input timing
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I2C mode.
EOC Mask control of error interrupt signal (INTSREx (x = 0 to 2))

mn
0 Disables generation of error interrupt INTSREx (INTSRx is generated).

1 Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
Set EOCmn = 0 in the CSI mode, simplified I2C mode, and during UART transmissionNote 3.
Notes 1. The SCR00, SCR02, SCR10, and SCR12 registers only.

2. The SCR00, SCR01, and SCR10 registers, and the SCR11 register of 100-pin products only. Others are
fixed to 1.
3. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated.
Caution Be sure to clear bits 3, 6, and 11 to “0” (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13
register to 0). Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 10, 30), mn = 00 to
03, 10 to 13
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Figure 18-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 SLCm SLC 0 1 DLSm DLS
mn mn mn mn mn mn1 mn0 mn n1Note 1 mn0 n1Note 2 mn0
PTC PTC Setting of parity bit in UART mode

mn1 mn0
Transmission Reception
0 0 Does not output the parity bit. Receives without parity

Note 3
0 1 Outputs 0 parity . No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I2C mode.
DIR Selection of data transfer sequence in CSI and UART modes

mn
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
Be sure to clear DIRmn = 0 in the simplified I2C mode.
SLCm SLC Setting of stop bit in UART mode

n1Note 1 mn0
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 00, 02, 10 , 12 only)
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I2C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) or 2 bits (SLCmn1, SLCmn0 = 1, 0) during UART transmission.
DLSm DLS Setting of data length in CSI and UART modes

n1Note 2 mn0
0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register) (settable in UART mode only)
1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Be sure to set DLSmn1, DLSmn0 = 1, 1 in the simplified I2C mode.
Notes 1. The SCR00, SCR02, SCR10, and SCR12 registers only.

2. The SCR00, SCR01, and SCR10 registers, and the SCR11 register of 100-pin products only. Others are
fixed to 1.
3. 0 is always added regardless of the data contents.
Caution Be sure to clear bits 3, 6, and 11 to “0” (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13
register to 0). Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 10, 30), mn = 00 to 03, 10
to 13
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18.3.5 Serial data register mn (SDRmn)

The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00,
SDR01, SDR10Note 1, and SDR11Note 1 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10Note 2, SDR11Note 2, SDR12,
and SDR13 function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets
the division ratio of the operation clock (fMCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by
bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (upper 7 bits) of SDR00, SDR02, and
SDR12 to 0000000B. The input clock fSCK (slave transfer in CSI mode) from the SCKp pin is used as the transfer clock.
The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be transmitted to the
shift register is set to the lower 8/9 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8/9 bits of the SDRmn register. When the SDRmn register is read during
operation, the higher 7 bits are always read as 0.
Reset signal generation clears the SDRmn register to 0000H.
Figure 18-9. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) After reset: 0000H R/W
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
SDRmn[15:9] Transfer clock setting by dividing the operating clock (fMCK)
0 0 0 0 0 0 0 fMCK/2
0 0 0 0 0 0 1 fMCK/4
0 0 0 0 0 1 0 fMCK/6
0 0 0 0 0 1 1 fMCK/8
● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ●
1 1 1 1 1 1 0 fMCK/254
1 1 1 1 1 1 1 fMCK/256
(Notes, Cautions, and Remarks are listed on the next page.)
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Notes 1. R5F10NPJ, R5F10NMJ, R5F10NPG only

2. R5F10NMG, R5F10NLG, R5F10NME, R5F10NLE only
Cautions 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR12, and SDR13 registers, and of the SDR10
and SDR11 registers in R5F10NPJ, R5F10NMJ, R5F10NPG to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9]
to 0000001B or greater.
4. Rewriting SDRmn[7:0] by 8-bit memory manipulation instruction is prohibited when the
operation is stopped (SEmn = 0) (all of SDRmn[15:9] are cleared (0)).
Remarks 1. For the function of the lower 8/9 bits of the SDRmn register, see 18.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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18.3.6 Serial flag clear trigger register mn (SIRmn)

The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 18-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03), After reset: 0000H R/W
F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 FECT PEC OVC

mnNote Tmn Tmn
FEC Clear trigger of framing error of channel n

Tmn
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC Clear trigger of parity error flag of channel n

Tmn
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC Clear trigger of overrun error flag of channel n

Tmn
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
Note The SIR01, SIR03, SIR11, and SIR13 registers only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00, SIR02, SIR10, or SIR12 register) to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13

2. When the SIRmn register is read, 0000H is always read.
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18.3.7 Serial status register mn (SSRmn)

The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The
errors indicated by this register are a framing error, parity error, and overrun error.
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Figure 18-11. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10) to F0142H, F0143H (SSR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0 TSFm BFFm 0 0 FEFm PEF OVF

n n nNote mn mn
TSF Communication status indication flag of channel n

mn
0 Communication is stopped or suspended.

1 Communication is in progress.
<Clear conditions>
● The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
set to 1 (communication is suspended).
● Communication ends.
<Set condition>
● Communication starts.
BFF Buffer register status indication flag of channel n

mn
0 Valid data is not stored in the SDRmn register.

1 Valid data is stored in the SDRmn register.
<Clear conditions>
● Transferring transmit data from the SDRmn register to the shift register ends during transmission.
● Reading receive data from the SDRmn register ends during reception.
● The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
set to 1 (communication is enabled).
<Set conditions>
● Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
(transmission or transmission and reception mode in each communication mode).
● Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission and reception mode in each communication mode).
● A reception error occurs.
Note The SSR01, SSR03, SSR11, and SSR13 registers only.
Caution When the CSI is performing reception operations in the SNOOZE mode (SWCm = 1), the BFFmn
flag will not change.
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Figure 18-11. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10) to F0142H, F0143H (SSR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0 TSFm BFFm 0 0 FEFm PEF OVF

n n nNote mn mn
FEF Framing error detection flag of channel n

mn
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
● 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
● A stop bit is not detected when UART reception ends.
PEF Parity/ACK error detection flag of channel n

mn
0 No error occurs.
1 Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission).
<Clear condition>
● 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
● The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
● No ACK signal is returned from the slave channel at the ACK reception timing during I2C transmission (ACK is
not detected).
OVF Overrun error detection flag of channel n

mn
0 No error occurs.
1 An error occurs
<Clear condition>
● 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
● Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
● Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note The SSR01, SSR03, SSR11, and SSR13 registers only.
Cautions 1. If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in
the register is discarded and an overrun error (OVEmn = 1) is detected.
2. When the CSI is performing reception operations in the SNOOZE mode (SWCm = 1), the
OVFmn flag will not change.
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18.3.8 Serial channel start register m (SSm)

The SSm register is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m
(SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1.
The SSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Figure 18-12. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS0 0 0 0 0 0 0 0 0 0 0 0 0 SS03 SS02 SS01 SS00
Address: F0162H, F0163H (SS1) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS1 0 0 0 0 0 0 0 0 0 0 0 0 SS13 SS12 SS11 SS10
SSmn Operation start trigger of channel n
1 Sets the SEmn bit to 1 and enters the communication wait status Note.
Note If set the SSmn = 1 to during a communication operation, will wait status to stop the communication.
At this time, holding status value of control register and shift register, SCKmn and SOmn pins, and FEFmn,
PEFmn, OVFmn flags.
Cautions 1. Be sure to clear bits 15 to 4 of the SS0 register, bits 15 to 2 of the SS1 register in 64-pin and
80-pin products, and bits 15 to 4 of the SS1 register in 100-pin products to “0”.
2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set
SSmn to 1 after 4 or more fMCK clocks have elapsed.

2. When the SSm register is read, 0000H is always read.
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18.3.9 Serial channel stop register m (STm)

The STm register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m
(SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn =
0.
The STm register can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears the STm register to 0000H.
Figure 18-13. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST0 0 0 0 0 0 0 0 0 0 0 0 0 ST03 ST02 ST01 ST00
Address: F0164H, F0165H (ST1) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1 0 0 0 0 0 0 0 0 0 0 0 0 ST13 ST12 ST11 ST10
STm Operation stop trigger of channel n

n
1 Clears the SEmn bit to 0 and stops the communication operationNote.
Note Holding status value of the control register and shift register, the SCKmn and SOmn pins, and FEFmn,
PEFmn, OVFmn flags.
Caution Be sure to clear bits 15 to 4 of the ST0 register, bits 15 to 2 of the ST1 register in 64-pin and 80-
pin products, and bit 15 to 4 of the ST1 register in 100-pin products to “0”.

2. When the STm register is read, 0000H is always read.
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18.3.10 Serial channel enable status register m (SEm)

The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1
is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication operation is
output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its value
from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by
software.
The SEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 18-14. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0) After reset: 0000H R

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE0 0 0 0 0 0 0 0 0 0 0 0 0 SE03 SE02 SE01 SE00
Address: F0160H, F0161H (SE1) After reset: 0000H R

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE1 0 0 0 0 0 0 0 0 0 0 0 0 SE13 SE12 SE11 SE10
SEm Indication of operation enable/stop status of channel n

n
0 Operation stops
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18.3.11 Serial output enable register m (SOEm)

The SOEm register is a register that is used to enable or stop output of the serial communication operation of each
channel.
Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m
(SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software, and that
value can be output from the serial data output pin. In this way, any waveform of the start condition and stop condition can
be created by software.
The SOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SOEmL.
Reset signal generation clears the SOEm register to 0000H.
Figure 18-15. Format of Serial Output Enable Register m (SOEm)
Address: F012AH, F012BH (SOE0) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE 0 SOE

02 00
Address: F016AH, F016BH (SOE1) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE1 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE 0 SOE
12 10
SOE Serial output enable/stop of channel n

mn
0 Stops output by serial communication operation.

1 Enables output by serial communication operation.
Caution Be sure to clear bits 15 to 3 and 1 of the SOE0 register, bits 15 to 1 of the SOE1 register in 64-pin
and 80-pin products, and bits 15 to 3 and 1 of the SOE1 register in 100-pin products to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12
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18.3.12 Serial output register m (SOm)

The SOm register is a buffer register for serial output of each channel.
The value of the SOmn bit of this register is output from the serial data output pin of channel n.
The value of the CKOmn bit of this register is output from the serial clock output pin of channel n.
The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When
serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be changed only
by a serial communication operation.
The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0).
While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of the CKOmn bit can be
changed only by a serial communication operation.
To use the pin for serial interface as a port function pin, set the corresponding CKOmn and SOmn bits to “1”.
The SOm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SO0 register to 0F0FH and SO1 register to 0F0FH or 0303H.
Figure 18-16. Format of Serial Output Register m (SOm)
Address: F0128H, F0129H (SO0) After reset: 0F0FH R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO0 0 0 0 0 1 CKO 1 CKO 0 0 0 0 1 SO 1 SO

02 00 02 00
Address: F0168H, F0169H (SO1) After reset: 0F0FH (R5F10NPJ, R5F10NMJ, R5F10NPG), 0303H (R5F10NMG, R5F10NLG,
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO1 0 0 0 0 1 CKO 1 CKO 0 0 0 0 1 SO 1 SO

12 10 12 10
CKO Serial clock output of channel n

mn
0 Serial clock output value is “0”.

1 Serial clock output value is “1”.
SO Serial data output of channel n

mn
0 Serial data output value is “0”.

1 Serial data output value is “1”.
Caution Be sure to clear bits 15 to 12 and 7 to 4 of the SO0 register to “0”. And be sure to set bits 11, 9, 3,
and 1 to “1”.
For the SO1 register in products with 64 or 128 Kbytes of code flash memory, be sure to clear
bits 15 to 10 and 7 to 2 to 0, and set bits 9, 8, and 1 to 1.
For the SO1 register in products with 256 Kbytes of code flash memory, be sure to clear bits 15
to 12 and 7 to 4 to 0, and set bits 11, 9, 8, 3, and 1 to 1.
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18.3.13 Serial output level register m (SOLm)

The SOLm register is a register that is used to set inversion of the data output level of each channel.
This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and simplifies
2
I C mode.
Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1).
When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
Rewriting the SOLm register is prohibited when the register is in operation (when SEmn = 1).
The SOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction with SOLmL.
Reset signal generation clears the SOLm register to 0000H.
Figure 18-17. Format of Serial Output Level Register m (SOLm)
Address: F0134H, F0135H (SOL0) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOL0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 0 SOL

02 00
Address: F0174H, F0175H (SOL1) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOL1 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 0 SOL

12 10
SOL Selects inversion of the level of the transmit data of channel n in UART mode
mn
0 Communication data is output as is.

1 Communication data is inverted and output.
Caution Be sure to clear bits 15 to 3, and 1 of the SOL0 register, bits 15 to 1 of the SOL1 register in 64-pin
and 80-pin products, and bits 15 to 3 and 1 of the SOL1 register in 100-pin products to “0”.
Figure 18-18 shows examples in which the level of transmit data is reversed during UART transmission.
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Figure 18-18. Examples of Reverse Transmit Data
(1) Non-reverse Output (SOLmn = 0)
SOLmn = 0 output
TXDq
ST P S
Transmit data
(2) Reverse Output (SOLmn = 1)
SOLmn = 1 output
TXDq
ST P S
Transmit data (inverted)
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18.3.14 Serial standby control register 0 (SSC0)

The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when
receiving CSI00 or UART0 serial data.
The SSC0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction with SSC0L.
Reset signal generation clears the SSC0 register to 0000H.
Caution The maximum transfer rate in the SNOOZE mode is as follows.

● When using CSI00 : Up to 1 Mbps
● When using UART0 : 4800 bps only
Figure 18-19. Format of Serial Standby Control Register 0 (SSC0)
Address: F0138H (SSC0) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS SWC
EC0 0
SS Selection of whether to enable or disable the generation of communication error interrupts in the SNOOZE
EC0 mode
0 Enable the generation of error interrupts (INTSRE0)

1 Stop the generation of error interrupts (INTSRE0)
● The SSECm bit can be set to 1 or 0 only when both the SWC0 and EOCmn bits are set to 1 during UART
reception in the SNOOZE mode. In other cases, clear the SSEC0 bit to 0.
● Setting SSEC0, SWC0 = 1, 0 is prohibited.
SWC Setting of the SNOOZE mode

0
0 Do not use the SNOOZE mode function.

1 Use the SNOOZE mode function.
● When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion
is performed without operating the CPU (the SNOOZE mode).
● The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for
the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
● Even when using SNOOZE mode, be sure to set the SWC0 bit to 0 in normal operation mode and change it to 1
just before shifting to STOP mode.
Also, be sure to change the SWC0 bit to 0 after returning from STOP mode to normal operation mode.
Figure 18-20. Interrupt in UART Reception Operation in SNOOZE Mode
EOCmn Bit SSECm Bit Reception Ended Successfully Reception Ended in an Error
0 0 INTSRx is generated. INTSRx is generated.

0 1 INTSRx is generated. INTSRx is generated.
1 0 INTSRx is generated. INTSREx is generated.
1 1 INTSRx is generated. No interrupt is generated.
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18.3.15 Input switch control register (ISC)

The ISC0 bit of the ISC register is used to realize a LIN-bus communication operation by UART0 in coordination with an
external interrupt and the timer array unit.
When bit 0 is set to 1, the input signal of the serial data input (RXD0) pin is selected as an external interrupt (INTP0)
that can be used to detect a wakeup signal.
The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the ISC register to 00H.
Figure 18-21. Format of Input Switch Control Register (ISC)

Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 0 ISC0
ISC0 Switching external interrupt (INTP0) input
0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1 Uses the input signal of the RXD0 pin as an external interrupt (wakeup signal detection).
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18.3.16 Noise filter enable register 0 (NFEN0)

The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin
to each channel.
Disable the noise filter of the pin used for CSI or simplified I2C communication, by clearing the corresponding bit of this
register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
When the noise filter is enabled, after synchronization is performed with the operation clock (fMCK) of the target channel,
2-clock match detection is performed. When the noise filter is disabled, only synchronization is performed with the
operation clock (fMCK) of the target channel.
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Figure 18-22. Format of Noise Filter Enable Register 0 (NFEN0)

Symbol 7 6 5 4 3 2 1 0
Note
NFEN0 0 SNFEN30 0 SNFEN20 0 SNFEN10 0 SNFEN00
SNFEN30 Use of noise filter of RXD3 pin
0 Noise filter OFF

1 Noise filter ON
Set SNFEN30 to 1 to use the RXD3 pin.
Clear SNFEN30 to 0 to use the other than RxD3 pin.
0 Noise filter OFF

1 Noise filter ON
Set SNFEN20 to 1 to use the RXD2 pin.

Clear SNFEN20 to 0 to use the other than RxD2 pin.
0 Noise filter OFF

1 Noise filter ON
Set the SNFEN10 bit to 1 to use the RXD1 pin.

Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
0 Noise filter OFF

1 Noise filter ON
Set the SNFEN00 bit to 1 to use the RXD0 pin.

Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Note This bit is only effective for R5F10NPJ, R5F10NMJ, and R5F10NPG. When writing 1 to this bit for
R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE, the value read is 0.
Caution Be sure to clear bits 7, 5, 3, and 1 to “0”.
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18.3.17 Registers controlling port functions of serial input/output pins

When using the serial array unit set the registers that control the port functions multiplexed on the target channel (port
mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx)).
For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.4 Port input mode registers
(PIMxx), and 4.3.5 Port output mode registers (POMxx).
When using a port pin with a multiplexed serial data or serial clock output function (e.g. P07/SO00/TxD0/TI02/TO02/
INTP2/TOOLTxD, P15/SEG9/(SCK00)/(SCL00)) for serial data or serial clock output, requires setting the corresponding
bits in the port mode register (PMxx) to 0, and the corresponding bit in the port register (Pxx) to 1.
When using the port pin in N-ch open-drain output (VDD tolerance) mode, set the corresponding bit in the port output
mode register (POMxx) to 1. When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V),
see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V).
Example: When using P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD for serial data output

Set the PM07 bit of the port mode register 0 to 0.
Set the P07 bit of the port register 0 to 1.
When using a port pin with a multiplexed serial data or serial clock input function (e.g.
P05/SCK00/SCL00/TI04/TO04/INTP3, P06/SI00/RxD0/TI03/TO03/SDA00/TOOLRxD) for serial data or serial clock input,
requires setting the corresponding bit in the port mode register (PMxx) to 1. In this case, the corresponding bit in the port
register (Pxx) can be set to 0 or 1.
When the TTL input buffer is selected, set the corresponding bit in the port input mode register (PIMxx) to 1. When
connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), see 4.4.4 Connecting to external
device with different potential (1.8 V, 2.5 V, 3 V).
Example: When using P06/SI00/RxD0/TI03/TO03/SDA00/TOOLRxD for serial data input

Set the P06 bit of port register 0 to 0 or 1.
The PMxx registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the PMxx registers to FFH.
See Table 4-3 to see which PMxx registers are provided for each product.
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To reset the serial array unit (SAU0 and SAU1), be sure to set bits 2 and 3 (SAU0RES and SAU1RES) to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
SAUnRES Control resetting of the serial array unit (units 0 and1)
0 Release of the reset state of the serial array unit (unit n)

1 The serial array unit (unit n) is in the reset state.
Remark n = 0, 1
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18.4 Operation Stop Mode
Each serial interface of serial array unit has the operation stop mode.
In this mode, serial communication cannot be executed, thus reducing the power consumption.
In addition, the pin for serial interface can be used as port function pins in this mode.
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18.4.1 Stopping the operation by units

The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0.
To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0.
Figure 18-24. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAUm to be stopped to 0.
7 6 5 4 3 2 1 0
× × × 0/1 0/1 ×
Control of SAUm input clock
0: Stops supply of input clock
1: Supplies input clock
Cautions 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the
register is read, only the default value is read
Note that this does not apply to the following registers.
● Port input mode register (PIMx)
● Port output mode register (POMx)
● Port mode register (PMx)
● Port register (Px)
2. Be sure to clear bits 7 and 1 to 0.
Remark ×: Bits not used with serial array units (depending on the settings of other peripheral functions)
0/1: Set to 0 or 1 depending on the usage of the user
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18.4.2 Stopping the operation by channels

The stopping of the operation by channels is set using each of the following registers.
Figure 18-25. Each Register Setting When Stopping the Operation by Channels
(a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STm STm3 STm2 STm1 STm0

0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1 0/1 0/1
1: Clears the SEmn bit to 0 and stops the communication operation
* Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0.
(b) Serial Channel Enable Status Register m (SEm) … This register indicates whether data
transmission/reception operation of each channel is enabled or stopped.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEm SEm3 SEm2 SEm1 SEm0

0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1 0/1 0/1
0: Operation stops
* The SEm register is a read-only status register, whose operation is stopped by using the STm register.
With a channel whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by
software.
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
output of the serial communication operation of each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software.
(d) Serial output register m (SOm) …This register is a buffer register for serial output of each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm CKOm2 CKOm0 SOm2 SOm0

0 0 0 0 1 0/1 1 0/1 0 0 0 0 1 0/1 1 0/1
1: Serial clock output value is “1” 1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOmn bits to “1”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)

2. : Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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18.5 Operation of 3-Wire Serial I/O (CSI00, CSI10, CSI30) Communication
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
● Data length of 7 or 8 bits
● Phase control of transmit/receive data
● MSB/LSB first selectable
[Clock control]
● Master/slave selection
● Phase control of I/O clock
● Setting of transfer period by prescaler and internal counter of each channel
● Maximum transfer rateNote
During master communication: Max. fMCK/2
During slave communication: Max. fMCK/6
● Overrun error
In addition, CSI00 supports the SNOOZE mode. When SCK input is detected while in the STOP mode, the SNOOZE
mode makes data reception that does not require the CPU possible. CSI00 supports the asynchronous reception.
Note Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics. For details, see CHAPTER 41
ELECTRICAL SPECIFICATIONS.
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The channel supporting 3-wire serial I/O (CSI00) is channel 0 of SAU0.

0 0 CSI00 UART0 (supporting LIN-bus) IIC00
1 – –
2 CSI10 UART1 IIC10
3 – –
1 0 – UART2 (supporting IrDA) –

1 – –
2 CSI30Note UART3 Note IIC30 Note
3 – –
Note 100-pin products only
3-wire serial I/O (CSI00, CSI10, CSI30) performs the following seven types of communication operations.
● Master transmission (See 18.5.1.)
● Master reception (See 18.5.2.)
● Master transmission/reception (See 18.5.3.)
● Slave transmission (See 18.5.4.)
● Slave reception (See 18.5.5.)
● Slave transmission/reception (See 18.5.6.)
● SNOOZE mode function (CSI00 only) (See 18.5.7.)
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18.5.1 Master transmission

Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device.
3-Wire Serial I/O CSI00 CSI10 CSI30
Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 2 of SAU1
Pins used SCK00, SO00 SCK10, SO10 SCK30, SO30
Interrupt INTCSI00 INTCSI10 INTCSI30
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag None
Transfer data length 7 or 8 bits
Transfer rateNote Max. fCLK/2 [Hz]

Min. fCLK/(2 × 215 × 128) [Hz] fCLK: System clock frequency
Data phase Selectable by the DAPmn bit of the SCRmn register

● DAPmn = 0: Data output starts from the start of the operation of the serial clock.
● DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register

● CKPmn = 0: Non-reverse (data output at the falling edge and data input at the rising edge of SCK)
● CKPmn = 1: Reverse (data output at the rising edge and data input at the falling edge of SCK)
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in
the electrical specifications (see CHAPTER 41 ELECTRICAL SPECIFICATIONS).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12
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(1) Register setting
Figure 18-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
(1/2)
(a) Serial mode register mn (SMRmn)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0/1
Operation clock (fMCK) of channel n Interrupt source of channel n

0: Prescaler output clock CKm0 set by the SPSm register 0: Transfer end interrupt
1: Prescaler output clock CKm1 set by the SPSm register 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn RXEmn DAPmn CKPmn EOCmn PTCmn1 PTCmn0 DIRmn SLCmn1 SLCmn0 DLSmn1 DLSmn0
1 0 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1
Selection of data transfer sequence Setting of data length

Selection of the data and clock 0: Inputs/outputs data with MSB first 0: 7-bit data length
phase (For details about the 1: Inputs/outputs data with LSB first. 1: 8-bit data length
setting, see 18.3 Registers
Controlling Serial Array Unit.)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting Transmit data

(Operation clock (fMCK) division setting) 0 (Transmit data setting)
SIOp
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1 1 0/1 0 0 0 0 1 0/1 1 0/1
Communication starts when these bits are 1 if the clock
phase is non-reversed (the CKPmn bit of the SCRmn = 0).
If the clock phase is reversed (CKPmn = 1),
communication starts when these bits are 0.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), p: CSI number (p = 00, 10, 30), mn = 00, 02,
12
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
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Figure 18-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (2/2)
(e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm SSm3 SSm2 SSm1 SSm0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
2. : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
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(2) Operation procedure
Figure 18-27. Initial Setting Procedure for Master Transmission
Starting initial setting
Setting the PER0 register Release the serial array unit from the
reset status and start clock supply.
Setting the SPSm register Set the operation clock.
Setting the SMRmn register Set an operation mode, etc.
Setting the SCRmn register Set a communication format.
Set a transfer baud rate (setting the

Setting the SDRmn register transfer clock by dividing the operation
clock (fMCK)).
Set the initial output level of the serial

Setting the SOm register
clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to “1” and enable data

Setting of the SOEm register
output of the target channel.
Setting a port register and a port mode

Setting port register (Enable data output and clock
output of the target channel by)
Set the SSmn bit of the target channel to

Writing to the SSm register
“1” (SEmn bit = 1: to enable operation).
Setting of SAU is completed.

Completing initial setting
Write transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
start communication.
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Figure 18-28. Procedure for Stopping Master Transmission
Starting setting to stop
If there is any data being transferred, wait for

No their completion.
(Selective) TSFmn = 0? (If there is an urgent must stop, do not wait)
Yes
(Essential) Writing the STm register Write “1” to the STmn bit of the target channel.
(SEmn = 0: to operation stop status)
(Essential) Changing setting of the SOEm register Set the SOEmn bit to “0” and stop the output
of the target channel.
The levels of the serial clock (CKOmn) and

(Selective) Changing setting of the SOm register
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
(Selective) Setting the PER0 register Reset the serial array unit by stopping the
clock supply to it.
The master transmission is stopped.

Stop setting is completed
Go to the next processing.
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Figure 18-29. Procedure for Resuming Master Transmission
Starting setting for resumption
Wait until stop the communication target

No (slave) or communication operation
(Essential) Slave ready? completed
Yes
Disable data output and clock output of
(Essential) Port manipulation
the target channel by setting a port
register and a port mode register.
Re-set the register to change the operation

(Selective) Changing setting of the SPSm register
clock setting.
Re-set the register to change the

(Selective) Changing setting of the SDRmn register
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (fMCK)).
Re-set the register to change serial

(Selective) Changing setting of the SMRmn register
mode register mn (SMRmn) setting.

(Selective) Changing setting of the SCRmn register communication operation setting register
mn (SCRmn) setting.
Set the SOEmn bit to “0” to stop output

(Selective) Changing setting of the SOEm register
from the target channel.

Set the SOEmn bit to “1” and enable

output from the target channel.
Enable data output and clock output of

(Essential) Port manipulation the target channel by setting a port

(Essential) Writing to the SSm register “1” (SEmn = 1: to enable operation).
Setting is completed
Completing resumption
Sets transmit data to the SIOp register (bits
setting
7 to 0 of the SDRmn register) and start
communication.
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait
until the transmission target (slave) stops or transmission finishes, and then perform initialization
instead of restarting the transmission.
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(3) Processing flow (in single-transmission mode)
Figure 18-30. Timing Chart of Master Transmission (in Single-Transmission Mode)

(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn Transmit data 1 Transmit data 2 Transmit data 3
SCKp pin
SOp pin Transmit data 1 Transmit data 2 Transmit data 3
Shift
Shift operation Shift operation Shift operation
register mn
INTCSIp
Data transmission Data transmission Data transmission

TSFmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), p: CSI number (p = 00, 10, 30), mn = 00, 02,
12
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Figure 18-31. Flowchart of Master Transmission (in Single-Transmission Mode)
Starting CSI communication
For the initial setting, see Figure 18-27.

SAU default setting
(Select Transfer end interrupt)
Main routine
Set data for transmission and the number of data. Clear communication end flag
Setting transmit data (Storage area, Transmission data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
Enables interrupt
interrupt enable (EI).
Writing transmit data to Read transmit data from storage area and write it
SIOp (=SDRmn[7:0]) to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and
SCKp signals out
(communication starts)
Wait for transmit completes

When Transfer end interrupt is generated, it
moves to interrupt processing routine
Transfer end interrupt
Interrupt processing routine
No
Transmitting next data?
Yes
Read transmit data, if any, from storage area and
Writing transmit data to Sets communication
write it to SIOp. Update transmit data pointer.
SIOp (=SDRmn[7:0]) completion flag
If not, set transmit end flag
RETI
No Check completion of transmission by

Transmission completed? verifying transmit end flag
Yes
Main routine
Disable interrupt (MASK)
Write STmn bit to 1
End of communication
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(4) Processing flow (in continuous transmission mode)
Figure 18-32. Timing Chart of Master Transmission (in Continuous Transmission Mode)
SSmn <1>
STmn <6>
SEmn
SCKp pin

Shift Shift operation Shift operation Shift operation
register mn
INTCSIp

MDmn0 <4>
TSFmn
BFFmn
<2><3> <2> <3> <2> <3> <5>

(Note)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
12
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Figure 18-33. Flowchart of Master Transmission (in Continuous Transmission Mode)
Starting setting

<1> SAU default setting (Select buffer empty interrupt)
Main routine
Enables interrupt
<2>
to SIOp. Update transmit data pointer.
SIOp (=SDRmn[7:0]) Writing to SIOp makes SOp
and SCKp signals out

When transfer end interrupt is generated, it moves to
<3><5> interrupt processing routine.
Buffer empty/transfer end interrupt

If transmit data is left, read them from storage area then

write into SIOp, and update transmit data pointer and
No
Number of number of transmit data.
communication data > 0? If no more transmit data, clear MDmn bit if it’s set. If not,
finish.
Yes
Writing transmit data to No

MDmn = 1?
SIOp (=SDRmn[7:0])
Yes
<4>
Subtract -1 from number of Sets communication
Clear MDmn0 bit to 0 completion interrupt flag
transmit data
RETI

Yes
Main routine
Write 1 to MDmn0 bit
Yes
Communication
continued?
No
<6> Write 1 to STmn bit
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 18-32 Timing Chart of Master
Transmission (in Continuous Transmission Mode).
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18.5.2 Master reception

Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device.
Pins used SCK00, SI00 SCK10, SI10 SCK30, SI30
can be selected.
Error detection flag Overrun error detection flag (OVFmn) only

Note
Transfer rate Max. fCLK/2 [Hz]

● DAPmn = 0: Data input starts from the start of the operation of the serial clock.
● DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.

● CKPmn = 0: Non-reverse
● CKPmn = 1: Reverse
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Figure 18-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
(1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting Receive data

(Operation clock (fMCK) division setting) 0 (Write FFH as dummy data.)
SIOp
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1 1 0/1 0 0 0 0 1 × 1 ×
phase is non-reversed (the CKPmn bit of the SCRmn = 0).
12
2. : Setting is fixed in the CSI master reception mode, : Setting disabled (set to the initial value)
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Figure 18-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (2/2)
(e) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 × 0 ×
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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Figure 18-35. Initial Setting Procedure for Master Reception
Release the serial array unit from the

Setting the PER0 register

Setting the SDRmn register
clock (fMCK)).

clock (CKOmn).
Enable clock output of the target channel

Setting port by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to “1”
Writing to the SSm register (SEmn bit = 1: to enable operation).
Set dummy data to the SIOp register (bits

End of initial setting 7 to 0 of the SDRmn register) and start
communication.
Figure 18-36. Procedure for Stopping Master Reception

Yes

clock supply to it.

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Figure 18-37. Procedure for Resuming Master Reception
Wait until stop the communication target (slave

No or communication operation completed
(Essential) Completing slave
preparations?
Yes Disable clock output of the target

(Essential) Port manipulation channel by setting a port register and a
port mode register.

clock setting.

clock (fMCK)).


mn (SCRmn) setting.

clock (CKOmn).
If the OVF flag remain set, clear this

(Selective) Clearing error flag using serial flag clear trigger register mn
(SIRmn).

(Essential) Port manipulation by setting a port register and a port mode
register.
(Essential) Set the SSmn bit of the target channel to “1”

(SEmn bit = 1: to enable operation).
Setting is completed
Completing resumption
Sets dummy data to the SIOp register (bits
setting
7 to 0 of the SDRmn register) and start
communication.
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(3) Processing flow (in single-reception mode)
Figure 18-38. Timing Chart of Master Reception (in Single-reception Mode)

SSmn
STmn
SEmn
Receive data 1 Receive data 2 Receive data 3
SDRmn Dummy data for reception Dummy data Dummy data
Write Write Write
Read Read Read
SCKp pin
SIp pin Receive data 1 Receive data 2 Receive data 3

Shift
register mn Reception & shift operation Reception & shift operation Reception & shift operation
INTCSIp
Data reception Data reception Data reception

TSFmn
12
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Figure 18-39. Flowchart of Master Reception (in Single-reception Mode)

Main routine
SAU default setting (Select Transfer end interrupt)
Setting storage area of the receive data, number of communication data

Setting receive data (Storage area, Reception data pointer, Number of communication data and
Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Writing to SIOp makes SCKp signals out

Writing dummy data to
SIOp (=SDRmn[7:0])
Wait for receive completes

When transfer end interrupt is generated, it moves
to interrupt processing routine

generated?
Read receive data then writes to storage area.

Reading receive data to
Update receive data pointer and number of
SIOp (=SDRmn[7:0])
communication data.
RETI
No
Check the number of communication data
All reception completed?
Yes
Main routine
Write STmn bit to 1
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(4) Processing flow (in continuous reception mode)
Figure 18-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1>
STmn <8>
SEmn
Receive data 3
SDRmn Dummy data Dummy data Receive data 1 Dummy data Receive data 2
<2> Write <2> Write <2> Write
Read Read Read
SCKp pin
Shift
Reception & shift operation Reception & shift operation Reception & shift operation
register mn
INTCSIp

MDmn0 <5>
TSFmn
BFFmn
<3> <3> <4> <3> <4> <6> <7>
Caution The MDmn0 bit can be rewritten even during operation.

However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 18-41 Flowchart of Master Reception
(in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), p: CSI number (p = 00, 10, 30), mn = 00,
02, 12
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Figure 18-41. Flowchart of Master Reception (in Continuous Reception Mode)

SAU default setting (Select buffer empty interrupt)
<1>
Setting storage area of the receive data, number of communication data

Setting receive data (Storage area, Reception data pointer, Number of communication data and
Main routine
Writing to SIOp makes SCKp

<2> signals out (communication starts)
SIOp (=SDRmn[7:0])
When interrupt is generated, it moves to

<3> <6>
interrupt processing routine
No
BFFmn = 1?
Yes
<4> Reading receive data from Read receive data, if any, then write them to storage
SIOp (=SDRmn[7:0]) area, and update receive data pointer (also subtract -1
<7> from number of transmit data)
Subtract -1 from number of

transmit data
=0 ≥2
Number of communication
data?
<2>
<5> =1
Clear MDmn0 bit to 0 SIOp (=SDRmn[7:0])
RETI
No
Number of communication When number of communication data
data = 0? becomes 0, receive completes
Yes
Main routine
Yes
Communication continued?
No
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 18-40 Timing Chart of Master Reception
(in Continuous Reception Mode).
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18.5.3 Master transmission/reception

Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data
to/from other device.
Pins used SCK00, SI00, SO00 SCK10, SI10, SO10 SCK30, SI30, SO30
can be selected.
Transfer rateNote Max. fCLK/2 [Hz]


● DAPmn = 0: Data I/O starts at the start of the operation of the serial clock.
● DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.

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Figure 18-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting

Transmit data setting/receive data register
(Operation clock (fMCK) division setting) 0
SIOp
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1 1 0/1 0 0 0 0 1 0/1 1 0/1
phase is non-reverse (the CKPmn bit of the SCRmn = 0).
12
2. : Setting is fixed in the CSI master transmission/reception mode
: Setting disabled (set to the initial value)
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Figure 18-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (2/2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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Figure 18-43. Initial Setting Procedure for Master Transmission/Reception


clock (fMCK)).


Changing setting of the SOEm register

Setting port the target channel by setting a port
Set transmit data to the SIOp register (bits

Completing initial setting 7 to 0 of the SDRmn register) and start
communication.
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Figure 18-44. Procedure for Stopping Master Transmission/Reception

Yes

clock supply to it.

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Figure 18-45. Procedure for Resuming Master Transmission/Reception

No (slave) or communication operation
(Essential) Completing slave
completed
preparations?
Yes
Disable data output and clock output of
(Selective) the target channel by setting a port
Port manipulation

(Essential) Changing setting of the SPSm register
clock setting.
Re-set the register to change the transfer

baud rate setting (setting the transfer
clock by dividing the operation clock
(fMCK)).
Changing setting of the SMRmn register

(Selective)

mn (SCRmn) setting.




the target channel by setting a port

(Essential) Writing to the SSm register
“1” (SEmn = 1: to enable operation).
Completing resumption setting
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(3) Processing flow (in single-transmission/reception mode)
Figure 18-46. Timing Chart of Master Transmission/Reception (in Single-Transmission/reception Mode)

SSmn
STmn
SEmn
Write Write Write
Read Read Read
SCKp pin
Shift
register mn
INTCSIp
Data transmission/reception Data transmission/reception Data transmission/reception

TSFmn
12
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Figure 18-47. Flowchart of Master Transmission/Reception (in Single-Transmission/reception Mode)

SAU default setting
(Select transfer end interrupt)
Main routine
Setting storage data and number of data for transmission/reception data

Setting (Storage area, Transmission data pointer, Reception data pointer, Number of
transmission/reception data communication data and Communication end flag are optionally set on the
internal RAM by the software)
Enables interrupt
SIOp (=SDRmn[7:0]) to SIOp. Update transmit data pointer. Writing to SIOp makes SOp
Wait for transmission/reception
completes
When transfer end interrupt is generated, it
moves to interrupt processing routine.
Read receive data then writes to storage area, update receive

Read receive data to SIOp
data pointer
(=SDRmn[7:0])
RETI
No Transmission/reception
If there are the next data, it continues
completed?
Yes
Main routine
Write STmn bit to 1
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(4) Processing flow (in continuous transmission/reception mode)
Figure 18-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
SSmn <1>
STmn <8>
SEmn
Receive data 3
SDRmn Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3 Receive data 2
Write Write Write
Read Read Read
SCKp pin
Shift
register mn
INTCSIp

MDmn0 <5>
TSFmn
BFFmn
<2><3> <2> Note 2 <3> <4> <2> <3> <4> <6> <7>
Note 2
Note 1
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 18-49 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), p: CSI number (p = 00, 10, 30), mn = 00, 02,
12
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Figure 18-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting setting

<1> SAU default setting
(Select buffer empty interrupt)
Main routine
Setting storage data and number of data for transmission/reception data

Setting
(Storage area, Transmission data pointer, Reception data, Number of
transmission/reception data communication data and Communication end flag are optionally set on the
internal RAM by the software)
Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt
enable (EI)
<2> Writing dummy data to Read transmit data from storage area and write it
SIOp (=SDRmn[7:0]) to SIOp. Update transmit data pointer.
Writing to SIOp makes SOp
completes
When transmission/reception interrupt is generated, it
<3> <6>

No
BFFmn = 1?
Yes Except for initial interrupt, read data received then write them
to storage area, and update receive data pointer
Reading reception data from
<4>
SIOp (=SDRmn[7:0])
<7>

transmit data
If transmit data is left (number of communication data is
equal or grater than 2), read them from storage area then
=0 =1 write into SIOp, and update transmit data pointer.
Number of
communication data? If it’s waiting for the last data to receive (number of
communication data is equal to 1), change interrupt timing
≥2 to communication end
<5>
Writing transmit data to
SIOp (=SDRmn[7:0]) Clear MDmn0 bit to 0
RETI
No
data = 0?
Yes

Main routine
Yes
Continuing Communication?
No
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 18-48 Timing Chart of Master
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18.5.4 Slave transmission

Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock
being input from another device.
Pins used SCK00, SO00 SCK10, SO10 SCK30, SO30
can be selected.
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2

● DAPmn = 0: Data output starts from the start of the operation of the serial clock.
● DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.

Notes 1. Because the external serial clock input to the SCK00, SCK10, and SCK30 pins is sampled internally and
used, the fastest transfer rate is fMCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see CHAPTER 41 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock frequency of target channel

2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12
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Figure 18-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Transmit data setting
Baud rate setting
0
SIOp
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 × 1 × 0 0 0 0 1 0/1 1 0/1
12
2. : Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value)
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Figure 18-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (2/2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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Figure 18-51. Initial Setting Procedure for Slave Transmission

Set bits 15 to 9 to 0000000B for baud rate

setting.

data (SOmn).

Enable data output of the target channel
register.
Writing to the SSm register “1” (SEmn bit = 1: to enable operation).
Initial setting is completed.

Set transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and wait for
a clock from the master.
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Figure 18-52. Procedure for Stopping Slave Transmission

Yes

clock supply to it.

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Figure 18-53. Procedure for Resuming Slave Transmission
No Wait until stop the communication target

(Essential) Completing master
preparations? (master)
Yes Disable data output of the target channel

Port manipulation by setting a port register and a port
(Selective)
mode register.

Changing setting of the SPSm register
(Selective) clock setting.
(Selective) Changing setting of the SDRmn register baud rate setting (setting the transfer clock
by dividing the operation clock (fMCK)).

Changing setting of the SMRmn register
(Selective) mode register mn (SMRmn) setting.

Changing setting of the SCRmn register communication operation setting register
(Selective)
mn (SCRmn) setting.

(Selective) Clearing error flag using serial flag clear trigger register mn
(SIRmn).

(Selective)

Changing setting of the SOm register
(Essential) data (SOmn).

(Essential) output from the target channel.

Port manipulation by setting a port register and a port mode
(Essential)
register.

(SEmn = 1: to enable operation).
Sets transmit data to the SIOp register (bits

(Essential) Starting communication 7 to 0 of the SDRmn register) and wait for a
clock from the master.
until the transmission target (master) stops or transmission finishes, and then perform initialization
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Figure 18-54. Timing Chart of Slave Transmission (in Single-Transmission Mode)

SSmn
STmn
SEmn

SCKp pin
Shift
register mn
INTCSIp

TSFmn
12
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Figure 18-55. Flowchart of Slave Transmission (in Single-Transmission Mode)

SAU default setting
Set storage area and the number of data for transmit data
Main routine
Writing transmit data to Read transmit data from storage area and write it to SIOp. Update
SIOp (=SDRmn[7:0]) transmit data pointer.
Start communication when master

start providing the clock
When transmit end, interrupt is generated
RETI Clear the interrupt request flag (xxIF).
Yes
Transmitting next data? Determine if it completes by counting number of communication data
No
Yes
Continuing transmit?
Main routine
No
Write 1 to STmn bit
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Figure 18-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode)
SSmn <1>
STmn <6>
SEmn

SCKp pin
Shift
register mn
INTCSIp

MDmn0 <4>
TSFmn
BFFmn
<2> <3> <2> <3> <2> <3> <5>

(Note)
However, rewrite it before transfer of the last bit is started.
12
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Figure 18-57. Flowchart of Slave Transmission (in Continuous Transmission Mode)
Starting setting
<1> For the initial setting, see Figure 18-51.

SAU default setting
Main routine
Setting transmit data Set storage area and the number of data for transmit data
(Storage area, Transmission data pointer, Number of communication data and
Enables interrupt
Read transmit data from buffer and write it to SIOp. Update transmit
<2> Writing transmit data to
SIOp (=SDRmn[7:0]) data pointer
Start communication when master start providing the

clock
When buffer empty/transfer end interrupt is generated,

<3> <5>
it moves to interrupt processing routine

No If transmit data is left, read them from storage area then write into
Number of transmit
data > 1? SIOp, and update transmit data pointer.
If not, change the interrupt to transmission complete
Yes
Reading transmit data

Clear MDmn0 bit to 0 <4>
SIOp (=SDRmn[7:0])
Subtract -1 from number of It is determined as follows depending on the number of communication data.
transmit data +1: Transmit data completion
0: During the last data received
RETI -1: All data received completion
No
data = -1?
Yes
Main routine
Yes
Communication continued?
No
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 18-56 Timing Chart of Slave
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18.5.5 Slave reception

Slave reception is that the RL78 microcontroller receive data from another device in the state of a transfer clock being
input from another device.
Pins used SCK00, SI00 SCK10, SI10 SCK30, SI30
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)

● DAPmn = 0: Data input starts from the start of the operation of the serial clock.
● DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.


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Figure 18-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
(1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0

1: Prescaler output clock CKm1 set by the SPSm register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Baud rate setting Receive data
0
SIOp
(d) Serial output register m (SOm) …The Register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 × 1 × 0 0 0 0 1 × 1 ×
12
2. : Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value)
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Figure 18-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
(2/2)
(e) Serial output enable register m (SOEm) …The Register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 × 0 ×
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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Figure 18-59. Initial Setting Procedure for Slave Reception
Starting initial settings

Set baud rate setting (bits 15 to 9) to

0000000B.
Enable data input and clock input of the

Setting port target channel by setting a port register
and a port mode register.
Writing to the SSm register (SEmn bit = 1: to enable operation). Wait
for a clock from the master.
Figure 18-60. Procedure for Stopping Slave Reception

Yes
(Essential) Changing setting of the SOEm register Set the SOEmn bit to 0 and stop the output of
the target channel.
clock supply to it.

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Figure 18-61. Procedure for Resuming Slave Reception

No (master)
Completing master
(Essential) preparations?
Yes Disable clock output of the target

channel by setting a port register and a
port mode register.

operation clock setting.


mn (SCRmn) setting.

(Selective) Clearing error flag
using serial flag clear trigger register mn
(SIRmn).

register.

Wait for a clock from the master.
until the transmission target (master) stops or transmission finishes, and then perform initialization
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(3) Processing flow (in single-reception mode)
Figure 18-62. Timing Chart of Slave Reception (in Single-reception Mode)

SSmn
STmn
SEmn
Receive data 3
SDRmn Receive data 1 Receive data 2
Read Read Read

SCKp pin
Shift
register mn
INTCSIp

TSFmn
12
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Figure 18-63. Flowchart of Slave Reception (in Single-reception Mode)

SAU default setting
(Select transfer end interrupt only)
Main routine
Clear storage area setting and the number of receive data

Ready for reception
(Storage area, Reception data pointer, Number of receive data are optionally
set on the internal RAM by the software)
Start communication when master start providing

the clock
When transmit end, interrupt is generated

Read receive data then writes to storage area, and counts

Reading receive data to
up the number of receive data.
SIOp (=SDRmn[7:0])
Update receive data pointer.
RETI
No
Check completion of number of receive data
Reception completed?
Main routine
Yes
Write STmn bit to 1
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18.5.6 Slave transmission/reception

Slave transmission/reception is that the RL78 microcontroller transmit/receive data to/from another device in the state
of a transfer clock being input from another device.
Pins used SCK00, SI00, SO00 SCK10, SI10, SO10 SCK30, SI30, SO30
can be selected.

● DAPmn = 0: Data I/O starts from the start of the operation of the serial clock.
● DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.


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Figure 18-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0/1 0/1 0 0 0 0 0/1 0 0 0 0 1 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Baud rate setting Transmit data setting/receive data register
0
SIOp
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 × 1 × 0 0 0 0 1 0/1 1 0/1
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
12
2. : Setting is fixed in the CSI slave transmission/reception mode,
: Setting disabled (set to the initial value)
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Figure 18-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI10, CSI30) (2/2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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Figure 18-65. Initial Setting Procedure for Slave Transmission/Reception

Set bits 15 to 9 to 0000000B for baud

rate setting.

data (SOmn).

data output of the target channel.

Setting port by setting a port register and a port
mode register.

(SEmn bit = 1: to enable operation).

Completing initial setting Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
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Figure 18-66. Procedure for Stopping Slave Transmission/Reception

Yes
the target channel.

clock supply to it.

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Figure 18-67. Procedure for Resuming Slave Transmission/Reception
No Wait until stop the communication target

(Essential) Completing
master (master)
Yes Disable data output of the target channel

(Essential) Port manipulation by setting a port register and a port
mode register.

Re-set the register to change serial mode

register mn (SMRmn) setting.

mn (SCRmn) setting.
If the OVF flag remain set, clear this using

(Selective) Clearing error flag serial flag clear trigger register mn
(SIRmn).


data (SOmn).


register.

(SEmn = 1: to enable operation).
Sets transmit data to the SIOp register

(Essential) Starting communication (bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
Cautions 1. Be sure to set transmit data to the SlOp register before the clock from the master is started.
2. If PER0 is rewritten while stopping the master transmission and the clock supply is stopped,
wait until the transmission target (master) stops or transmission finishes, and then perform
initialization instead of restarting the transmission.
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(3) Processing flow (in single-transmission/reception mode)
Figure 18-68. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)

SSmn
STmn
SEmn
Write Write Write
Read Read Read
SCKp pin
Shift
register mn
INTCSIp

TSFmn
12
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Figure 18-69. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)

SAU default setting
(Select Transfer end interrupt)
Setting storage area and number of data for transmission/reception data

Setting (Storage area, Transmission/reception data pointer, Number of communication data
transmission/reception data and Communication end flag are optionally set on the internal RAM by the software)
Main routine
Writing transmit data to Read transmit data from storage area and write it to SIOp.
SIOp (=SDRmn[7:0]) Update transmit data pointer.

clock
completes
Reading receive data to Read receive data and write it to storage area. Update
SIOp (=SDRmn[7:0]) receive data pointer.
RETI
No Transmission/reception
completed?
Yes
Update the number of communication data and confirm
Yes if next transmission/reception data is available
Transmission/reception
Main routine
next data?
No
Write STmn bit to 1
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(4) Processing flow (in continuous transmission/reception mode)
Figure 18-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
SSmn <1>
STmn <8>
SEmn
Receive data 3
SDRmn Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3 Receive data 2
Write Write Write
Read Read Read
SCKp pin
Shift
register mn
INTCSIp

MDmn0 <5>
TSFmn
BFFmn
<2> <3> <2> <3> <4> <2> <3> <4> <6> <7>
Note 2 Note 2
Note 1
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 18-71 Flowchart of Slave
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), p: CSI number (p = 00, 10, 30), mn = 00,
02, 12
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Figure 18-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting setting
<1> For the initial setting, see Figure 18-65.

SAU default setting
Main routine
Setting storage area and number of data for transmission/reception data

Setting (Storage area, Transmission/reception data pointer, Number of communication data
transmission/reception data and Communication end flag are optionally set on the internal RAM by the software)

clock
Wait for transmission completes
When buffer empty/transfer end is generated, it moves

<3> <6>
No
BFFmn = 1?
Yes
Other than the first interrupt, read reception data then writes
<4> Read receive data to SIOp
to storage area, update receive data pointer
(=SDRmn[7:0])
<7>

transmit data
If transmit data is remained (number of communication data ≥ 2),

=0 =1
Number of communication read it from storage area, write it to SIOp, and then, update
data? storage pointer.
If transmit is completed (number of communication data = 1),
Yes ≥2 change to transfer end interrupt.
<5>
Writing transmit data to Clear MDmn0 bit to 0
SIOp (=SDRmn[7:0])
RETI
No Number of communication
data = 0?
Yes
Main routine
Yes
Communication
continued?
No
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 18-70 Timing Chart of Slave
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18.5.7 SNOOZE mode function

SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops
communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU
operation by detecting SCKp pin input.
When using the CSI in SNOOZE mode, make the following setting before switching to the STOP mode (see Figure 18-
73 Flowchart of SNOOZE Mode Operation (Once Startup) and Figure 18-75 Flowchart of SNOOZE Mode
Operation (Continuous Startup)).
● When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just
before switching to the STOP mode. After the initial setting has been completed, set the SSm0 bit of serial channel
start register m (SSm) to 1.
● After a transition to the STOP mode, it transits to SNOOZE mode upon detection of an effective edge of the SCKp
pin.
The CSIp starts reception operations with the serial clock input of SCKp pin.
Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock (fIH) or the
medium-speed on-chip oscillator clock (fIM) is selected for fCLK.
2. The maximum transfer rate when using CSIp in the SNOOZE mode is 1 Mbps.
(1) SNOOZE mode operation (once startup)
Figure 18-72. Timing Chart of SNOOZE Mode Operation (Once Startup) (Type 1: DAPm0 = 0, CKPm0 = 0)
CPU operation status Normal operation STOP mode SNOOZE mode Normal operation
<4>
SSm0 <3> <11>
STm0 <1> <9>
SEm0
SWCm
<10>
SSECm L

(internal signal)
Receive data 2
SDRm0 Receive data 1
<8> ReadNote
SCKp pin
SIp pin Receive data 1 Receive data 2
Shift
Reception & shift operation Reception & shift operation
register m0
INTCSIp
Data reception Data reception

TSFm0
<2> <5><6> <7>
Note Only read received data while SWCm = 1 and before the next effective edge of the SCKp pin input is
detected.
Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the STm0 bit to 1 (clear the SEm0 bit, and stop the operation).
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode
release).
2. When SWCm = 1, the BFFm1 and OVFm1 flags will not change.
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 18-73 Flowchart of SNOOZE Mode
Operation (Once Startup).
2. m = 0; p = 00
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Figure 18-73. Flowchart of SNOOZE Mode Operation (Once Startup)
SNOOZE mode operation
No
TSFmn = 0 for all channels?
Yes
Become the operation STOP status (SEm0 = 0)
Normal operation
<1> Write 1 to STm0 bit
SMRm0, SCRm0: Communication setting

SAU default setting
SDRm0 [15:9]: Setting 0000000B
<2> Setting SSCm register Setting SNOOZE mode

(SWCm = 1, SSECm = 0)
<3> Write 1 to SSm0 bit Become the communication wait status (SEm0 = 1)
Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
processing and enable interrupt processing.
<4> Entered the STOP mode CPU/peripheral hardware clock fCLK supplied
to the SAU is stopped.
STOP mode
Effective edge of SCKp pin

<5> detected
(Entered the SNOOZE mode)
Serial clock input of SCKp pin

SNOOZE mode
<6> (CSIp reception operation)
<7> Transfer interrupt (INTCSIp) is

generated
(CSIp is receive completion)
<8> Reading receive data from The mode switches from SNOOZE to normal operation.
SIOp (=SDRmn[7:0])
Normal operation
<9> Write 1 to STm0 bit Become the operation STOP status (SEm0 = 0)
<10> Write 0 to SWCm bit Reset SNOOZE mode setting
<11> Write 1 to SSm0 bit It becomes communication ready state (SEm0 = 1) under
normal operation
End of SNOOZE mode
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 18-72 Timing Chart of SNOOZE
Mode Operation (Once Startup).
2. m = 0; p = 00
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(2) SNOOZE mode operation (continuous startup)
Figure 18-74. Timing Chart of SNOOZE Mode Operation (Continuous Startup) (Type 1: DAPm0 = 0, CKPm0 = 0)
CPU operation status Normal operation STOP mode SNOOZE mode Normal operation STOP mode SNOOZE mode
<4> <4>
SSm0 <3> <3>
STm0 <1> <9>
SEm0
SWCm <10>
SSECm L

(internal signal)
Receive data 2
SDRm0 Receive data 1
<8> Read Note
SCKp pin
SIp pin Receive data 1 Receive data 2
Shift
register m0 Reception & shift operation Reception & shift operation
INTCSIp

TSFm0
<2> <5><6> <7> <2> <5><6>
Note Only read received data while SWCm = 1 and before the next effective edge of the SCKp pin input is
detected.
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE release).
2. When SWCm = 1, the BFFm1 and OVFm1 flags will not change.
Operation (Continuous Startup).
2. m = 0; p = 00
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Figure 18-75. Flowchart of SNOOZE Mode Operation (Continuous Startup)
SNOOZE mode operation
No
TSFmn = 0 for all channels?
Yes
Normal operation
Become the operation STOP status (SEm0 = 0)

SMRm0, SCRm0: Communication setting

SAU default setting
SDRm0[15:9]: Setting 0000000B
<2> Setting SSCm register Setting SNOOZE mode

Write 1 to SSm0 bit Become the communication wait status (SEm0 = 1)

<3>
Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
processing and enable interrupt processing.
<4> Entered the STOP mode CPU/peripheral hardware clock fCLK supplied
STOP mode
to the SAU is stopped.
Effective edge of SCKp pin

<5> detected
SNOOZE mode
Serial clock input of SCKp pin

<6> (CSIp reception operation)
<7> Transfer interrupt (INTCSIp) is

generated
(CSIp is receive completion)
<8> Reading receive data from The mode switches from SNOOZE to normal operation.
SIOp (=SDRmn[7:0])
Normal operation
<10> Clear SWCm bit to 0 Reset SNOOZE mode setting
Mode Operation (Continuous Startup).
2. m = 0; p = 00
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18.5.8 Calculating transfer clock frequency

The transfer clock frequency for 3-wire serial I/O (CSI00, CSI10, CSI30) communication can be calculated by the
following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note [Hz]
Note The permissible maximum transfer clock frequency is fMCK/6.
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 18-2. Selection of Operation Clock For 3-Wire Serial I/O
SMRmn SPSm Register Operation Clock (fMCK)Note

Register
CKSmn PRS PRS PRS PRS PRS PRS PRS PRS fCLK = 24 MHz
m13 m12 m11 m10 m03 m02 m01 m00
0 X X X X 0 0 0 0 fCLK 24 MHz
X X X X 0 0 0 1 fCLK/2 12 MHz
2
X X X X 0 0 1 0 fCLK/2 6 MHz
X X X X 0 0 1 1 fCLK/23 3 MHz
4
X X X X 0 1 0 0 fCLK/2 1.5 MHz
X X X X 0 1 0 1 fCLK/25 750 kHz
6
X X X X 0 1 1 0 fCLK/2 375 kHz
X X X X 0 1 1 1 fCLK/27 187.5 kHz
8
X X X X 1 0 0 0 fCLK/2 93.8 kHz
X X X X 1 0 0 1 fCLK/29 46.9 kHz
X X X X 1 0 1 0 fCLK/210 23.4 kHz
X X X X 1 0 1 1 fCLK/211 11.7 kHz
X X X X 1 1 0 0 fCLK/212 5.86 kHz
13
X X X X 1 1 0 1 fCLK/2 2.93 kHz
X X X X 1 1 1 0 fCLK/214 1.46 kHz
15
X X X X 1 1 1 1 fCLK/2 732 Hz
1 0 0 0 0 X X X X fCLK 24 MHz
0 0 0 1 X X X X fCLK/2 12 MHz
0 0 1 0 X X X X fCLK/22 6 MHz
0 0 1 1 X X X X fCLK/23 3 MHz
0 1 0 0 X X X X fCLK/24 1.5 MHz
0 1 0 1 X X X X fCLK/25 750 kHz
6
0 1 1 0 X X X X fCLK/2 375 kHz
0 1 1 1 X X X X fCLK/27 187.5 kHz
8
1 0 0 0 X X X X fCLK/2 93.8 kHz
1 0 0 1 X X X X fCLK/29 46.9 kHz
10
1 0 1 0 X X X X fCLK/2 23.4 kHz
1 0 1 1 X X X X fCLK/211 11.7 kHz
1 1 0 0 X X X X fCLK/212 5.86 kHz
13
1 1 0 1 X X X X fCLK/2 2.93 kHz
1 1 1 0 X X X X fCLK/214 1.46 kHz
15
1 1 1 1 X X X X fCLK/2 732 Hz
unit (SAU).
Remarks 1. X: Don’t care

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18.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI10, CSI30)
communication
The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI10, CSI30) communication is
described in Figure 18-76.
Figure 18-76. Processing Procedure in Case of Overrun Error
Software Manipulation Hardware Status Remark
Reads serial data register mn (SDRmn). The BFFmn bit of the SSRmn register is This is to prevent an overrun error if the
set to 0 and channel n is enabled to next reception is completed during error
receive data. processing.
Reads serial status register mn Error type is identified and the read
(SSRmn). value is used to clear error flag.
Writes 1 to serial flag clear trigger Error flag is cleared. Error can be cleared only during
register mn (SIRmn). reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
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18.6 Operation of UART (UART0 to UART3) Communication
This is a start-stop synchronization function using two lines: serial/data transmission (TXD) and serial/data reception
(RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex asynchronous communication UART communication can be performed by using a
channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered
channel). The LIN-bus can be implemented by using UART0, timer array unit 0 (channel 7), and an external interrupt
(INTP0).
● Data length of 7, 8, or 9 bitsNote
● Select the MSB/LSB first
● Level setting of transmit/receive data (selecting whether to reverse the level)
● Parity bit appending and parity check functions
● Stop bit appending, stop bit check function
● Error interrupt in case of framing error, parity error, or overrun error
● Framing error, parity error, or overrun error
In addition, UART0 reception supports the SNOOZE mode. When RxD pin input is detected while in the STOP mode,
the SNOOZE mode makes data reception that does not require the CPU possible. Only UART0 can be specified for the
reception baud rate adjustment function.
The LIN-bus is accepted in UART0 (channels 0 and 1 of unit 0).
[LIN-bus functions]
● Wakeup signal detection Using the external interrupt (INTP0) and
● Break field (BF) detection timer array unit 0 (channel 7)
● Sync field measurement, baud rate calculation
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UART0 uses channels 0 and 1 of SAU0.


(supporting LIN-bus)
1 – –
2 CSI10 UART1 IIC10
3 – –
1 0 – UART2 –
(supporting IrDA)
1 – –
Note Note
2 CSI30 UART3 IIC30 Note
3 – –
Select any function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1
of unit 0, for example, these channels cannot be used for CSI00. At this time, however, channel 2 or 3 of the same unit
can be used for a function other than UART0, such as UART1 and IIC10.
Caution When using a serial array unit for UART, both the transmitter side (even-numbered channel) and the
receiver side (odd-numbered channel) can only be used for UART.
UART performs the following four types of communication operations.

● UART transmission (See 18.6.1.)
● UART reception (See 18.6.2.)
● LIN transmission (UART0 only) (See 18.7.1.)
● LIN reception (UART0 only) (See 18.7.2.)
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18.6.1 UART transmission

UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously
(start-stop synchronization).
Of two channels used for UART, the even channel is used for UART transmission.
UART UART0 UART1 UART2 UART3
Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1 Channel 2 of SAU1
Pins used TxD0 TxD1 TxD2 TxD3
Interrupt INTST0 INTST1 INTST2 INTST3
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be
selected.
Transfer data 7, 8, or 9 bitsNote 1
length
Transfer rate Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or more), Min. fCLK/(2 × 215 × 128) [bps]Note 2
Data phase Non-reverse output (default: high level)

Reverse output (default: low level)
Parity bit The following selectable

● No parity bit
● Appending 0 parity
● Appending even parity
● Appending odd parity
Stop bit The following selectable

● Appending 1 bit
● Appending 2 bits

fCLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12
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Figure 18-77. Example of Contents of Registers for UART Transmission of UART

(UART0 to UART3) (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn CCSmn MDmn2 MDmn1 MDmn0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0/1


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEmn RXEmn DAPmn CKPmn EOCmn PTCmn1 PTCmn0 DIRmn SLCmn1 SLCmn0 DLSmn1 DLSmn0
SCRmn
1 0 0 0 0 0 0/1 0/1 0/1 0 0/1 0/1 0 1 0/1 0/1
Note 1
Setting of parity bit Setting of stop bit

01B: Appending 1 bit
00B: No parity 10B: Appending 2 bits
01B: Appending 0 parity Selection of data transfer sequence
10B: Appending Even parity 0: Inputs/outputs data with MSB first
11B: Appending Odd parity 1: Inputs/outputs data with LSB first.
(c) Serial data register mn (SDRmn) (lower 8 bits: TXDq)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting Transmit data setting

0 Note 2
TXDq
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOLm SOLm2 SOLm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
0: Non-reverse (normal) transmission
1: Reverse transmission
Notes 1. Only provided for the SCR00 and SCR01 registers. This bit is fixed to 1 for the other registers.
2. When UART0 performs 9-bit communication, bits 0 to 8 of the SDRm0 register are used as the
transmission data specification area. Only UART0 can be specified for the 9-bit data length.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3),
mn = 00, 02, 10, 12
2. : Setting is fixed in the UART transmission mode, : Setting disabled (set to the initial value)
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Figure 18-77. Example of Contents of Registers for UART Transmission of UART

(e) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm2 SOm0
SOm CKOm2 CKOm0
0 0 0 0 1 1 0 0 0 0 1 0/1 1 0/1
× × Note Note
0: Serial data output value is “0”

1: Serial data output value is “1”
(f) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
Note Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0, and
set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the
communication data during communication operation.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 3), q: UART number (q = 0 to 3)

mn = 00, 02, 10, 12
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Figure 18-78. Initial Setting Procedure for UART Transmission


clock (fMCK)).
Changing setting of the SOLm register Set an output data level.
Setting the SOm register Set the initial output level of the serial
data (SOmn).

data output of the target channel.

register.

Writing to the SSm register and set the SEmn bit to 1 (to enable
operation).
Completing initial setting Set transmit data to the SDRmn[7:0] bits
(TXDq register) (8 bits) or the SDRmn[8:0]
bits (9 bits) and start communication.
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Figure 18-79. Procedure for Stopping UART Transmission

Yes
the target channel.

clock supply to it.

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Figure 18-80. Procedure for Resuming UART Transmission
Completing master No Wait until stop the communication target

(Essential) preparations?
or communication operation completed
Yes
Disable data output of the target channel
(Selective) Port manipulation
by setting a port register and a port mode
register.


clock (fMCK)).
Re-set the register to change the serial

(Selective) Changing setting of the SCRmn register
communication operation setting register
mn (SCRmn) setting.

(Selective) Changing setting of the SOLm register
output level register m (SOLm) setting.
(Selective) Changing setting of the SOEm register Clear the SOEmn bit to “0” and stop
output.

data (SOmn).

(Essential) Changing setting of the SOEm register
output.

register.
Set the SSmn bit of the target channel to “1” and

set the SEmn bit to “1” (to enable operation).
Setting is completed.
Set transmit data to the SDRmn[7:0] bits
(TXDq register) (8 bits) or the SDRmn[8:0] bits
(9 bits) and start communication.
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the
transmission target stops or transmission finishes, and then perform initialization instead of restarting the
transmission.
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Figure 18-81. Timing Chart of UART Transmission (in Single-Transmission Mode)
SSmn
STmn
SEmn
TxDq pin ST Transmit data 1 P SP ST Transmit data 2 P SP ST Transmit data 3 P SP

Shift
register mn
INTSTq

TSFmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)

mn = 00, 02, 10, 12
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Figure 18-82. Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication

SAU default setting
Setting transmit data (Storage area, transmission data pointer, number of communication data and
Main routine
communication end flag are optionally set on the internal RAM by the software)
Enables interrupt
SDRmn[7:0] bits (TXDq to TXDq. Update transmit data pointer.
register) (8 bits) or the Communication starts by writing
SDRmn[8:0] bits (9 bits)
to SDRmn[7:0]

When Transfer end interrupt is generated, it
No Read transmit data, if any, from storage area and

Transmitting next data? write it to TXDq. Update transmit data pointer.
If not, set transmit end flag
Yes
Sets communication
Writing transmit data to completion flag
SDRmn[7:0] bits (TXDq
register) (8 bits) or the
RETI
Main routine

Yes
Write STmn bit to 1
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Figure 18-83. Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSmn <1>
STmn <6>
SEmn
TxDq pin ST Transmit data 1 P SP ST Transmit data 2 P SP ST Transmit data 3 P SP

Shift
register mn
INTSTq

MDmn0 <4>
TSFmn
BFFmn
<2><3> <2> <3> <2> <3> <5>

Note
Caution The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)

mn = 00, 02, 10, 12
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Figure 18-84. Flowchart of UART Transmission (in Continuous Transmission Mode)
Starting UART
communication

<1> SAU default setting (Select buffer empty interrupt)
Main routine
Enables interrupt

<2> SDRmn[7:0] bits (TXDq Read transmit data from storage area and write it
register) (8 bits) or the to TXDq. Update transmit data pointer.
SDRmn[8:0] bits (9 bits) Transmission starts by writing to
the SDRmn[7:0] bits (TXDq
SDRmn[8:0] bits (9 bits).

interrupt processing routine.
<3>

If transmit data is left, read them from storage area then

write into TxDq, and update transmit data pointer and
No
Number of number of transmit data.
communication data > 0? If no more transmit data, clear MDmn bit if it’s set. If
not, finish.
Yes
Writing transmit data to No

<2> SDRmn[7:0] bits (TXDq MDmn = 1?
Yes <5>
<4>
Sets communication
Clear MDmn0 bit to 0
transmit data completion interrupt flag
RETI

Yes
Write MDmn0 bit to 1
Main routine
Yes
Communication
continued?
No
<6> Write STmn bit to 1
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 18-83 Timing Chart of UART
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18.6.2 UART reception

UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device
(start-stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
Target channel Channel 1 of SAU0 Channel 3 of SAU0 Channel 1 of SAU1 Channel 3 of SAU1
Pins used RxD0 RxD1 RxD2 RxD3
Interrupt INTSR0 INTSR1 INTSR2 INTSR3
Error interrupt INTSRE0 INTSRE1 INTSRE2 INTSRE3
Error detection ● Framing error detection flag (FEFmn)

flag ● Parity error detection flag (PEFmn)
● Overrun error detection flag (OVFmn)
Transfer data 7, 8 or 9 bitsNote 1
length
Transfer rate Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or more), Min. fCLK/(2 × 215 × 128) [bps]Note 2

Parity bit The following selectable

● No parity bit (no parity check)
● No parity judgment (0 parity)
● Even parity check
● Odd parity check
Stop bit Appending 1 bit

2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13
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Figure 18-85. Example of Contents of Registers for UART Reception of UART


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 1 0 0/1 1 0 0 0 1 0
0: Normal reception
Operation clock (fMCK) of channel n Operation mode of channel n
0: Prescaler output clock CKm0 1: Reverse reception 0: Transfer end interrupt
set by the SPSm register
1: Prescaler output clock CKm1
set by the SPSm register
(b) Serial mode register mr (SMRmr)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmr CKSmr CCSmr MDmr2 MDmr1 MDmr0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0/1
Same setting value as CKSmn bit Operation mode of channel r

0: Transfer end interrupt
1: Buffer empty interrupt
(c) Serial communication operation setting register mn (SCRmn)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLSmn1
SCRmn TXEmn RXEmn DAPmn CKPmn EOCmn PTCmn1 PTCmn0 DIRmn SLCmn1 SLCmn0 DLSmn0
0 0 0 1 0/1
0 1 0 0 0/1 0/1 0/1 0/1 0 1 Note 1 0/1
Setting of parity bit

00B: No parity check Selection of data transfer sequence Setting of data length
0: Inputs/outputs data with MSB first
01B: No parity judgment
1: Inputs/outputs data with LSB first.
10B: Even parity check
11B: Odd parity check
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting 0 Note Receive data register
2
RXDq
Notes 1. Only provided for the SCR00 and SCR01 registers. This bit is fixed to 1 for the other registers.
2. When UART performs 9-bit communication, bits 0 to 8 of the SDRm1 register are used as the
transmission data specification area. Only UART0 can be specified for the 9-bit data length.
Caution For the UART reception, be sure to set the SMRmr register of channel r to UART transmission
mode that is to be paired with channel n.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13
r: Channel number (r = n – 1), q: UART number (q = 0 to 3)
2. : Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value)
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Figure 18-85. Example of Contents of Registers for UART Reception of UART

(e) Serial output register m (SOm) … The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKOm2 CKOm0 SOm2 SOm0
SOm
0 0 0 0 1 × 1 × 0 0 0 0 1 × 1 ×
(f) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 × 0 ×
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0/1 × 0/1 ×
Caution For the UART reception, be sure to set the SMRmr register of channel r to UART Transmission
mode that is to be paired with channel n.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13
2. : Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value)
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Figure 18-86. Initial Setting Procedure for UART Reception

Set an operation mode, etc.

Setting the SMRmn and SMRmr registers
Set a communication format.

Setting the SCRmn register

clock (fMCK)).
Enable data input of the target channel
Setting port by setting a port register and a port
mode register.
Writing to the SSm register Set the SSmn bit of the target channel to “1”
and set the SEmn bit to “1” (to enable
operation). Become wait for start bit detection.
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more fMCK
clocks have elapsed.
Figure 18-87. Procedure for Stopping UART Reception

Yes
clock supply to it.

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Figure 18-88. Procedure for Resuming UART Reception
No Stop the target for communication or wait

Completing master
(Essential) until completes its communication
preparations?
operation.
Yes
(Selective) Changing setting of the SPSm register clock setting.

(Selective) Changing setting of the SDRmn
baud rate setting (setting the transfer clock
by dividing the operation clock (fMCK)).
Changing setting of the SMRmn Re-set the registers to change serial mode
(Selective) registers mn, mr (SMRmn, SMRmr)
and SMRmr registers
setting.
(Selective) Re-set the register to change serial

Changing setting of the SCRmn register
communication operation setting register
mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain

(Selective) Clearing error flag set, clear them using serial flag clear
trigger register mn (SIRmn).
Enable data input of the target channel

(Essential) Setting port
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to “1” and

set the SEmn bit to “1” (to enable operation).
Become wait for start bit detection.
Caution After is set RXEmn bit to 1 of SCRmn register, set the SSmn = 1 from an interval of at least
four clocks of fMCK.
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(3) Processing flow
Figure 18-89. Timing Chart of UART Reception
SSmn
STmn
SEmn
Receive data 3
SDRmn Receive data 1 Receive data 2
RxDq pin ST Receive data 1 P SP ST Receive data 2 P SP ST Receive data 3 P SP

Shift Shift operation Shift operation Shift operation
register mn
INTSRq

TSFmn
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Figure 18-90. Flowchart of UART Reception
Starting UART communication

(setting to mask for error interrupt)
SAU default setting
Setting storage area of the receive data, number of communication

Setting receive data data (storage area, reception data pointer, number of communication
data and communication end flag are optionally set on the internal
RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask
Enables interrupt
(XXMK) and set

Starting reception if start bit is
detected
When receive complete, transfer end
interrupt is generated,
Reading receive data from Read receive data then writes to storage area.
the SDRmn[7:0] bits
Update receive data pointer and number of
(RXDq register) (8 bits) or
communication data.
the SDRmn[8:0] bits (9 bits)
No
Indicating normal reception?
Yes
RETI
Error processing
No
Reception completed? Check the number of communication data,
Yes determine the completion of reception
Disable interrupt (mask)
Writing 1 to the STmn bit
End of UART
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18.6.3 SNOOZE mode function

The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP
mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the
UART to perform reception operations without CPU operation. Only UART0 can be set to the SNOOZE mode.
When using UARTq in the SNOOZE mode, make the following settings before entering the STOP mode. (See Figure
18-93 and Figure 18-95 Flowchart of SNOOZE Mode Operation.)
● In the SNOOZE mode, the baud rate setting for UART reception needs to be changed to a value different from that in
normal operation. Set the SPSm register and bits 15 to 9 of the SDRmn register with reference to Table 18-3.
● Set the EOCmn and SSECmn bits. This is for enabling or stopping generation of an error interrupt (INTSRE0) when
a communication error occurs.
● When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just
before switching to the STOP mode. After the initial setting has completed, set the SSm1 bit of serial channel start
register m (SSm) to 1.
● Upon detecting the start bit input of RxDq after a transition was made to the STOP mode, UARTq reception is started.
Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected
for fCLK.
2. The maximum transfer rate when using UARTq in the SNOOZE mode is 4800 bps.
3. When SWCm = 1, UARTq can be used only when the reception operation is started in the STOP
mode. When used simultaneously with another SNOOZE mode function or interrupt, if the
reception operation is started in a state other than the STOP mode, such as those given below,
data may not be received correctly and a framing error or parity error may be generated.
● When after the SWCm bit has been set to 1, the reception operation is started before the
STOP mode is entered
● When the reception operation is started while another function is in the SNOOZE mode
● When after returning from the STOP mode to normal operation due to an interrupt or other
cause, the reception operation is started before the SWCm bit is returned to 0
4. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFmn,
FEFmn, or OVFmn flag is not set and an error interrupt (INTSREq) is not generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFmn, FEFmn, or OVFmn flag before setting
the SWC0 bit to 1 and read the value in bits 7 to 0 (RxDq register) of the SDRm1 register.
5. The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq
signal. Note, however, that the UART reception may not start and the CPU may remain in the
SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a start bit.
In such cases, data may not be received correctly, and this may lead to a framing error or parity
error in the next UART reception.
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Table 18-3. Baud Rate Setting for UART Reception in SNOOZE Mode
High-speed On-chip Baud Rate for UART Reception in SNOOZE Mode

Oscillator (fIH)
Baud Rate of 4800 bps
Operation Clock (fMCK) SDRmn[15:9] Maximum Permissible Minimum Permissible

Value Value
Note 5
24 MHz ± 1.0% fCLK/2 79 1.60% -2.18%
Note 4
16 MHz ± 1.0% fCLK/2 105 2.27% -1.53%
Note 4
12 MHz ± 1.0% fCLK/2 79 1.60% -2.19%
8 MHz ± 1.0% Note fCLK/23 105 2.27% -1.53%
6 MHz ± 1.0% Note fCLK/23 79 1.60% -2.19%
4 MHz ± 1.0% Note fCLK/22 105 2.27% -1.53%

Note 2
3 MHz ± 1.0% fCLK/2 79 1.60% -2.19%
Note
2 MHz ± 1.0% fCLK/2 105 2.27% -1.54%
Note
1 MHz ± 1.0% fCLK 105 2.27% -1.57%
Note When the accuracy of the clock frequency of the high-speed on-chip oscillator is ±1.5%, the permissible range
becomes smaller as shown below.
● In the case of fIH ± 1.5%, perform (Maximum permissible value – 0.5%) and (Minimum permissible value +
0.5%) to the values in the above table.
Remark The maximum permissible value and minimum permissible value are permissible values for the baud rate in
UART reception. The baud rate on the transmitting side should be set to fall inside this range.
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(1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1)

Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is
not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated.
Figure 18-91. Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1)
<4>
SS01 <3> <12>
ST01 <1> <10>
SE01
SWC0
<11>
EOC01 L
SSEC0 L
(internal signal)
Receive data 2
SDR01 Receive data 1
<9> Read Note
RxD0 pin ST Receive data 1 P SP ST Receive data 2 P SP
Shift
register 01 Shift operation Shift operation
INTSRq
Data reception <7> Data reception
INTSREq L
TSF01
<2> <5><6> <8>
Note Read the received data when SWCm is 1.
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release).
Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).
2. m = 0; q = 0
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(2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled)
Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error
occurs.
Figure 18-92. Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0)
<4>
SS01 <3> <12>
ST01 <1> <10>
SE01
SWC0 <11>
EOC01
SSEC0 L

(internal signal) Receive data 2
<9> Read Note
Shift
register 01 Shift operation Shift operation
INTSRq
Data reception <7> Data reception

INTSREq L
TSF01
<2> <5> <6> <8>
Note Read the received data when SWCm is 1.
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release).
Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).
2. m = 0; q = 0
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Figure 18-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0)
S e tting sta rt
Do es TS F mn = 0 on a ll No
cha nn els?
Yes
<1 > W riting 1 to the ST mn b it T h e op e ra tion o f all cha nn els is a ls o sto pp ed to sw itch to the
→ S E mn = 0 STOP m ode .
Normal operation
C h anne l 1 is s pec ified fo r U A RT re ce ption .

S A U defau lt s e tting
C h ange to th e UA R T rec ep tio n b au d rate in S N OO Z E mo de
(S P S m reg iste r a nd bits 15 to 9 in S DR m 1 re giste r).
<2 > S e tting SS Cm reg iste r
S N OOZE m od e se tting
(S W C m = 1 )
<3 > W riting 1 to the S S m n bit C ommu nica tio n w ait s ta tus
→ S E m1 = 1
C le ar in te rrupt re qu es t flag (XX IF ), res e t inte rrupt m ask (X XM K )

E n ab le in te rru p t
a n d se t inte rrupt en ab le (IE ).
<4 > E n tered th e S T O P mo de f CLK su pp lied to the SA U is s to pp ed .

STOP mode
Effective edge of RxDq pin

<5 > Rdetected
xD q edge detected
(Enteredthe
(Entered theSN
SNOOZE
OO ZE mmode)
ode)
SNOOZE mode
<6 > C lock

Start bitsupply
input of RxDq pin
(UART rece ive opera tion)
detected
(UARTq reception operation)
operation)
<7 >
Transfer end interrupt (IN TSR q) or
<8 >
error interrupt (IN TSR Eq) gene rated
IN TS R Eq IN T S R q
R e ad ing rec eive da ta fro m <9> R e ad ing rece ive da ta fro m

T h e m ode sw itch es fro m S N O O Z E to no rm al
the S D Rmn [7 :0 ] b its (RX Dq th e S D R m n [7 :0 ] b its (RX D q
regis te r) (8 b its ) o r the re gister) (8 b its ) o r the op era tion .
S DR m n [8:0 ] bits (9 bits ) S D R m n [8:0 ] bits (9 bits )
Normal operation
W ritin g 1 to th e ST m 1 b it < 1 0> W riting 1 to the ST m 1 b it To o pe ra tion stop sta tus (S Em1 = 0)
C le ar the S W C m b it t o 0 < 1 1> C le ar the S W Cm b it t o 0 Re se t SN OOZE m od e se tting .
E rro r p roce ss in g
C h an ge to the UA R T C han ge to th e UA R T Se t th e SPS m registe r an d b its 1 5 to 9 in the

re ce ption b aud ra te in re ce pti on b au d ra te in S D R m 1 re g is te r.
n o rm al o pe ra tion n o rm al o pe ra tion
W ritin g 1 t o t he S S m n b it < 1 2> W riting 1 t o the S S mn b it T o comm un icatio n w a it s ta tus (S E mn = 1 )
N o rm a l op e ra tio n No rm a l op e ra tio n
Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 18-92 Timing Chart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 0).
2. m = 0; q = 0
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(3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped)
Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error
occurs.
Figure 18-94. Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
Normal operation
CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode
<4>
SS01 <3>
ST01 <1> <10>
SE01
SWC0 <11>
EOC01
<11>
SSEC0

(internal signal)
Receive data 2
Read Note <9>

Shift
Shift operation Shift operation
register 01
INTSRq
INTSREq L
TSF01
<2> <5> <6> <7> <5> <6> <7>, <11>

<8>
Note Read the received data when SWCm = 1.
finishes, set the STm1 bit to 1 (clear the SEm1 bit and stop the operation).
After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
2. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the
PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated.
Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag
before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or
SDRm1[8:0] (9 bits).
Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0
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Figure 18-95. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
Setting start
Does TSFmn = 0 on all No

channels?
Yes
SIRm1 = 0007H Clear the all error flags
<1> Writing 1 to the STmn bit The operation of all channels is also stopped to switch to
the STOP mode.
Normal operation
→ SEmn = 0
Channel 1 is specified for UART reception.
Change to the UART reception baud rate in SNOOZE mode
SAU default setting (SPSm register and bits 15 to 9 in SDRm1 register).
EOCm1: Make the setting to enable generation of error interrupt INTSREq.
<2> Setting SSCm register SNOOZE mode setting (make the setting to enable genera tion
(SWCm = 1, SSECm = 1) of error interrupt INTSREq in SNOOZE mode) .
Writing 1 to the SSmn bit Communication wait status

<3>
→ SEmn = 1
Setting interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt disable (DI).
<4> fCLK supplied to the SAU is stopped.

Entered the STOP mode
STOP
SNOOZE mode mode
Effective edge of RxDq pin detected

<5> RxDq edge detected
<6> (Entered the SNOOZE mode)
Start bitsupply
Clock input of RxDq pin detected
(UART receive
(UARTq operation)
reception operation)
<7>
Reception error detected
STOP mode
If an error occurs, because the CPU switches to

the STOP mode again, the error flag is not set.
Effective
RxDq edge of RxDq pin detected
edge detected
(Entered
(Entered thethe SNOOZE
SNOOZE mode)
mode)
SNOOZE mode
Clockbit
Start supply
input of RxDq pin detected
(UART receive operation)
(UARTq reception operation)
<7>
<8> Transfer end interrupt (INTSRq) generated
INTSRq
<9> Reading receive data from

the SDRmn[7:0] bits (RXDq The mode switches from SNOOZE to normal operation.
Normal operation
To operation stop status (SEm1 = 0)

<10> Writing 1 to the STm1 bit
Reset SNOOZE mode setting

<11> Setting SSCm register
Change to the UART Set the SPSm register and bits 15 to 9 in the SDRm1
reception baud rate in
register.
normal operation
Writing 1 to the SSmn bit

To communication wait status (SEmn = 1)
Normal operation
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(Caution and Remarks are listed on the next page.)
Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1,
FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting
the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9
bits).
Mode Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0
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18.6.4 Calculating baud rate
(1) Baud rate calculation expression

The baud rate for UART (UART0 to UART3) communication can be calculated by the following expressions.
(Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps]
Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
Remarks 1. When UART is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register
(0000010B to 1111111B) and therefore is 2 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 18-4. Selection of Operation Clock For UART

Register
m13 m12 m11 m10 m03 m02 m01 m00
0 X X X X 0 0 0 0 fCLK 24 MHz
X X X X 0 0 0 1 fCLK/2 12 MHz
2
X X X X 0 0 1 0 fCLK/2 6 MHz
X X X X 0 0 1 1 fCLK/23 3 MHz
4
X X X X 0 1 0 0 fCLK/2 1.5 MHz
X X X X 0 1 0 1 fCLK/25 750 kHz
6
X X X X 0 1 1 0 fCLK/2 375 kHz
X X X X 0 1 1 1 fCLK/27 187.5 kHz
8
X X X X 1 0 0 0 fCLK/2 93.8 kHz
X X X X 1 0 0 1 fCLK/29 46.9 kHz
X X X X 1 0 1 0 fCLK/210 23.4 kHz
X X X X 1 0 1 1 fCLK/211 11.7 kHz
X X X X 1 1 0 0 fCLK/212 5.86 kHz
13
X X X X 1 1 0 1 fCLK/2 2.93 kHz
X X X X 1 1 1 0 fCLK/214 1.46 kHz
15
X X X X 1 1 1 1 fCLK/2 732 Hz
1 0 0 0 0 X X X X fCLK 24 MHz
0 0 0 1 X X X X fCLK/2 12 MHz
0 0 1 0 X X X X fCLK/22 6 MHz
0 0 1 1 X X X X fCLK/23 3 MHz
0 1 0 0 X X X X fCLK/24 1.5 MHz
0 1 0 1 X X X X fCLK/25 750 kHz
6
0 1 1 0 X X X X fCLK/2 375 kHz
0 1 1 1 X X X X fCLK/27 187.5 kHz
8
1 0 0 0 X X X X fCLK/2 93.8 kHz
1 0 0 1 X X X X fCLK/29 46.9 kHz
10
1 0 1 0 X X X X fCLK/2 23.4 kHz
1 0 1 1 X X X X fCLK/211 11.7 kHz
1 1 0 0 X X X X fCLK/212 5.86 kHz
13
1 1 0 1 X X X X fCLK/2 2.93 kHz
1 1 1 0 X X X X fCLK/214 1.46 kHz
15
1 1 1 1 X X X X fCLK/2 732 Hz
unit (SAU).

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(2) Baud rate error during transmission

The baud rate error of UART (UART0 to UART3) communication during transmission can be calculated by the
following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate
range at the reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 – 100 [%]
Here is an example of setting a UART baud rate at fCLK = 24 MHz.
UART Baud Rate fCLK = 24 MHz

(Target Baud Rate)
Operation Clock (fMCK) SDRmn[15:9] Calculated Baud Rate Error from Target Baud Rate
9
300 bps fCLK/2 77 300.48 bps +0.16%
8
600 bps fCLK/2 77 600.96 bps +0.16%
1200 bps fCLK/27 77 1201.92 bps +0.16%
2400 bps fCLK/26 77 2403.85 bps +0.16%
4800 bps fCLK/25 77 4807.69 bps +0.16%

4
9600 bps fCLK/2 77 9615.38 bps +0.16%
3
19200 bps fCLK/2 77 19230.8 bps +0.16%
3
31250 bps fCLK/2 47 31250.0 bps ±0.0%
2
38400 bps fCLK/2 77 38461.5 bps +0.16%
76800 bps fCLK/2 77 76923.1 bps +0.16%
153600 bps fCLK 77 153846 bps +0.16%
312500 bps fCLK 37 315789 bps +1.05%
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(3) Permissible baud rate range for reception

The permissible baud rate range for reception during UART (UART0 to UART3) communication can be calculated
by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud
rate range at the reception side.
2 × k × Nfr
(Maximum receivable baud rate) = × Brate
2 × k × Nfr – k + 2
2 × k × (Nfr – 1)
(Minimum receivable baud rate) = × Brate
2 × k × Nfr – k – 2
Brate: Calculated baud rate value at the reception side (See 18.6.4 (1) Baud rate calculation expression.)
k: SDRmn[15:9] + 1
Nfr: 1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Figure 18-96. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Latch
timing
Data frame length Start Parity Stop

Bit 0 Bit 1 Bit 7
of SAU bit bit bit
FL
1 data frame (11 × FL)
Permissible minimum Start Parity Stop

Bit 0 Bit 1 Bit 7
data frame length bit bit bit
(11 × FL) min.
Permissible maximum Start Parity Stop

Bit 0 Bit 1 Bit 7
data frame length bit bit bit
(11 × FL) max.
As shown in Figure 18-96, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
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18.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication
The procedure for processing errors that occurred during UART (UART0 to UART3) communication is described in
Figures 18-97 and 18-98.
Figure 18-97. Processing Procedure in Case of Parity Error or Overrun Error
Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the
is set to 0 and channel n is enabled to next reception is completed during error
(SDRmn).
Writes 1 to serial flag clear trigger Error flag is cleared. Error can be cleared only during
register mn (SIRmn). reading, by writing the value read from
Figure 18-98. Processing Procedure in Case of Framing Error
Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the
is set to 0 and channel n is enabled to next reception is completed during error
(SDRmn).
Writes serial flag clear trigger register mn Error flag is cleared. Error can be cleared only during
(SIRmn). reading, by writing the value read from
Sets the STmn bit of serial channel stop The SEmn bit of serial channel enable
register m (STm) to 1. status register m (SEm) is set to 0 and
channel n stops operating.
Synchronization with other party of Synchronization with the other party of

communication communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets the SSmn bit of serial channel start The SEmn bit of serial channel enable
register m (SSm) to 1. status register m (SEm) is set to 1 and
channel n is enabled to operate.
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18.7 LIN Communication Operation
18.7.1 LIN transmission

Of UART transmission, UART0 support LIN communication.
For LIN transmission, channel 0 of unit 0 is used.
Support of LIN Supported Not supported Not supported Not supported

communication
Target channel Channel 0 of SAU0 – – –
Pins used TxD0 – – –
Interrupt INTST0 – – –
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can
be selected.
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR00[15:9] = 2 or more), Min. fCLK/(2 × 215 × 128) [bps]Note

Parity bit No parity bit
Stop bit Appending 1 bit
Data direction LSB first
the electrical specifications (see CHAPTER 41 ELECTRICAL SPECIFICATIONS). In addition, LIN
communication is usually 2.4/9.6/19.2 kbps is often used.
Remark fMCK: Operation clock frequency of target channel

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LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to
reduce the cost of an automobile network.
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave receives
this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%, communication
can be established.
Figure 18-99 outlines a master transmission operation of LIN.
<R> Figure 18-99. Transmission Operation of LIN
Wakeup signal Break field Sync field Protected Data field Data field Checksum
frame Identifier field
field
LIN Bus
13-bit length
Break 55H PID Data Data Checksum
8-bit lengthNote 1 transmissionNote 2 transmission transmission transmission transmission transmission
TxD0
(output)
Delimiter
transmission
INTST0Note 3
Notes 1. Set the baud rate in accordance with the wakeup signal regulations and transmit data of 80H.
2. A break field is defined to have a width of 13 bits and output a low level. Where the baud rate for main
transfer is N [bps], therefore, the baud rate of the break field is calculated as follows.
(Baud rate of break field) = 9/13 × N
By transmitting data of 00H at this baud rate, a break field is generated.
3. INTST0 is output upon completion of transmission. INTST0 is also output at BF transmission.
Remark The interval between fields is controlled by software.
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<R> Figure 18-100. Flowchart for LIN Transmission
Starting LIN Operation of the hardware (Reference)

communication
Transmitting wakeup signal frame

(80H  TXD0)
No Wakeup signal frame generation

TSF10 = 0? Transmitting wakeup 8-bit length
signal frame Note TxD0
Yes
UART0 stop Waiting for completion 80H
(1  ST10 bit) of transmission
Changing UART0 baud rate Changing baud rate

(zz  SDR [15:9]) for BF
UART0 restart
(1  SS10 bit)
BF transmission
00  TXD0
BF generation
Waiting for
No
completion of BF 13-bit length
TxD0
TSF10 = 0? transmission
Yes
000H
UART0 stop
(1  ST10 bit)
Changing UART0 baud rate Return the baud rate

(xx  SDR[15:9])
UART0 restart
(1  SS10 bit)
Transmitting sync field Transmitting Sync field data generation

55H  TXD0 sync field
No Waiting for buffer TxD0

BFF10 = 0? empty
Yes 55H
Transmitting PID to
Data  TXD0 checksum
No Waiting for buffer empty

BFF10 = 0?
Yes
No
Completing all data
Waiting for transmission PID to checksum
transmission?
Yes
No
Waiting for completion of transmission
TSF10 = 0? (transmission completed to the LIN bus)
Yes
End of LIN
communication
Note When LIN-bus start from sleep status only
Remark Default setting of the UART is complete, and the flow from the transmission enable status.
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18.7.2 LIN reception

Of UART reception, UART0 support LIN communication.
For LIN reception, channel 1 of unit 0 is used.
Support of LIN communication Supported Not supported Not supported Not supported
Target channel Channel 1 of SAU0 – – –
Pins used RxD0 – – –
Interrupt INTSR0 – – –
Error interrupt INTSRE0 – – –
Error detection flag ● Framing error detection flag (FEF01)

● Overrun error detection flag (OVF01)
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR01[15:9] = 2 or more), Min. fCLK/(2 × 215 × 128) [bps]Note

Parity bit No parity bit (The parity bit is not checked.)
Stop bit Check the first bit
Data direction LSB first
Remark fMCK: Operation clock frequency of target channel

Figure 18-101 outlines a reception operation of LIN.
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<R> Figure 18-101. Reception Operation of LIN
Protected
Wakeup signal Checksum
Break field Sync field identifier Data field Data field
frame field
field
LIN Bus
Header Response
Break 55H PID Data Data Checksum
reception reception reception reception reception reception
<2> <5>
RxD0
UART0 STOP Reception
INTSR0
<1>
Edge detection
(INTP0)
<3> <4>
Pulse interval
TM07 STOP Pulse width measurement
measurement
INTTM07
Here is the flow of signal processing.
<1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
detected, change TM07 to pulse width measurement upon detection of the wakeup signal to measure the low-
level width of the BF signal. Then wait for BF signal reception.
<2> TM07 starts measuring the low-level width upon detection of the falling edge of the BF signal, and then captures
the data upon detection of the rising edge of the BF signal. The captured data is used to judge whether it is the
BF signal.
<3> When the BF signal has been received normally, change TM07 to pulse interval measurement and measure the
interval between the falling edges of the RxD0 signal in the Sync field four times.
<4> When BF reception has been correctly completed, start channel 7 of the timer array unit and measure the bit
interval (pulse width) of the sync field (see 8.8.3 Operation as input pulse interval measurement).
<5> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART0 once and adjust (re-set) the baud
rate.
<6> The checksum field should be distinguished by software. In addition, processing to initialize UART0 after the
checksum field is received and to wait for reception of BF should also be performed by software.
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<R> Figure 18-102. Flowchart for LIN Reception
Status of LIN bus signal and operation

Starting LIN communication
of the hardware
Wakeup signal frame

No Wait for wakeup frame
Generate INTP0? RxD0 pin
signalNote
Yes Edge detection
The low-level width INTP0
Starting in low-level width of RxD0 is
measurement mode for TM07 measured using
TM07 and BF is
detected. Break field
No
Generate INTTM07?
If the detected RxD0 pin
Yes pulse width is 11 Channel 7 Pulse width
No bits or more, it is of TAU0 measurement
11 bit lengths or more? judged as BF. INTTM07 Channel 7
Yes
Changing TM07 to pulse width Set up TM07 to measure the
measurement interval between the falling edges.
Ignore the first INTTM07.
No
Generate INTTM07?
Yes Sync field
RxD0 pin
No Measure the intervals
Generate INTTM07? between five falling Channel 7 Pulse interval
edges of SF, and of TAU0 measurement
Yes INTTM07
accumulate the four
Capture value cumulative captured values.
No Cumulative four
Completed 4 times? times
Yes
Changing TM07 to low-level Change TM07 to low-level width measurement
width measurement to detect a Sync break field.
Divide the accumulated value by 8 to obtain the bit

Calculate the baud rate width. Use this value to determine the setting values
of SPS0, SDR00, and SDR01.
UART0 default setting L Set up the initial setting of UART0 according
to the LIN communication conditions.
Starting UART0 reception
(1  SS01)
Receive the PID, data, and checksum fields (if the

Data reception PID matches).
No
Completing all data
transmission?
Yes
Stop UART0 reception
(1  ST01)
End of LIN communication
Note Required in the sleep status only.
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Figure 18-103 shows the configuration of a port that manipulates reception of LIN.
The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0).
The length of the sync field transmitted from the master can be measured by using the external event capture operation of
the timer array unit 0 to calculate a baud-rate error.
By controlling switch of port input (ISC0), the input source of port input (RxD0) for reception can be input to the external
interrupt pin (INTP0) and timer array unit
Figure 18-103. Port Configuration for Manipulating Reception of LIN
[64-pin]
P06/SI00/RxD0/TI03/TO03/
SDA00/TOOLRxD/SEG36
[80-pin]
SDA00/TOOLRxD/SEG36 Selector Selector
[100-pin]
SDA00/TOOLRxD RXD0 input
[100-pin, 80-pin]
P16/SEG10/(SI00)/
(RxD0)/(SDA00)
[64-pin]
P16/SEG10/INTP7/
(SI00)/(RxD0)/(SDA00)
PIOR01 Port mode
(PM06 or PM16)
Output latch
(P06 or P16)
Selector
Selector
P137/INTP0
INTP0 input
P70/SEG16/(INTP0)
Port input
PIOR04 switch control
[64-pin]
P30/TI07/TO07/INTP5/ (ISC0)
RXD2/IrRXD/SEG24 <ISC0>
[80-pin] 0: Selects INTP0 (P137 or P70)
P02/SCK10/SCL10/TI07/ 1: Selects RxD0 (P06 or P16)
TO07/INTP5/SEG32 Selector Selector
[100-pin] Selector
P02/SCK10/SCL10/
TI07/TO07/INTP5
Channel 7 input of
P30/SEG24/(TI07)/(TO07) timer array unit
PIOR00 Port mode

(PM02 or PM30) Selection of timer input used
with channel 7 of the timer
array unit (TIS07, TIS06)
Output latch <TIS07, TIS06>
(P02 or P30) 00: Selects TI07 (P02 or P30)
01: Selects RTCOUT (P62 or P150)
10: Selects RXD0 (P06 or P16)
11: Selects an event input signal from ELC
Remarks 1. ISC0: Bit 0 of the input switch control register (ISC) (See Figure 18-21.)
PIOR00, PIOR01, PIOR04: Bits 0 to 4 of the peripheral I/O redirection register (PIOR0)
(See Figure 4-8.)
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The peripheral functions used for the LIN communication operation are as follows.
<Peripheral functions used>

● External interrupt (INTP0); Wakeup signal detection
Usage: To detect an edge of the wakeup signal and the start of communication
● Channel 7 of timer array unit; Baud rate error detection, break field detection.
Usage: To detect the length of the sync field (SF) and divide it by the number of bits in order to detect an error (The
interval of the edge input to RxD0 is measured in the capture mode.)
Measured the low-level width, determine whether break field (BF).
● Channels 0 and 1 (UART0) of serial array unit 0 (SAU0)
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18.8 Operation of Simplified I2C (IIC00, IIC10, IIC30) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such
as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master.
Operate the control registers by software for setting the start and stop conditions while observing the specifications of
the I2C bus line
● Master transmission, master reception (only master function with a single master)
● ACK output functionNote and ACK detection function
● Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
● Generation of start condition and stop condition for software
● Transfer end interrupt
● Parity error (ACK error)
* [Functions not supported by simplified I2C]

● Slave transmission, slave reception
● Multi-master function (arbitration loss detection function)
● Wait detection function
Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn (SOEm register) bit and serial
communication data output is stopped. See the processing flow in 18.8.3 (2) for details.
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The channels supporting simplified I2C (IIC00, IIC10, IIC30) are channels 0 and 2 of SAU0 and channel 2 of SAU1.

(supporting LIN-bus)
1 – –
2 CSI10 UART1 IIC10
3 – –
1 0 – UART2 –
2 CSI30 Note UART3 Note IIC30 Note
3 – –
Simplified I2C (IIC00, IIC10, IIC30) performs the following four types of communication operations.
● Address field transmission (See 18.8.1.)

● Data transmission (See 18.8.2.)
● Data reception (See 18.8.3.)
● Stop condition generation (See 18.8.4.)
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18.8.1 Address field transmission

Address field transmission is a transmission operation that first executes in I2C communication to identify the target for
transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in
one frame.
Simplified I2C IIC00 IIC10 IIC30
Pins used SCL00, SDA00Note 1 SCL10, SDA10Note 1 SCL30, SDA30Note 1
Interrupt INTIIC00 INTIIC10 INTIIC30
Error detection flag ACK error detection flag (PEFmn)
Transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W control)
Note 2
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel
However, the following condition must be satisfied in each mode of I2C.
● Max. 1 MHz (fast mode plus)
● Max. 400 kHz (fast mode)
● Max. 100 kHz (standard mode)
Data level Non-reversed output (default: high level)
Stop bit Appending 1 bit (for ACK reception timing)
Data direction MSB first
Notes 1. To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode for the
port output mode register (POM0) (see 4.3.5 Port output mode registers (POMxx) for details). When
IIC00, IIC10, IIC30 communicating with an external device with a different potential, set the N-ch open-drain
output (VDD tolerance) mode also for the clock input/output pins (SCL00, SCL10) (see 4.4.4 Connecting to
external device with different potential (1.8 V, 2.5 V, 3 V) for details).
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Figure 18-104. Example of Contents of Registers for Address Field Transmission of Simplified I2C
(IIC00, IIC10, IIC30) (1/2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
Operation clock (fMCK) of channel n Operation mode of channel n

1: Prescaler output clock CKm1 set by the SPSm register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
Setting of parity bit Setting of stop bit
00B: No parity 01B: Appending 1 bit (ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting Transmit data setting (address + R/W)
0
SIOr
(d) Serial output register m (SOm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1 1 0/1 0 0 0 0 1 0/1 1 0/1
Start condition is generated by manipulating the SOmn bit.
(e) Serial output enable register m (SOEm)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30), mn = 00, 02,
12
2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
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Figure 18-104. Example of Contents of Registers for Address Field Transmission of Simplified I2C
(IIC00, IIC10, IIC30) (2/2)
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
SSmn = 0 until the start condition is generated, and SSmn = 1
after generation.
12
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Figure 18-105. Initial Setting Procedure for Simplified I2C


clock (fMCK)).
Set the initial output level (1) of the serial

data (SOmn) and serial clock (CKOmn).
Enable data output, clock output, and N-ch open-

drain output (VDD tolerance) mode of the target
Setting port channel by setting the port register, port mode
register, and port output mode register.
Starting communication
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(3) Processing flow
Figure 18-106. Timing Chart of Address Field Transmission
SSmn
SEmn
SOEmn
SDRmn Address field transmission
SCLr output
CKOmn
bit manipulation
SDAr output D7 D6 D5 D4 D3 D2 D1 D0
SOmn bit manipulation
R/W
Address
SDAr input D7 D6 D5 D4 D3 D2 D1 D0 ACK
Shift
Shift operation
register mn
INTIICr
TSFmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30), mn = 00, 02,
12
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Figure 18-107. Flowchart of Simplified I2C Address Field Transmission
Transmitting address field
Default setting For the initial setting, see Figure 18-105.
Writing 0 to the SOmn bit Setting 0 to the SOmn bit
Start condition generate

Wait To secure a hold time of SCL signal
Writing 0 to the CKOmn bit Prepare to communicate the SCL signal is

fall
Writing 1 to the SOEmn bit Enable serial output
Writing 1 to the SSmn bit To serial operation enable status
Writing address and R/W

Transmitting address field
data to SIOr (SDRmn[7:0])
Wait for address field

transmission complete.
Transfer end interrupt No
generated? (Clear the interrupt request flag)
Yes ACK response from the slave

will be confirmed in PEFmn bit.
No if ACK (PEFmn = 0), to the next
Responded ACK? processing, if NACK (PEFmn =
1) to error processing.
Yes
Communication error
processing
Address field
transmission completed
To data transmission flow

and data reception flow
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18.8.2 Data transmission

Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field.
After all data are transmitted to the slave, a stop condition is generated and the bus is released.

Note 1 Note 1
Pins used SCL00, SDA00 SCL10, SDA10 SCL30, SDA30Note 1
Error detection ACK error flag (PEFmn)

flag
Transfer data 8 bits

length
Transfer rateNote 2 Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel
Stop bit Appending 1 bit (for ACK reception timing)
port output mode registers (POM0) (see 4.3.5 Port output mode registers (POMxx) for details). When
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Figure 18-108. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC10, IIC30) (1/2)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 1 0 1 1Note 1 1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) … During data transmission/reception, valid only
lower 8-bits (SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Note 2 Transmit data setting
Baud rate setting
0
SIOr
(d) Serial output register m (SOm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1Note3 1 0/1Note3 0 0 0 0 1 0/1Note3 1 0/1Note3
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Notes 1. Only provided for the SCR00 register. This bit is fixed to 1 for the other registers.
2. Because the setting is completed by address field transmission, setting is not required.
3. The value varies depending on the communication data during communication operation.
12
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Figure 18-108. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC10) (2/2)
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
12
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(2) Processing flow
Figure 18-109. Timing Chart of Data Transmission
SSmn “L”
SEmn
“H”
SOEmn “H”
SDRmn Transmit data 1
SCLr output
SDAr output D7 D6 D5 D4 D3 D2 D1 D0
SDAr input D7 D6 D5 D4 D3 D2 D1 D0 ACK
Shift
Shift operation
register mn
INTIICr
TSFmn
Figure 18-110. Flowchart of Simplified I2C Data Transmission
Address field
transmission completed
Starting data transmission
Writing data to SIOr

(SDRmn[7:0]) Transmission start by writing
Wait for transmission complete.

Transfer end interrupt No
Yes
ACK acknowledgment from the slave
No If ACK (PEF = 0), to the next process
Responded ACK?
if NACK (PEF = 1), to error handling
Yes
Communication error
processing
No
Data transfer completed?
Yes
Data transmission
completed
Stop condition generation
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18.8.3 Data reception

Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.

Note 1 Note 1
Pins used SCL00, SDA00 SCL10, SDA10 SCL30, SDA30Note 1
Error detection Overrun error detection flag (OVFmn) only

flag
Transfer data 8 bits

length
Transfer rateNote 2 Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel
Stop bit Appending 1 bit (ACK transmission)
port output mode registers (POM0) (see 4.3.5 Port output mode registers (POMxx) for details). When
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Figure 18-111. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC10, IIC30) (1/2)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0/1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate settingNote 1 Dummy transmit data setting (FFH)
0
SIOr
(d) Serial output register m (SOm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0/1Note 1 0/1Note 0 0 0 0 1 0/1Note 1 0/1Note
2 2 2 2
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm SOEm2 SOEm0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1
Notes 1. The baud rate setting is not required because the baud rate has already been set when the address
field was transmitted.
2. The value varies depending on the communication data during communication operation.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30),
mn = 00, 02, 12
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Figure 18-111. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC10, IIC30) (2/2)
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30),
mn = 00, 02, 12
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
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(2) Processing flow
Figure 18-112. Timing Chart of Data Reception
(a) When starting data reception
SSmn
STmn
SEmn
SOEmn “H”
TXEmn,
TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1
RXEmn
SDRmn Dummy data (FFH) Receive data
SCLr output
SDAr output ACK
SDAr input D7 D6 D5 D4 D3 D2 D1 D0
Shift
Shift operation
register mn
INTIICr
TSFmn
(b) When receiving last data
STmn
SEmn
SOEmn Output is enabled by serial Output is stopped by serial communication operation

communication operation
TXEmn,
TXEmn = 0 / RXEmn = 1
RXEmn
SDRmn Dummy data (FFH) Receive data Dummy data (FFH) Receive data
SCLr output
SDAr output ACK NACK
SDAr input D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Shift
Shift operation Shift operation
register mn
INTIICr
TSFmn
Reception of last byte SOmn bit SOmn bit

manipulation manipulation
IIC operation stop CKOmn bit

manipulation
Step condition
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30), mn = 00, 02, 12
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Figure 18-113. Flowchart of Data Reception
Address field transmission completed
Data reception completed
Stop operation for rewriting SCRmn

Writing 1 to the STmn bit register.
Set to receive only the operating

Writing 0 to the TXEmn bit, and 1 to the RXEmn bit
mode of the channel.
Operation restart
Writing 1 to the SSmn bit
No
Last byte received?
Yes
Disable output so that not the ACK
response to the last received data.
Writing 0 to the SOEmn bit
Writing dummy data (FFH) to Starting reception operation

SIOr (SDRmn[7:0])
No Wait for the completion of reception.

Yes
Reading receive data, perform
Reading SIOr (SDRmn[7:0])
processing (stored in the RAM etc.).
No
Data transfer completed?
Yes
Data reception completed
Stop condition generation
Caution ACK is not output when the last data is received (NACK). Communication is then completed by
setting “1” to the STmn bit of serial channel stop register m (STm) to stop operation and generating
a stop condition.
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18.8.4 Stop condition generation

After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 18-114. Timing Chart of Stop Condition Generation
STmn
SEmn
SOEmn Note
SCLr output
SDAr output
Operation SOmn CKOmn SOmn

stop bit manipulation bit manipulation bit manipulation
Stop condition
Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
Figure 18-115. Flowchart of Stop Condition Generation
Completion of data
transmission/data reception
Starting generation of stop condition.
Writing 1 to the STmn bit to clear Operation stop status (operable CKOmn
(the SEmn bit is cleared to 0)
manipulation)
Operation disable status (operable SOmn

Writing 0 to the SOEmn bit manipulation)
Writing 0 to the SOmn bit
Writing 1 to the CKOmn bit Timing to satisfy the low width standard of SCL
for the I2C bus.
Wait Secure a wait time so that the specifications of

I2C on the slave side are satisfied.
Writing 1 to the SOmn bit
End of IIC communication
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18.8.5 Calculating transfer rate

The transfer rate for simplified I2C (IIC00, IIC10, IIC30) communication can be calculated by the following expressions.
(Transfer rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution SDRmn[15:9] must not be set to 00000000B. Be sure to set a value of 00000001B or greater
for SDRmn[15:9]. The duty ratio of the SCL signal output by the simplified I2C is 50%. The I2C
bus specifications define that the low-level width of the SCL signal is longer than the high-
level width. If 400 kbps (fast mode) or 1 Mbps (fast mode plus) is specified, therefore, the low-
level width of the SCL output signal becomes shorter than the value specified in the I2C bus
specifications. Make sure that the SDRmn[15:9] value satisfies the I2C bus specifications.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to
1111111B) and therefore is 1 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
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Table 18-5. Selection of Operation Clock For Simplified I2C

Register
m13 m12 m11 m10 m03 m02 m01 m00
0 X X X X 0 0 0 0 fCLK 24 MHz
X X X X 0 0 0 1 fCLK/2 12 MHz
X X X X 0 0 1 0 fCLK/22 6 MHz
X X X X 0 0 1 1 fCLK/23 3 MHz
4
X X X X 0 1 0 0 fCLK/2 1.5 MHz
X X X X 0 1 0 1 fCLK/25 750 kHz
6
X X X X 0 1 1 0 fCLK/2 375 kHz
X X X X 0 1 1 1 fCLK/27 187.5 kHz
8
X X X X 1 0 0 0 fCLK/2 93.8 kHz
X X X X 1 0 0 1 fCLK/29 46.9 kHz
X X X X 1 0 1 0 fCLK/210 23.4 kHz
X X X X 1 0 1 1 fCLK/211 11.7 kHz
1 0 0 0 0 X X X X fCLK 24 MHz
0 0 0 1 X X X X fCLK/2 12 MHz
0 0 1 0 X X X X fCLK/22 6 MHz
0 0 1 1 X X X X fCLK/23 3 MHz
0 1 0 0 X X X X fCLK/24 1.5 MHz
5
0 1 0 1 X X X X fCLK/2 750 kHz
0 1 1 0 X X X X fCLK/26 375 kHz
7
0 1 1 1 X X X X fCLK/2 187.5 kHz
1 0 0 0 X X X X fCLK/28 93.8 kHz
1 0 0 1 X X X X fCLK/29 46.9 kHz
10
1 0 1 0 X X X X fCLK/2 23.4 kHz
1 0 1 1 X X X X fCLK/211 11.7 kHz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).

Here is an example of setting an I2C transfer rate where fMCK = fCLK = 24 MHz.
I2C Transfer Mode fCLK = 24 MHz

(Desired Transfer Rate) Operation Clock (fMCK) SDRmn[15:9] Calculated Error from Desired Transfer
Transfer Rate Rate
100 kHz fCLK/2 59 100 kHz 0.0%
400 kHz fCLK 29 380 kHz 5.0%Note
1 MHz fCLK 5 0.84 MHz 16.0%Note
Note The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%.
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18.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC10, IIC30) communication
The procedure for processing errors that occurred during simplified I2C (IIC00, IIC10, IIC30) communication is
described in Figures 18-116 and 18-117.
Figure 18-116. Processing Procedure in Case of Overrun Error
Reads serial data register mn The BFFmn bit of the SSRmn register is This is to prevent an overrun error if the
(SDRmn). set to 0 and channel n is enabled to next reception is completed during
receive data. error processing.
Reads serial status register mn (SSRmn). The error type is identified and the read
value is used to clear the error flag.
Writes 1 to serial flag clear trigger The error flag is cleared. The error only during reading can be
register mn (SIRmn). cleared, by writing the value read
from the SSRmn register to the
SIRmn register without modification.
Figure 18-117. Processing Procedure in Case of ACK Error in Simplified I2C Mode
Reads serial status register mn (SSRmn). The error type is identified and the read
value is used to clear the error flag.
Writes 1 to serial flag clear trigger The error flag is cleared. The error only during reading can be
register mn (SIRmn). cleared, by writing the value read from
Sets the STmn bit of serial channel The SEmn bit of serial channel enable The slave is not ready for reception
stop register m (STm) to 1. status register m (SEm) is set to 0 and because ACK is not returned.
channel n stops operation. Therefore, a stop condition is created,
the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
Creates a stop condition. transmission can be redone from
Creates a start condition. address transmission.
Sets the SSmn bit of serial channel The SEmn bit of serial channel enable
start register m (SSm) to 1. status register m (SEm) is set to 1 and
channel n is enabled to operate.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 00, 10, 30), mn = 00, 02, 12
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RL78/I1C CHAPTER 19 SERIAL INTERFACE IICA
CHAPTER 19 SERIAL INTERFACE IICA
19.1 Functions of Serial Interface IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode

This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
(2) I2C bus mode (multimaster supported)

This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLAn) line and a
serial data bus (SDAAn) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus. The
slave device automatically detects these received status and data by hardware. This function can simplify the part
of application program that controls the I2C bus.
Since the SCLAn and SDAAn pins are used for open drain outputs, serial interface IICA requires pull-up resistors
for the serial clock line and the serial data bus line.
(3) Wakeup mode

The STOP mode can be released by generating an interrupt request signal (INTIICAn) when an extension code
from the master device or a local address has been received while in STOP mode. This can be set by using the
WUPn bit of IICA control register n1 (IICCTLn1).
Figure 19-1 shows a block diagram of serial interface IICA.
Remark n=0
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Figure 19-1. Block Diagram of Serial Interface IICA0
Internal bus
IICA status register 0 (IICS0)

WUP0
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IICA control register 00
Sub-circuit (IICCTL00)
for standby
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Filter
Slave address Clear Start
SDAA0/ register 0 (SVA0) condition
Set generator
P61 Match
Noise signal
eliminator
Stop
IICA shift SO latch condition
D Q
register 0 (IICA0) generator
DFC0 IICWL0
Data hold
TRC0 time correction
N-ch open- circuit
drain output
Output control ACK
Output generator Wakeup
PM61 controller
latch
(P61)
ACK detector
Start condition
detector
Filter
Stop condition
SCLA0/ detector
P60
Interrupt request
Noise Serial clock signal generator INTIICA0
eliminator counter
IICS0.MSTS0, EXC0, COI0
DFC0 Serial clock
Serial clock wait controller IICA shift register 0 (IICA0)
controller Bus status
N-ch open-
drain output fCLK IICCTL00.STT0, SPT0 detector
Selector
Output fMCK
PM60 Counter IICS0.MSTS0, EXC0, COI0
latch fCLK/2
(P60)
Match signal
IICCTL01.PRS0
IICA low-level width IICA high-level width WUP0 CLD0 DAD0 SMC0 DFC0 PRS0 STCF0 IICBSY0 STCEN0 IICRSV0
setting register 0 (IICWL0) setting register 0 (IICWH0)
IICA control register 01 IICA flag register 0
(IICCTL01) (IICF0)
Internal bus
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Figure 19-2 shows a serial bus configuration example.
Figure 19-2. Serial Bus Configuration Example Using I2C Bus
+ VDD + VDD
Master CPU1 Serial data bus Master CPU2

SDAAn SDAAn
Slave CPU1 Slave CPU2
Serial clock
SCLAn SCLAn
Address 0 Address 1
SDAAn Slave CPU3
Address 2
SCLAn
SDAAn
Slave IC
SCLAn Address 3
SDAAn
Slave IC
Address N
SCLAn
Remark n=0
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19.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 19-1. Configuration of Serial Interface IICA

Item Configuration
Registers IICA shift register n (IICAn)
Slave address register n (SVAn)
Peripheral Reset Control Register 0 (PRR0)
IICA control register n0 (IICCTLn0)
IICA status register n (IICSn)
IICA flag register n (IICFn)
IICA control register n1 (IICCTLn1)
IICA low-level width setting register n (IICWLn)
IICA high-level width setting register n (IICWHn)
Port mode register 6 (PM6)
Port register 6 (P6)
Remark n=0
(1) IICA shift register n (IICAn)

The IICAn register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with
the serial clock. The IICAn register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to the IICAn
register.
Cancel the wait state and start data transfer by writing data to the IICAn register during the wait period.
The IICAn register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICAn to 00H.
Figure 19-3. Format of IICA Shift Register n (IICAn)
Symbol 7 6 5 4 3 2 1 0
IICAn
Cautions 1. Do not write data to the IICAn register during data transfer.
2. Write or read the IICAn register only during the wait period. Accessing the IICAn register in a
communication state other than during the wait period is prohibited. When the device serves
as the master, however, the IICAn register can be written only once after the communication
trigger bit (STTn) is set to 1.
3. When communication is reserved, write data to the IICAn register after the interrupt triggered
by a stop condition is detected.
Remark n=0
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(2) Slave address register n (SVAn)

This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
The SVAn register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STDn = 1 (while the start condition is detected).
Reset signal generation clears the SVAn register to 00H.
Figure 19-4. Format of Slave Address Register n (SVAn)
Symbol 7 6 5 4 3 2 1 0
SVAn A6 A5 A4 A3 A2 A1 A0 0Note
Note Bit 0 is fixed to 0.
(3) SO latch
The SO latch is used to retain the SDAAn pin’s output level.
(4) Wakeup controller

This circuit generates an interrupt request (INTIICAn) when the address received by this register matches the
address value set to the slave address register n (SVAn) or when an extension code is received.
(5) Serial clock counter

This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
(6) Interrupt request signal generator

This circuit controls the generation of interrupt request signals (INTIICAn).
An I2C interrupt request is generated by the following two triggers.
● Falling edge of eighth or ninth clock of the serial clock (set by the WTIMn bit)
● Interrupt request generated when a stop condition is detected (set by the SPIEn bit)
Remark WTIMn bit: Bit 3 of IICA control register n0 (IICCTLn0)

SPIEn bit: Bit 4 of IICA control register n0 (IICCTLn0)
(7) Serial clock controller

In master mode, this circuit generates the clock output via the SCLAn pin from a sampling clock.
(8) Serial clock wait controller

This circuit controls the wait timing.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(10) Data hold time correction circuit

This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
Remark n=0
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(11) Start condition generator

This circuit generates a start condition when the STTn bit is set to 1.
However, in the communication reservation disabled status (IICRSVn bit = 1), when the bus is not released
(IICBSYn bit = 1), start condition requests are ignored and the STCFn bit is set to 1.
(12) Stop condition generator

This circuit generates a stop condition when the SPTn bit is set to 1.
(13) Bus status detector

This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCENn bit.
Remarks 1. STTn bit: Bit 1 of IICA control register n0 (IICCTLn0)

SPTn bit: Bit 0 of IICA control register n0 (IICCTLn0)
IICRSVn bit: Bit 0 of IICA flag register n (IICFn)
IICBSYn bit: Bit 6 of IICA flag register n (IICFn)
STCFn bit: Bit 7 of IICA flag register n (IICFn)
STCENn bit: Bit 1 of IICA flag register n (IICFn)
2. n=0
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19.3 Registers Controlling Serial Interface IICA
Serial interface IICA is controlled by the following ten registers.

● Peripheral Reset Control Register 0 (PRR0)
● IICA control register n0 (IICCTLn0)
● IICA flag register n (IICFn)
● IICA status register n (IICSn)
● IICA low-level width setting register n (IICWLn)
● IICA high-level width setting register n (IICWHn)
● Port register 6 (P6)
Remark n=0
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When serial interface IICA0 is used, be sure to set bit 4 (IICA0EN) of this register to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
IICA0EN Control of serial interface IICA0 input clock supply

● SFR used by the serial interface IICA0 cannot be written. The read value is 0H. However, the SFR
is not initialized. Note
● SFR used by the serial interface IICA0 can be read and written.
Note To initialize the serial interface IICA0 and the SFR used by the serial interface IICA0, use bit 4 (IICA0RES) of
PRR0.
Cautions 1. When setting serial interface IICAn, be sure to set the following registers first while the IICAnEN
bit is set to 1. If IICAnEN = 0, writing to the control registers of serial interface IICA is ignored
(except for port mode register 6 (PM6) and port register 6 (P6)).
● IICA flag register n (IICFn)
● IICA status register n (IICSn)
● IICA low-level width setting register n (IICWLn)
● IICA high-level width setting register n (IICWHn)
2. Be sure to clear bit 7, 1 to “0”.
Remark n=0
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To reset the serial interface IICA0, be sure to set bits 4 (IICA0RES) to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
IICA0RES Control resetting of the serial interface IICA0
0 Release of the reset state of the serial interface IICA0

1 The serial interface IICA0 is in the reset state.
19.3.3 IICA control register n0 (IICCTLn0)

This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
The IICCTLn0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIEn, WTIMn,
and ACKEn bits while IICEn = 0 or during the wait period. These bits can be set at the same time when the IICEn bit is set
from “0” to “1”.
Remark n=0
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Figure 19-7. Format of IICA Control Register n0 (IICCTLn0) (1/4)

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICCTLn0 IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
IICEn I2C operation enable

0 Stop operation. Reset the IICA status register n (IICSn)Note 1. Stop internal operation.
1 Enable operation.
Be sure to set this bit (1) while the SCLAn and SDAAn lines are at high level.
Condition for clearing (IICEn = 0) Condition for setting (IICEn = 1)
● Cleared by instruction ● Set by instruction
● Reset
LRELnNotes 2, 3 Exit from communications
0 Normal operation
1 This exits from the current communications and sets standby mode. This setting is automatically
cleared to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLAn and SDAAn lines are set to high impedance.
The following flags of IICA control register n0 (IICCTLn0) and the IICA status register n (IICSn) are
cleared to 0.
• STTn • SPTn • MSTSn • EXCn • COIn • TRCn • ACKDn • STDn
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
● After a stop condition is detected, restart is in master mode.
● An address match or extension code reception occurs after the start condition.
Condition for clearing (LRELn = 0) Condition for setting (LRELn = 1)
● Automatically cleared after execution ● Set by instruction
● Reset
WRELnNotes 2, 3 Wait cancellation
0 Do not cancel wait

1 Cancel wait. This setting is automatically cleared after wait is canceled.
When the WRELn bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRCn = 1), the SDAAn line goes into the high impedance state (TRCn = 0).
Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1)
● Automatically cleared after execution ● Set by instruction
● Reset
Notes 1. The IICA status register n (IICSn), the STCFn and IICBSYn bits of the IICA flag register n (IICFn),
and the CLDn and DADn bits of IICA control register n1 (IICCTLn1) are reset.
2. The signal of this bit is invalid while IICEn is 0.
3. When the LRELn and WRELn bits are read, 0 is always read.
Caution If the operation of I2C is enabled (IICEn = 1) when the SCLAn line is high level, the SDAAn
line is low level, and the digital filter is turned on (DFCn bit of IICCTLn1 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LRELn bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of I2C
(IICEn = 1).
Remark n=0
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Symbol <7> <6> <5> <4> <3> <2> <1> <0>
SPIEnNotes 1 Enable/disable generation of interrupt request when stop condition is detected
0 Disable
1 Enable
If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn
= 1.
Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1)

● Reset
WTIMnNote 1 Control of wait and interrupt request generation
0 Interrupt request is generated at the eighth clock’s falling edge.

Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock’s falling edge.

Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn = 0) Condition for setting (WTIMn = 1)

● Reset
ACKEnNotes 1, 2 Acknowledgment control
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDAAn line is set to low level.
Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)

● Reset
Notes 1. The signal of this bit is invalid while IICEn is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
Remark n=0
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Symbol <7> <6> <5> <4> <3> <2> <1> <0>
STTnNotes 1, 2 Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in standby state, when IICBSYn = 0):

If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
● When communication reservation function is enabled (IICRSVn = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
● When communication reservation function is disabled (IICRSVn = 1)
Even if this bit is set (1), the STTn bit is cleared and the STTn clear flag (STCFn) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing

● For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKEn bit has been cleared to 0 and slave has been notified of final reception.
● For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
● Cannot be set to 1 at the same time as stop condition trigger (SPTn).
● Once STTn is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (STTn = 0) Condition for setting (STTn = 1)

● Cleared by setting the STTn bit to 1 while ● Set by instruction
communication reservation is prohibited.
● Cleared by loss in arbitration
● Cleared after start condition is generated by master
device
● Cleared by LRELn = 1 (exit from communications)
● When IICEn = 0 (operation stop)
● Reset
Notes 1. The signal of this bit is invalid while IICEn is 0.

2. The STTn bit is always read as 0.
Remarks 1. IICRSVn: Bit 0 of IIC flag register n (IICFn)

STCFn: Bit 7 of IIC flag register n (IICFn)
2. n = 0
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Symbol <7> <6> <5> <4> <3> <2> <1> <0>
SPTnNote Stop condition trigger
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
Cautions concerning set timing

● For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when the ACKEn bit has been cleared to 0 and
slave has been notified of final reception.
● For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
● Cannot be set to 1 at the same time as start condition trigger (STTn).
● The SPTn bit can be set to 1 only when in master mode.
● When the WTIMn bit has been cleared to 0, if the SPTn bit is set to 1 during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIMn
bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPTn bit should
be set to 1 during the wait period that follows the output of the ninth clock.
● Once SPTn is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (SPTn = 0) Condition for setting (SPTn = 1)

● Cleared by loss in arbitration ● Set by instruction
● Automatically cleared after stop condition is detected
● Reset
Note The SPTn bit is always read as 0.
Caution When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5
(WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is
canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to
high impedance. Release the wait performed while the TRCn bit is 1 (transmission status)
by writing to the IICA shift register n.
Remark n=0
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19.3.4 IICA status register n (IICSn)

This register indicates the status of I2C.
The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait
period.
Caution Reading the IICSn register while the address match wakeup function is enabled (WUPn = 1) in STOP
mode is prohibited. When the WUPn bit is changed from 1 to 0 (wakeup operation is stopped),
regardless of the INTIICAn interrupt request, the change in status is not reflected until the next start
condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIEn = 1)
the interrupt generated by detecting a stop condition and read the IICSn register after the interrupt
has been detected.
Remark STTn: bit 1 of IICA control register n0 (IICCTLn0)

WUPn: bit 7 of IICA control register n1 (IICCTLn1)
Figure 19-8. Format of IICA Status Register n (IICSn) (1/3)
Address: FFF51H After reset: 00H R

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
MSTSn Master status check flag
0 Slave device status or communication standby status

1 Master device communication status
Condition for clearing (MSTSn = 0) Condition for setting (MSTSn = 1)
● When a stop condition is detected ● When a start condition is generated
● When ALDn = 1 (arbitration loss)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
ALDn Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared.
Condition for clearing (ALDn = 0) Condition for setting (ALDn = 1)
● Automatically cleared after the IICSn register is ● When the arbitration result is a “loss”.
readNote
stop)
● Reset
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than the IICSn register. Therefore, when using the ALDn bit, read the data of this bit before the data
of the other bits.
Remarks 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0)

IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n=0
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Symbol <7> <6> <5> <4> <3> <2> <1> <0>
EXCn Detection of extension code reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1)

● When a start condition is detected ● When the higher four bits of the received address
● When a stop condition is detected data is either “0000” or “1111” (set at the rising edge
● Cleared by LRELn = 1 (exit from communications) of the eighth clock).
stop)
● Reset
COIn Detection of matching addresses
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COIn = 0) Condition for setting (COIn = 1)

● When a start condition is detected ● When the received address matches the local
● When a stop condition is detected address (slave address register n (SVAn))
● Cleared by LRELn = 1 (exit from communications) (set at the rising edge of the eighth clock).
stop)
● Reset
TRCn Detection of transmit/receive status
0 Receive status (other than transmit status). The SDAAn line is set for high impedance.
1 Transmit status. The value in the SOn latch is enabled for output to the SDAAn line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRCn = 0) Condition for setting (TRCn = 1)

<Both master and slave> <Master>
● When a stop condition is detected ● When a start condition is generated
● Cleared by LRELn = 1 (exit from communications) ● When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
stop)
(during address transfer)
● Cleared by WRELn = 1Note (wait cancel)
<Slave>
● When the ALDn bit changes from 0 to 1 (arbitration
● When 1 (slave transmission) is input to the LSB
loss)
● Reset (transfer direction specification bit) of the first byte
●When not used for communication (MSTSn, EXCn, COIn from the master (during address transfer)
= 0)
<Master>
● When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
● When a start condition is detected
● When “0” is input to the first byte’s LSB (transfer
direction specification bit)
(Note and Remarks are listed on the next page.)
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Note When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5
(WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is
canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to high
impedance. Release the wait performed while the TRCn bit is 1 (transmission status) by writing to
the IICA shift register n.

2. n=0
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Symbol <7> <6> <5> <4> <3> <2> <1> <0>
ACKDn Detection of acknowledge (ACK)
0 Acknowledge was not detected.
1 Acknowledge was detected.
Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1)
● When a stop condition is detected ● After the SDAAn line is set to low level at the rising
● At the rising edge of the next byte’s first clock edge of SCLAn line’s ninth clock
stop)
● Reset
STDn Detection of start condition
0 Start condition was not detected.
1 Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STDn = 0) Condition for setting (STDn = 1)
● When a stop condition is detected ● When a start condition is detected

● At the rising edge of the next byte’s first clock
following address transfer
stop)
● Reset
SPDn Detection of stop condition
0 Stop condition was not detected.
1 Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Condition for clearing (SPDn = 0) Condition for setting (SPDn = 1)
● At the rising edge of the address transfer byte’s first ● When a stop condition is detected
clock following setting of this bit and detection of a
start condition
● When the WUPn bit changes from 1 to 0
stop)
● Reset

2. n=0
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19.3.5 IICA flag register n (IICFn)

This register sets the operation mode of I2C and indicates the status of the I2C bus.
The IICFn register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STTn clear flag
(STCFn) and I2C bus status flag (IICBSYn) bits are read-only.
The IICRSVn bit can be used to enable/disable the communication reservation function.
The STCENn bit can be used to set the initial value of the IICBSYn bit.
The IICRSVn and STCENn bits can be written only when the operation of I2C is disabled (bit 7 (IICEn) of IICA control
register n0 (IICCTLn0) = 0). When operation is enabled, the IICFn register can be read.
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Figure 19-9. Format of IICA Flag Register n (IICFn)
Address: FFF52H After reset: 00H R/WNote
Symbol <7> <6> 5 4 3 2 <1> <0>

IICFn STCFn IICBSYn 0 0 0 0 STCENn IICRSVn
STCFn STTn clear flag

0 Generate start condition
1 Start condition generation unsuccessful: clear the STTn flag
Condition for clearing (STCFn = 0) Condition for setting (STCFn = 1)
● Cleared by STTn = 1 ● Generating start condition unsuccessful and the
● When IICEn = 0 (operation stop) STTn bit cleared to 0 when communication
● Reset reservation is disabled (IICRSVn = 1).
IICBSYn I2C bus status flag

0 Bus release status (communication initial status when STCENn = 1)
1 Bus communication status (communication initial status when STCENn = 0)
Condition for clearing (IICBSYn = 0) Condition for setting (IICBSYn = 1)
● Detection of stop condition ● Detection of start condition
● When IICEn = 0 (operation stop) ● Setting of the IICEn bit when STCENn = 0
● Reset
STCENn Initial start enable trigger

0 After operation is enabled (IICEn = 1), enable generation of a start condition upon detection of
a stop condition.
1 After operation is enabled (IICEn = 1), enable generation of a start condition without detecting
a stop condition.
Condition for clearing (STCENn = 0) Condition for setting (STCENn = 1)

● Detection of start condition
● Reset
IICRSVn Communication reservation function disable bit

0 Enable communication reservation
1 Disable communication reservation
Condition for clearing (IICRSVn = 0) Condition for setting (IICRSVn = 1)
● Reset
Note Bits 6 and 7 are read-only.
Cautions 1. Write to the STCENn bit only when the operation is stopped (IICEn = 0).
2. As the bus release status (IICBSYn = 0) is recognized regardless of the actual bus
status when STCENn = 1, when generating the first start condition (STTn = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
3. Write to IICRSVn only when the operation is stopped (IICEn = 0).
Remarks 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0)

2. n=0
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19.3.6 IICA control register n1 (IICCTLn1)

This register is used to set the operation mode of I2C and detect the statuses of the SCLAn and SDAAn pins.
The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn
bits are read-only.
Set the IICCTLn1 register, except the WUPn bit, while operation of I2C is disabled (bit 7 (IICEn) of IICA control register
n0 (IICCTLn0) is 0).
Address: F0231H After reset: 00H R/WNote 1
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
IICCTLn1 WUPn 0 CLDn DADn SMCn DFCn 0 PRSn
WUPn Control of address match wakeup
0 Stops operation of address match wakeup function in STOP mode.
1 Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUPn = 1, execute the STOP instruction at least three clocks of fMCK after setting
(1) the WUPn bit (see Figure 19-23 Flow When Setting WUPn = 1).
Clear (0) the WUPn bit after the address has matched or an extension code has been received. The
subsequent communication can be entered by the clearing (0) WUPn bit. (The wait must be released and
transmit data must be written after the WUPn bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUPn
= 1, is identical to the interrupt timing when WUPn = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUPn = 1, a stop condition interrupt is not generated even if the SPIEn bit is set to
1.
Condition for clearing (WUPn = 0) Condition for setting (WUPn = 1)
●Cleared by instruction (after address match or ●Set by instruction (when the MSTSn, EXCn, and
extension code reception) COIn bits are “0”, and the STDn bit also “0”
(communication not entered))Note 2
Notes 1. Bits 4 and 5 are read-only.

2. The status of the IICA status register n (IICSn) must be checked and the WUPn bit must be set
during the period shown below.
<1> <2>
SCLAn
SDAAn A6 A5 A4 A3 A2 A1 A0 R/W
The maximum time from reading IICSn to setting

WUPn is the period from <1> to <2>.
Check the IICSn operation status and set

WUPn during this period.
Remark n=0
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Symbol <7> 6 <5> <4> <3> <2> 1 <0>
IICCTLn1 WUPn 0 CLDn DADn SMCn DFCn 0 PRSn
CLDn Detection of SCLAn pin level (valid only when IICEn = 1)
0 The SCLAn pin was detected at low level.
1 The SCLAn pin was detected at high level.
Condition for clearing (CLDn = 0) Condition for setting (CLDn = 1)
● When the SCLAn pin is at low level ● When the SCLAn pin is at high level
● Reset
DADn Detection of SDAAn pin level (valid only when IICEn = 1)
0 The SDAAn pin was detected at low level.
1 The SDAAn pin was detected at high level.
Condition for clearing (DADn = 0) Condition for setting (DADn = 1)
● When the SDAAn pin is at low level ● When the SDAAn pin is at high level
● Reset
SMCn Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
DFCn Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode and fast mode plus.
The digital filter is used for noise elimination. The transfer clock does not vary, regardless of the DFCn bit being
set (1) or cleared (0).
PRSn IICA operation clock (fMCK) control
0 Selects fCLK (1 MHz ≤ fCLK ≤ 20 MHz)
1 Selects fCLK/2 (20 MHz < fCLK)
Cautions 1. The maximum operating frequency of the IICA operating clock (fMCK) is 20 MHz
(Max.). Set the IICA control register n1 (IICCTLn1) bit 0 (PRSn) to “1” only when fCLK
exceeds 20 MHz.
2. Note the minimum fCLK operation frequency when setting the transfer clock.
The minimum fCLK operation frequency for serial interface IICA is determined
according to the mode.
Fast mode: fCLK = 3.5 MHz (MIN.)
Fast mode plus: fCLK = 10 MHz (MIN.)
Normal mode: fCLK = 1 MHz (MIN.)
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Cautions 3. The fast mode plus is only available in the products for “A: Consumer applications
(TA = –40°C to +85°C)” and “D: Industrial applications (TA = –40°C to +85°C)”.
Remarks 1. IICEn: Bit 7 of IICA control register n0 (IICCTLn0)

2. n=0
19.3.7 IICA low-level width setting register n (IICWLn)

This register is used to set the low-level width (tLOW) of the SCLAn pin signal that is output by serial interface IICA and
to control the SDAAn pin signal.
The IICWLn register can be set by an 8-bit memory manipulation instruction.
Set the IICWLn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
For details about setting the IICWLn register, see 19.4.2 Setting transfer clock by using IICWLn and IICWHn
registers.
The data hold time is one-quarter of the time set by the IICWLn register.
Figure 19-11. Format of IICA Low-Level Width Setting Register n (IICWLn)

Symbol 7 6 5 4 3 2 1 0
IICWLn
19.3.8 IICA high-level width setting register n (IICWHn)

This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA and to
control the SDAAn pin signal.
The IICWHn register can be set by an 8-bit memory manipulation instruction.
Set the IICWHn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
Figure 19-12. Format of IICA High-Level Width Setting Register n (IICWHn)
Symbol 7 6 5 4 3 2 1 0
IICWHn
Remarks 1. For setting procedures of the transfer clock on master side and of the IICWLn and IICWHn
registers on slave side, see 19.4.2 (1) and 19.4.2 (2), respectively.
2. n=0
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19.3.9 Port mode register 6 (PM6)

This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the
output latches of P60 and P61 to 0.
Set the IICEn bit (bit 7 of IICA control register n0 (IICCTLn0)) to 1 before setting the output mode because the
P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICEn bit is 0.
The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 19-13. Format of Port Mode Register 6 (PM6)
Address: FFF26H After reset: FFH R/W

Symbol 7 6 5 4 3 2 1 0
PM6 1 1 1 1 1 PM62 PM61 PM60
PM6n P6n pin I/O mode selection (n = 0 to 2)

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19.4 I2C Bus Mode Functions
19.4.1 Pin configuration

The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows.
(1) SCLAn .... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDAAn .... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 19-14. Pin Configuration Diagram
Slave device
VDD
Master device
SCLAn SCLAn
Clock output (Clock output)

VDD
VSS VSS
(Clock input) Clock input
SDAAn SDAAn
Data output Data output
VSS VSS
Data input Data input
Remark n = 0
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19.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
fMCK
Transfer clock = IICWL0 + IICWH0 + fMCK (tR + tF)
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)
● When the fast mode
0.52
IICWLn = Transfer clock × fMCK
0.48
IICWHn = ( Transfer clock – tR – tF) × fMCK
● When the normal mode
0.47
0.53
● When the fast mode plus
0.50
0.50
(2) Setting IICWLn and IICWHn registers on slave side

(The fractional parts of all setting values are truncated.)
● When the fast mode
IICWLn = 1.3 µs × fMCK

IICWHn = (1.2 µs – tR – tF) × fMCK
● When the normal mode

● When the fast mode plus

(Caution and Remarks are listed on the next page.)
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Cautions 1. The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (Max.).
Set bit 0 (PRSn) of the IICA control register n1 (IICCTLn1) to “1” only when the fCLK exceeds 20
MHz.
2. Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode: fCLK = 3.5 MHz (MIN.)
Fast mode plus: fCLK = 10 MHz (MIN.)
Normal mode: fCLK = 1 MHz (MIN.)
Remarks 1. Calculate the rise time (tR) and fall time (tF) of the SDAAn and SCLAn signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
tF: SDAAn and SCLAn signal falling times
tR: SDAAn and SCLAn signal rising times
fMCK: IICA operation clock frequency
3. n=0
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19.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 19-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C
bus’s serial data bus.
Figure 19-15. I2C Bus Serial Data Transfer Timing
SCLAn 1-7 8 9 1-8 9 1-8 9
SDAAn
Start Address R/W ACK Data ACK Data ACK Stop

condition condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
The serial clock (SCLAn) is continuously output by the master device. However, in the slave device, the SCLAn pin low
level period can be extended and a wait can be inserted.
19.5.1 Start conditions

A start condition is met when the SCLAn pin is at high level and the SDAAn pin changes from high level to low level.
The start conditions for the SCLAn pin and SDAAn pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 19-16. Start Conditions
H
SCLAn
SDAAn
A start condition is output when bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set (1) after a stop condition has
been detected (SPDn: Bit 0 of the IICA status register n (IICSn) = 1). When a start condition is detected, bit 1 (STDn) of
the IICSn register is set (1).
Remark n = 0
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19.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
matches the data values stored in the slave address register n (SVAn). If the address data matches the SVAn register
values, the slave device is selected and communicates with the master device until the master device generates a start
condition or stop condition.
Figure 19-17. Address
SCLAn 1 2 3 4 5 6 7 8 9
Address
Note
INTIICAn
Note INTIICAn is not issued if data other than a local address or extension code is received during slave device
operation.
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
19.5.3 Transfer direction specification are written to the IICA shift register n (IICAn). The received addresses are
written to the IICAn register.
The slave address is assigned to the higher 7 bits of the IICAn register.
19.5.3 Transfer direction specification

In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to
a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is
receiving data from a slave device.
Figure 19-18. Transfer Direction Specification
SCLAn 1 2 3 4 5 6 7 8 9
Transfer direction specification

Note
INTIICAn
Note INTIICAn is not issued if data other than a local address or extension code is received during slave device
operation.
Remark n = 0
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19.5.4 Acknowledge (ACK)

ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side,
it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected
can be checked by using bit 2 (ACKDn) of the IICA status register n (IICSn).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave
does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission.
If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally.

<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDAAn line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKEn) of IICA control register n0 (IICCTLn0) to 1. Bit 3
(TRCn) of the IICSn register is set by the data of the eighth bit that follows 7-bit address information. Usually, set the
ACKEn bit to 1 for reception (TRCn = 0).
If a slave can receive no more data during reception (TRCn = 0) or does not require the next data item, then the slave
must inform the master, by clearing the ACKEn bit to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRCn = 0), it must clear the ACKEn bit to 0 so
that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
Figure 19-19. ACK
SCLAn 1 2 3 4 5 6 7 8 9
SDAAn A6 A5 A4 A3 A2 A1 A0 R/W ACK
When the local address is received, ACK is automatically generated, regardless of the value of the ACKEn bit. When
an address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if the ACKEn bit is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
● When 8-clock wait state is selected (bit 3 (WTIMn) of IICCTLn0 register = 0):
By setting the ACKEn bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock
of the SCLAn pin.
● When 9-clock wait state is selected (bit 3 (WTIMn) of IICCTLn0 register = 1):
ACK is generated by setting the ACKEn bit to 1 in advance.
Remark n = 0
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19.5.5 Stop condition

When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 19-20. Stop Condition
H
SCLAn
SDAAn
A stop condition is generated when bit 0 (SPTn) of IICA control register n0 (IICCTLn0) is set to 1. When the stop
condition is detected, bit 0 (SPDn) of the IICA status register n (IICSn) is set to 1 and INTIICAn is generated when bit 4
(SPIEn) of the IICCTLn0 register is set to 1.
Remark n = 0
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19.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
data (i.e., is in a wait state).
Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 19-21. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKEn = 1)
Master
Master returns to high
impedance but slave Wait after output
is in wait state (low level). of ninth clock
IICAn IICA0 data write (cancel wait)
SCLAn 6 7 8 9 1 2 3
Slave
Wait after output
of eighth clock
FFH is written to IICAn or WRELn is set to 1
IICAn
SCLAn
H
ACKEn
Transfer lines
Wait from slave Wait from master
SCLAn 6 7 8 9 1 2 3
SDAAn D2 D1 D0 ACK D7 D6 D5
Remark n = 0
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Figure 19-21. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKEn = 1)
Master Master and slave both wait

after output of ninth clock
IICAn data write (cancel wait)
IICAn
SCLAn 6 7 8 9 1 2 3
Slave
FFH is written to IICAn or WRELn is set to 1
IICAn
SCLAn
ACKEn H
Wait from
master and
Transfer lines slave Wait from slave
SCLAn 6 7 8 9 1 2 3
SDAAn D2 D1 D0 ACK D7 D6 D5
Generate according to previously setACKEn value
Remark ACKEn: Bit 2 of IICA control register n0 (IICCTLn0)

WRELn: Bit 5 of IICA control register n0 (IICCTLn0)
A wait may be automatically generated depending on the setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0).
Normally, the receiving side cancels the wait state when bit 5 (WRELn) of the IICCTLn0 register is set to 1 or when
FFH is written to the IICA shift register n (IICAn), and the transmitting side cancels the wait state when data is written to
the IICAn register.
The master device can also cancel the wait state via either of the following methods.
● By setting bit 1 (STTn) of the IICCTLn0 register to 1
● By setting bit 0 (SPTn) of the IICCTLn0 register to 1
Remark n = 0
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19.5.7 Canceling wait

The I2C usually cancels a wait state by the following processing.
● Writing data to the IICA shift register n (IICAn)

● Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait)
● Setting bit 1 (STTn) of the IICCTLn0 register (generating start condition)Note
● Setting bit 0 (SPTn) of the IICCTLn0 register (generating stop condition)Note
Note Master only
When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed.
To cancel a wait state and transmit data (including addresses), write the data to the IICAn register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WRELn) of the IICCTLn0
register to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STTn) of the IICCTLn0 register to 1.
To generate a stop condition after canceling a wait state, set bit n (SPTn) of the IICCTLn0 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICAn register after canceling a wait state by setting the WRELn bit to 1, an
incorrect value may be output to SDAAn line because the timing for changing the SDAAn line conflicts with the timing for
writing the IICAn register.
In addition to the above, communication is stopped if the IICEn bit is cleared to 0 when communication has been
aborted, so that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LRELn) of the
IICCTLn0 register, so that the wait state can be canceled.
Caution If a processing to cancel a wait state is executed when WUPn = 1, the wait state will not be canceled.
Remark n = 0
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19.5.8 Interrupt request (INTIICAn) generation timing and wait control

The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is
generated and the corresponding wait control, as shown in Table 19-2.
Table 19-2. INTIICAn Generation Timing and Wait Control
WTIMn During Slave Device Operation During Master Device Operation

Address Data Reception Data Transmission Address Data Reception Data Transmission
Notes 1, 2 Note 2 Note 2
0 9 8 8 9 8 8
Notes 1, 2 Note 2 Note 2
1 9 9 9 9 9 9
Notes 1. The slave device’s INTIICAn signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register n (SVAn).
At this point, ACK is generated regardless of the value set to the IICCTLn0 register’s bit 2 (ACKEn). For a
slave device that has received an extension code, INTIICAn occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICAn is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of the slave address register n (SVAn) and extension
code is not received, neither INTIICAn nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
● Slave device operation: Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIMn bit.
● Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
WTIMn bit.
(2) During data reception
● Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
(3) During data transmission
● Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
(4) Wait cancellation method

The four wait cancellation methods are as follows.
● Writing data to the IICA shift register n (IICAn)

● Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait)
● Setting bit 1 (STTn) of IICCTLn0 register (generating start condition)Note
● Setting bit 0 (SPTn) of IICCTLn0 register (generating stop condition)Note
Note Master only.
When an 8-clock wait has been selected (WTIMn = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
(5) Stop condition detection

INTIICAn is generated when a stop condition is detected (only when SPIEn = 1).
Remark n = 0
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19.5.9 Address match detection method

In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected automatically by hardware. An interrupt request (INTIICAn) occurs when the address
set to the slave address register n (SVAn) matches the slave address sent by the master device, or when an extension
code has been received.
19.5.10 Error detection

In I2C bus mode, the status of the serial data bus (SDAAn) during data transmission is captured by the IICA shift
register n (IICAn) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted
IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
Remark n = 0
19.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXCn)
is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling edge of the
eighth clock. The local address stored in the slave address register n (SVAn) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
the SVAn register is set to 11110xx0. Note that INTIICAn occurs at the falling edge of the eighth clock.
● Higher four bits of data match: EXCn = 1

● Seven bits of data match: COIn = 1
Remark EXCn: Bit 5 of IICA status register n (IICSn)

COIn: Bit 4 of IICA status register n (IICSn)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 to set the standby mode for the next communication
operation.
Table 19-3. Bit Definitions of Major Extension Codes
Slave Address R/W Bit Description
0000 000 0 General call address
1111 0xx 0 10-bit slave address specification (during address

authentication)
1111 0xx 1 10-bit slave address specification (after address match, when
read command is issued)
Remarks 1. See the I2C bus specifications issued by NXP Semiconductors for details of extension codes other than
those described above.
2. n = 0
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19.5.12 Arbitration
When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn
bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in the IICA status register n (IICSn)
is set (1) via the timing by which the arbitration loss occurred, and the SCLAn and SDAAn lines are both set to high
impedance, which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
condition is detected, etc.) and the ALDn = 1 setting that has been made by software.
For details of interrupt request timing, see 19.5.8 Interrupt request (INTIICAn) generation timing and wait control.
Remark STDn: Bit 1 of IICA status register n (IICSn)

STTn: Bit 1 of IICA control register n0 (IICCTLn0)
Figure 19-22. Arbitration Timing Example
Master 1
Hi-Z
SCLAn
Hi-Z
SDAAn
Master 2 Master 1 loses arbitration
SCLAn
SDAAn
Transfer lines
SCLAn
SDAAn
Remark n = 0
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Table 19-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration Interrupt Request Generation Timing
During address transmission At falling edge of eighth or ninth clock following byte transferNote 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer When stop condition is generated (when SPIEn = 1)Note 2
When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transferNote 1
condition
When stop condition is detected while attempting to generate a When stop condition is generated (when SPIEn = 1)Note 2
restart condition
When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transferNote 1
condition
When SCLAn is at low level while attempting to generate a

restart condition
Notes 1. When the WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) = 1, an interrupt request occurs at the
falling edge of the ninth clock. When WTIMn = 0 and the extension code’s slave address is received, an
interrupt request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIEn = 1 for master device operation.
Remarks 1. SPIEn: Bit 4 of IICA control register n0 (IICCTLn0)

2. n=0
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19.5.13 Wakeup function

The I2C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and
extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
To use the wakeup function in the STOP mode, set the WUPn bit to 1. Addresses can be received regardless of the
operation clock. An interrupt request signal (INTIICAn) is also generated when a local address and extension code have
been received. Operation returns to normal operation by using an instruction to clear (0) the WUPn bit after this interrupt
has been generated.
Figure 19-23 shows the flow for setting WUPn = 1 and Figure 19-24 shows the flow for setting WUPn = 0 upon an
address match.
Figure 19-23. Flow When Setting WUPn = 1
START
No
MSTSn = STDn = EXCn = COIn =0?
Yes
WUPn = 1
Wait Waits for 3 clocks of fMCK.
STOP instruction execution
Remark n = 0
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Figure 19-24. Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception)
STOP mode state

No
INTIICAn = 1?
Yes
WUPn = 0
Reading IICSn
Executes processing corresponding to the operation to be executed

after checking the operation state of serial interface IICA.
Use the following flows to perform the processing to release the STOP mode other than by an interrupt request
(INTIICAn) generated from serial interface IICA.
● When operating next IIC communication as master: Flow shown in Figure 19-25
● When operating next IIC communication as slave:
When restored by INTIICAn interrupt: Same as the flow in Figure 19-23
When restored by other than INTIICAn interrupt: Until the INTIICAn interrupt occurs, continue operating with WUPn
left set to 1
Remark n = 0
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Figure 19-25. When Operating as Master Device After Releasing STOP Mode Other than by INTIICAn
START
SPIEn = 1
WUPn = 1
STOP instruction
STOP mode state
Releasing STOP mode Releases STOP mode by an interrupt other than INTIICAn.
WUPn = 0
No
INTIICAn = 1?
Yes Generates a STOP condition or selects

as a slave device.
Reading IICSn
Executes processing corresponding to the operation to be executed

after checking the operation state of serial interface IICA.
Remark n = 0
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19.5.14 Communication reservation
(1) When communication reservation function is enabled (bit n (IICRSVn) of IICA flag register n (IICFn) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which the
bus is not used.
● When arbitration results in neither master nor slave operation

● When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 and saving communication).
If bit 1 (STTn) of the IICCTLn0 register is set to 1 while the bus is not used (after a stop condition is detected), a
start condition is automatically generated and wait state is set.
If an address is written to the IICA shift register n (IICAn) after bit 4 (SPIEn) of the IICCTLn0 register was set to 1,
and it was detected by generation of an interrupt request signal (INTIICAn) that the bus was released (detection of
the stop condition), then the device automatically starts communication as the master. Data written to the IICAn
register before the stop condition is detected is invalid.
When the STTn bit has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
● If the bus has been released ........................................ a start condition is generated

● If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using the MSTSn bit (bit 7 of the IICA status
register n (IICSn)) after the STTn bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STTn = 1 to checking the MSTSn flag:

(IICWLn setting value + IICWHn setting value + 4)/fMCK + tF × 2
Remarks 1. IICWLn: IICA low-level width setting register n

2. n=0
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Figure 19-26 shows the communication reservation timing.
Figure 19-26. Communication Reservation Timing
Write to
Program processing STTn = 1
IICAn
Communi- Set SPDn

Set
Hardware processing cation and
STDn
reservation INTIICAn
SCLAn 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6
SDAAn
Generate by master device with bus mastership
Remark IICAn: IICA shift register n

STTn: Bit 1 of IICA control register n0 (IICCTLn0)
STDn: Bit 1 of IICA status register n (IICSn)
SPDn: Bit 0 of IICA status register n (IICSn)
Communication reservations are accepted via the timing shown in Figure 19-27. After bit 1 (STDn) of the IICA
status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IICA
control register n0 (IICCTLn0) to 1 before a stop condition is detected.
Figure 19-27. Timing for Accepting Communication Reservations
SCLAn
SDAAn
STDn
SPDn
Standby mode (Communication can be reserved by setting STTn to 1 during this period.)
Figure 19-28 shows the communication reservation protocol.
Remark n = 0
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Figure 19-28. Communication Reservation Protocol
DI
SET1 STTn Sets STTn flag (communication reservation)
Define communication Defines that communication reservation is in effect

reservation (defines and sets user flag to any part of RAM)
Wait Secures wait timeNote 1 by software.
(Communication reservation)Note 2
MSTSn = 0? Confirmation of communication reservation
Yes
No
(Generate start condition)
Cancel communication
Clear user flag
reservation
MOV IICAn, #××H IICAn write operation
EI
Notes 1. The wait time is calculated as follows.

2. The communication reservation operation executes a write to the IICA shift register n (IICAn) when a
stop condition interrupt request occurs.
Remarks 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0)

MSTSn: Bit 7 of IICA status register n (IICSn)
IICAn: IICA shift register n
IICWLn: IICA low-level width setting register n
2. n = 0
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(2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1)
When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
● When arbitration results in neither master nor slave operation

● When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LRELn) of the IICCTLn0 register to 1 and saving communication)
To confirm whether the start condition was generated or request was rejected, check STCFn (bit 7 of the IICFn
register). It takes up to 5 clocks of fMCK until the STCFn bit is set to 1 after setting STTn = 1. Therefore, secure the
time by software.
Remark n = 0
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19.5.15 Cautions
(1) When STCENn = 0

Immediately after I2C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized
regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to
a master device communication mode, first generate a stop condition to release the bus, then perform master
device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register n1 (IICCTLn1).

<2> Set bit 7 (IICEn) of IICA control register n0 (IICCTLn0) to 1.
<3> Set bit 0 (SPTn) of the IICCTLn0 register to 1.
(2) When STCENn = 1

Immediately after I2C operation is enabled (IICEn = 1), the bus released status (IICBSYn = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STTn = 1), it is necessary to confirm that
the bus has been released, so as to not disturb other communications.
(3) If other I2C communications are already in progress

If I2C operation is enabled and the device participates in communication already in progress when the SDAAn pin
is low and the SCLAn pin is high, the macro of I2C recognizes that the SDAAn pin has gone low (detects a start
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I2C communications. To avoid this, start I2C in the following sequence.
<1> Clear bit 4 (SPIEn) of the IICCTLn0 register to 0 to disable generation of an interrupt request signal
(INTIICAn) when the stop condition is detected.
<2> Set bit 7 (IICEn) of the IICCTLn0 register to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LRELn) of the IICCTLn0 register to 1 before ACK is returned (4 to 72 clocks of fMCK after setting the
IICEn bit to 1), to forcibly disable detection.
(4) Setting the STTn and SPTn bits (bits 1 and 0 of the IICCTLn0 register) again after they are set and before they are
cleared to 0 is prohibited.
(5) When transmission is reserved, set the SPIEn bit (bit 4 of the IICCTLn0 register) to 1 so that an interrupt request is
generated when the stop condition is detected. Transfer is started when communication data is written to the IICA
shift register n (IICAn) after the interrupt request is generated. Unless the interrupt is generated when the stop
condition is detected, the device stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necessary to set the SPIEn bit to 1 when the MSTSn bit (bit 7 of the
IICA status register n (IICSn)) is detected by software.
Remark n = 0
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19.5.16 Communication operations

The following shows three operation procedures with the flowchart.
(1) Master operation in single master system

The flowchart when using the RL78/I1C as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings
at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system

In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the RL78/I1C takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the RL78/I1C looses in arbitration and is specified as the slave is omitted here, and only the
processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then,
wait for the communication request as the master or wait for the specification as the slave. The actual
communication is performed in the communication processing, and it supports the transmission/reception with the
slave and the arbitration with other masters.
(3) Slave operation

An example of when the RL78/I1C is used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for
the INTIICAn interrupt occurrence (communication waiting). When an INTIICAn interrupt occurs, the
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
Remark n = 0
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(1) Master operation in single-master system
Figure 19-29. Master Operation in Single-Master System
START
Setting the PER0 register Release the serial interface IICAn from the reset status and start clock supply.
2 Note
Initializing I C bus
Setting of the port used alternatively as the pin to be used.

Setting port First, set the port to input mode and the output latch to 0 (see 19.3.9 Port mode register 6 (PM6)).
IICWLn, IICWHn  XXH Sets a transfer clock.
SVAn  XXH Sets a local address.
IICFn  0XH
Sets a start condition.
Setting STCENn, IICRSVn = 0
Setting IICCTLn1
Initial setting
IICCTLn0  0XX111XXB
ACKEn = WTIMn = SPIEn = 1
IICCTLn0  1XX111XXB
IICEn = 1
Set the port from input mode to output mode and enable the output of the I2C bus
Setting port (see 19.3.9 Port mode register 6 (PM6)).
Yes
STCENn = 1?
No
Prepares for starting communication
SPTn = 1 (generates a stop condition).
INTIICAn No
interrupt occurs?
Waits for detection of the stop condition.
Yes
STTn = 1 Prepares for starting communication

(generates a start condition).
Starts communication
Writing IICAn (specifies an address and transfer
direction).
INTIICAn No
interrupt occurs? Waits for detection of acknowledge.
Yes
No
ACKDn = 1?
ACKEn = 1
Yes WTIMn = 0
No
TRCn = 1? Starts reception.
WRELn = 1
Yes
Communication processing
INTIICAn
No
Writing IICAn Starts transmission. interrupt occurs?
Waits for data
reception.
Yes
INTIICAn
No Reading IICAn
interrupt occurs?
Waits for data transmission.
Yes
End of transfer? No
ACKDn = 1? No
Yes
Yes
ACKEn = 0
No
End of transfer?
WTIMn = 1
Yes
WRELn = 1
No
Restart?
INTIICAn
No
SPTn = 1 interrupt occurs?
Yes Waits for detection
of acknowledge.
Yes
END
Note Release (SCLAn and SDAAn pins = high level) the I2C bus in conformance with the specifications of the product
that is communicating. If EEPROM is outputting a low level to the SDAAn pin, for example, set the SCLAn pin in
the output port mode, and output a clock pulse from the output port until the SDAAn pin is constantly at high level.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. n = 0
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(2) Master operation in multi-master system
Figure 19-30. Master Operation in Multi-Master System (1/3)
START
Setting port Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 19.3.9 Port mode register 6 (PM6)).
IICWLn, IICWHn ← XXH Selects a transfer clock.
SVAn ← XXH Sets a local address.
IICFn ← 0XH
Setting STCENn and IICRSVn
Setting IICCTLn1
IICCTLn0 ← 0XX111XXB
ACKE0n = WTIMn = SPIEn = 1
Initial setting
IICE0 = 1
Set the port from input mode to output mode and enable the output of the I 2C bus
Setting port
(see 19.3.9 Port mode register 6 (PM6)).
Releases the bus for a specific period.

Checking bus statusNote
Bus status is No
being checked. STCENn = 1?
Prepares for starting
No INTIICAn Yes SPTn = 1 communication
interrupt occurs? (generates a stop condition).
Yes
INTIICAn No
interrupt occurs?
No Waits for detection
SPDn = 1?
of the stop condition.
Yes
Yes Slave operation
No
SPDn = 1?
Yes
Slave operation
● Waiting to be specified as a slave by other master
1
● Waiting for a communication start request (depends on user program)
Master operation No
Waits for a communication
starts? (No communication start request)
Yes SPIEn = 0
(Communication start request)
INTIICAn No
SPIEn = 1 interrupt occurs?
Waits for a communication request.
Yes
IICRSVn = 0? No Slave operation
Yes
A B
Enables reserving Disables reserving
communication. communication.
Note Confirm that the bus is released (CLDn bit = 1, DADn bit = 1) for a specific period (for example, for a period of
one frame). If the SDAAn pin is constantly at low level, decide whether to release the I2C bus (SCLAn and
SDAAn pins = high level) in conformance with the specifications of the product that is communicating.
Remark n = 0
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A Enables reserving communication.

Wait Secure wait timeNote by software.

No
MSTSn = 1?
Yes INTIICAn No
interrupt occurs? Waits for bus release
(communication being reserved).
Yes
No
EXCn = 1 or COIn = 1?
Wait state after stop condition
was detected and start condition
was generated by the communication Yes
reservation function.
C Slave operation
Note The wait time is calculated as follows.

B Disables reserving communication.
No
IICBSYn = 0?
Yes
D

No
STCFn = 0?
Yes INTIICAn No
interrupt occurs? Waits for bus release
Yes
C
EXCn = 1 or COIn = 1? No
Detects a stop condition.
Yes
Slave operation D
Remarks 1. IICWLn: IICA low-level width setting register n

2. n=0
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Starts communication
Writing IICAn
(specifies an address and transfer direction).
INTIICAn No
interrupt occurs? Waits for detection of ACK.
Yes
No
MSTSn = 1?
Yes
2
No
ACKDn = 1?
ACKEn = 1
WTIMn = 0
Yes
No
TRCn = 1? WRELn = 1 Starts reception.
Yes
WTIMn = 1 INTIICAn No
interrupt occurs? Waits for data reception.
Yes
Writing IICAn Starts transmission.
No
MSTSn = 1?
INTIICAn No Yes
interrupt occurs? 2
Waits for data transmission.
Reading IICAn
Yes
No
MSTSn = 1? No
Transfer end?
Yes
2 Yes
No ACKEn = 0
ACKDn = 1?
Yes WTIMn = 1
No
Transfer end? WRELn = 1
Yes
INTIICAn No
interrupt occurs? Waits for detection of ACK.
No
Restart?
Yes
SPTn = 1
Yes
No
MSTSn = 1?
STTn = 1 END
Yes 2
C
No
EXCn = 1 or COIn = 1?
Yes 1
Slave operation Does not participate

in communication.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the device as a master in a multi-master system, read the MSTSn bit each time interrupt
INTIICAn has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICA status register
n (IICSn) and IICA flag register n (IICFn) each time interrupt INTIICAn has occurred, and determine the
processing to be performed next.
4. n=0
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(3) Slave operation

The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It is
also assumed that the INTIICAn interrupt servicing only performs status transition processing, and that actual data
communication is performed by the main processing.
INTIICAn Flag
Interrupt servicing
Setting
IICA Main processing
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing them
to the main processing instead of INTIICAn.
<1> Communication mode flag

This flag indicates the following two communication statuses.
● Clear mode: Status in which data communication is not performed
● Communication mode: Status in which data communication is performed (from valid address detection to
stop condition detection, no detection of ACK from master, address mismatch)
<2> Ready flag

This flag indicates that data communication is enabled. Its function is the same as the INTIICAn interrupt for
ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing.
Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by
interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag
being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag

This flag indicates the direction of communication. Its value is the same as the TRCn bit.
Remark n = 0
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The main processing of the slave operation is explained next.

Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and start
condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is completed.
For reception, the necessary amount of data is received. When communication is completed, ACK is not returned
as the next data. After that, the master generates a stop condition or restart condition. Exit from the
communication status occurs in this way.
Figure 19-31. Slave Operation Flowchart (1)
START
Setting port Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see19.3.9 Port mode register 6 (PM6)).
IICWLn, IICWHn ← XXH Selects a transfer clock.
SVAn ← XXH Sets a local address.

Initial setting
IICFn ← 0XH
Setting IICRSVn
Setting IICCTLn1
ACKEn = WTIMn = 1, SPIn = 0
IICEn = 1
Set the port from input mode to output mode and enable the output of the 2IC bus
Setting port (see 19.3.9 Port mode register 6 (PM6)).
No
Communication
mode flag = 1?
Yes
No
Communication
direction flag = 1?
Yes
Starts SPIEn = 1
Writing IICAn
transmission.
No Starts
Communication WRELn = 1
mode flag = 1? reception.
Yes
No No
Communication Communication
direction flag = 1? mode flag = 1?
Yes Yes
No No
Ready flag = 1? Communication
direction flag = 1?
Yes Yes
No
Clearing ready flag Ready flag = 1?
Yes
Yes
ACKDn = 1? Reading IICAn
No
Clearing communication
mode flag Clearing ready flag
WRELn = 1
Remarks 1. Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
2. n=0
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An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is
performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following
operations are performed.
<1> Communication is stopped if the stop condition is issued.

<2> If the start condition is issued, the address is checked and communication is completed if the address does
not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns
from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 19-32 Slave Operation Flowchart (2).
Figure 19-32. Slave Operation Flowchart (2)
INTIICAn generated
Yes <1>
SPDn = 1?
No
Yes <2>
STDn = 1?
No No
COIn = 1?
<3>
Yes
Set ready flag
Communication direction flag

← TRCn Clear communication direction
Set communication mode flag flag, ready flag, and
Clear ready flag communication mode flag
Interrupt servicing completed
Remark n = 0
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19.5.17 Timing of I2C interrupt request (INTIICAn) occurrence

The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of
the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Remarks 1. ST: Start condition

AD6 to AD0: Address
R/W: Transfer direction specification
ACK: Acknowledge
D7 to D0: Data
SP: Stop condition
2. n=0
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(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIMn = 0
SPTn = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP

1 2 3 4 5
1: IICSn = 1000×110B
2: IICSn = 1000×000B
3: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note
4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn
interrupt request signal.
Remark : Always generated

: Generated only when SPIEn = 1
×: Don’t care
(ii) When WTIMn = 1
SPTn = 1

1 2 3 4
1: IICSn = 1000×110B
2: IICSn = 1000×100B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIMn = 0
STTn = 1 SPTn = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
1 2 3 4 5 6 7
1: IICSn = 1000×110B
2: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note 1
3: IICSn = 1000××00B (Clears the WTIMn bit to 0Note 2, sets the STTn bit to 1)
4: IICSn = 1000×110B
5: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note 3
7: IICSn = 00000001B
Notes 1. To generate a start condition, set the WTIMn bit to 1 and change the timing for generating the
INTIICAn interrupt request signal.
2. Clear the WTIMn bit to 0 to restore the original setting.
3. To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the
INTIICAn interrupt request signal.

×: Don’t care
(ii) When WTIMn = 1
STTn = 1 SPTn = 1
1 2 3 4 5
1: IICSn = 1000×110B
2: IICSn = 1000××00B (Sets the STTn bit to 1)
3: IICSn = 1000×110B
5: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission)
(i) When WTIMn = 0
SPTn = 1

1 2 3 4 5
1: IICSn = 1010×110B
2: IICSn = 1010×000B
3: IICSn = 1010×000B (Sets the WTIMn bit to 1)Note
5: IICSn = 00000001B
Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn
interrupt request signal.

×: Don’t care
(ii) When WTIMn = 1
SPTn = 1

1 2 3 4
1: IICSn = 1010×110B
2: IICSn = 1010×100B
4: IICSn = 00001001B

×: Don’t care
Remark n = 0
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(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIMn = 0

1 2 3 4
1: IICSn = 0001×110B
2: IICSn = 0001×000B
3: IICSn = 0001×000B
4: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1

1 2 3 4
1: IICSn = 0001×110B
2: IICSn = 0001×100B
3: IICSn = 0001××00B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, matches with SVAn)
1 2 3 4 5
1: IICSn = 0001×110B
2: IICSn = 0001×000B
3: IICSn = 0001×110B
4: IICSn = 0001×000B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, matches with SVAn)
1 2 3 4 5
1: IICSn = 0001×110B
2: IICSn = 0001××00B
3: IICSn = 0001×110B
4: IICSn = 0001××00B
5: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, does not match address (= extension code))
1 2 3 4 5
1: IICSn = 0001×110B
2: IICSn = 0001×000B
3: IICSn = 0010×010B
4: IICSn = 0010×000B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, does not match address (= extension code))
1 2 3 4 5 6
1: IICSn = 0001×110B
2: IICSn = 0001××00B
3: IICSn = 0010×010B
4: IICSn = 0010×110B
5: IICSn = 0010××00B
6: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, does not match address (= not extension code))
1 2 3 4
1: IICSn = 0001×110B
2: IICSn = 0001×000B
3: IICSn = 00000×10B
4: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, does not match address (= not extension code))
1 2 3 4
1: IICSn = 0001×110B
2: IICSn = 0001××00B
3: IICSn = 00000×10B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(3) Slave device operation (when receiving extension code)

The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIMn = 0

1 2 3 4
1: IICSn = 0010×010B
2: IICSn = 0010×000B
3: IICSn = 0010×000B
4: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1

1 2 3 4 5
1: IICSn = 0010×010B
2: IICSn = 0010×110B
3: IICSn = 0010×100B
4: IICSn = 0010××00B
5: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, matches SVAn)
1 2 3 4 5
1: IICSn = 0010×010B
2: IICSn = 0010×000B
3: IICSn = 0001×110B
4: IICSn = 0001×000B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, matches SVAn)
1 2 3 4 5 6
1: IICSn = 0010×010B
2: IICSn = 0010×110B
3: IICSn = 0010××00B
4: IICSn = 0001×110B
5: IICSn = 0001××00B
6: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, extension code reception)
1 2 3 4 5
1: IICSn = 0010×010B
2: IICSn = 0010×000B
3: IICSn = 0010×010B
4: IICSn = 0010×000B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, extension code reception)
1 2 3 4 5 6 7
1: IICSn = 0010×010B
2: IICSn = 0010×110B
3: IICSn = 0010××00B
4: IICSn = 0010×010B
5: IICSn = 0010×110B
6: IICSn = 0010××00B
7: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIMn = 0 (after restart, does not match address (= not extension code))
1 2 3 4
1: IICSn = 0010×010B
2: IICSn = 0010×000B
3: IICSn = 00000×10B
4: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1 (after restart, does not match address (= not extension code))
1 2 3 4 5
1: IICSn = 0010×010B
2: IICSn = 0010×110B
3: IICSn = 0010××00B
4: IICSn = 00000×10B
5: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop

1
1: IICSn = 00000001B
Remark : Generated only when SPIEn = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)

When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request
signal INTIICAn has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIMn = 0

1 2 3 4
1: IICSn = 0101×110B
2: IICSn = 0001×000B
3: IICSn = 0001×000B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(ii) When WTIMn = 1

1 2 3 4
1: IICSn = 0101×110B
2: IICSn = 0001×100B
3: IICSn = 0001××00B
4: IICSn = 00000001B

×: Don’t care
(b) When arbitration loss occurs during transmission of extension code
(i) When WTIMn = 0

1 2 3 4
1: IICSn = 0110×010B
2: IICSn = 0010×000B
3: IICSn = 0010×000B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(ii) When WTIMn = 1

1 2 3 4 5
1: IICSn = 0110×010B
2: IICSn = 0010×110B
3: IICSn = 0010×100B
4: IICSn = 0010××00B
5: IICSn = 00000001B

×: Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request
signal INTIICAn has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIMn = 1)

1 2
1: IICSn = 01000110B
2: IICSn = 00000001B

Remark n = 0
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(b) When arbitration loss occurs during transmission of extension code

1 2
1: IICSn = 0110×010B
Sets LRELn = 1 by software
2: IICSn = 00000001B

×: Don’t care
(c) When arbitration loss occurs during transmission of data
(i) When WTIMn = 0

1 2 3
1: IICSn = 10001110B
2: IICSn = 01000000B
3: IICSn = 00000001B

Remark n = 0
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(ii) When WTIMn = 1

1 2 3
1: IICSn = 10001110B
2: IICSn = 01000100B
3: IICSn = 00000001B

(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVAn)
ST AD6 to AD0 R/W ACK D7 to Dm ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
1 2 3
1: IICSn = 1000×110B
2: IICSn = 01000110B
3: IICSn = 00000001B

×: Don’t care
m = 6 to 0
Remark n = 0
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(ii) Extension code
ST AD6 to AD0 R/W ACK D7 to Dm ST AD6 to AD0 R/W ACK D7 to D0 ACK SP

1 2 3
1: IICSn = 1000×110B
2: IICSn = 01100010B
Sets LRELn = 1 by software
3: IICSn = 00000001B

×: Don’t care
m = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 R/W ACK D7 to Dm SP

1 2
1: IICSn = 10000110B
2: IICSn = 01000001B

×: Don’t care
m = 6 to 0
Remark n = 0
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(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIMn = 0
STTn = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK D7 to D0 ACK SP

1 2 3 4 5
1: IICSn = 1000×110B
2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
3: IICSn = 1000×100B (Clears the WTIMn bit to 0)
4: IICSn = 01000000B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1
STTn = 1
1 2 3 4
1: IICSn = 1000×110B
2: IICSn = 1000×100B (Sets the STTn bit to 1)
3: IICSn = 01000100B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition
(i) When WTIMn = 0
STTn = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP

1 2 3 4
1: IICSn = 1000×110B
4: IICSn = 01000001B

×: Don’t care
(ii) When WTIMn = 1
STTn = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
1 2 3
1: IICSn = 1000×110B
3: IICSn = 01000001B

×: Don’t care
Remark n = 0
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(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIMn = 0
SPTn = 1

1 2 3 4 5
1: IICSn = 1000×110B
3: IICSn = 1000×100B (Clears the WTIMn bit to 0)
4: IICSn = 01000100B
5: IICSn = 00000001B

×: Don’t care
(ii) When WTIMn = 1
SPTn = 1

1 2 3 4
1: IICSn = 1000×110B
2: IICSn = 1000×100B (Sets the SPTn bit to 1)
3: IICSn = 01000100B
4: IICSn = 00000001B

×: Don’t care
Remark n = 0
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19.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 19-33 and 19-34 show timing charts of the data communication.
The IICA shift register n (IICAn)’s shift operation is synchronized with the falling edge of the serial clock (SCLAn). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAAn pin.
Data input via the SDAAn pin is captured into IICAn at the rising edge of SCLAn.
Remark n = 0
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Figure 19-33. Example of Master to Slave Communication

(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
(1) Start condition ~ address ~ data
Master side
Note 1
IICAn
<2> <5>
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait) H
ACKEn
(ACK control) H
MSTSn
(communication status)
STTn
(ST trigger) <1>
SPTn
(SP trigger) L
WRELn
(wait cancellation) L
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line Start condition

SCLAn (bus)
(clock line)
Note 2 <4>
SDAAn (bus)
(data line) AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D17
Slave address <3>
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait) H
ACKEn
(ACK control) H
MSTSn
(communication status) L
WRELn Note 3
<6>
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive) L
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master
device.
2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is
at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode.
3. For releasing wait state during reception of a slave device, write “FFH” to IICAn or set the WRELn bit.
Remark n = 0
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The following is a description of the Figure 19-33 (1) Start condition ~ address ~ data <1> to <6>.
<1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1
changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start
condition is subsequently detected, the master device enters the master device communication status
(MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0)
after the hold time has elapsed.
<2> The master device writes the address + W (transmission) to the IICA shift register n (IICAn) and transmits
the slave address.
<3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that
slave device sends an ACK by hardware to the master device. The ACK is detected by the master device
(ACKDn = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th
clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn =
0) and issues an interrupt (INTIICAn: address match)Note.
<5> The master device writes the data to transmit to the IICAn register and releases the wait status that it set by
the master device.
<6> If the slave device releases the wait status (WRELn = 1), the master device starts transferring data to the
slave device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn
interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remarks 1. <1> to <15> in Figure 19-33 represent the entire procedure for communicating data using the I2C
bus.
Figure 19-33 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure
19-33 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 19-33 (3)
Data ~ data ~ stop condition shows the processing from <7> to <15>.
2. n=0
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(2) Address ~ data ~ data
Master side
Note 1 Note 1
IICAn
<5> <9>
ACKDn
(ACK detection)
WTIMn H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
(communication status) H
STTn
(ST trigger) L
SPTn
(SP trigger) L
WRELn
INTIICAn
(interrupt)
TRCn
(transmit/receive) H
Bus line
SCLAn (bus)
(clock line)
<4> <8>
SDAAn (bus)
W ACK D 17 D16 D15 D14 D13 D 12 D11 D10 ACK D27
(data line)
<3> <7>
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection) L
WTIMn H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
WRELn <6> <10>
Note 2 Note 2
(wait cancellation)
INTIICAn
(interrupt)
TRCn
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a
master device.
Remark n = 0
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The following is a description of the Figure 19-33 (2) Address ~ data ~ data <3> to <10>.
<5> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait
status that it set by the master device.
<6> If the slave device releases the wait status (WRELn = 1), the master device starts transferring data to the
slave device.
<7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the
master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock.
<8> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICAn: end of transfer).
<9> The master device writes the data to transmit to the IICAn register and releases the wait status that it set by
the master device.
<10> The slave device reads the received data and releases the wait status (WRELn = 1). The master device
then starts transferring data to the slave device.
bus.
2. n=0
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(3) Data ~ data ~ Stop condition
Master side
Note 1
IICAn
<9>
ACKDn
(ACK detection)
WTIMn
H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
STTn
(ST trigger) L
SPTn
(SP trigger)
WRELn <14>
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line Stop condition
SCLAn (bus)
(clock line)
<8> <12>
SDAAn (bus)
D150 ACK D167 D166 D165 D164 D163 D162 D161 D160 ACK
(data line)
<7> <11> Note 2
Slave side <15>
IICAn
ACKDn
(ACK detection)
STDn
(ST detection) L
SPDn
(SP detection)
WTIMn H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
WRELn
<10> Note 3 <13> Note 3
(wait cancellation)
INTIICAn
(interrupt)
TRCn
: Wait state by master device
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master
device.
2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop
condition after a stop condition has been issued is at least 4.0 µs when specifying standard mode and
at least 0.6 µs when specifying fast mode.
Remark n = 0
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The following is a description of the Figure 19-33 (3) Data ~ data ~ stop condition <7> to <15>.
<9> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait
status that it set by the master device.
<10> The slave device reads the received data and releases the wait status (WRELn = 1). The master device
then starts transferring data to the slave device.
<11> When data transfer is complete, the slave device (ACKEn =1) sends an ACK by hardware to the master
device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock.
<13> The slave device reads the received data and releases the wait status (WRELn = 1).
<14> By the master device setting a stop condition trigger (SPTn = 1), the bus data line is cleared (SDAAn = 0)
and the bus clock line is set (SCLAn = 1). After the stop condition setup time has elapsed, by setting the
bus data line (SDAAn = 1), the stop condition is then generated (i.e. SCLAn =1 changes SDAAn from 0 to
1).
<15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt
(INTIICAn: stop condition).
bus.
2. n=0
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(4) Data ~ restart condition ~ address
Master side
IICAn
<iii>
ACKDn
(ACK detection)
WTIMn
H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
STTn
(ST trigger) <ii>
SPTn
(SP trigger) L
WRELn
INTIICAn
(interrupt)
TRCn
Bus line Restart condition

SCLAn (bus)
(clock line)
<8>
SDAAn (bus)
D13 D12 D11 D10 ACK AD6 AD5 AD4 AD3 AD2 AD1
(data line)
<7> Slave address
Note 1
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection) L
WTIMn
H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
L
WRELn Note 2
<i>
(wait cancellation)
INTIICAn
(interrupt)
TRCn
Notes 1. Make sure that the time between the rise of the SCLAn pin signal and the generation of the start
condition after a restart condition has been issued is at least 4.7 µs when specifying standard mode and
at least 0.6 µs when specifying fast mode.
Remark n = 0
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The following describes the operations in Figure 19-33 (4) Data ~ restart condition ~ address. After the
operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the
processing to step <iii>, the data transmission step.
<i> The slave device reads the received data and releases the wait status (WRELn = 1).
<ii> The start condition trigger is set again by the master device (STTn = 1) and a start condition (i.e. SCLAn =1
changes SDAAn from 1 to 0) is generated once the bus clock line goes high (SCLAn = 1) and the bus data
line goes low (SDAAn = 0) after the restart condition setup time has elapsed. When the start condition is
subsequently detected, the master device is ready to communicate once the bus clock line goes low
(SCLAn = 0) after the hold time has elapsed.
<iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICAn) enables the
slave address to be transmitted.
Remark n = 0
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Figure 19-34. Example of Slave to Master Communication

(1) Start condition ~ address ~ data
Master side
IICAn
<2>
ACKDn
(ACK detection)
WTIMn <5>
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
STTn <1>
(ST trigger)
SPTn
(SP trigger) L
WRELn <7> Note 1

(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line Start condition
SCLAn (bus)
(clock line)
Note 2 <4>
SDAAn (bus)
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R ACK D17
(data line)
Slave address <3>
Slave side
Note 3
IICAn
<6>
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
WRELn
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Notes 1. For releasing wait state during reception of a master device, write “FFH” to IICAn or set the WRELn bit.
2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is
at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode.
3. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a
slave device.
Remark n = 0
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The following is a description of the Figure 19-34 (1) Start condition ~ address ~ data <1> to <7>.
<1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1
changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start
condition is subsequently detected, the master device enters the master device communication status
(MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0)
after the hold time has elapsed.
<2> The master device writes the address + R (reception) to the IICA shift register n (IICAn) and transmits the
slave address.
<5> The timing at which the master device sets the wait status changes to the 8th clock (WTIMn = 0).
<6> The slave device writes the data to transmit to the IICAn register and releases the wait status that it set by
the slave device.
<7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device
to the master device.
bus.
2. n=0
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(2) Address ~ data ~ data
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait) <5>
ACKEn
(ACK control) H
MSTSn
STTn
(ST trigger) L
SPTn
(SP trigger) L
WRELn Note 1 Note 1

(wait cancellation)
INTIICAn <7> <9>
(interrupt)
TRCn
L
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
<4> <8> <11>
SDAAn (bus)
(data line) R ACK D17 D16 D15 D14 D13 D12 D11 D10 ACK D27
<3> <10>
Slave side
IICAn
<6> Note 2 <12> Note 2
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection) L
WTIMn
H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
WRELn
INTIICAn
(interrupt)
TRCn
Notes 1. For releasing wait state during reception of a master device, write “FFH” to IICAn or set the WRELn bit.
slave device.
Remark n = 0
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The following is a description of the Figure 19-34 (2) Address ~ data ~ data <3> to <12>.
<5> The master device changes the timing of the wait status to the 8th clock (WTIMn = 0).
<6> The slave device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status
that it set by the slave device.
<7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device
to the master device.
<8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICAn: end of transfer). Because of ACKEn = 1 in the master device, the master device then
sends an ACK by hardware to the slave device.
<9> The master device reads the received data and releases the wait status (WRELn = 1).
<10> The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and the slave device
issue an interrupt (INTIICAn: end of transfer).
<12> By the slave device writing the data to transmit to the IICAn register, the wait status set by the slave device
is released. The slave device then starts transferring data to the master device.
bus.
2. n=0
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(8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Data ~ data ~ stop condition
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
<14>
ACKEn
(ACK control)
MSTSn
STTn
(ST trigger) L
SPTn
(SP trigger)
WRELn Note 1 Note 1 <17>
(wait cancellation)
INTIICAn <9> <15>
(interrupt)
TRCn
Bus line Stop condition
SCLAn (bus)
(clock line)
<8> <11> <13> <16>
SDAAn (bus) Note 2
(data line) D150 ACK D167 D166 D165 D164 D163 D162 D161 D160 NACK
<10>
Slave side
<19>
IICAn
<12> Note 3
ACKDn
(ACK detection)
STDn
(ST detection) L
SPDn
(SP detection)
WTIMn
H
(8 or 9 clock wait)
ACKEn
(ACK control) H
MSTSn
(communication L
status) <18>
WRELn Notes 1, 4
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive) Note 4
Notes 1. To cancel a wait state, write “FFH” to IICAn or set the WRELn bit.
2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop
condition after a stop condition has been issued is at least 4.0 µs when specifying standard mode and at
least 0.6 µs when specifying fast mode.
slave device.
4. If a wait state during transmission by a slave device is canceled by setting the WRELn bit, the TRCn bit
will be cleared.
Remark n = 0
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The following is a description of the Figure 19-34 (3) Data ~ data ~ stop condition <8> to <19>.
<8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICAn: end of transfer). Because of ACKEn = 0 in the master device, the master device then
sends an ACK by hardware to the slave device.
<9> The master device reads the received data and releases the wait status (WRELn = 1).
<10> The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and the slave device
issue an interrupt (INTIICAn: end of transfer).
<12> By the slave device writing the data to transmit to the IICA register, the wait status set by the slave device is
released. The slave device then starts transferring data to the master device.
<13> The master device issues an interrupt (INTIICAn: end of transfer) at the falling edge of the 8th clock, and
sets a wait status (SCLAn = 0). Because ACK control (ACKEn = 1) is performed, the bus data line is at the
low level (SDAAn = 0) at this stage.
<14> The master device sets NACK as the response (ACKEn = 0) and changes the timing at which it sets the
wait status to the 9th clock (WTIMn = 1).
<15> If the master device releases the wait status (WRELn = 1), the slave device detects the NACK (ACK = 0) at
the rising edge of the 9th clock.
<17> When the master device issues a stop condition (SPTn = 1), the bus data line is cleared (SDAAn = 0) and
the master device releases the wait status. The master device then waits until the bus clock line is set
(SCLAn = 1).
<18> The slave device acknowledges the NACK, halts transmission, and releases the wait status (WRELn = 1)
to end communication. Once the slave device releases the wait status, the bus clock line is set (SCLAn =
1).
<19> Once the master device recognizes that the bus clock line is set (SCLAn = 1) and after the stop condition
setup time has elapsed, the master device sets the bus data line (SDAAn = 1) and issues a stop condition
(i.e. SCLAn =1 changes SDAAn from 0 to 1). The slave device detects the generated stop condition and
slave device issue an interrupt (INTIICAn: stop condition).
bus.
2. n=0
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RL78/I1C CHAPTER 20 IrDA
CHAPTER 20 IrDA
The IrDA sends and receives IrDA data communication waveforms in cooperation with the Serial Array Unit (SAU)
based on the IrDA (Infrared Data Association) standard 1.0.
20.1 Functions of IrDA
Enabling the IrDA function by using the IRE bit in the IRCR register allows encoding and decoding the TxD2 and RxD2
signals of the SAU to the waveforms conforming to the IrDA standard 1.0 (IrTxD and IrRxD pins). Connecting these
waveforms to an infrared transmitter/receiver implements infrared data communication conforming to the IrDA standard
1.0 system.
With the IrDA standard 1.0 system, data transfer can be started at 9600 bps and the transfer rate can be changed
whenever necessary. Since the IrDA cannot change the transfer rate automatically, the transfer rate should be changed
through software.
When the high-speed on-chip oscillator (fIH =24/12/6/3 MHz) is selected, the following baud rates can be selected:
● 115.2 kbps/57.6 kbps/38.4 kbps/19.2 kbps/9600 bps/2400 bps
Figures 20-1 is a block diagram showing cooperation between IrDA and SAU.
Figure 20-1. Block Diagram Showing Cooperation Between IrDA and SAU
SAU (unit 1) IrDA
IRE bit = 0
TxD2
TxD2/IrTxD
Pulse encoder Phase inverter
IRE bit = 1 IRE bit = 1
Pulse encoder Phase inverter
RxD2
RxD2/IrRxD
IRE bit = 0
IRE IRCKS2-0 IRTXINV IRRXINV
IrDA control register (IRCR)
Table 20-1. IrDA Pin Configuration
Pin Name I/O Function
IrTxD Output Outputs data to be transmitted.

IrRxD Input Inputs received data.
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20.2 Registers
Table 20-2 lists the IrDA register configuration.
Table 20-2. IrDA Register Configuration
Item Configuration
IrDA control register (IRCR)

When the IrDA is used, be sure to set bit 6 (IRDAEN) of this register to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
IRDAEN Control of IrDA input clock supply

● SFR used by IrDA cannot be written. The read value is 00H. However, the SFR is not
initialized. Note
● SFR used by IrDA can be read and written.
Note To initialize the IrDA and the SFR used by the IrDA, use bit 6 (IRDARES) of PRR0.
Cautions 1. When setting the IrDA, be sure to set the IRDAEN bit to 1 first.
If IRDAEN = 0, writing to a control register of the IrDA is ignored, and read value of
the register is all the initial value.
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To reset the IrDA, be sure to set bit 6 (IRDARES) to 1.

Symbol 7 <6> <5> <4> <3> <2> 1 <0>
IRDARES Control resetting of the IrDA
0 Releases the IrDA from the reset state.

1 The IrDA is in the reset state.
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20.2.3 IrDA control register (IRCR)

The IRCR register is used to control the IrDA function. This register is used to switch the polarity of receive data and
transmit data, select the IrDA clock, and select the serial I/O pin function (normal serial function or IrDA function).
The IRCR register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 20-4. Format of IrDA Control Register (IRCR)
Address: F03A0H After reset: 00H R/W

Symbol <7> 6 5 4 <3> <2> 1 0
IRCR IRE IRCKS2 IRCKS2 IRCKS0 IRTXINV IRRXINV 0 0
IRE IrDA enable
0 Serial I/O pins are used for normal serial communication.

1 Serial I/O pins are used for IrDA data communication.
IRCKS2 IRCKS1 IRCKS0 IrDA clock selection
0 0 0 B × 3/16 (B = bit rate)

0 0 1 fCLK/2
0 1 0 fCLK/4
0 1 1 fCLK/8
1 0 0 fCLK/16
1 0 1 fCLK/32
1 1 0 fCLK/64
1 1 1 Setting prohibited
IRTXINV IrTxD data polarity switching
0 Data to be transmitted is output to IrTxD as is.

1 Data to be transmitted is output to IrTxD after the polarity is inverted.
IRRXINV IrRxD data polarity switching
0 IrRxD input is used as received data as is.

1 IrRxD input is used as received data after the polarity is inverted.
Cautions 1. Be sure to clear bits 1 and 0 to “0”.

2. IRCKS[2:0], IRTXINV, and IRRXINV can be set only when IRE bit is 0.
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20.3 Operation
20.3.1 IrDA communication operation procedure
(1) IrDA Communication Initial configuration flow

Perform IrDA initial configuration as follows:
<1> Set PER0 register bit IRDAEN to 1.

<2> Set the IRCR register.
<3> Set the SAU related registers (refer to the UART mode configuration procedure).
(2) IrDA communication termination flow
<1> Configure the port register and port mode register to set the status of the IrTxD pin after stopping IrDA
communication.
Remark The output status may change because the IrTxD pin changes to normal serial interface UART data
output when IrDA is reset in step 3.
● To output low level from IrTxD pin

Set port register to 0. Immediately after this, the IrTxD pin is fixed at low level.
● To output high level from IrTxD pin
Set port register to 1. This will fix IrTxD pin at high level immediately after IrDA reset in step 3.
● To set IrTxD pin to Hi-Z status
Set port mode register to 1. Immediately after this, IrTxD pin is set to Hi-Z.
<2> Set STm register (SAU related register) bits STm0 and STm1 to 1 (stop SAU channels 0 and 1).
<3> Set PER0 register bit IRDAEN to 0 and reset IrDA.
Do not set STm register bits STm0 and STm1 to 1 or IrDA bit IRE to 0 with any procedure other than the above.
(3) Procedure when IrDA framing error occurs

If a framing error occurs during IrDA communication, the following procedure is necessary to enable receiving of
subsequent data.
<1> Set SAU STm register bit STm1 to 1 (stop SAU CH1 operation)
<2> Set SAU SSm register bit SSm1 to 1 (start SAU CH1 operation)
Remark m: Unit number (m = 0, 1)
Also refer to the chapter on SAU for information on SAU framing error processing.
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20.3.2 Transmission
In transmission, the signals output from the SAU (UART frames) are converted to the IR frame data through the IrDA
(see Figure 20-5). When IRTXINV bit is 0 and serial data is 0, high-level pulses with the width of 3/16 the bit rate (1-bit
width period) are output (initial setting). The high-level pulse width can be changed by using the IRCKS2 to IRCKS0 bits.
The standard prescribes that the minimum high-level pulse width should be 1.41 µs and the maximum high-level pulse
width be (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs.
When the CPU/peripheral hardware clock (fCLK) is 20 MHz, the high-level pulse width can be 1.41 µs to 1.6 µs.
When serial data is 1, no pulses are output.
Figure 20-5. IrDA Transmission/Reception
UART frame
Data
Start bit Stop bit
0 1 0 1 0 0 1 1 0 1
Transmission Reception
IR frame
Data
Start bit Stop bit
0 1 0 1 0 0 1 1 0 1
Bit Pulse width is 1.4 µs to 3/16

period Bit period + 1.08 µs
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20.3.3 Reception
In reception, the IR frame data is converted to the UART frame data through the IrDA and is input to the SAU.
Low-level data is output when the IRRXINV bit is 0 and a high-level pulse is detected, and high-level data is output
when no pulse is detected for 1-bit period. Note that a pulse shorter than 1.41 µs, which is the minimum pulse width, is
identified as a low signal.
20.3.4 Selecting high-level pulse width

When the pulse width should be shorter than the bit rate × 3/16 for transmission, applicable IRCKS2 to IRCKS0 bit
settings (minimum pulse width) and the corresponding high-level pulse widths shown in Table 20-4 can be used.
Table 20-4. IRCKS2 to IRCKS0 Bit Settings
fCLK Item <Upper Row> Bit Rate [kbps]

[MHz] <Lower Row> Bit Rate × 3/16 [µs]
2.4 9.6 19.2 38.4 57.6 115.2
78.13 19.53 9.77 4.87 3.26 1.63
1 IRCKS2 to IRCKS0 001 001 001 – – –
Note 1 Note 1
High-level pulse width [µs] 2.00 2.00 2.00 – – –Note 1
2 IRCKS2 to IRCKS0 010 010 010 010 010 –Note 1
High-level pulse width [µs] 2.00 2.00 2.00 2.00 2.00 –Note 1
3 IRCKS2 to IRCKS0 011 011 011 011 011 –Note 1
High-level pulse width [µs] 2.67 2.67 2.67 2.67 2.67 –Note 1
4 IRCKS2 to IRCKS0 011 011 011 011 011 000Note 2
High-level pulse width [µs] 2.00 2.00 2.00 2.00 2.00 1.50
Note 2
6 IRCKS2 to IRCKS0 100 100 100 100 100 000
Note 2
8 IRCKS2 to IRCKS0 100 100 100 100 100 000
Note 2
12 IRCKS2 to IRCKS0 101 101 101 101 101 000
16 IRCKS2 to IRCKS0 101 101 101 101 101 000Note 2
Note 2
24 IRCKS2 to IRCKS0 110 110 110 110 110 000
Note 2
32 IRCKS2 to IRCKS0 110 110 110 110 110 000
Notes 1. “–” indicates that the communication specification cannot be satisfied.

2. The pulse width cannot be shorter than the bit rate × 3/16.
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20.4 Usage Notes on IrDA
(1) The IrDA function cannot be used to transition to SNOOZE via IrRxD reception.
(2) The input of IrDA operating clock can be disabled/enabled with the peripheral enable register. Initially, register
access is disabled because clock input is disabled. Enable IrDA operating clock input with the peripheral enable
register before setting the register.
(3) During HALT mode, the IrDA function continues to run.
(4) The use of SAU initialization function (SS bit= 1) is prohibited during IrDA communication.
(5) The IRCR register bits IRRXINV, IRTXINV, and IRCKS[2:0] can be set only when IRE bit is 0.
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RL78/I1C CHAPTER 21 LCD CONTROLLER/DRIVER
CHAPTER 21 LCD CONTROLLER/DRIVER
The number of LCD display function pins of the RL78/I1C differs depending on the product. The following table shows
the number of pins of each product.
Table 21-1. Number of LCD Display Function Pins of Each Product
Item RL78/I1C
64 pins (R5F10NLx (x = G, E)) 80 pins (R5F10NMx (x = J, G, E)) 100 pins (R5F10NPx (x = J, G))
Note Note
LCD controller/driver Segment signal outputs: 19 (15) Segment signal outputs: 34 (30) Segment signal outputs: 42 (38)Note
Common signal outputs: 8 Common signal outputs: 8 Common signal outputs: 8
Multiplexed I/O port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Segment P0 – – – – – – – – SEG SEG SEG SEG SEG SEG – – – – – – – – – –
37 36 35 34 33 32
P1 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
11 10 9 8 7 6 5 4 11 10 9 8 7 6 5 4 11 10 9 8 7 6 5 4
P3 – – – – – – SEG SEG – – – – SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
25 24 27 26 25 24 31 30 29 28 27 26 25 24
P5 – – – – – – – – – – – – – – – – SEG SEG SEG SEG SEG SEG SEG SEG
39 38 37 36 35 34 33 32
P7 – – – SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
20 19 18 17 16 23 22 21 20 19 18 17 16 23 22 21 20 19 18 17 16
P8 – – – – – – – – – – – – SEG SEG SEG SEG – – SEG SEG SEG SEG SEG SEG
15 14 13 12 41 40 15 14 13 12
Alternate relationship –
between COM signal
output pins and I/O
pots
Alternate COM SEG0 SEG0 SEG0
relationship 4
between COM
COM SEG1 SEG1 SEG1
signal output
5
pins and
LCD display COM SEG2 SEG2 SEG2
function pins 6
COM SEG3 SEG3 SEG3
Note ( ) indicates the number of signal output pins when 8 com is used.
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21.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver in the RL78/I1C microcontrollers are as follows.
(1) Waveform A or B selectable

(2) The LCD driver voltage generator can switch internal voltage boosting method, capacitor split method, and
external resistance division method.
(3) Automatic output of segment and common signals based on automatic display data register read
(4) The reference voltage to be generated when operating the voltage boost circuit can be selected from 16 steps
(contrast adjustment).
(5) LCD blinking is available
Table 21-2 lists the maximum number of pixels that can be displayed in each display mode.
Table 21-2. Maximum Number of Pixels (1/3)
(a) 64-pin products
Drive Waveform for LCD Driver Voltage Bias Mode Number of Time Maximum Number of Pixels
LCD Driver Generator Slices
Waveform A External resistance – Static 19 (19 segment signals, 1 common signal)
division 1/2 2 38 (19 segment signals, 2 common signals)
3 57 (19 segment signals, 3 common signals)
1/3 3
1/4 8
Internal voltage 1/3 3 57 (19 segment signals, 3 common signals)
boosting 4 76 (19 segment signals, 4 common signals)
1/4 6 102 (17 segment signals, 6 common signals)
Capacitor split 1/3 3 57 (19 segment signals, 3 common signals)
Waveform B External resistance 1/3 3 57 (19 segment signals, 3 common signals)
division, internal 4 76 (19 segment signals, 4 common signals)
voltage boosting 6 102 (17 segment signals, 6 common signals)
1/4 8

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(b) 80-pin products
1/3 3
1/4 8
1/4 8
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(c) 100-pin products
1/3 3
1/4 8
1/4 8
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21.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
Table 21-3. Configuration of LCD Controller/Driver
Item Configuration
Control registers LCD mode register 0 (LCDM0)

LCD mode register 1 (LCDM1)
LCD clock control register 0 (LCDC0)
LCD boost level control register (VLCD)
LCD input switch control register (ISCLCD)
LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)
Port mode registers 0, 1, 3, 5, 7, 8 (PM0, PM1, PM3, PM5, PM7, PM8)
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RL78/I1C
Figure 21-1. Block Diagram of LCD Controller/Driver
Aug 31, 2018

Internal bus
Subsystem clock LCD clock control LCD mode LCD boost level control Display data memory
supply option control register 0 (LCDC0) register 0 (LCDM0) register (VLCD)
R01UH0587EJ0200 Rev.2.00
register (OSMC) 00H ........... 03H 04H ........... 29H
WUTMMCK0 LCDC5 LCDC4 LCDC3 LCDC2 LCDC1 LCDC0 LCTY2 LCTY1 LCTY0 LBAS1 LBAS0 LWAVE VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 76543210 76543210 76543210 76543210
6 5
6
fSUB
fLCD
LCD LCDCL
Selector
fIL clock
fMAIN selector
........... ...........
Timing
controller
Clock generator 76543210 76543210 76543210 ........... 76543210
for Clock generator VLCON
INTRTCPRD Selector Selector Selector Selector
capacitor split for voltage boost
LCDON LCDON LCDON LCDON
........... ...........
Capacitor split Voltage boost
circuit circuit ......... .........
Segment voltage ........... ...........
.........
........... .........
...........
controller
LCD drive voltage controller Common voltage

Common driver Segment ........... Segment Segment ........... Segment
controller driver driver driver driver
. . . . . . . .
. . . . . . . . . .
CAPH CAPL VL1 VL2 VL3 VL4 COM0 . . . . COM3 COM4/ . . . . COM7/ SEG4 SEG41
SEG0 SEG3
2 2
MDSET1 MDSET0 LCDON SCOC VLCON BLON LCDSEL

LCD mode LCD mode
register 0 (LCDM0) register 1 (LCDM1)
Internal bus
788
21.3 Registers Controlling LCD Controller/Driver
The following ten registers are used to control the LCD controller/driver.
● LCD mode register 0 (LCDM0)

● LCD mode register 1 (LCDM1)
● LCD clock control register 0 (LCDC0)
● LCD boost level control register (VLCD)
● LCD input switch control register (ISCLCD)
● LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)
● Port mode registers 0, 1, 3, 5, 7, 8 (PM0, PM1, PM3, PM5, PM7, PM8)
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21.3.1 LCD mode register 0 (LCDM0)

LCDM0 specifies the LCD operation.
This register is set by using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDM0 to 00H.
Figure 21-2. Format of LCD Mode Register 0 (LCDM0) (1/2)

Symbol 7 6 5 4 3 2 1 0
LCDM0 MDSET1 MDSET0 LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0
MDSET1 MDSET0 LCD drive voltage generator selection
0 0 External resistance division method
0 1 Internal voltage boosting method
1 0 Capacitor split method
LWAVE LCD display waveform selection
0 Waveform A
1 Waveform B
LDTY2 LDTY1 LDTY0 Selection of time slice of LCD display
0 0 0 Static
0 0 1 2-time slice
0 1 0 3-time slice
0 1 1 4-time slice
1 0 0 6-time slice
1 0 1 8-time slice
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Symbol 7 6 5 4 3 2 1 0
LCDM0 MDSET1 MDSET0 LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0
LBAS1 LBAS0 LCD display bias mode selection
0 0 1/2 bias method
0 1 1/3 bias method
1 0 1/4 bias method
Cautions 1. Do not rewrite the LCDM0 value while the SCOC bit of the LCDM1 register = 1.
2. When “Static” is selected (LDTY2 to LDTY0 bits = 000B), be sure to set the LBAS1 and LBAS0
bits to the default value (00B). Otherwise, the operation will not be guaranteed.
3. Only the combinations of display waveform, number of time slices, and bias method shown in
Table 21-4 are supported.
Combinations of settings not shown in Table 21-4 are prohibited.
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Table 21-4. Combinations of Display Waveform, Time Slices, Bias Method, and Frame Frequency
Display Mode Set Value Driving Voltage Generation Method
Display Number Bias LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0 External Internal Capacitor Split
Waveform of Time Mode Resistance Voltage
Slices Division Boosting
Օ Օ
Waveform A 8 1/4 0 1 0 1 1 0 ×
(24 to 128 Hz) (24 to 64 Hz)
Օ
Waveform A 6 1/4 0 1 0 0 1 0 × ×
(32 to 86 Hz)
Օ Օ Օ
Waveform A 8 1/3 0 1 0 1 0 1
(32 to 128 Hz) (32 to 64 Hz) (32 to 128 Hz)
Օ Օ Օ
Waveform A 6 1/3 0 1 0 0 0 1
(32 to 128 Hz) (32 to 86 Hz) (32 to 128 Hz)
Օ Օ Օ
Waveform A 4 1/3 0 0 1 1 0 1
(24 to 128 Hz) (24 to 128 Hz) (24 to 128 Hz)
Օ Օ Օ
Waveform A 3 1/3 0 0 1 0 0 1
(32 to 128 Hz) (32 to 128 Hz) (32 to 128 Hz)
Օ
Waveform A 3 1/2 0 0 1 0 0 0 × ×
(32 to 128 Hz)
Օ
Waveform A 2 1/2 0 0 0 1 0 0 × ×
(24 to 128 Hz)
Օ
Waveform A Static 0 0 0 0 0 0 × ×
(24 to 128 Hz)
Օ Օ ×
Waveform B 8 1/4 1 1 0 1 1 0
(24 to 128 Hz) (24 to 64 Hz)
Օ Օ Օ
Waveform B 8 1/3 1 1 0 1 0 1
(32 to 128 Hz) (32 to 64 Hz) (32 to 128 Hz)
Օ Օ Օ
Waveform B 6 1/3 1 1 0 0 0 1
(32 to 128 Hz) (32 to 86 Hz) (32 to 128 Hz)
Օ Օ Օ
Waveform B 4 1/3 1 0 1 1 0 1
(24 to 128 Hz) (24 to 128 Hz) (24 to 128 Hz)
Օ Օ Օ
Waveform B 3 1/3 1 0 1 0 0 1
(32 to 128 Hz) (32 to 128 Hz) (32 to 128 Hz)
Remark Օ: Supported
×: Not supported
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21.3.2 LCD mode register 1 (LCDM1)

LCDM1 enables or disables display operation, voltage boost circuit operation, and capacitor split circuit operation, and
specifies the display data area and the low voltage mode.
LCDM1 is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDM1 to 00H.

Symbol <7> <6> <5> <4> <3> 2 1 <0>
LCDM1 LCDON SCOC VLCON BLON LCDSEL 0 0 LCDVLM
SCOC LCDON LCD display enable/disable
When normal liquid crystal waveform (waveform A or B) is output
0 0 Output ground level to segment/common pin
0 1
1 0 Display off (all segment outputs are deselected.)
1 1 Display on
VLCONNote 1 Voltage boost circuit or capacitor split circuit operation enable/disable
0 Stops voltage boost circuit or capacitor split circuit operation
1 Enables voltage boost circuit or capacitor split circuit operation
BLONNote 2 LCDSEL Display data area control
0 0 Displaying an A-pattern area data (lower four bits of LCD display data register)
0 1 Displaying a B-pattern area data (higher four bits of LCD display data register)
1 0 Alternately displaying A-pattern and B-pattern area data (blinking display corresponding
to the fixed-cycle interrupt (INTRTCPRD) timing of the independent power supply RTC)
1 1
Notes 1. Cannot be set during external resistance division mode.

2. When fIL is selected as the LCD source clock (fLCD), be sure to set the BLON bit to “0”.
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Symbol <7> <6> <5> <4> <3> 2 1 <0>
LCDM1 LCDON SCOC VLCON BLON LCDSEL 0 0 LCDVLM
LCDVLMNote Control of default value of voltage boosting pin
0 Set when VDD ≥ 2.7 V
1 Set when VDD ≤ 4.2 V
Note A function to set the initial state of the VLx pin and efficiently boost voltage when using a voltage boosting
circuit. Set LCDVLM bit = 0 when VDD at the start of voltage boosting is 2.7 V or more. Set LCDVLM bit = 1
when VDD is 4.2 V or less.
However, when 2.7 V ≤ VDD ≤ 4.2 V, operation is possible with LCDVLM = 0 or LCDVLM = 1.
Cautions 1. When the voltage boost circuit is used, set SCOC = 0 and VLCON = 0, and MDSET1, MDSET0
= 00 in order to reduce power consumption when the LCD is not used. When MDSET1,
MDSET0 = 01, power is consumed by the internal reference voltage generator.
2. When the external resistance division method has been set (MDSET1 and MDSET0 of LCDM0
= 00B) or capacitor split method has been set (MDSET1 and MDSET0 = 10B), set the LCDVLM
bit to 0.
3. Do not rewrite the VLCON and LCDVLM bits while SCOC = 1.
4. Set the BLON and LCDSEL bits to 0 when 8 has been selected as the number of time slices
for the display mode.
5. To use the internal voltage boosting method, specify the reference voltage by using the
VLCD register (select the internal boosting method (by setting the MDSET1 and MDSET0 bits
of the LCDM0 register to 01B) if the default reference voltage is used), wait for the reference
voltage setup time (5 ms (min.)), and then set the VLCON bit to 1.
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Figure 21-4. Format of Subsystem clock supply option control register (OSMC)
Address: F00F3H After reset: 00H R/W Note 1

Symbol <7> 6 5 <4> 3 2 1 0
RTCLPC Setting in STOP mode or HALT mode while sub clock (fSX) is selected as CPU clock
Note 4
0 Enables supply of sub clock (fSX) to peripheral functions

1 Stops supply of sub clock (fSX) to peripheral functions other than the independent power supply
RTC, 12-bit interval timer, 8-bit interval timer, clock output/buzzer output controller, LCD
controller/driver, oscillation stop detection circuit, and frequency measurement circuit.
WUTMMCK0 Selection of the operating clock for Selection of the count Selection of the output clock for
the 12-bit interval timer, 8-bit interval operation/stop trigger clock the clock output/buzzer output
timer, LCD controller/driver, and for the frequency controller
frequency measurement circuit measurement circuit
1 Low-speed on-chip oscillator clock Low-speed on-chip oscillator Clock output is prohibited. Note 5
Notes 2, 3, 6, 7
(fIL) clock (fIL) selected Note 6
Notes 1. Be sure to set bits 0 to 3, 5, and 6 to “0”.

3. Switching between the sub clock (fSX) and the low-speed on-chip oscillator clock (fIL) can be
enabled by the WUTMMCK0 bit only when all of the 12-bit interval timer, 8-bit interval timer,
clock output/buzzer output controller, LCD controller/driver, and frequency measurement circuit
are stopped.
4. When the sub clock (fSX) is selected (SELLOSC = 0) by bit 0 (SELLOSC) of the CKSEL register
and RTCLPC is set to 1, the subsystem clock (fSUB) is stopped. However, when the low-speed
on-chip oscillator clock is selected (SELLOSC = 1) and RTCLPC is set to 1, the subsystem
clock (fSUB) is not stopped.
7. When the WUTMMCK0 bit is set to 1, internal voltage boosting cannot be used for the LCD
drive voltage generator of the LCD controller/driver.
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21.3.4 LCD clock control register 0 (LCDC0)

LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
Reset signal generation sets LCDC0 to 00H.
Figure 21-5. Format of LCD Clock Control Register 0 (LCDC0)

Symbol 7 6 5 4 3 2 1 0
LCDC0 0 0 LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00
LCDC05 LCDC04 LCDC03 LCDC02 LCDC01 LCDC00 LCD clock (LCDCL)

WUTMMCK0 = 0 WUTMMCK0 = 1
0 0 0 0 0 1 fSUB/22 fIL/22
3
0 0 0 0 1 0 fSUB/2 fIL/23
0 0 0 0 1 1 fSUB/24 fIL/24
0 0 0 1 0 0 fSUB/25 fIL/25
0 0 0 1 0 1 fSUB/26 fIL/26
0 0 0 1 1 0 fSUB/27 fIL/27
0 0 0 1 1 1 fSUB/28 fIL/28
0 0 1 0 0 0 fSUB/29 fIL/29
0 0 1 0 0 1 fSUB/210
0 1 0 0 0 1 fMAIN/28
0 1 0 0 1 0 fMAIN/29
0 1 0 0 1 1 fMAIN/210
0 1 0 1 0 0 fMAIN/211
0 1 0 1 0 1 fMAIN/212
0 1 0 1 1 0 fMAIN/213
0 1 0 1 1 1 fMAIN/214
0 1 1 0 0 0 fMAIN/215
0 1 1 0 0 1 fMAIN/216
0 1 1 0 1 0 fMAIN/217
0 1 1 0 1 1 fMAIN/218
1 0 1 0 1 1 fMAIN/219
Cautions 1. Be sure to set bits 6 and 7 to “0”.

2. Set the frame frequency between 32 and 128 Hz (24 to 128 Hz when fIL is selected). Also, when
set to internal voltage boosting method, capacitor spit method, set the LCD clock (LCDCL) to
512 Hz or less (235 Hz or less when fIL is selected).
3. Do not set LCDC0 when the SCOC bit of the LCDM1 register is 1.
Remark fMAIN: Main system clock frequency

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21.3.5 LCD boost level control register (VLCD)

VLCD selects the reference voltage that is to be generated when operating the voltage boost circuit (contrast
adjustment). The reference voltage can be selected from 16 steps.
Reset signal generation sets VLCD to 04H.
Figure 21-6. Format of LCD Boost Level Control Register (VLCD)

Symbol 7 6 5 4 3 2 1 0
VLCD 0 0 0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0
VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 Reference voltage VL4 voltage

selection
1/3 bias 1/4 bias
(contrast adjustment)
method method
0 0 1 0 0 1.00 V (default) 3.00 V 4.00 V

0 0 1 0 1 1.05 V 3.15 V 4.20 V
0 0 1 1 0 1.10 V 3.30 V 4.40 V
0 0 1 1 1 1.15 V 3.45 V 4.60 V
0 1 0 0 0 1.20 V 3.60 V 4.80 V
0 1 0 0 1 1.25 V 3.75 V 5.00 V
0 1 0 1 0 1.30 V 3.90 V 5.20 V
0 1 0 1 1 1.35 V 4.05 V Setting prohibited
Cautions 1. The VLCD setting is valid only when the voltage boost circuit is operating.
2. Be sure to set bits 5 to 7 to “0”.
3. Be sure to change the VLCD value after having stopped the operation of the voltage boost
circuit (VLCON = 0).
4. To use the internal voltage boosting method, specify the reference voltage by using the
VLCD register (select the internal boosting method (by setting the MDSET1 and MDSET0
bits of the LCDM0 register to 01B) if the default reference voltage is used), wait for the
reference voltage setup time (5 ms (min.)), and then set VLCON to 1.
5. To use the external resistance division method or capacitor split method, use the VLCD
register with its initial value (04H).
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21.3.6 LCD input switch control register (ISCLCD)

Input to the Schmitt trigger buffer must be disabled until the CAPL/P126, CAPH/P127, and VL3/P125 pins are set to
operate as LCD function pins in order to prevent through-current from entering.
This register is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets ISCLCD to 00H.
Figure 21-7. Format of LCD Input Switch Control Register (ISCLCD)

Symbol 7 6 5 4 3 2 1 0
ISCLCD 0 0 0 0 0 0 ISCVL3 ISCCAP
ISCVL3 VL3/P125 pin Schmitt trigger buffer control
0 Input invalid
1 Input valid
ISCCAP CAPL/P126, CAPH/P127 pins Schmitt trigger buffer control
0 Input invalid
1 Input valid
Cautions 1. If ISCVL3 = 0, set the corresponding port registers as follows:

2. If ISCCAP = 0, set the corresponding port registers as follows:
(1) Operation of ports that alternately function as VL3, CAPL, and CAPH pins
The functions of the VL3/P125, CAPL/P126, and CAPH/P127 pins can be selected by using the LCD input switch
control register (ISCLCD), LCD mode register 0 (LCDM0), and port mode register 12 (PM12).
● VL3/P125
Table 21-5. Settings of VL3/P125 Pin Function
Bias Setting ISCVL3 Bit of PM125 Bit of Pin Function Initial Status
(LBAS1 and LBAS0 Bits of ISCLCD Register PM12 Register
LCDM0 Register )
Other than 1/4 bias method 0 1 Digital input invalid mode √

(LBAS1, LBAS0 = 00 or 01)
1/4 bias method 0 1 VL3 function mode –

(LBAS1, LBAS0 = 10)
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The following shows the VL3/P125 pin function status transitions.
Figure 21-8. VL3/P125 Pin Function Status Transitions
Reset status
Reset release
LBAS1, LBAS0 = 10 Digital input

invalid mode
ISCVL3 = 1
VL3 Digital input PMmn = 0 Digital output

PMmn = 1
Caution Be sure to set the VL3 function mode before segment output starts (while SCOC bit of LCD
● CAPL/P126 and CAPH/P127
Table 21-6. Settings of CAPL/P126 and CAPH/P127 Pin Functions
LCD Drive Voltage Generator ISCCAP Bit of PM126 and Pin Function Initial Status
(MDSET1 and MDSET0 Bits of ISCLCD Register PM127 Bits of
LCDM0 Register) PM12 Register
External resistance division 0 1 Digital input invalid mode √

(MDSET1, MDSET0 = 00)
Internal voltage boosting or 0 1 CAPL/CAPH function mode –

capacitor split
(MDSET1, MDSET0 = 01 or 10)
The following shows the CAPL/P126 and CAPH/P127 pin function status transitions.
Figure 21-9. CAPL/P126 and CAPH/P127 Pin Function Status Transitions
Reset status
Reset release
MDSET1, MDSET0 = 01 or 10
Digital input
invalid mode
MDSET1, MDSET0 = 00
ISCCAP = 1
CAPL/CAPH Digital input PMmn = 0 Digital output

PMmn = 1
Caution Be sure to set the CAPL/CAPH function mode before segment output starts (while SCOC bit
of LCD mode register 1 (LCDM1) is 0).
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21.3.7 LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)

These registers specify whether to use pins P02 to P07, P10 to P17, P30 to P37, P50 to P57, P70 to P77, and P80 to
P85 as port pins (other than segment output pins) or segment output pins.
These registers are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to the value after a reset shown in Figure 21-10.
Remark The correspondence between the segment output pins (SEGxx) and the PFSEG register (PFSEGxx bits)
and the existence of SEGxx pins in each product are shown in Table 21-7 Segment Output Pins in Each
Product and Correspondence with PFSEG Register (PFSEG Bits).
Figure 21-10. Format of LCD port function registers 0 to 5 (PFSEG0 to PFSEG5)
Address: F0300H After reset: F0H R/W

Symbol 7 6 5 4 3 2 1 0
PFSEG0 PFSEG07 PFSEG06 PFSEG05 PFSEG04 0 0 0 0

Symbol 7 6 5 4 3 2 1 0

Note 3 Note 3 Note 3 Note 3

Symbol 7 6 5 4 3 2 1 0

Symbol 7 6 5 4 3 2 1 0

Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3 Note 3 Note 3
Symbol 7 6 5 4 3 2 1 0

Notes 1, 2 Notes 1, 2
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Symbol 7 6 5 4 3 2 1 0
PFSEG5 0 0 0 0 0 0 PFSEG41 PFSEG40
PFSEGxx Port (other than segment output)/segment outputs specification of Pmn pins
(xx = 04 to (mn = 02 to 07, 10 to 17, 30 to 37, 50 to 57, 70 to 77, 80 to 85)
41)
0 Used the Pmn pin as port (other than segment output)

1 Used the Pmn pin as segment output
Notes 1. For R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE, the initial value is 0.
Writing 1 to this bit does not affect operation, and the value read is 0.
2. Be sure to set “1” for 80-pin products.
3. Be sure to set “1” for 64-pin products.
Caution To use the Pmn pins as segment output pins (PFSEGxx = 1), be sure to set the PUmn bit of the
PUm register, POMmn bit of the POMm register, and PIMmn bit of the PIMm register to “0”.
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Table 21-7. Segment Output Pins in Each Product and Correspondence with PFSEG Register (PFSEG Bits)
Bit Name of PFSEG Register Corresponding SEGxx Pins Alternate Port 64-pin 80-pin 100-pin
PFSEG10 SEG10 P16 √ √ √
PFSEG11 SEG11 P17 √ √ √
PFSEG12 SEG12 P80 – √ √
PFSEG13 SEG13 P81 – √ √
PFSEG14 SEG14 P82 – √ √
PFSEG15 SEG15 P83 – √ √
PFSEG16 SEG16 P70 √ √ √
PFSEG17 SEG17 P71 √ √ √
PFSEG18 SEG18 P72 √ √ √
PFSEG19 SEG19 P73 √ √ √
PFSEG20 SEG20 P74 √ √ √
PFSEG21 SEG21 P75 – √ √
PFSEG22 SEG22 P76 – √ √
PFSEG23 SEG23 P77 – √ √
PFSEG24 SEG24 P30 √ √ √
PFSEG25 SEG25 P31 √ √ √
PFSEG26 SEG26 P32 – √ √
PFSEG27 SEG27 P33 – √ √
PFSEG28 SEG28 P34 – – √
PFSEG29 SEG29 P35 – – √
PFSEG30 SEG30 P36 – – √
PFSEG31 SEG31 P37 – – √
PFSEG32 SEG32 P02 – √ –
P50 – – √
PFSEG33 SEG33 P03 – √ –
P51 – – √
PFSEG34 SEG34 P04 – √ –
P52 – – √
PFSEG35 SEG35 P05 – √ –
P53 – – √
PFSEG36 SEG36 P06 – √ –
P54 – – √
PFSEG37 SEG37 P07 – √ –
P55 – – √
PFSEG38 SEG38 P56 – – √
PFSEG39 SEG39 P57 – – √
PFSEG40 SEG40 P84 – – √
PFSEG41 SEG41 P85 – – √
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(1) Operation of ports that alternately function as SEGxx pins

The functions of ports that also serve as segment output pins (SEGxx) can be selected by using the port mode
register (PMxx) and LCD port function registers 0 to 5 (PFSEG0 to PFSEG5).
● P02 to P07, P10 to P17, P30 to P37, P50 to P57, P70 to P77, P80 to P85
(ports that do not serve as analog input pins (ANIxx))
Table 21-8. Settings of SEGxx/Port Pin Function
PFSEGxx Bit of PMxx Bit of Pin Function Initial Status

PFSEG0 to PFSEG5 PMxx Register
Registers
1 1 Digital input invalid mode √
1 0 Segment output mode –
The following shows the SEGxx/Pxx pin function status transitions.
Figure 21-11. SEGxx/Pxx Pin Function Status Transitions
Reset status
Reset release
Digital input PMmn = 0 Segment

invalid mode output mode
PFSEGxx = 0
Digital input PMmn = 0 Digital output

mode mode
PMmn = 1
Caution Be sure to set the segment output mode before segment output starts (while SCOC bit of LCD
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21.3.8 Port mode registers 0, 1, 3, 5, 7, 8 (PM0, PM1, PM3, PM5, PM7, PM8)
These registers specify input/output of ports 0, 1, 5, 7, and 8 in 1-bit units.
When using the ports (such as P10/SEG4) to be shared with the segment output pin for segment output, set the port
mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P10/SEG4 for segment output

Set the PM10 bit of port mode register 1 to “0”.
Set the P10 bit of port register 1 to “0”.
These registers are set by using a 1-bit or 8-bit memory manipulation instruction.
Figure 21-12. Format of Port Mode Registers 0, 1, 3, 5, 7, 8 (PM0, PM1, PM3, PM5, PM7, PM8)
PM0 PM07 PM06 PM05 PM04 PM03 PM02 1 1 FFF20H FFH R/W
PMmn Pmn pin I/O mode selection

(m = 0, 1, 3, 5, 7, 8; n = 0 to 7)

Remark The figure shown above presents the format of port mode registers 0, 1, 3, 5, 7, and 8. The format of
the port mode register of other products, see Table 4-3 PMxx, Pxx, PUxx, PIMxx, POMxx registers
and the bits mounted on each product.
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21.4 LCD Display Data Registers
The LCD display data registers are mapped as shown in Table 21-9. The contents displayed on the LCD can be
changed by changing the contents of the LCD display data registers.
Table 21-9. Relationship Between LCD Display Data Register Contents and Segment/Common Outputs (1/4)
(a) Other than 6-time slice and 8-time slice (static, 2-time slice, 3-time slice, and 4-time slice) (1/2)
Register Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100-pin 80-pin 64-pin
Name
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
SEG0 F0400H SEG0 (B-pattern area) SEG0 (A-pattern area) √ √ √

SEG10 F040AH SEG10 (B-pattern area) SEG10 (A-pattern area) √ √ √
SEG11 F040BH SEG11 (B-pattern area) SEG11 (A-pattern area) √ √ √
SEG12 F040CH SEG12 (B-pattern area) SEG12 (A-pattern area) √ √ –
SEG13 F040DH SEG13 (B-pattern area) SEG13 (A-pattern area) √ √ –
SEG14 F040EH SEG14 (B-pattern area) SEG14 (A-pattern area) √ √ –
SEG15 F040FH SEG15 (B-pattern area) SEG15 (A-pattern area) √ √ –
SEG21 F0415H SEG21 (B-pattern area) SEG21 (A-pattern area) √ √ –
SEG26 F041AH SEG26 (B-pattern area) SEG26 (A-pattern area) √ √ –
SEG27 F041BH SEG27 (B-pattern area) SEG27 (A-pattern area) √ √ –
SEG28 F041CH SEG28 (B-pattern area) SEG28 (A-pattern area) √ – –
SEG29 F041DH SEG29 (B-pattern area) SEG29 (A-pattern area) √ – –
SEG30 F041EH SEG30 (B-pattern area) SEG30 (A-pattern area) √ – –
SEG31 F041FH SEG31 (B-pattern area) SEG31 (A-pattern area) √ – –
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(a) Other than 6-time slice and 8-time slice (static, 2-time slice, 3-time slice, and 4-time slice) (2/2)
Register Name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100-pin 80-pin 64-pin
SEG38 F0426H SEG38 (B-pattern area) SEG38 (A-pattern area) √ – –
Remark √: Supported, –: Not supported
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(b) 6-time slice and 8-time slice (1/2)

Register Name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100-pin 80-pin 64-pin
Note
SEG0 F0400H SEG0 √ √ √
SEG1 F0401H SEG1Note √ √ √
Note
SEG2 F0402H SEG2 √ √ √
Note
SEG3 F0403H SEG3 √ √ √
SEG4 F0404H SEG4 √ √ √
SEG5 F0405H SEG5 √ √ √
SEG6 F0406H SEG6 √ √ √
SEG7 F0407H SEG7 √ √ √
SEG8 F0408H SEG8 √ √ √
SEG9 F0409H SEG9 √ √ √
SEG10 F040AH SEG10 √ √ √
SEG11 F040BH SEG11 √ √ √
SEG12 F040CH SEG12 √ √ –
SEG13 F040DH SEG13 √ √ –
SEG14 F040EH SEG14 √ √ –
SEG15 F040FH SEG15 √ √ –
SEG16 F0410H SEG16 √ √ √
SEG17 F0411H SEG17 √ √ √
SEG18 F0412H SEG18 √ √ √
SEG19 F0413H SEG19 √ √ √
SEG20 F0414H SEG20 √ √ √
SEG21 F0415H SEG21 √ √ –
SEG22 F0416H SEG22 √ √ –
SEG23 F0417H SEG23 √ √ –
SEG24 F0418H SEG24 √ √ √
SEG25 F0419H SEG25 √ √ √
SEG26 F041AH SEG26 √ √ –
SEG27 F041BH SEG27 √ √ –
SEG28 F041CH SEG28 √ – –
SEG29 F041DH SEG29 √ – –
SEG30 F041EH SEG30 √ – –
SEG31 F041FH SEG31 √ – –
SEG32 F0420H SEG32 √ √ –
SEG33 F0421H SEG33 √ √ –
SEG34 F0422H SEG34 √ √ –
SEG35 F0423H SEG35 √ √ –
SEG36 F0424H SEG36 √ √ –
SEG37 F0425H SEG37 √ √ –
SEG38 F0426H SEG38 √ – –
SEG39 F0427H SEG39 √ – –
SEG40 F0428H SEG40 √ – –
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(b) 6-time slice and 8-time slice (2/2)

Register Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100-pin 80-pin 64-pin
Name
SEG41 F0429H SEG41 √ – –
Note The COM4 to COM7 pins and SEG0 to SEG3 pins are used alternatively.
Remark √: Supported, –: Not supported
To use the LCD display data register when the number of time slices is static, two, three, or four, the lower four bits and
higher four bits of each address of the LCD display data register become an A-pattern area and a B-pattern area,
respectively.
The correspondences between A-pattern area data and COM signals are as follows: bit 0 ↔ COM0, bit 1 ↔ COM1, bit
2 ↔ COM2, and bit 3 ↔ COM3.
The correspondences between B-pattern area data and COM signals are as follows: bit 4 ↔ COM0, bit 5 ↔ COM1, bit
6 ↔ COM2, and bit 7 ↔ COM3.
A-pattern area data will be displayed on the LCD panel when BLON = LCDSEL = 0 has been selected, and B-pattern
area data will be displayed on the LCD panel when BLON = 0 and LCDSEL = 1 have been selected.
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21.5 Selection of LCD Display Register
With RL78/I1C, to use the LCD display data registers when the number of time slices is static, two, three, or four, the
LCD display data register can be selected from the following three types, according to the BLON and LCDSEL bit settings.
● Displaying an A-pattern area data (lower four bits of LCD display data register)
● Displaying a B-pattern area data (higher four bits of LCD display data register)
● Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period
interrupt timing of the independent power supply RTC)
Caution When the number of time slices is six or eight, LCD display data registers (A-pattern, B-pattern, or
blinking display) cannot be selected.
Figure 21-13. Example of Setting LCD Display Registers When Pattern Is Changed
A-pattern area and B-pattern area are alternately

displayed when blinking display (BLON = 1) is selected
B-pattern area A-pattern area
Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name COM COM COM COM COM COM COM COM
3 2 1 0 3 2 1 0
… … …
SEG5 F0405H
SEG4 F0404H Set these bits to 1 for blinking display
SEG3 F0403H
SEG2 F0402H
SEG1 F0401H
SEG0 F0400H
Set a complement to these bits for blinking display
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21.5.1 A-pattern area and B-pattern area data display

When BLON = LCDSEL = 0, A-pattern area (lower four bits of the LCD display data register) data will be output as the
LCD display register.
When BLON = 0, and LCDSEL = 1, B-pattern area (higher four bits of the LCD display data register) data will be output
as the LCD display register.
See 21.4 LCD Display Data Registers about the display area.
21.5.2 Blinking display (Alternately displaying A-pattern and B-pattern area data)
When BLON = 1 has been set, A-pattern and B-pattern area data will be alternately displayed, according to the fixed-
cycle interrupt (INTRTCPRD) timing of the independent power supply RTC. See CHAPTER 9 REALTIME CLOCK
WITH INDEPENDENT POWER SUPPLY about the setting of the fixed-cycle interrupt (INTRTCPRD, 0.5 s setting
only) timing of the independent power supply RTC.
For blinking display of the LCD, set inverted values to the B-pattern area bits corresponding to the A-pattern area bits.
(Example: Set 1 to bit 0 of 00H, and set 0 to bit 4 of F0400H for blinking display.) When not setting blinking display of the
LCD, set the same values. (Example: Set 1 to bit 2 of F0402H, and set 1 to bit 6 of F0402H for lighting display.)
See 21.4 LCD Display Data Registers about the display area.
Next, the timing operation of display switching is shown.
Figure 21-14. Switching Operation from A-Pattern Display to Blinking Display
Fixed-cycle interrupt of the independent

power supply RTC
(INTRTCPRD)
BLON, LCDSEL bits BLON = 0, LCDSEL = 0 BLON = 1, LCDSEL = 0 or 1
Segment display A-pattern

A- B-pattern A-pattern B-pattern
pattern
Blinking display always starts from an A pattern.
Figure 21-15. Switching Operation from Blinking Display to A-Pattern Display
Fixed-cycle interrupt of the independent

power supply RTC
(INTRTCPRD)
BLON = 1,
BLON, LCDSEL bits LCDSEL = 0 or 1 BLON = 0, LCDSEL = 0
Segment display B-pattern A-pattern B-pattern A-pattern
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21.6 Setting the LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
Cautions 1. To operate the LCD controller/driver, be sure to follow procedures (1) to (3). Unless these
procedures are observed, the operation will not be guaranteed.
2. The steps shown in the flowcharts in (1) to (3) are performed by the CPU.
(1) External resistance division method
Figure 21-16. External Resistance Division Method Setting Procedure
START
Select the display waveform (select waveform A or B), number of time slices,
and bias method by using the LWAVE, LDTY2 to LDTY0, LBAS1,
and LBAS0 bits of the LCDM0 register.
MDSET1 and MDSET0 bits of LCDM0 register = 00B

(Specify the external resistance division method.)
Specify the segment output pins by using the PFSEGx register.
Store display data in RAM for LCD display.
No
No. of time slices 4 or lower ?
Yes
Set a display data area (A-pattern or B-pattern area, or blinking display)

by using the BLON and LCDSEL bits of the LCDM1 register.
Specify the LCD clock by using the LCDC0 and MCDC registers.
SCOC bit of LCDM1 register = 1

(Common pin outputs select signal and segment pin outputs deselect signal.)
The SCOC and
LCDON bits can be set
LCDON bit of LCDM1 register = 1 together.
(Common and segment pins output select and deselect signals
in accordance with display data.)
[To change BLON and LCDSEL bit settings during operation]

Set a display data area (A-pattern or B-pattern area, or blinking display) by
using the BLON and LCDSEL bits of the LCDM1 register.
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(2) Internal voltage boosting method
Figure 21-17. Internal Voltage Boosting Method Setting Procedure
START
Set the LCDVLM bit of the LCDM1 register according to the VDD voltage. For details, see Figure 21-3 Format of
LCD Mode Register 1 (LCDM1).

(Specify the internal voltage boosting method.)
No
Yes

Select the LCD clock by using the LCDC0 register.
Select the reference voltage for voltage boosting by using the VLCD register.
No
Setup time of reference voltage has elapsed?
Yes
VLCON bit of LCDM1 register = 1 (Enable voltage boosting circuit operation.)
No
Voltage boosting wait time has elapsed?
Yes

The SCOC and

Cautions 1. Wait until the setup time has elapsed even if not changing the setting of the VLCD register.
2. For the specifications of the reference voltage setup time and voltage boosting wait time, see
CHAPTER 41 ELECTRICAL SPECIFICATIONS.
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(3) Capacitor split method
Figure 21-18. Capacitor Split Method Setting Procedure
START

(Specify the capacitor split method.)
No
Yes

Specify the LCD clock by using the LCDC0 register.
VLCON bit of LCDM1 register = 1 (Enable capacitor split circuit operation.)
No
Voltage boosting wait time has elapsed?
Yes

The SCOC and

Caution For the specifications of the voltage boosting wait time, see CHAPTER 41 ELECTRICAL
SPECIFICATIONS.
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21.7 Operation Stop Procedure
To stop the operation of the LCD while it is displaying waveforms, follow the steps shown in the flowchart below.
The LCD stops operating when the LCDON bit of LCDM1 register and SCOC bit of the LCDM1 register are set to “0”.
Figure 21-19. Operation Stop Procedure
LCDON bit of LCDM1 register = 0

(Display data off. Segment pin outputs deselect signal.)
LCDON and SCOC bits can be
set together.
(Common/segment pins output ground signal. Segment pin outputs deselect signal.)
Internal voltage boosting method/ No

capacitor split method?
Yes
VLCON bit of LCDM1 register = 0

(Voltage boost circuit/capacitor split circuit stop operating.)
(The external resistance division method is selected.)
END
Caution Stopping the voltage boost/capacitor split circuits is prohibited while the display is on (SCOC and
LCDON bits of LCDM1 register = 11B). Otherwise, the operation will not be guaranteed. Be sure to
turn off display (SCOC and LCDON bits of LCDM1 register = 00B) before stopping the voltage
boost/capacitor split circuits (VLCON bit of LCDM1 register = 0).
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21.8 Supplying LCD Drive Voltages VL1, VL2, VL3, and VL4
The external resistance division method, internal voltage boosting method, and capacitor split method can be selected
as LCD drive power generating method.
21.8.1 External resistance division method

Figure 21-20 shows examples of LCD drive voltage connection, corresponding to each bias method.
Figure 21-20. Examples of LCD Drive Power Connections (External Resistance Division Method) (1/2)
(a) Static display mode (b) 1/2 bias method
VDD VDD
VL4 VL4
VL4 VL4
R
VL3 VL3/P125Note 2 VL3/
VL3
P125Note
VL2 VL2Note 1 V2
VL2
R
VL1 VL1Note 1
VL1 VL1
VSS
VSS
VSS
VSS
VL4 = VDD
VL4 = VDD
Notes 1. Connect VL1 and VL2 to GND or leave open.

2. VL3 can be used as port (P125).
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Figure 21-20. Examples of LCD Drive Power Connections (External Resistance Division Method) (2/2)
(c) 1/3 bias method (d) 1/4 bias method
VDD VDD
VL4 VL4
VL4 VL4
R VL3/ R
VL3/ VL3 P125
P125
P125Note
R
VL2 VL2
VL2 VL2
R R
VL1 VL1
VL1 VL1
R R
VSS VSS
VSS VSS
VL4 = VDD VL4 = VDD
Note VL3 can be used as port (P125).
Caution The reference resistance “R” value for external resistance division is 10 kΩ to 1 MΩ. Also, to
stabilize the potential of the VL1 to VL4 pins, connect a capacitor between each of pins VL1 to VL4
and the GND pin as needed. The reference capacitance is about 0.47 µF but it depends on the
LCD panel used, the number of segment pins, the number of common pins, the frame frequency,
and the operating environment. Thoroughly evaluate these values in accordance with your
system and adjust and determine the capacitance.
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21.8.2 Internal voltage boosting method

RL78/I1C contains an internal voltage boost circuit for generating LCD drive power supplies. The internal voltage boost
circuit and external capacitors (0.47 µF±30%) are used to generate an LCD drive voltage. Only 1/3 bias mode or 1/4 bias
mode can be set for the internal voltage boosting method.
The LCD drive voltage of the internal voltage boosting method can supply a constant voltage, regardless of changes in
VDD, because it is a power supply separate from the main unit.
In addition, a contrast can be adjusted by using the LCD boost level control register (VLCD).
Table 21-10. LCD Drive Voltages (Internal Voltage Boosting Method)
Bias Method 1/3 Bias Method 1/4 Bias Method
LCD Drive Voltage Pin
VL4 3 × VL1 4 × VL1
VL3 – 3 × VL1
VL2 2 × VL1 2 × VL1
VL1 LCD reference voltage LCD reference voltage
Figure 21-21. Examples of LCD Drive Power Connections (Internal Voltage Boosting Method)
(a) 1/3 bias method (b) 1/4 bias method
VDD VDD
4 × VL1 VL4
3 × VL1 VL4
3 × VL1 VL3/P125
VL3/P125Note
Drive voltage 2 × VL1 VL2

Drive voltage VL2 generator
2 × VL1
generator
VL1
VL1
CAPH C2 C3 C4 C5
C2 C3 C4
CAPH C1
CAPL
C1
CAPL
Note VL3 can be used as port (P125).
Remark Use a capacitor with as little leakage as possible.

In addition, make C1 a nonpolar capacitor.
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21.8.3 Capacitor split method

RL78/I1C contains an internal voltage reduction circuit for generating LCD drive power supplies. The internal voltage
reduction circuit and external capacitors (0.47 µF±30%) are used to generate an LCD drive voltage. Only 1/3 bias mode
can be set for the capacitor split method.
Different from the external resistance division method, there is always no current flowing with the capacitor split method,
so current consumption can be reduced.
Table 21-11. LCD Drive Voltages (Capacitor Split Method)
Bias Method 1/3 Bias Method

LCD Drive Voltage Pin
VL4 VDD
VL3 –
VL2 2/3 × VL4
VL1 1/3 × VL4
Figure 21-22. Examples of LCD Drive Power Connections (Capacitor Split Method)
• 1/3 bias method
VDD
VDD VL4 Note 1
VL3/P125 Note 2
2/3 × VDD VL2
Drive voltage 1/3 × VDD VL1

generator
CAPH
C1
C2 C3
CAPL
Notes 1. When switching to internal voltage boosting method, connect capacitor C4 as shown in Figure 21-21. Examples
of LCD Drive Power Connections (Internal Voltage Boosting Method)
2. VL3 can be used as port (P125).
Remark Use a capacitor with as little leakage as possible.

In addition, make C1 a nonpolar capacitor.
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21.9 Common and Segment Signals
21.9.1 Normal liquid crystal waveform

Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment
signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference
becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem,
this LCD panel is driven by AC voltage.
(1) Common signals

Each common signal is selected sequentially according to a specified number of time slices at the timing listed in
Table 21-12. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the COM3
pin open.
Use the COM4 to COM7 pins other than in the six-time-slice mode and eight-time-slice mode, and COM6, COM7
pins in the six-time-slice mode as open or segment pins.
Table 21-12. COM Signals
COM Signal COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
Number of
Time Slices
Static display mode Note Note Note Note
Two-time-slice mode Open Open Note Note Note Note
Three-time-slice mode Open Note Note Note Note
Four-time-slice mode Note Note Note Note

Six-time-slice mode Note Note
Eight-time-slice mode
Note Use the pins as open or segment pins.
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(2) Segment signals

The segment signals correspond to the LCD display data register (see 21.4 LCD Display Data Registers).
When the number of time slices is eight, bits 0 to 7 of each display data register are read in synchronization with
COM0 to COM7, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the
deselect voltage. The conversion results are output to the segment pins (SEG4 to SEG41).
When the number of time slices is number other than eight, bits 0 to 3 of each byte in A-pattern area are read in
synchronization with COM0 to COM3, and bits 4 to 7 of each byte in B-pattern area are read in synchronization with
COM0 to COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the
deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG41).
Check, with the information given above, what combination of front-surface electrodes (corresponding to the
segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns in the
LCD display data register, and write the bit data that corresponds to the desired display pattern on a one-to-one
basis.
Remark The mounted segment output pins vary depending on the product.
● 64-pin products: SEG0 to SEG11, SEG16 to SEG20, SEG24 to SEG25
● 80-pin products: SEG0 to SEG27, SEG32 to SEG37
● 100-pin products: SEG0 to SEG41
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(3) Output waveforms of common and segment signals

The voltages listed in Table 21-13 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained. The
other combinations of the signals correspond to the display off-voltage.
Table 21-13. LCD Drive Voltage
(a) Static display mode
Segment Signal Select Signal Level Deselect Signal Level
Common Signal VSS/VL4 VL4/VSS
VL4/VSS –VLCD/+VLCD 0 V/0 V
(b) 1/2 bias method
Common Signal VSS/VL4 VL4/VSS
Select signal level VL4/VSS –VLCD/+VLCD 0 V/0 V

1 1 1 1
Deselect signal level VL2 – VLCD/+ VLCD + VLCD/– VLCD
2 2 2 2
(c) 1/3 bias method (waveform A or B)
Common Signal VSS/VL4 VL2/VL1

1 1
Select signal level VL4/VSS –VLCD/+VLCD – VLCD/+ VLCD
3 3
1 1 1 1
Deselect signal level VL1/VL2 – VLCD/+ VLCD + VLCD/– VLCD
3 3 3 3
(d) 1/4 bias method (waveform A or B)
Common Signal VSS/VL4 VL2

1 1
Select signal level VL4/VSS –VLCD/+VLCD – VLCD/+ VLCD
2 2
1 1 1 1
Deselect signal level VL1/VL3 – VLCD/+ VLCD + VLCD/– VLCD
4 4 4 4
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Figure 21-23 shows the common signal waveforms, and Figure 21-24 shows the voltages and phases of the common
and segment signals.
Figure 21-23. Common Signal Waveforms (1/3)
(a) Static display mode
VL4
COMn
VLCD
(Static display)
VSS
TF = T
T: One LCD clock period TF: Frame frequency
(b) 1/2 bias method
VL4
COMn
VL2 VLCD
(Two-time-slice mode)
VSS
TF = 2 × T
VL4
COMn
VL2 VLCD
(Three-time-slice mode)
VSS
TF = 3 × T
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(c) 1/3 bias method
VL4
COMn VL2
VLCD
(Three-time-slice mode) VL1
VSS
TF = 3 × T
VL4
COMn VL2
VLCD
(Four-time-slice mode) VL1
VSS
TF = 4 × T
COMn
VL2
VLCD
(Six-time-slice mode) VL1
VSS
VL4
TF = 6 × T
COMn
VL2
VLCD
(Eight-time-slice mode) VL1
VSS
VL4
TF = 8 × T
< Example of calculation of LCD frame frequency (When four-time-slice mode is used) >
LCD clock: 32768/27 = 256 Hz (When setting to LCDC0 = 06H)
LCD frame frequency: 64 Hz
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(d) 1/4 bias method
VL4
VL3
COMn VL2 VLCD
(Six-time-slice mode) VL1
VSS
TF = 6 × T
VL4
VL3
COMn VL2 VLCD
(Eight-time-slice mode) VL1
VSS
TF = 8 × T
< Example of calculation of LCD frame frequency (When eight-time-slice mode is used) >
LCD clock: 32768/27 = 256 Hz (When setting to LCDC0 = 06H)
LCD frame frequency: 32 Hz
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Figure 21-24. Voltages and Phases of Common and Segment Signals (1/3)
(a) Static display mode (waveform A)
Select Deselect
VL4
Common signal VLCD
VSS
VL4
Segment signal VLCD
VSS
T T
T: One LCD clock period
(b) 1/2 bias method (waveform A)
Select Deselect
VL4
Common signal VL2 VLCD
VSS
VL4
Segment signal VL2 VLCD
VSS
T T
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(c) 1/3 bias method (waveform A)
Select Deselect
VL4
VL2
Common signal VLCD
VL1
VSS
VL4
VL2
Segment signal VLCD
VL1
VSS
T T
(d) 1/3 bias method (waveform B)
Select Deselect
VL4
VL2
Common signal VLCD
VL1
VSS
VL4
VL2
Segment signal VLCD
VL1
VSS
T/2 T/2 T/2 T/2
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(e) 1/4 bias method (waveform A)
Select Deselect
VL4
VL3
VL1
VSS
VL4
VL3
VL1
VSS
T T
(f) 1/4 bias method (waveform B)
Select Deselect
VL4
VL3
VL1
VSS
VL4
VL3
VL1
VSS
T/2 T/2 T/2 T/2
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21.10 Display Modes
21.10.1 Static display example

Figure 21-26 shows how the three-digit LCD panel having the display pattern shown in Figure 21-25 is connected to
the segment signals (SEG0 to SEG23) and the common signal (COM0). This example displays data “12.3” in the LCD
panel. The contents of the display data register (F0400H to F0417H) correspond to this display.
The following description focuses on numeral “2.” ( ) displayed in the second digit. To display “2.” in the LCD panel, it
is necessary to apply the select or deselect voltage to the SEG8 to SEG15 pins according to Table 21-14 at the timing of
the common signal COM0; see Figure 21-25 for the relationship between the segment signals and LCD segments.
Table 21-14. Select and Deselect Voltages (COM0)
Segment SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
Common
COM0 Select Deselect Select Select Deselect Select Select Select
According to Table 21-14, it is determined that the bit-0 pattern of the display data register locations (F0408H to
F040FH) must be 10110111.
Figure 21-27 shows the LCD drive waveforms of SEG11 and SEG12, and COM0. When the select voltage is applied
to SEG11 at the timing of COM0, an alternate rectangle waveform, +VLCD/–VLCD, is generated to turn on the corresponding
LCD segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected together
to increase the driving capacity.
Figure 21-25. Static LCD Display Pattern and Electrode Connections
SEG8n+3
SEG8n+4 SEG8n+2
SEG8n+5 COM0
SEG8n+6 SEG8n+1
SEG8n
SEG8n+7
Remark 100-pin products: n = 0 to 4
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Figure 21-26. Example of Connecting Static LCD Panel
COM 3
Timing Strobe
COM 2 Can be connected
COM 1 together
COM 0
Bit 3
Bit 2
Bit 1
Bit 0
SEG 0
F0400H
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0
SEG 1
1
SEG 2
2
SEG 3
3
SEG 4
4
SEG 5
5
SEG 6
6
SEG 7
7
SEG 8
8
Data memory address
SEG 9
9
SEG 10
A
LCD panel
SEG 11
B
SEG 12
C
SEG 13
D
SEG 14
E
SEG 15
F
SEG 16
F0410H
SEG 17
1
SEG 18
2
SEG 19
3
SEG 20
4
SEG 21
5
SEG 22
6
SEG 23
7
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Figure 21-27. Static LCD Drive Waveform Examples for SEG11, SEG12, and COM0
1 frame 1 frame
Internal signal LCD clock
VL4
COM0
VSS
VL4
COM1
VSS
VL4
COM2
VSS
VL4
COM3
VSS
VL4
SEG11
VSS
VL4
SEG12
VSS
COM0-SEG11
Lights Lights Lights Lights Lights Lights Lights Lights
+VL4
COM0-SEG11 0
-VL4
COM0-SEG12
Extinguishes Extinguishes Extinguishes Extinguishes Extinguishes Extinguishes Extinguishes Extinguishes
+VL4
COM0-SEG12 0
-VL4
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21.10.2 Two-time-slice display example

Figure 21-29 shows how the 6-digit LCD panel having the display pattern shown in Figure 21-28 is connected to the
segment signals (SEG0 to SEG23) and the common signals (COM0 and COM1). This example displays data “12345.6” in
the LCD panel. The contents of the display data register (F0400H to F0417H) correspond to this display.
The following description focuses on numeral “3” ( ) displayed in the fourth digit. To display “3” in the LCD panel, it is
necessary to apply the select or deselect voltage to the SEG12 to SEG15 pins according to Table 21-15 at the timing of
the common signals COM0 and COM1; see Figure 21-28 for the relationship between the segment signals and LCD
segments.
Table 21-15. Select and Deselect Voltages (COM0 and COM1)
Segment SEG12 SEG13 SEG14 SEG15
Common
COM0 Select Select Deselect Deselect
COM1 Deselect Select Select Select
According to Table 21-15, it is determined that the display data register location (F040FH) that corresponds to SEG15
must contain xx10.
Figure 21-30 shows examples of LCD drive waveforms between the SEG15 signal and each common signal. When
the select voltage is applied to SEG15 at the timing of COM1, an alternate rectangle waveform, +VLCD/–VLCD, is generated
to turn on the corresponding LCD segment.
Figure 21-28. Two-Time-Slice LCD Display Pattern and Electrode Connections
SEG4n+2 SEG4n+1 COM0
SEG4n+3 SEG4n
COM1
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Figure 21-29. Example of Connecting Two-Time-Slice LCD Panel
COM 3
Timing strobe
Open
COM 2
Open
COM 1
COM 0
Bit 3
Bit 2
Bit 1
Bit 0
SEG 0
F0400H
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1
SEG 1
1
SEG 2
2
SEG 3
3
SEG 4
4
SEG 5
5
SEG 6
6
SEG 7
7
Data memory address
SEG 8
8
SEG 9
9
SEG 10
A
LCD panel
SEG 11
B
SEG 12
C
SEG 13
D
SEG 14
E
SEG 15
F
SEG 16
F0410H
SEG 17
1
SEG 18
2
SEG 19
3
SEG 20
4
SEG 21
5
SEG 22
6
SEG 23
7
×: Can always be used to store any data because the two-time-slice mode is being used.
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Figure 21-30. Two-Time-Slice LCD Drive Waveform Examples Between SEG15 and Each Common Signals
(1/2 Bias Method)
1 frame 1 frame
VL4
COM0 VL2 = VL1
VSS
VL4
COM1 VL2 = VL1
VSS
VL4
SEG15 VL2 = VL1
VSS
COM0-SEG15
+VL4
+VL2 = +VL1
COM0-SEG15 0
-VL2 = -VL1
-VL4
COM1-SEG15
Extinguishes Lights Extinguishes Lights Extinguishes Lights Extinguishes Lights
+VL4
+VL2 = +VL1
COM1-SEG15 0
-VL2 = -VL1
-VL4
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21.10.3 Three-time-slice display example

segment signals (SEG0 to SEG23) and the common signals (COM0 to COM2). This example displays data “123456.78”
in the LCD panel. The contents of the display data register (addresses F0400H to F0417H) correspond to this display.
The following description focuses on numeral “6.” ( ) displayed in the third digit. To display “6.” in the LCD panel, it is
necessary to apply the select or deselect voltage to the SEG6 to SEG8 pins according to Table 21-16 at the timing of the
common signals COM0 to COM2; see Figure 21-31 for the relationship between the segment signals and LCD segments.
Table 21-16. Select and Deselect Voltages (COM0 to COM2)
Segment SEG6 SEG7 SEG8
Common
COM0 Deselect Select Select
COM1 Select Select Select
COM2 Select Select –
According to Table 21-16, it is determined that the display data register location (F0406H) that corresponds to SEG6
must contain x110.
Figures 21-33 and 21-34 show examples of LCD drive waveforms between the SEG6 signal and each common signal
in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to SEG6 at the timing of COM1 or COM2,
an alternate rectangle waveform, +VLCD/–VLCD, is generated to turn on the corresponding LCD segment.
Figure 21-31. Three-Time-Slice LCD Display Pattern and Electrode Connections
SEG3n+1 COM0
SEG3n+2 SEG3n
COM1
COM2
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Figure 21-32. Example of Connecting Three-Time-Slice LCD Panel
COM 3
Timing strobe
Open
COM 2
COM 1
COM 0
Bit 1
Bit 3
Bit 0
Bit 2
SEG 0
F0400H
× × × × × × × × × × × × × × × × ×
1 0 x’ 0 0 x’ 1 0 x’ 1 1 x’ 0 0 x’ 1 0
1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1
1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1
SEG 1
1
SEG 2
2
SEG 3
3
SEG 4
4
SEG 5
5
SEG 6
6
SEG 7
7
SEG 8
8
SEG 9
Data memory address
9
SEG 10
A
SEG 11
LCD panel
B
SEG 12
C
SEG 13
D
SEG 14
E
SEG 15
F
SEG 16
F0410H
SEG 17
x’ 0 0 x’ 1 0 x’
1
× × × × × × ×
0 0 1 1 1 0 0
0 0 1 0 1 1 0
SEG 18
2
SEG 19
3
SEG 20
4
SEG 21
5
SEG 22
6
SEG 23
7
×’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
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Figure 21-33. Three-Time-Slice LCD Drive Waveform Examples Between SEG6 and Each Common Signals
(1/2 Bias Method)
1 frame 1 frame
VL4
COM0 VL2 = VL1
VSS
VL4
COM1 VL2 = VL1
VSS
VL4
COM2 VL2 = VL1
VSS
VL4
SEG6 VL2 = VL1
VSS
COM0-SEG6
+VL4
+VL2 = +VL1
COM0-SEG6 0
-VL2 = -VL1
-VL4
COM1-SEG6
Extinguishes Lights Extinguishes Extinguishes Lights Extinguishes Extinguishes Lights
+VL4
+VL2 = +VL1
COM1-SEG6 0
-VL2 = -VL1
-VL4
COM2-SEG6
Extinguishes Extinguishes Lights Extinguishes Extinguishes Lights Extinguishes Extinguishes
+VL4
+VL2 = +VL1
COM2-SEG6 0
-VL2 = -VL1
-VL4
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Figure 21-34. Three-Time-Slice LCD Drive Waveform Examples Between SEG6 and Each Common Signals
(1/3 Bias Method)
1 frame 1 frame
VL4
VL2
COM0
VL1
VSS
VL4
VL2
COM1
VL1
VSS
VL4
VL2
COM2
VL1
VSS
VL4
VL2
SEG6
VL1
VSS
COM0-SEG6
+VL4
+VL2
+VL1
COM0-SEG6 0
-VL1
-VL2
-VL4
COM1-SEG6
Extinguishes Lights Extinguishes Extinguishes Lights Extinguishes Extinguishes Lights
+VL4
+VL2
+VL1
COM1-SEG6 0
-VL1
-VL2
-VL4
COM2-SEG6
Extinguishes Extinguishes Lights Extinguishes Extinguishes Lights Extinguishes Extinguishes
+VL4
+VL2
+VL1
COM2-SEG6 0
-VL1
-VL2
-VL4
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21.10.4 Four-time-slice display example

segment signals (SEG0 to SEG23) and the common signals (COM0 to COM3). This example displays data
“123456.789012” in the LCD panel. The contents of the display data register (addresses F0400H to F0417H) correspond
to this display.
The following description focuses on numeral “6.” ( ) displayed in the seventh digit. To display “6.” in the LCD panel, it
is necessary to apply the select or deselect voltage to the SEG12 and SEG13 pins according to Table 21-17 at the timing
of the common signals COM0 to COM3; see Figure 21-35 for the relationship between the segment signals and LCD
segments.
Segment SEG12 SEG13
Common
COM0 Select Select
COM1 Deselect Select
COM2 Select Select
COM3 Select Select
According to Table 21-17, it is determined that the display data register location (F040CH) that corresponds to SEG12
must contain 1101.
Figure 21-37 shows examples of LCD drive waveforms between the SEG12 signal and each common signal. When
the select voltage is applied to SEG12 at the timing of COM0, an alternate rectangle waveform, +VLCD/–VLCD, is generated
to turn on the corresponding LCD segment.
Figure 21-35. Four-Time-Slice LCD Display Pattern and Electrode Connections
SEG2n
COM0 COM1
COM2
COM3
SEG2n+1
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Figure 21-36. Example of Connecting Four-Time-Slice LCD Panel
COM 3
Timing strobe
COM 2
COM 1
COM 0
Bit 3
Bit 2
Bit 1
Bit 0
SEG 0
F0400H
0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0
0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1
0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
SEG 1
1
SEG 2
2
SEG 3
3
SEG 4
4
SEG 5
5
SEG 6
6
SEG 7
7
SEG 8
8
SEG 9
Data memory address
9
SEG 10
A
LCD panel
SEG 11
B
SEG 12
C
SEG 13
D
SEG 14
E
SEG 15
F
SEG 16
F0410H
SEG 17
1
SEG 18
2
SEG 19
3
SEG 20
4
SEG 21
5
SEG 22
6
SEG 23
7
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Figure 21-37. Four-Time-Slice LCD Drive Waveform Examples Between SEG12 and Each Common Signals
(1/3 Bias Method) (1/2)
(a) Waveform A
1 frame 1 frame
VL4
VL2
COM0
VL1
VSS
VL4
VL2
COM1
VL1
VSS
VL4
VL2
COM2
VL1
VSS
VL4
VL2
COM3
VL1
VSS
VL4
VL2
SEG12
VL1
VSS
COM0-SEG12
Lights Extinguishes Extinguishes Extinguishes Lights Extinguishes Extinguishes Extinguishes
+VL4
+VL2
+VL1
COM0-SEG12 0
-VL1
-VL2
-VL4
COM1-SEG12
+VL4
+VL2
+VL1
COM1-SEG12 0
-VL1
-VL2
-VL4
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Figure 21-37. Four-Time-Slice LCD Drive Waveform Examples Between SEG12 and Each Common Signals
(b) Waveform B
1 frame 1 frame
VL4
VL2
COM0
VL1
VSS
VL4
VL2
COM1
VL1
VSS
VL4
VL2
COM2
VL1
VSS
VL4
VL2
COM3
VL1
VSS
VL4
VL2
SEG12
VL1
VSS
COM0-SEG12
Lights Extinguishes Lights Extinguishes Lights Extinguishes Lights Extinguishes
+VL4
+VL2
+VL1
COM0-SEG12 0
-VL1
-VL2
-VL4
COM1-SEG12
+VL4
+VL2
+VL1
COM1-SEG12 0
-VL1
-VL2
-VL4
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21.10.5 Six-time-slice display example

Figure 21-39 shows how the 15x6 dot LCD panel having the display pattern shown in Figure 21-38 is connected to the
segment signals (SEG2 to SEG16) and the common signals (COM0 to COM5). This example displays data “123” in the
LCD panel. The contents of the display data register (addresses F0402H to F0410H) correspond to this display.
The following description focuses on numeral “3.” ( ) displayed in the first digit. To display “3.” in the LCD panel, it is
Segment SEG2 SEG3 SEG4 SEG5 SEG6
Common
COM0 Select Select Select Select Select
COM1 Deselect Select Deselect Deselect Deselect
COM2 Deselect Deselect Select Deselect Deselect
COM4 Select Deselect Deselect Deselect Select
COM5 Deselect Select Select Select Deselect
must contain 010001.
Figure 21-40 shows examples of LCD drive waveforms between the SEG2 signal and each common signal. When the
select voltage is applied to SEG2 at the timing of COM0, a waveform is generated to turn on the corresponding LCD
segment.
Figure 21-38. Six-Time-Slice LCD Display Pattern and Electrode Connections
S S S S S
E E E E E
G G G G G
5n+6 5n+5 5n+4 5n+3 5n+2
COM0
COM1
COM2
COM3
COM4
COM5
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Figure 21-39. Example of Connecting Six-Time-Slice LCD Panel
COM 7
Open
COM 6
Open
COM 5
Timing strobe COM 4
COM 3
COM 2
COM 1
COM 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG 2
F0402H
0 1 1 1 0 1 1 1 1 1 0 1 1 1 0
0 0 1 0 0 0 0 1 0 0 1 0 0 0 1
0 0 1 0 0 0 0 0 1 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 1 0 0 1 0 0
0 1 1 0 0 1 0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1 1 0 1 1 1 1 1
× × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × ×
SEG 3
3
SEG 4
4
SEG 5
5
SEG 6
Data memory address
6
SEG 7
7
LCD panel
SEG 8
8
SEG 9
9
SEG 10
A
SEG 11
B
SEG 12
C
SEG 13
D
SEG 14
E
SEG 15
F
SEG 16
F0410H
×: Can always be used to store any data because the six-time-slice mode is being used.
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Figure 21-40. Six-Time-Slice LCD Drive Waveform Examples Between SEG2 and Each Common Signals
(1/4 Bias Method)
(a) Waveform A
1 frame
VL4
VL3
COM0 VL2
VL1
VSS
VL4
VL3
COM1 VL2
VL1
VSS
VL4
VL3
COM2 VL2
VL1
VSS
..
.
VL4
VL3
COM5 VL2
VL1
VSS
VL4
VL3
SEG2 VL2
VL1
VSS
COM0-SEG2
Lights Extinguishes
+VL4
+VL3
+VL2
+VL1
COM0-SEG2 0
-VL1
-VL2
-VL3
-VL4
COM1-SEG2
Extinguishes
+VL4
+VL3
+VL2
+VL1
COM1-SEG2 0
-VL1
-VL2
-VL3
-VL4
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21.10.6 Eight-time-slice display example

Figure 21-42 shows how the 15x8 dot LCD panel having the display pattern shown in Figure 21-41 is connected to the
segment signals (SEG4 to SEG18) and the common signals (COM0 to COM7). This example displays data “123” in the
LCD panel. The contents of the display data register (addresses F0404H to F0412H) correspond to this display.
The following description focuses on numeral “3.” ( ) displayed in the first digit. To display “3.” in the LCD panel, it is
Segment SEG4 SEG5 SEG6 SEG7 SEG8
Common
COM0 Select Select Select Select Select
COM2 Deselect Deselect Select Deselect Deselect
COM4 Select Deselect Deselect Deselect Deselect
COM5 Select Deselect Deselect Deselect Select
COM6 Deselect Select Select Select Deselect
COM7 Deselect Deselect Deselect Deselect Deselect
must contain 00110001.
Figure 21-43 shows examples of LCD drive waveforms between the SEG4 signal and each common signal. When the
select voltage is applied to SEG4 at the timing of COM0, a waveform is generated to turn on the corresponding LCD
segment.
Figure 21-41. Eight-Time-Slice LCD Display Pattern and Electrode Connections
S S S S S
E E E E E
G G G G G
5n+8 5n+7 5n+6 5n+5 5n+4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
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RL78/I1C
Aug 31, 2018

Data memory address
Timing strobe
1
2
F
9
8
7
6
5
E
B
A
D
C
R01UH0587EJ0200 Rev.2.00
F0410H
F0404H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7
0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 Bit 6
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 Bit 5
0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 Bit 4
0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 Bit 3
0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 Bit 2
0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 Bit 1
0 0 1 0 0 0 1 1 1 0 1 1 1 1 1 Bit 0
SEG 9
SEG 8
SEG 7
SEG 6
SEG 5
SEG 4
SEG 18
SEG 17
SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
Figure 21-42. Example of Connecting Eight-Time-Slice LCD Panel
LCD panel
846
Figure 21-43. Eight-Time-Slice LCD Drive Waveform Examples Between SEG4 and Each Common Signals
(a) Waveform A
1 frame
VL4
VL3
COM0 VL2
VL1
VSS
VL4
VL3
COM1 VL2
VL1
VSS
VL4
VL3
COM2 VL2
VL1
VSS
..
.
VL4
VL3
COM7 VL2
VL1
VSS
VL4
VL3
SEG4 VL2
VL1
VSS
COM0-SEG4
Lights Extinguishes
+VL4
+VL3
+VL2
+VL1
COM0-SEG4 0
-VL1
-VL2
-VL3
-VL4
COM1-SEG4
Extinguishes
+VL4
+VL3
+VL2
+VL1
COM1-SEG4 0
-VL1
-VL2
-VL3
-VL4
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Figure 21-43. Eight-Time-Slice LCD Drive Waveform Examples Between SEG4 and Each Common Signals
(b) Waveform B
1 frame
VL4
VL3
COM0 VL2
VL1
VSS
VL4
VL3
COM1 VL2
VL1
VSS
VL4
VL3
COM2 VL2
VL1
VSS
..
.
VL4
VL3
COM7 VL2
VL1
VSS
VL4
VL3
SEG4 VL2
VL1
VSS
COM0-SEG4
Lights Extinguishes Lights Extinguishes
+VL4
+VL3
+VL2
+VL1
COM0-SEG4 0
-VL1
-VL2
-VL3
-VL4
COM1-SEG4
Extinguishes
+VL4
+VL3
+VL2
+VL1
COM1-SEG4 0
-VL1
-VL2
-VL3
-VL4
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RL78/I1C CHAPTER 22 DATA TRANSFER CONTROLLER (DTC)
CHAPTER 22 DATA TRANSFER CONTROLLER (DTC)
The term “8 higher-order bits of the address” in this chapter indicates bits 15 to 8 of 20-bit address as shown below.
20-bit address
4 highest-order bits 8 higher-order bits 8 lower-order bits
4 lower-order bits
Unless otherwise specified, the 4 highest-order address bits all become 1 (values are of the form FxxxxH).
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22.1 Functions of DTC
The data transfer controller (DTC) is a function that transfers data between memories without using the CPU. The DTC
is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the same bus, and the
DTC takes priority over the CPU in using the bus.
Table 22-1 lists the DTC specifications.
Table 22-1. DTC Specifications
Item Specification
<R> Activation sources 64- and 80-pin products: 36 sources, 100-pin products: 38 sources
Allocatable control data 24 sets
Address space Address space 64 Kbytes (F0000H to FFFFFH), excluding general-purpose registers
which can be Sources Special function register (SFR), RAM area (excluding general-purpose registers), mirror areaNote,
transferred data flash memory area Note, extended special function register (2nd SFR)
Destinations Special function register (SFR), RAM area (excluding general-purpose registers), extended
special function register (2nd SFR)
Maximum number Normal mode 256 times
of transfers Repeat mode 255 times
Maximum size of Normal mode 256 bytes
block to be (8-bit transfer)
transferred Normal mode 512 bytes
(16-bit transfer)
Repeat mode 255 bytes
Unit of transfers 8 bits/16 bits
Transfer mode Normal mode Transfers end on completion of the transfer causing the DTCCTj register value to change from 1
to 0.
Repeat mode On completion of the transfer causing the DTCCTj register value to change from 1 to 0, the
repeat area address is initialized and the DTRLDj register value is reloaded to the DTCCTj
register to continue transfers.
Address control Normal mode Fixed or incremented
Repeat mode Addresses of the area not selected as the repeat area are fixed or incremented.
Priority of activation sources See Table 22-5 DTC Activation Sources and Vector Addresses.
Interrupt request Normal mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed,
the activation source interrupt request is generated for the CPU, and interrupt handling is
performed on completion of the data transfer.
Repeat mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed
while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the activation
source interrupt request is generated for the CPU, and interrupt handling is performed on
completion of the transfer.
Transfer start When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data
transfer is started each time the corresponding DTC activation sources are generated.
Transfer stop Normal mode ● When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
● When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed.
Repeat mode ● When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
● When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed
while the RPTINT bit is 1 (interrupt generation enabled).
Note In the HALT and SNOOZE modes, these areas cannot be set as the sources for DTC transfer since the flash
memory is stopped.
Remark i = 0 to 4, j = 0 to 23
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22.2 Configuration of DTC
Figure 22-1 shows the DTC block diagram.
Figure 22-1. DTC Block Diagram
Peripheral interrupt signal
Interrupt source/ Data transfer control

transfer activation
source selection
Peripheral interrupt signal
DTCENi DTCBAR
Internal bus
RAM
Control data vector

table
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22.3 Registers Controlling DTC
Table 22-2 lists the registers controlling DTC.
Table 22-2. Registers Controlling DTC
Register Name Symbol

Peripheral Enable Register 1 PER1
DTC Activation Enable Register 0 DTCEN0
DTC Base Address Register DTCBAR
Table 22-3 lists DTC control data.

DTC control data is allocated in the DTC control data area in RAM.
The DTCBAR register is used to set the 256-byte area, including the DTC control data area and the DTC vector table
area where the start address for control data is stored.
Table 22-3. DTC Control Data

DTC Control Register j DTCCRj
DTC Block Size Register j DTBLSj
DTC Transfer Count Register j DTCCTj
DTC Transfer Count Reload Register j DTRLDj
DTC Source Address Register j DTSARj
DTC Destination Address Register j DTDARj
Remark j = 0 to 23
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22.3.1 Allocation of DTC control data area and DTC vector table area
The DTCBAR register is used to set the 256-byte area where DTC control data and the vector table within the RAM
area.
Figure 22-2 shows a memory map example when DTCBAR register is set to FBH.
In the 192-byte DTC control data area, the space not used by the DTC can be used as RAM.
Figure 22-2. Memory Map Example When DTCBAR Register Is Set to FBH (R5F10NPGDFB, R5F10NMGDFB,
R5F10NLGDFB)
FFFFFH
Special-function register
(SFR)
FFF00H
General-purpose
FFEE0H register FFC00H
FFBFFH
RAM
8 KB
FDF00H
Mirror
F2000H
Reserved DTC control data area
F17FFH 192 bytes
Data flash memory
F1000H
F0800H Reserved
Special-function register
(2nd SFR) FFB40H
F0000H Reserved area
24 bytes
FFB27H
Reserved
DTC vector table area
1FFFFH 40 bytes
Code flash memory FFB00H

128 KB
Value set in DTCBAR register DTC used area
00000H 256 bytes
The areas where the DTC control data and vector table can be allocated differ depending on the product.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as the DTC
control data area or DTC vector table area.
2. Make sure the stack area, the DTC control data area, and the DTC vector table area do not
overlap.
3. The internal RAM area in the following products cannot be used as the DTC control data area or
DTC vector table area when using the self-programming and data-flash functions.
R5F10NMJ, R5F10NPJ: FBF00H to FC309H
R5F10NMG, R5F10NLG: FDF00H to FE309H
4. The internal RAM area of the following products cannot be used as the DTC control data area or
DTC vector table area when using the trace function of on-chip debugging.
R5F10NMJ, R5F10NPJ: FC300H to FC6FFH
R5F10NMG, R5F10NLG: FE300H to FE6FFH
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22.3.2 Control data allocation

Control data is allocated beginning with each start address in the order: Registers DTCCRj, DTBLSj, DTCCTj, DTRLDj,
DTSARj, and DTDARj (j = 0 to 23).
The higher 8 bits for start addresses 0 to 23 are set by the DTCBAR register, and the lower 8 bits are separately set
according to the vector table assigned to each activation source.
Figure 22-3 shows control data allocation.
Cautions 1. Change the data in registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj when the
corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register is set to 0
(DTC activation disabled).
2. Do not access DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj using a DTC transfer.
Figure 22-3. Control Data Allocation
Start address of control data Address
FxxBEH DTDAR15 register

FxxF8H Control data 23
FxxBCH DTSAR15 register
8 bytes
FxxBBH DTRLD15 register
When j = 15 FxxBAH DTCCT15 register
FxxB9H DTBLS15 register
FxxB8H DTCCR15 register
FxxyyH Control data j
Fxx48H DTCCR1 register

Fxx50H Control data 2 Fxx46H DTDAR0 register
Fxx48H Control data 1
Fxx44H DTSAR0 register
Fxx40H Control data 0 8 bytes
Fxx43H DTRLD0 register
Fxx42H DTCCT0 register
Fxx41H DTBLS0 register
Fxx40H DTCCR0 register
Remark xx: Value set in DTCBAR register
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Table 22-4. Start Address of Control Data
j Address j Address
11 Fxx98H 23 FxxF8H
10 Fxx90H 22 FxxF0H
9 Fxx88H 21 FxxE8H
8 Fxx80H 20 FxxE0H
7 Fxx78H 19 FxxD8H
6 Fxx70H 18 FxxD0H
5 Fxx68H 17 FxxC8H
4 Fxx60H 16 FxxC0H
3 Fxx58H 15 FxxB8H
2 Fxx50H 14 FxxB0H
1 Fxx48H 13 FxxA8H
0 Fxx40H 12 FxxA0H
Remark xx: Value set in DTCBAR register
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22.3.3 Vector table

When the DTC is activated, one control data is selected according to the data read from the vector table which has
been assigned to each activation source, and the selected control data is read from the DTC control data area.
Table 22-5 lists the activation sources and vector addresses. A one byte of the vector table is assigned to each
activation source, and data from 40H to F8H is stored in each area to select one of the 24 control data sets. The higher 8
bits for the vector address are set by the DTCBAR register, and 00H to 27H are allocated to the lower 8 bits corresponding
to the activation source.
Caution Change the start address of the DTC control data area to be set in the vector table when the
corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register is set to 0
(activation disabled).
Figure 22-4. Start Address of Control Data and Vector Table
Example: When DTCBAR is set to FBH.
Control data 23
FFBF8H
Control data 15
FFB88H
DTC control data area
FFB40H to FFBF8H
(when DTCBAR is set to FBH)
Control data 2
FFB50H
Example: When the DTC
activating trigger is Control data 1
generated as a result of FFB48H
the A/D conversion
Control data 0
The DTC reads the control FFB40H
data at FFB88H in the
control data area of the
vector table (88H) and
transfers the data from the
Comparator
ADC. FFB27H 68H
detection 1
88H End of A/D

FFB0AH DTC vector table
conversion
FFB00H to FFB27H
(when DTCBAR is set to FBH)
FFB02H 48H INTP1

FFB01H 50H INTP0
FFB00H F8H Reserved
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Table 22-5. DTC Activation Sources and Vector Addresses
Interrupt Request Source Source No. Vector Address Priority

Reserved 0 Address set in DTCBAR register +00H Highest
INTP0 1 Address set in DTCBAR register +01H
Key return signal detection 9 Address set in DTCBAR register +09H
24-bit ΔΣ-type A/D converter 10 Address set in DTCBAR register +0AH
10-bit SAR-type A/D conversion end 11 Address set in DTCBAR register +0BH
UART0 reception transfer end 12 Address set in DTCBAR register +0CH
UART0 transmission transfer end/CSI00 transfer end or 13 Address set in DTCBAR register +0DH
buffer empty/IIC00 transfer end
UART1 reception transfer end 14 Address set in DTCBAR register +0EH
UART1 transmission transfer end 15 Address set in DTCBAR register +0FH
/CSI10 transfer end or buffer empty
/IIC10 transfer end
UART2 reception transfer end 16 Address set in DTCBAR register +10H
UART2 transmission transfer end 17 Address set in DTCBAR register +11H
UART3 reception transfer end Note 18 Address set in DTCBAR register +12H
UART3 transmission transfer end/CSI30 transfer end or 19 Address set in DTCBAR register +13H
buffer empty/IIC30 transfer end Note
End of channel 0 of timer array unit 0 count or capture 20 Address set in DTCBAR register +14H
End of channel 6 of timer array unit 0 count or capture 26 Address set in DTCBAR register +1AH
End of channel 7 of timer array unit 0 count or capture 27 Address set in DTCBAR register +1BH
8-bit interval timer 00 28 Address set in DTCBAR register +1CH
8-bit interval timer 01 29 Address set in DTCBAR register +1DH
8-bit interval timer 10 30 Address set in DTCBAR register +1EH
8-bit interval timer 11 31 Address set in DTCBAR register +1FH
12-bit interval timer detection 32 Address set in DTCBAR register +20H
AES encryption/decryption end 33 Address set in DTCBAR register +21H
Zero-cross detection 0 34 Address set in DTCBAR register +22H
Zero-cross detection 1 35 Address set in DTCBAR register +23H
External interrupt (RTCIC0) 36 Address set in DTCBAR register +24H
Reserved 39 Address set in DTCBAR register +27H Low
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The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
When using the DTC, be sure to set bit 3 (DTCEN) to 1.

Symbol 7 <6> 5 4 <3> 2 1 <0>
DTCEN Control of DTC input clock supply

● DTC cannot run.
● DTC can run.
Caution Be sure to clear bits 7, 5, 4, 2 and 1 to “0”.
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22.3.5 DTC control register j (DTCCRj) (j = 0 to 23)

The DTCCRj register is used to control the DTC operating mode.
Figure 22-6. Format of DTC Control Register j (DTCCRj)
Address: See 22.3.2 Control data allocation. After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
DTCCRj 0 SZ RPTINT CHNE DAMOD SAMOD RPTSEL MODE
SZ Transfer data size selection

0 8 bits
1 16 bits
RPTINT Enabling/disabling repeat mode interrupts

0 Interrupt generation disabled
1 Interrupt generation enabled
The setting of the RPTINT bit is invalid when the MODE bit is 0 (normal mode).
CHNE Enabling/disabling chain transfers

0 Chain transfers disabled
1 Chain transfers enabled
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
DAMOD Transfer destination address control

0 Fixed
1 Incremented
The setting of the DAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 0 (transfer
destination is the repeat area).
SAMOD Transfer source address control

0 Fixed
1 Incremented
The setting of the SAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 1 (transfer
source is the repeat area).
RPTSEL Repeat area selection

0 Transfer destination is the repeat area
1 Transfer source is the repeat area
The setting of the RPTSEL bit is invalid when the MODE bit is 0 (normal mode).
MODE Transfer mode selection

0 Normal mode
1 Repeat mode
Caution Do not access the DTCCRj register using a DTC transfer.
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22.3.6 DTC block size register j (DTBLSj) (j = 0 to 23)

This register is used to set the block size of the data to be transferred by one activation.
Figure 22-7. Format of DTC Block Size Register j (DTBLSj)
Symbol 7 6 5 4 3 2 1 0
DTBLSj DTBLSj7 DTBLSj6 DTBLSj5 DTBLSj4 DTBLSj3 DTBLSj2 DTBLSj1 DTBLSj0
DTBLSj Transfer block size

8-bit transfer 16-bit transfer
00H 256 bytes 512 bytes
01H 1 byte 2 bytes
02H 2 bytes 4 bytes
03H 3 bytes 6 bytes
... ... ...
FDH 253 bytes 506 bytes
FEH 254 bytes 508 bytes
FFH 255 bytes 510 bytes
Caution Do not access the DTBLSj register using a DTC transfer.
22.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23)

This register is used to set the number of DTC data transfers. The value is decremented by 1 each time DTC transfer is
activated once.
Figure 22-8. Format of DTC Transfer Count Register j (DTCCTj)
Symbol 7 6 5 4 3 2 1 0
DTCCTj DTCCTj7 DTCCTj6 DTCCTj5 DTCCTj4 DTCCTj3 DTCCTj2 DTCCTj1 DTCCTj0
DTCCTj Number of transfers

00H 256 times
01H Once
02H 2 times
03H 3 times
... ...
FDH 253 times
FEH 254 times
FFH 255 times
Caution Do not access the DTCCTj register using a DTC transfer.
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22.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23)

This register is used to set the initial value of the transfer count register in repeat mode. Since the value of this register
is reloaded to the DTCCT register in repeat mode, set the same value as the initial value of the DTCCT register.
Figure 22-9. Format of DTC Transfer Count Reload Register j (DTRLDj)
Symbol 7 6 5 4 3 2 1 0
DTRLDj DTRLDj7 DTRLDj6 DTRLDj5 DTRLDj4 DTRLDj3 DTRLDj2 DTRLDj1 DTRLDj0
Caution Do not access the DTRLDj register using a DTC transfer.
22.3.9 DTC source address register j (DTSARj) (j = 0 to 23)

This register is used to specify the transfer source address for data transfer.
When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest bit is ignored and the address is handled
as an even address.
Figure 22-10. Format of DTC Source Address Register j (DTSARj)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSARj DTSA DTSA DTSA DTS DTS DTSA DTS DTS DTS DTS DTS DTS DTS DTS DTS DTS
Rj15 Rj14 Rj13 ARj12 ARj11 Rj10 ARj9 ARj8 ARj7 ARj6 ARj5 ARj4 ARj3 ARj2 ARj1 ARj0
Cautions 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer source
address.
2. Do not access the DTSARj register using a DTC transfer.
22.3.10 DTC destination address register j (DTDARj) (j = 0 to 23)

This register is used to specify the transfer destination address for data transfer.
When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest bit is ignored and the address is handled
as an even address.
Figure 22-11. Format of DTC Destination Address Register j (DTDARj)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTDARj DTDA DTD DTD DTDA DTDA DTD DTD DTD DTD DTD DTD DTD DTD DTD DTD DTD
Rj15 ARj14 ARj13 Rj12 Rj11 ARj10 ARj9 ARj8 ARj7 ARj6 ARj5 ARj4 ARj3 ARj2 ARj1 ARj0
Cautions 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer source
address.
2. Do not access the DTDARj register using a DTC transfer.
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22.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4)

This is an 8-bit register which enables or disables DTC activation by interrupt sources. Table 22-6 lists the
correspondence between interrupt sources and bits DTCENi0 to DTCENi7.
The DTCENi register can be set by an 8-bit memory manipulation instruction or a 1-bit memory manipulation instruction.
Cautions 1. Modify bits DTCENi0 to DTCENi7 if an activation source corresponding to the bit has not been
generated.
2. Do not access the DTCENi register using a DTC transfer.
Figure 22-12. DTC Activation Enable Register i (DTCENi) (i = 0 to 4)
Address: F02E8H (DTCEN0), F02E9H (DTCEN1), F02EAH (DTCEN2), After reset: 00H R/W
F02EBH (DTCEN3), F02ECH (DTCEN4)
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
DTCENi DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0
DTCENi7 DTC activation enable i7

0 Activation disabled
1 Activation enabled
The DTCENi7 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.





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Table 22-6. Correspondences Between Interrupt Sources and Bits DTCENi0 to DTCENi7
Register DTCENi7 Bit DTCENi6 Bit DTCENi5 Bit DTCENi4 Bit DTCENi3 Bit DTCENi2 Bit DTCENi1 Bit DTCENi0 Bit
DTCEN0 Reserved INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6
UART0 UART1
transmission transmission
transfer end transfer end
10-bit SAR-
Key return 24-bit ΔΣ- UART0 /CSI00 UART1 /CSI10
type A/D
DTCEN1 INTP7 signal type A/D reception transfer end reception transfer end
conversion
detection converter transfer end or buffer transfer end or buffer
end
empty empty
/IIC00 /IIC10
transfer end transfer end
UART3
transmission
transfer end
End of End of End of End of
UART3 /CSI30
UART2 UART2 channel 0 of channel 1 of channel 2 of channel 3 of
reception transfer end
DTCEN2 reception transmission timer array timer array timer array timer array
transfer end or buffer
transfer end transfer end unit 0 count unit 0 count unit 0 count unit 0 count
Note empty
or capture or capture or capture or capture
/IIC30
transfer end
Note
End of End of End of End of

channel 4 of channel 5 of channel 6 of channel 7 of
8-bit interval 8-bit interval 8-bit interval 8-bit interval
DTCEN3 timer array timer array timer array timer array
timer 00 timer 01 timer 10 timer 11
unit 0 count unit 0 count unit 0 count unit 0 count
or capture or capture or capture or capture
Zero-cross Zero-cross
AES External External External
12-bit detection 0 detection 1
encryption/ interrupt interrupt interrupt
DTCEN4 interval timer of 24-bit ΔΣ- of 24-bit ΔΣ- Reserved
decryption request of request of request of
detection type A/D type A/D
end RTCIC0 pin RTCIC1 pin RTCIC2 pin
converter converter
Remark i = 0 to 4
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22.3.12 DTC base address register (DTCBAR)

This is an 8-bit register used to set the following addresses: the vector address where the start address of the DTC
control data area is stored and the address of the DTC control data area. The value of the DTCBAR register is handled as
the higher 8 bits to generate a 16-bit address.
Cautions 1. Change the DTCBAR register value with all DTC activation sources set to activation disabled.
2. Do not rewrite the DTCBAR register more than once.
3. Do not access the DTCBAR register using a DTC transfer.
4. For the allocation of the DTC control data area and the DTC vector table area, see the Notes on
22.3.1 Allocation of DTC control data area and DTC vector table area.
Figure 22-13. Format of DTC Base Address Register (DTCBAR)
Address: F02E0H After reset: FDH R/W

Symbol 7 6 5 4 3 2 1 0
DTCBAR DTCBAR7 DTCBAR6 DTCBAR5 DTCBAR4 DTCBAR3 DTCBAR2 DTCBAR1 DTCBAR0
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22.4 DTC Operation
When the DTC is activated, control data is read from the DTC control data area to perform data transfers and control
data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can be stored in the
DTC control data area, which allows 24 types of data transfers to be performed.
There are two transfer modes (normal mode and repeat mode) and two transfer sizes (8-bit transfer and 16-bit transfer).
When the CHNE bit in the DTCCRj (j = 0 to 23) register is set to 1 (chain transfers enabled), multiple control data is read
and data transfers are continuously performed by one activation source (chain transfers).
A transfer source address is specified by the 16-bit register DTSARj, and a transfer destination address is specified by
the 16-bit register DTDARj.
The values in registers DTSARj and DTDARj are separately incremented or fixed according to the control data after the
data transfer.
22.4.1 Activation sources

The DTC is activated by an interrupt signal from the peripheral functions. The interrupt signals to activate the DTC are
selected with the DTCENi (i = 0 to 4) register.
The DTC sets the corresponding bit among bits DTCENi0 to DTCENi7 in the DTCENi register to 0 (activation disabled)
during operation when the setting of data transfer (the first transfer in chain transfers) is either of the following:
- A transfer that causes the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode
- A transfer that causes the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1
(interrupt generation enabled) in repeat mode
Figure 22-14 shows the DTC internal operation flowchart.
Figure 22-14. DTC Internal Operation Flowchart
Branch (1)
DTC activation source 0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated when transfer is
generation either of the following:
- A transfer that causes the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- A transfer that causes the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode
Read DTC vector Remark:

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 4) register
RPTINT, CHNE: Bits in DTCCRj (j = 0 to 23) register
Read control data

(Note)
Write 0 to the bit among bits
Yes DTCENi0 to DTCENi7
Branch (1) Generate an interrupt
request
No
Read control data Transfer data Read control data

Transfer data
Write back Write back Transfer data

Transfer data control data
control data
Yes Yes Write back

Write back
CHNE = 1? CHNE = 1? control data
control data
No No Yes
Yes CHNE = 1?
CHNE = 1?
No No
End Interrupt handling
Note 0 is not written to the bit among bits DTCENi0 to DTCENi7 for data transfers activated by the setting to enable chain
transfers (the CHNE bit is 1). Also, no interrupt request is generated.
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22.4.2 Normal mode

One to 256 bytes of data are transferred by one activation during 8-bit transfer and 2 to 512 bytes during 16-bit transfer.
The number of transfers can be 1 to 256 times. When the data transfer causing the DTCCTj (j = 0 to 23) register value to
change to 0 is performed, the DTC generates an interrupt request corresponding to the activation source to the interrupt
controller during DTC operation, and sets the corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the
DTCENi register to 0 (activation disabled).
Table 22-7 shows register functions in normal mode. Figure 22-15 shows data transfers in normal mode.
Table 22-7. Register Functions in Normal Mode
Register Name Symbol Function

DTC block size register j DTBLSj Size of the data block to be transferred by one activation
DTC transfer count register j DTCCTj Number of data transfers
DTC transfer count reload register j DTRLDj Not usedNote
DTC source address register j DTSARj Data transfer source address
DTC destination address register j DTDARj Data transfer destination address
Note Initialize this register to 00H when parity error resets are enabled (RPERDIS = 0) using the RAM parity error
detection function.
Remark j = 0 to 23
Figure 22-15. Data Transfers in Normal Mode
FFFFFH
Transfer
Size of the data block to be transferred
by one activation
(N bytes)
SRC DST
DTBLSj register = N
DTSARj register = SRC
DTDARj register = DST
j = 0 to 23
F0000H
DTCCR Register Setting Source Address Destination Address Source Address Destination Address
DAMOD SAMOD RPTSEL MODE Control Control after Transfer after Transfer
0 0 X 0 Fixed Fixed SRC DST
0 1 X 0 Incremented Fixed SRC + N DST
1 0 X 0 Fixed Incremented SRC DST + N
1 1 X 0 Incremented Incremented SRC + N DST + N
X: 0 or 1
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(1) Example 1 of using normal mode: Consecutively capturing A/D conversion results
The DTC is activated by an A/D conversion end interrupt and the value of the A/D conversion result register is
transferred to RAM.
● The vector address is FFB0AH and control data is allocated at FFBA0H to FFBA7H
● Transfers 2-byte data of the A/D conversion result register (FFF1EH, FFF1FH) to 80 bytes of FFD80H to
FFDCFH of RAM for 40 times.
Figure 22-16. Example 1 of Using Normal Mode: Consecutively Capturing A/D Conversion Results
DTCBAR = FBH
Vector address (FFB0AH) = A0H

DTCCR12 (FFBA0H) = 48H
DTBLS12 (FFBA1H) = 01H FDCEH
DTCCT12 (FFBA2H) = 28H
DTSAR12 (FFBA4H) = FF1EH RAM
DTDAR12 (FFBA6H) = FD80H
A/D conversion result
register FD80H
DTCEN15 = 1
Starting A/D conversion
A/D conversion No
end interrupt?
Yes
Yes
DTCCT12 = 01H?
No Occurrence of A/D conversion

end interrupt
DTCEN15 = 0
Data transfer
Data transfer
Interrupt handling
The processing shown inside the dotted

line is automatically executed by the DTC.
The value of the DTRLD12 register is not used because of normal mode, but initialize the register to 00H when parity
error resets are enabled (RPERDIS = 0) using the RAM parity error detection function.
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(2) Example 2 of using normal mode: UART0 consecutive transmission

The DTC is activated by a UART0 transmit buffer empty interrupt and the value of RAM is transferred to the
UART0 transmit buffer.
● The vector address is FFB0CH and control data is allocated at FFBC8H to FFBCFH
● Transfers 8 bytes of FFCF8H to FFCFFH of RAM to the UART0 transmit buffer (FFF10H)
Figure 22-17. Example 2 of Using Normal Mode: UART0 Consecutive Transmission
DTCBAR = FBH
Vector address (FFB0CH) = C8H

DTCCR17 (FFBC8H) = 04H
DTBLS17 (FFBC9H) = 01H
DTCCT17 (FFBCAH) = 08H FCFFH
DTSAR17 (FFBCCH) = FCF8H UART0 transmit buffer
DTDAR17 (FFBCEH) = FF10H
RAM
FCF8H
DTCEN13 = 1
Starting UART0 transmission
No
Transmit buffer
empty interrupt?
Yes
Yes
DTCCT17 = 01H?
No Occurrence of UART0 transmit

buffer empty interrupt
DTCEN13 = 0
Data transfer
Data transfer
Interrupt handling

The value of the DTRLD17 register is not used because of normal mode, but initialize the register to 00H when parity
error resets are enabled (RPERDIS = 0) using the RAM parity error detection function.
Start the first UART0 transmission by software. The second and subsequent transmissions are automatically sent
when the DTC is activated by a transmit buffer empty interrupt.
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22.4.3 Repeat mode

One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be
specified as the repeat area. The number of transfers can be 1 to 255 times. On completion of the specified number of
transfers, the DTCCTj (j = 0 to 23) register and the address specified for the repeat area are initialized to continue
transfers. When the data transfer causing the DTCCTj register value to change to 0 is performed while the RPTINT bit in
the DTCCRj register is 1 (interrupt generation enabled), the DTC generates an interrupt request corresponding to the
activation source to the interrupt controller during DTC operation, and sets the corresponding bit among bits DTCENi0 to
DTCENi7 (i = 0 to 4) in the DTCENi register to 0 (activation disabled). When the RPTINT bit in the DTCCRj register is 0
(interrupt generation disabled), no interrupt request is generated even if the data transfer causing the DTCCTj register
value to change to 0 is performed. Also, bits DTCENi0 to DTCENi7 are not set to 0.
Table 22-8 lists register functions in repeat mode. Figure 22-18 shows data transfers in repeat mode.
Table 22-8. Register Functions in Repeat Mode
Register Name Symbol Function

DTC block size register j DTBLSj Size of the data block to be transferred by one activation
DTC transfer count register j DTCCTj Number of data transfers
DTC transfer count reload register j DTRLDj This register value is reloaded to the DTCCT register
(the number of transfers is initialized).
DTC source address register j DTSARj Data transfer source address
DTC destination address register j DTDARj Data transfer destination address
Remark j = 0 to 23
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Figure 22-18. Data Transfers in Repeat Mode
DTCCTj register = 1
FFFFFH
Transfer
Size of the data block to be transferred
by one activation
(N bytes)
SRC DST
DTBLSj register = N
DTCCTj register = 1
j = 0 to 23
F0000H
DAMOD SAMOD RPTSEL MODE Control Control After Transfer After Transfer
0 X 1 1 Repeat area Fixed SRC + N DST
1 X 1 1 Repeat area Incremented SRC + N DST + N
X 0 0 1 Fixed Repeat area SRC DST + N
X 1 0 1 Incremented Repeat area SRC + N DST + N
X: 0 or 1
DTCCTj register = 1
FFFFFH
DTBLSj register = N
DTCCTj register = 1
SRC/DST
j = 0 to 23
SRC0/DST0
Address of the repeat area is initialized after a data transfer
F0000H
DAMOD SAMOD RPTSEL MODE Control Control After Transfer After Transfer
0 X 1 1 Repeat area Fixed SRC0 DST
1 X 1 1 Repeat area Incremented SRC0 DST + N
X 0 0 1 Fixed Repeat area SRC DST0
X 1 0 1 Incremented Repeat area SRC + N DST0
SRC0: Initial source address value

DST0: Initial destination address value
X: 0 or 1
Cautions 1. When repeat mode is used, the lower 8 bits of the initial value for the repeat area address must be
00H.
2. When repeat mode is used, the data size of the repeat area must be set to 255 bytes or less.
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(1) Example of using repeat mode: Outputting a stepping motor control pulse using ports
The DTC is activated by an interval timer interrupt and the pattern of the motor control pulse stored in the code
flash memory is transferred to general-purpose ports.
● The vector address is FFC0CH and control data is allocated at FFCD0H to FFCD7H
● Transfers 8-byte data of 02000H to 02007H of the code flash memory from the mirror space (F2000H to
F2007H) to port register 1 (FFF01H)
● A repeat mode interrupt is disabled
Figure 22-19. Example 1 of Using Repeat Mode: Outputting a Stepping Motor Control Pulse Using Ports
DTCBAR = FCH
Vector address (FFC17H) = D0H

DTCCR23 (FFCD0H) = 03H
DTBLS23 (FFCD1H) = 01H
DTCCT23 (FFCD2H) = 08H 2007H
DTRLD23 (FFCD3H) = 08H Port register 1
DTSAR23 (FFCD4H) = 2000H
DTDAR23 (FFCD6H) = FF01H
Code flash
2000H
DTCEN20 = 1
Timer setting
Setting P10 to P13 to output mode
Starting timer operation No P13

Interval timer interrupt?
P12
P11
Yes
P10
Yes
DTCCT23 = 01H?
Example of 1-2 phase excitation
Data transfer No
DTCCT23 = DTRLD23 Data transfer

To stop the output, stop the timer first and then clear DTCEN20.
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22.4.4 Chain transfers

When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers can be
continuously performed by one activation source.
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area. When the
CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately following the current control
data is read and transferred after the current transfer is completed. This operation is repeated until the data transfer with
the control data for which the CHNE bit is 0 (chain transfers disabled) is completed.
When chain transfers are performed using multiple control data, the number of transfers set for the first control data is
enabled, and the number of transfers set for the second and subsequent control data to be processed will be invalid
Figure 22-20 shows data transfers during chain transfers.
Figure 22-20. Data Transfers During Chain Transfers
FFFFFH
DTC activation source generation
Read DTC vector
DTDAR2 register
Read control data 1
DTSAR2 register
Control data 2
DTRLD2 register DTCCT2 register (the CHNE bit is 0)
Transfer data
DTBLS2 register DTCCR2 register
DTDAR1 register
Write back control data 1
DTSAR1 register Control data 1
(the CHNE bit is 1)
DTRLD1 register DTCCT1 register
Read control data 2
DTBLS1 register DTCCR1 register
Higher address Lower address

Transfer data
Write back control data 2
F0000H
End of DTC transfers
Cautions 1. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
2. During chain transfers, bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register are not set to
0 (DTC activation disabled) for the second and subsequent transfers. Also, no interrupt request is
generated.
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(1) Example of using chain transfers: Consecutively capturing A/D conversion results and UART transmission
The DTC is activated by an A/D conversion end interrupt and A/D conversion results are transferred to RAM, and
then transmitted using the UART.
● The vector address is FFB0AH
● Control data of capturing A/D conversion results is allocated at FFBA0H to FFBA7H
● Control data of UART transmission is allocated at FFBA8H at FFBAFH
● An A/D conversion end interrupt is assigned to TRIGER23
● Transfers 2-byte data of the A/D conversion result register (FFF1FH, FFF1EH) to FFD80H to FFDCFH of RAM,
and transfers the upper 1 byte (FFF1FH) of the A/D conversion result register to the UART transmit buffer
(FFF10H)
Figure 22-21. Example of Using Chain Transfers: Consecutively Capturing A/D Conversion Results and UART
Transmission
DTCBAR = FBH
Setting control data of capturing UART transmit buffer

A/D conversion results
Vector address (FFB0AH) = A0H
DTCCR10 (FFBA0H) = 58H
DTBLS10 (FFBA1H) = 01H
DTCCT10 (FFBA2H) = 50H A/D conversion result FDCEH
DTRLD10 (FFBA3H) = 50H register
DTSAR10 (FFBA4H) = FF1EH RAM
DTDAR10 (FFBA6H) = FD80H
FD80H
Setting control data
of UART transmission
Vector address (FFB0CH) = C8H
DTCCR12 (FFBC8H) = 00H
DTBLS12 (FFBC9H) = 01H
DTCCT12 (FFBCAH) = 00H
DTRLD12 (FFBCBH) = 00H
DTSAR12 (FFBCCH) = FF1FH A/D conversion No
DTDAR12 (FFBCEH) = FF10H end interrupt?
Yes
DTCEN15 = 1
Yes
DTCCT10 = 01H?
UART setting Occurrence of INTDTC10

No
DTCEN15 = 0
Transfer from A/D conversion
Starting A/D conversion result register to RAM
Transfer from A/D conversion
result register to RAM
Transfer from A/D conversion result
register to UART transmit buffer
Transfer from A/D conversion result
register to UART transmit buffer

line is automatically executed by the DTC. Interrupt handling
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22.5 Notes on DTC
22.5.1 Setting DTC control data and vector table
● Do not access the DTC SFRs, the DTC control data area, the DTC vector table area, or the general-register (FFEE0H
to FFEFFH) space using a DTC transfer.
● Modify the DTC base address register (DTCBAR) while all DTC activation sources are set to activation disabled.
● Do not rewrite the DTC base address register (DTCBAR) twice or more.
● Modify the data of the DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj register when the corresponding bit
among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (DTC activation disabled).
● Modify the start address of the DTC control data area to be set in the vector table when the corresponding bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (DTC activation disabled).
● Do not allocate RAM addresses which are used as a DTC transfer destination/transfer source to the area FFE20H to
FFEDFH when performing self-programming and rewriting the data flash memory.
22.5.2 Allocation of DTC control data area and DTC vector table area
The areas where the DTC control data and vector table can be allocated differ.
● It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as the DTC control data area or DTC
vector table area.
● Make sure the stack area, the DTC control data area, and the DTC vector table area do not overlap.
● The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector table
area when using the self-programming and data-flash functions.
R5F10NMJ, R5F10NPJ: FBF00H to FC309H
R5F10NMG, R5F10NLG: FDF00H to FE309H
● The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector table
area when using the on-chip trace function.
R5F10NMJ, R5F10NPJ: FC300H to FC6FFH
R5F10NMG, R5F10NLG: FE300H to FE6FFH
● Initialize the DTRLD register to 00H even in normal mode when parity error resets are enabled (RPERDIS = 0) using
the RAM parity error detection function.
22.5.3 DTC pending instruction

Even if a DTC transfer request is generated, data transfer is held pending immediately after the following instructions.
Also, the DTC is not activated between PREFIX instruction code and the instruction immediately after that code.
● Call/return instruction
● Unconditional branch instruction
● Conditional branch instruction
● Read access instruction for code flash memory
● Bit manipulation instructions for IFxx, MKxx, PRxx, and PSW, and an 8-bit manipulation instruction that has the ES
register as operand
● Instruction for accessing the data flash memory
● Instruction of Multiply, Divide, Multiply & Accumulate (excluding MULU)
Cautions 1. When a DTC transfer request is acknowledged, all interrupt requests are held pending until DTC
transfer is completed.
2. While the DTC is held pending by the DTC pending instruction, all interrupt requests are held
pending.
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22.5.4 Operation when accessing data flash memory space

When accessing the data flash space after an instruction execution from the start of DTC data transfer, a wait of
three clock cycles will be inserted to the next instruction.
Instruction 1
DTC data transfer
Instruction ← The wait of three clock cycles occurs.
MOV A, ! Data Flash space
22.5.5 Number of DTC execution clock cycles

Table 22-8 lists the operations following DTC activation and required number of clock cycles for each operation.
Table 22-9. Operations Following DTC Activation and Required Number of Cycles
Control Data
Vector Read Data Read Data Write
Read Write-back
1 4 Note 1 Note 2 Note 2
Notes 1. For the number of clock cycles required for control data write-back, see Table 22-10 Number of Clock
Cycles Required for Control Data Write-Back Operation.
2. For the number of clock cycles required for data read/write, see Table 22-11 Number of Clock Cycles
Required for Data Read/Write Operation.
Table 22-10. Number of Clock Cycles Required for Control Data Write-Back Operation
DTCCR Register Setting Address Setting Control Register to be Written Back Number
DTCCTj DTRLDj DTSARj DTDARj of Clock
DAMOD SAMOD RPTSEL MODE Source Destination
Register Register Register Register Cycles
Written Written Not written Not written

0 0 X 0 Fixed Fixed 1
back back back back
Written Written Written Not written
0 1 X 0 Incremented Fixed 2
back back back back
Written Written Not written Written
1 0 X 0 Fixed Incremented 2
back back back back
Written Written Written Written
1 1 X 0 Incremented Incremented 3
back back back back
Written Written Written Not written
0 X 1 1 Fixed 2
back back back back
Repeat area
1 X 1 1 Incremented 3
back back back back
Written Written Not written Written
X 0 0 1 Fixed 2
back back back back
Repeat area
X 1 0 1 Incremented 3
back back back back
Remark j = 0 to 23; X: 0 or 1
Table 22-11. Number of Clock Cycles Required for Data Read/Write Operation
Operation RAM Code Flash Data Flash SFR 2nd SFR

Memory Memory No Wait State Wait States
Data read 1 2 4 1 1 1 + number of wait statesNote
Data write 1 - - 1 1 1 + number of wait statesNote
Note The number of wait states differs depending on the specifications of the register allocated to the second SFR to
be accessed.
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22.5.6 DTC response time

Table 22-12 lists the DTC response time. The DTC response time is the time from when the DTC activation source is
detected until DTC transfer starts, excluding the number of DTC execution clocks.
Table 22-12. DTC Response Time
Minimum Time Maximum Time

Response Time 3 clocks 19 clocks
Note that the response from the DTC may be further delayed under the following cases. The number of delayed clock
cycles differs depending on the conditions.
● When executing an instruction from the internal RAM

Maximum response time: 20 clocks
● When executing a DTC pending instruction (see 22.5.3 DTC pending instruction)
Maximum response time: Maximum response time for each condition + execution clock cycles for the instruction
to be held pending under the condition.
● When accessing a register that a wait occurs
Maximum response time: Maximum response time for each condition + 1 clock
Remark 1 clock: 1/fCLK (fCLK: CPU/peripheral hardware clock)
22.5.7 DTC activation sources
● After inputting a DTC activation source, do not input the same activation source again until DTC transfer is completed.
● While a DTC activation source is generated, do not manipulate the DTC activation enable bit corresponding to the
source.
● If DTC activation sources conflict, their priority levels are determined in order to select the source for activation when
the CPU acknowledges the DTC transfer. For details on the priority levels of activation sources, see 22.3.3 Vector
table.
● When DTC activation is enabled under either of the following conditions, a DTC transfer is started and an interrupt is
generated after completion of the transfer. Therefore, enable DTC activation after confirming the comparator monitor
flag (CnMON) as necessary. (n = 0, 1)
- The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt request at the rising
edge for the comparator, and IVCMP > IVREF (or internal reference voltage: 1.45 V)
- The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt request at the falling
edge for the comparator, and IVCMP < IVREF (or internal reference voltage: 1.45 V)
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22.5.8 Operation in standby mode status
Status DTC Operation

HALT mode Operable (Operation is disabled while in the low power consumption RTC mode)
STOP mode DTC activation sources can be acceptedNote 2
SNOOZE mode OperableNotes 1, 3, 4, 5
Notes 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock (fIH) or the middle-
speed on-chip oscillator clock (fIM) is selected as fCLK.
2. In the STOP mode, detecting a DTC activation source enables transition to SNOOZE mode and DTC
transfer. After completion of transfer, the system returns to the STOP mode. However, since the code flash
memory and the data flash memory are stopped during the HALT or SNOOZE mode, the flash memory
cannot be set as the transfer source.
3. When a transfer end interrupt is set as a DTC activation source from the CSIp SNOOZE mode function,
release the SNOOZE mode using the transfer end interrupt to start CPU processing after completion of DTC
transfer, or use a chained transfer to set CSIp reception again (writing 1 to the STm0 bit, writing 0 to the
SWCm bit, setting of the SSCm register, and writing 1 to the SSm0 bit).
4. When a transfer end interrupt is set as a DTC activation source from the UARTq SNOOZE mode function,
release the SNOOZE mode using the transfer end interrupt to start CPU processing after completion of DTC
transfer, or use a chained transfer to set UARTq reception again (writing 1 to the STm1 bit, writing 0 to the
SWCm bit, setting of the SSCm register, and writing 1 to the SSm1 bit).
5. When an A/D conversion end interrupt is set as a DTC activation source from the A/D converter SNOOZE
mode function, release the SNOOZE mode using the A/D conversion end interrupt to start CPU processing
after completion of DTC transfer, or use a chained transfer to set the A/D converter SNOOZE mode function
again after clear the AWC bit.
Caution The SNOOZE function for the DTC and the SNOOZE function for UART cannot be used at the same
time.
Remark p = 00; q = 0; m = 0
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RL78/I1C CHAPTER 23 EVENT LINK CONTROLLER (ELC)
CHAPTER 23 EVENT LINK CONTROLLER (ELC)
23.1 Functions of ELC
The event link controller (ELC) mutually connects (links) events output from each peripheral function. By linking events,
it becomes possible to coordinate operation between peripheral functions directly without going through the CPU.
The ELC has the following functions.
● Capable of directly linking event signals from 22 types of peripheral functions to specified peripheral functions
● Event signals can be used as activation sources for operating any one of five types of peripheral functions
23.2 Configuration of ELC
Figure 23-1 shows the ELC block diagram.
Figure 23-1. ELC Block Diagram
Internal bus
Event output destination select register

ELSELRn (n = 00 to 19)
Peripheral function Event control Peripheral function

(Event output side) (Link connection processor) (Event receive side)
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23.3 Registers Controlling ELC
Table 23-1 lists the registers controlling ELC.
Table 23-1. Registers Controlling ELC

Event output destination select register 00 ELSELR00
Timer input select register 0 TIS0
A/D converter mode register 1 ADM1
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23.3.1 Event output destination select register n (ELSELRn) (n = 00 to 21)

An ELSELRn register links each event signal to an operation of an event-receiving peripheral function (link destination
peripheral function) after reception.
Do not set multiple event inputs to the same event output destination (event receive side). The operation of the event-
receiving peripheral function will become undefined, and event signals may not be received correctly. In addition, do not
set the event link generation source and the event link output destination to the same function. Set an ELSELRn register
during a period when no event output peripheral functions are generating event signals.
Table 23-2 lists the correspondence between ELSELRn (n = 00 to 21) registers and peripheral functions, and Table 23-
3 lists the correspondence between values set to ELSELRn (n = 00 to 21) registers and operation of link destination
peripheral functions at reception.
Figure 23-2. Format of Event Output Destination Select Register n (ELSELRn)
Address: F0240H (ELSELR00) to F0255H (ELSELR21) After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
ELSELRn 0 0 0 0 0 ELSELRn2 ELSELRn1 ELSELRn0
ELSELRn2 ELSELRn1 ELSELRn1 Event link selection
0 0 0 Event link disabled

0 0 1 Select operation of peripheral function 1 to linkNote
Note See Table 23-3 Correspondence Between Values Set to ELSELRn (n = 00 to 21) Registers and Operation
of Link Destination Peripheral Functions at Reception.
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Table 23-2. Correspondence Between ELSELRn (n = 00 to 21) Registers and Peripheral Functions
Register Name Event Generator (Output Origin of Event Input n) Event Description
ELSELR00 External interrupt edge detection 0 INTP0

ELSELR08 Key return signal detection INTKR
ELSELR09 12-bit interval timer interval signal detection INTIT
ELSELR10 8-bit interval timer channel 00 compare match or INTIT00
16-bit interval timer channel 0 compare match (cascaded)
ELSELR11 8-bit interval timer channel 10 compare match or INTIT10
16-bit interval timer channel 1 compare match (cascaded)
ELSELR12 Fixed-cycle signal of real-time clock INTRTCPRD
ELSELR13 TAU channel 00 count end/capture end INTTM00
ELSELR19 24-bit ΔΣ-type A/D conversion end INTDSAD
ELSELR20 Zero-cross detection 0 of 24-bit ΔΣ-type A/D converter INTDSADZC0
ELSELR21 Zero-cross detection 1 of 24-bit ΔΣ-type A/D converter INTDSADZC1
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Table 23-3. Correspondence Between Values Set to ELSELRn (n = 00 to 21) Registers and Operation of Link
Destination Peripheral Functions at Reception
Bits ELSELRn2 to ELSELRn0 Link Destination Link Destination Operation When Receiving Event
in ELSELRn Register Number Peripheral Function
001B 1 A/D converter A/D conversion starts

010B 2 Timer input of timer array Delay counter, input pulse interval measurement,
unit channel 0Note 1 external event counter
Notes 1. To select the timer input of timer array unit channel 0 as the link destination peripheral function, set the
operating clock for channel 0 to fCLK using timer clock select register 0 (TPS0), set the noise filter of the TI00
pin to OFF (TNFEN00 = 0) using noise filter enable register 1 (NFEN1), and then set the timer output used
for channel 0 to an event input signal from the ELC using timer input select register 0 (TIS0).
2. To select the timer input of timer array unit channel 1 as the link destination peripheral function, set the
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23.3.2 Timer input select register 0 (TIS0)

The TIS0 register is used to select the timer input for channels 0, 1, 5, 6, and 7 of the timer array unit (TAU0).
Figure 23-3. Format of Timer Input Select Register 0 (TIS0)

Symbol 7 6 5 4 3 2 1 0
TIS07 TIS06 Selection of timer input used with channel 7
0 0 Input signal of timer input pin (TI07)

0 1 RTCOUT output signal
1 0 RxD0 input pin
1 1 Event input signal from ELC



0 1 1 Middle-speed on-chip oscillator clock (fIM)
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This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal.
The ADM1 register can be set by a 1-bit or an 8-bit memory manipulation instruction.

Symbol 7 6 5 4 3 2 1 0
ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0
ADTRS1 ADTRS0 Selection of the hardware trigger signal
0 0 End of timer channel 01 count or capture interrupt signal (INTTM01)

0 1 Event signal selected by ELC
1 0 Independent power supply RTC alarm interrupt signal (INTRTCALM), independent power
supply RTC fixed-cycle interrupt signal (INTRTCPRD)
1 1 12-bit interval timer interrupt signal (INTIT)
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23.4 ELC Operation
The path for using an event signal generated by a peripheral function as an interrupt request to the interrupt control
circuit is independent from the path for using it as an ELC event. Therefore, each event signal can be used as an event
signal for operation of an event-receiving peripheral function, regardless of interrupt control.
Figure 23-5 shows the relationship between interrupt handling and ELC. The figure show an example of an interrupt
request status flag and a peripheral function possessing the enable bits that control enabling/disabling of such interrupts.
A peripheral function which receives an event from the ELC will perform the operation corresponding to the event-
receiving peripheral function after reception of an event (See Table 23-3 Correspondence Between Values Set to
ELSELRn (n = 00 to 21) Registers and Operation of Link Destination Peripheral Functions at Reception).
Figure 23-5. Relationship Between Interrupt Handling and ELC
Peripheral function (Event output side)
Interrupt request Peripheral function

ELC
(Event signal) (Event receive side)
Status flag Note
Interrupt control
Interrupt enable CPU
circuit
control Note
Note Not available depending on the peripheral function.
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Table 23-4 lists the response of peripheral functions that receive events.
Table 23-4. Response of Peripheral Functions That Receive Events
Event
Event Link Destination
Receiver Operation after Event Reception Response
Function
No.
1 A/D converter A/D conversion An event from the ELC is directly used as a
hardware trigger of A/D conversion.
2 Timer array unit Delay counter The edge is detected 3 or 4 cycles of fCLK after
Timer input of channel 0 Input pulse width measurement an ELC event is generated.
External event counter
23.5 Points for Caution when Using the ELC
● Attempting to link multiple event inputs to a single event trigger is prohibited.

● Ensure that conditions for the generation of an event signal are not satisfied in a related peripheral module while
setting control registers of the ELC.
● Setting the same module as the source of an event signal and destination for linkage is prohibited.
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RL78/I1C CHAPTER 24 INTERRUPT FUNCTIONS
CHAPTER 24 INTERRUPT FUNCTIONS
The interrupt function switches the program execution to other processing. When the branch processing is finished, the
program returns to the interrupted processing.
64-pin 80-pin 100-pin
Maskable interrupts External 9 12 12

Internal 41 41 44
24.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts

These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H, PR13L).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two
or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed
according to the default priority of vectored interrupt servicing. Default priority, see Table 24-1.
A standby release signal is generated and STOP, HALT, and SNOOZE modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
(2) Software interrupts

This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are
disabled. The software interrupt does not undergo interrupt priority control.
24.2 Interrupt Sources and Configuration
Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to seven reset
sources (see Table 24-1). The vector codes that store the program start address when branching due to the generation of
a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
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Table 24-1. Interrupt Source List (1/4)

Interrupt Interrupt Source Internal/ Vector
Default PriorityNote 1
TypeNote 2
Basic Configuration
100-pin
80-pin
64-pin
Type External Table
Name Trigger Address
Maskable 0 INTWDTI Watchdog timer intervalNote 3 Internal 0004H (A) √ √ √

(75% of overflow time+1/2fIL)
1 INTLVI Voltage detectionNote 4 0006H √ √ √
Note 5
2 INTP0 Pin input edge detection External 0008H (B) √ √ √
3 INTP1 000AH √ √ √
4 INTP2 000CH √ √ √
5 INTP3 000EH √ √ √
6 INTP4 0010H √ √ √
7 INTP5 0012H √ √ √
8 INTST2 UART2 transmission transfer end or buffer empty Internal 0014H (A) √ √ √
interrupt
9 INTSR2 UART2 reception transfer end 0016H √ √ √
10 INTSRE2 UART2 reception communication error occurrence 0018H √ √ √
11 INTCR End of high-speed on-chip oscillator clock 001AH √ √ √
frequency correction
12 INTAES AES encryption/decryption end 001CH √ √ √
INTAESF AES encryption/decryption end of first block √ √ √
13 INTST0/ UART0 transmission transfer end or buffer 001EH √ √ √
INTCSI00/ empty interrupt/CSI00 transfer end or buffer
INTIIC00 empty interrupt/IIC00 transfer end
14 INTIICA0 End of IICA0 communication 0020H √ √ √
16 INTSRE0 UART0 reception communication error 0024H √ √ √
occurrence
INTTM01H End of timer channel 01 count or capture (at √ √ √
higher 8-bit timer operation)
17 INTST1/ UART1 transmission transfer end or buffer 0026H √ √ √
19 INTSRE1 UART1 reception communication error 002AH √ √ √
occurrence
INTTM03H End of timer channel 03 count or capture (at √ √ √
higher 8-bit timer operation)
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 42 indicates the lowest priority.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 24-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
5. The input buffer power supply of P137 pins is connected to internal VDD. For PIOR04 = 0, interrupts can be
accepted even when a battery backup function is used and power is supplied from the VBAT pin.
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TypeNote 2
Basic Configuration
100-pin
80-pin
64-pin
Type External Table
Name Trigger Address
Maskable 20 INTTM00 End of timer channel 00 count or capture Internal 002CH (A) √ √ √
22 INTFM End of frequency measurement 0030H √ √ √
23 INTTM01 End of timer channel 01 count or capture (at 16- 0032H √ √ √
bit/lower 8-bit timer operation)
24 INTTM02 End of timer channel 02 count or capture 0034H √ √ √
25 INTTM03 End of timer channel 03 count or capture (at 16- 0036H √ √ √
bit/lower 8-bit timer operation)
26 INTAD End of A/D conversion 0038H √ √ √
27 INTRTCALM Alarm match detection of real-time clock 003AH √ √ √
INTRTCPRD Fixed-cycle signal of real-time clock √ √ √

28 INTIT Interval signal of 12-bit interval timer detection 003CH √ √ √
29 INTKR Key return signal detection External 003EH (B) √ √ √
30 INTST3/ UART3 transmission transfer end or buffer Internal 0040H (A) √ - -
31 INTSR3 UART3 reception transfer end 0042H √ - -
32 INTDSAD End of ΔΣ A/D conversion 0044H √ √ √
35 INTP6 Pin input edge detection External 004AH (B) √ √ √
36 INTP7 004CH √ √ √
37 INTRTCIC0 Tamper detection of RTCIC0 pin 004EH √ √ -
Note 3
38 INTRTCIC1 Tamper detection of RTCIC1 pin 0050H √ √ -

Note 3
39 INTRTCIC2 Tamper detection of RTCIC2 pin 0052H √ √ -

Note 3
40 INTTM06 End of timer channel 06 count or capture Internal 0054H (A) √ √ √

42 INTIT00 8-bit interval timer channel 00/channel 0 (when 0058H √ √ √
cascade) compare match detection
43 INTIT01 8-bit interval timer channel 01 compare match 005AH √ √ √
detection
3. The input buffer power supply of the INTRTCIC0, INTRTCIC1, and INTRTCIC2 pins is connected to
internal VDD. Interrupts can be accepted even when a battery backup function is used and power is
supplied from the VBAT pin.
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TypeNote 2
Basic Configuration
100-pin
80-pin
64-pin
Type External Table
Maskable Name Trigger Address
Maskable 44 INTSRE3 UART3 reception communication error Internal 005CH (A) √ - -

occurrence
45 INTMACLOF Multiply-accumulation overflow/underflow 005EH √ √ √
interrupt
46 INTOSDC Oscillation stop detection 0060H √ √ √
Note 3
47 INTFL Reserved 0062H √ √ √
48 INTDSADZC Zero-cross detection 0 of 24-bit ΔΣ-type A/D 0064H √ √ √
0 converter
49 INTDSADZC Zero-cross detection 1 of 24-bit ΔΣ-type A/D 0066H √ √ √
1 converter
50 INTIT10 8-bit interval timer channel 10/channel 1 (when 0068H √ √ √
cascade) compare match detection
51 INTIT11 8-bit interval timer channel 11 compare match 006AH √ √ √
detection
52 INTLVDVDD Voltage detection of VDD pin 006CH √ √ √
53 INTLVDVBA Voltage detection of VBAT pin 006EH √ √ √
T
54 INTLVDVRT Voltage detection of VRTC pin 0070H √ √ √
C
55 INTLVDEXL Voltage detection of EXLVD pin 0072H √ √ √
VD
3. Be used at the flash self-programming library or the data flash library.
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TypeNote 2
Basic Configuration
100-pin
80-pin
64-pin
Type External Table
Address
Software – BRK Execution of BRK instruction – 007EH (C) √ √ √

Reset – RESET RESET pin input – 0000H – √ √ √
POR Power-on-reset √ √ √
Note 3
LVD Voltage detection √ √ √
WDT Overflow of watchdog timer √ √ √
TRAP Execution of illegal instructionNote 4 √ √ √
IAW Illegal-memory access √ √ √
RPE RAM parity error √ √ √
3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1.
4. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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Figure 24-1. Basic Configuration of Interrupt Function
(A) Internal maskable interrupt
Internal bus
MK IE PR1 PR0 ISP1 ISP0
Interrupt Vector table

Priority controller
request IF address generator
Standby release
signal
(B) External maskable interrupt (INTPn, RTCICm)
Internal bus
External interrupt edge

enable register MK IE PR1 PR0 ISP1 ISP0
(EGP, EGN)
Priority controller Vector table

INTPn, RTCICm pin input Edge
IF address generator
detector
Standby release
signal
(C) Software interrupt
Internal bus
Interrupt Vector table

request address generator
IF: Interrupt request flag

IE: Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
Remark n = 0 to 7, m = 0 to 2
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24.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
● Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L)
● Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)
● Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H, PR13L)
● External interrupt rising edge enable register (EGP0, EGP1)
● External interrupt falling edge enable register (EGN0, EGN1)
● Program status word (PSW)
Table 24-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to
interrupt request sources.
Table 24-2. Flags Corresponding to Interrupt Request Sources (1/3)
Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Source
INTWDTI WDTIIF IF0L WDTIMK MK0L WDTIPR0, WDTIPR1 PR00L,

INTLVI LVIIF LVIMK LVIPR0, LVIPR1 PR10L
INTP0 PIF0 PMK0 PPR00, PPR10

INTST2 STIF2 IF0H STMK2 MK0H STPR02, STPR12 PR00H,
INTSR2 SRIF2 SRMK2 SRPR02, SRPR12 PR10H
INTSRE2 SREIF2 SREMK2 SREPR02, SREPR12

INTCR CRIF CRMK CRPR0, CRPR1
INTAES AESIF AESMK AESPR0, AESPR1
INTAESF AESFIF AESFMK AESFPR0, AESFPR1
INTCSI00 CSIIF00 CSIMK00 CSIPR000, CSIPR100
INTIIC00 IICIF00 IICMK00 IICPR000, IICPR100
INTST0 STIF0 STMK0 STPR00, STPR10
INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10
INTSR0 SRIF0 SRMK0 SRPR00, SRPR10
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Source
INTSRE0 SREIF0 IF1L SREMK0 MK1L SREPR00, SREPR10 PR01L,

INTTM01H TMIF01H TMMK01H TMPR001H, TMPR101H PR11L

INTSRE1 SREIF1 SREMK1 SREPR01 SREPR11
INTTM03H TMIF03H TMMK03H TMPR003H, TMPR103H
INTTM00 TMIF00 TMMK00 TMPR000, TMPR100
INTFM FMIF FMMK FMPR0, FMPR1
INTTM02 TMIF02 IF1H TMMK02 MK1H TMPR002, TMPR102 PR01H,
INTTM03 TMIF03 TMMK03 TMPR003, TMPR103 PR11H
INTAD ADIF ADMK ADPR0, ADPR1

INTRTCALM RTCAIF RTCAMK RTCAPR0, RTCAPR1
INTRTCPRD RTCRIF RTCRMK RTCRPR0, RTCRPR1
INTIT TMKAIF TMKAMK TMKAPR0, TMKAPR1
INTKR KRIF KRMK KRPR0, KRPR1
INTDSAD DSAIF IF2L DSAMK MK2L DSAPR0, DSAPR1 PR02L,
INTTM04 TMIF04 TMMK04 TMPR004, TMPR104 PR12L

INTRTCIC0 RTCIIF0 RTCIMK0 RTCIPR00, RTCIPR10
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Source
INTTM06 TMIF06 IF2H TMMK06 MK2H TMPR006, TMPR106 PR02H,

INTTM07 TMIF07 TMMK07 TMPR007, TMPR107 PR12H
INTIT00 ITIF00 ITMK00 ITPR000, ITPR100

INTSRE3 SREIF3 SREMK3 SREPR03, SREPR13
INTMACLOF MACIF MACMK MACPR0, MACPR1
INTOSDC OSDIF OSDMK OSDPR0, OSDPR1
INTFL FLIF FLMK FLPR0, FLPR1
INTDSADZC0 DSAZIF0 IF3L DSAZMK0 MK3L DSAZPR00, DSAZPR10 PR03L,
INTDSADZC1 DSAZIF1 DSAZMK1 DSAZPR01, DSAZPR11 PR13L

INTLVDVDD LVDVDIF LVDVDMK LVDVDPR0, LVDVDPR1
INTLVDVBAT LVDVBIF LVDVBMK LVDVBPR0, LVDVBPR1
INTLVDVRTC LVDVRIF LVDVRMK LVDVRPR0, LVDVRPR1
INTLVDEXLVD LVDEXIF LVDEXMK LVDEXPR0, LVDEXPR1
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24.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, and IF3L registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, and the IF2L and IF2H registers are
combined to form 16-bit registers IF0, IF1, and IF2, they can be set by a 16-bit memory manipulation instruction.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 24-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (1/2)
Address: FFFE0H After reset: 00H R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H SRIF0 IICAIF0 STIF0 AESIF CRIF SREIF2 SRIF2 STIF2

CSIIF00 AESFIF
IICIF00

Symbol <7> <6> 5 <4> <3> <2> <1> <0>
IF1L TMIF01 FMIF 0 TMIF00 SREIF1 SRIF1 STIF1 SREIF0

TMIF03H IICIF10 TMIF01H
CSIIF10

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1H SRIF3 STIF3 KRIF TMKAIF RTCAIF ADIF TMIF03 TMIF02

CSIIF30 RTCRIF
IICIF30
Address: FFFD0H After reset: 00H R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF2L RTCIIF2 RTCIIF1 RTCIIF0 PIF7 PIF6 TMIF05 TMIF04 DSAIF

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF2H FLIF OSDIF MACIF SREIF3 ITIF01 ITIF00 TMIF07 TMIF06
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Figure 24-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (2/2)

Symbol <7> <6> <5 <4> <3> <2> <1> <0>
IF3L LVDEXIF LVDVRIF LVDVBIF LVDVDIF ITIF11 ITIF10 DSAZIF1 DSAZIF0
XXIFX Interrupt request flag
0 No interrupt request signal is generated

1 Interrupt request is generated, interrupt request status
Cautions 1. For details about the bits, see Table 24-2. Be sure to clear bits that are not available to 0.
2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
“IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
“IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to 0
at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
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24.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt.
The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, and MK3L registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, and the MK2L and MK2H registers are
combined to form 16-bit registers MK0, MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Figure 24-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)
Address: FFFE4H After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H SRMK0 IICAMK0 STMK0 AESMK CRMK SREMK2 SRMK2 STMK2

CSIMK00 AESFMK
IICMK00

Symbol <7> <6> 5 <4> <3> <2> <1> <0>
MK1L TMMK01 FMMK 1 TMMK00 SREMK1 SRMK1 STMK1 SREMK0

TMMK03H IICMK10 TMMK01H
CSIMK10

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK1H SRMK3 STMK3 KRMK TMKAMK RTCAMK ADMK TMMK03 TMMK02

CSIMK30 RTCRMK
IICMK30
Address: FFFD4H After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK2L RTCIMK2 RTCIMK1 RTCIMK0 PMK7 PMK6 TMMK05 TMMK04 DSAMK

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK2H FLMK OSDMK MACMK SREMK3 ITMK01 ITMK00 TMMK07 TMMK06

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK3L LVDEXMK LVDVRMK LVDVBMK LVDVDMK ITMK11 ITMK10 DSAZMK1 DSAZMK0
XXMKX Interrupt servicing control
0 Interrupt servicing enabled

1 Interrupt servicing disabled
Caution For details about the bits, see Table 24-2. Be sure to set bits that are not available to the initial value.
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24.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H, PR13L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, 2H, or 3L).
The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, and
the PR13L registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, the
PR01L and PR01H registers, the PR02L and PR02H registers, the PR10L and PR10H registers, the PR11L and PR11H
registers, and the PR12L and PR12H registers are combined to form 16-bit registers PR00, PR01, PR02, PR10, PR11,
and PR12, they can be set by a 16-bit memory manipulation instruction.
Figure 24-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (1/2)

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0
Address: FFFECH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00H SRPR00 IICAPR00 STPR00 AESPR0 CRPR0 SREPR02 SRPR02 STPR02

CSIPR000 AESFPR0
IICPR000
Address: FFFEDH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10H SRPR10 IICAPR10 STPR10 AESPR1 CRPR1 SREPR12 SRPR12 STPR12

CSIPR100 AESFPR1
IICPR100
Address: FFFEAH After reset: FFH R/W

Symbol <7> <6> 5 <4> <3> <2> <1> <0>
PR01L TMPR001 FMPR0 1 TMPR000 SREPR01 SRPR01 STPR01 SREPR00
TMPR003H IICPR010 TMPR001H
CSIPR010
Address: FFFEEH After reset: FFH R/W

Symbol <7> <6> 5 <4> <3> <2> <1> <0>
PR11L TMPR101 FMPR1 1 TMPR100 SREPR11 SRPR11 STPR11 SREPR10

TMPR103H IICPR110 TMPR101H
CSIPR110
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Figure 24-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (2/2)
Address: FFFEBH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR01H SRPR03 CSIPR030 KRPR0 TMKAPR0 RTCAPR0 ADPR0 TMPR003 TMPR002

IICPR030 RTCRPR0
STPR03
Address: FFFEFH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR11H SRPR13 STPR13 KRPR1 TMKAPR1 RTCAPR1 ADPR1 TMPR103 TMPR102

IICPR130 RTCRPR1
CSIPR130

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR02L RTCIPR02 RTCIPR01 RTCIPR00 PPR07 PPR06 TMPR005 TMPR004 DSAPR0
Address: FFFDCH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR12L RTCIPR12 RTCIPR11 RTCIPR10 PPR17 PPR16 TMPR105 TMPR104 DSAPR1

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR02H FLPR0 OSDPR0 MACPR0 SREPR03 ITPR001 ITPR000 TMPR007 TMPR006
Address: FFFDDH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR12H FLPR1 OSDPR1 MACPR1 SREPR13 ITPR101 ITPR100 TMPR107 TMPR106
Address: FFFDAH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR03L LVDEXPR0 LVDVRPR0 LVDVBPR0 LVDVDPR0 ITPR011 ITPR010 DSAZPR01 DSAZPR00
Address: FFFDEH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR13L LVDEXPR1 LVDVRPR1 LVDVBPR1 LVDVDPR1 ITPR111 ITPR110 DSAZPR11 DSAZPR10
XXPR1X XXPR0X Priority level selection

0 0 Specify level 0 (high priority level)
0 1 Specify level 1
1 0 Specify level 2
1 1 Specify level 3 (low priority level)
Caution For details about the bits, see Table 24-2. Be sure to set bits that are not available to the initial value.
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24.3.4 External interrupt rising edge enable register (EGP0, EGP1), External interrupt falling edge enable register
(EGN0, EGN1)
These registers specify the valid edge for INTP0 to INTP7 and RTCIC0 to RTCIC2.
The EGP0, EGP1, EGN0 and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 24-5. Format of External Interrupt Rising Edge Enable Register (EGP0, EGP1) and External Interrupt
Falling Edge Enable Register (EGN0, EGN1)

Symbol 7 6 5 4 3 2 1 0
EGP0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0

Symbol 7 6 5 4 3 2 1 0
EGN0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
Address: FFF3AH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
EGP1 0 EGP14 EGP13 EGP12 0 0 0 0
Address: FFF3BH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
EGN1 0 EGN14 EGN13 EGN12 0 0 0 0
EGPn EGNn INTP0 to INTP7 and RTCIC0 to RTCIC2 pin valid edge selection
(n = 0 to 7, 12 to 14)
0 0 Edge detection disabled

0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
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Table 24-3 shows the ports corresponding to the EGPn and EGNn bits.
Table 24-3. Ports Corresponding to EGPn and EGNn bits
Detection Enable Bit Interrupt Request Signal 80, 100-pin 64-pin
EGP0 EGN0 INTP0 √ √

EGP12 EGP12 RTCIC0 √ -
EGP13 EGN13 RTCIC1 √ -
EGP14 EGN14 RTCIC2 √ -
Caution When the input port pins used for the external interrupt functions are switched to the output mode,
the INTPn interrupt might be generated upon detection of a valid edge.
When switching the input port pins to the output mode, set the port mode register (PMxx) to 0 after
disabling the edge detection (by setting EGPn and EGNn to 0).
Remarks 1. For edge detection port, see 2.1 Port Function.

2. n = 0 to 7, 12 to 14
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24.3.5 Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for an interrupt
request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. Upon acknowledgment of a
maskable interrupt request, if the value of the priority specification flag register of the acknowledged interrupt is not 00, its
value minus 1 is transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH
PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 24-6. Configuration of Program Status Word
<7> <6> <5> <4> <3> <2> <1> 0 After reset
PSW IE Z RBS1 AC RBS0 ISP1 ISP0 CY 06H
Used when normal instruction is executed
ISP1 ISP0 Priority of interrupt currently being serviced

0 0 Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
0 1 Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
1 0 Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
1 1 Enables all interrupts
(waits for acknowledgment of an interrupt).
IE Interrupt request acknowledgment enable/disable

0 Disabled
1 Enabled
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24.4 Interrupt Servicing Operations
24.4.1 Maskable interrupt request acknowledgment

A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK)
flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
Table 24-4 below.
For the interrupt request acknowledgment timing, see Figures 24-8 and 24-9.
Table 24-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time Maximum TimeNote
Servicing time 9 clocks 16 clocks
Note Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 24-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 24-7. Interrupt Request Acknowledgment Processing Algorithm
Start
No
××IF = 1?
Yes (interrupt request generation)
No
××MK = 0?
Yes
Interrupt request held pending
(××PR1, ××PR0) No (Low priority)

≥ (ISP1, ISP0)
Higher priority No
than other interrupt requests
simultaneously
generated?
Yes Interrupt request held pending
Higher default
priorityNote than other interrupt No
requests with the same priority
simultaneously
generated?
Yes
No
IE = 1?
Yes
Vectored interrupt servicing
××IF: Interrupt request flag

××MK: Interrupt mask flag
××PR0: Priority specification flag 0
××PR1: Priority specification flag 1
IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 24-6)
Note For the default priority, see Table 24-1 Interrupt Source List.
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Figure 24-8. Interrupt Request Acknowledgment Timing (Minimum Time)
6 clocks
PSW and PC saved, Interrupt servicing
CPU processing Instruction Instruction jump to interrupt
servicing program
xxIF
9 clocks
Figure 24-9. Interrupt Request Acknowledgment Timing (Maximum Time)
8 clocks 6 clocks
Previous interrupt PSW and PC saved, Interrupt servicing

CPU processing Instruction Instruction jump to interrupt
instruction servicing program
xxIF
16 clocks
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24.4.2 Software interrupt request acknowledgment

A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH,
0007FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Can not use the RETI instruction for restoring from the software interrupt.
24.4.3 Multiple interrupt servicing

Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE =
1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to
enable interrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupt servicing.
<R> In the interrupt enabled state, if an interrupt request with a priority higher than that of the interrupt currently being
serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority equal to or lower
than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple
interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or
because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt
request is acknowledged following execution of at least one main processing instruction execution.
Table 24-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 24-10
shows multiple interrupt servicing examples.
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Table 24-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request Maskable Interrupt Request Software

Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Interrupt
(PR = 00) (PR = 01) (PR = 10) (PR = 11) Request
Interrupt Being Serviced IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0

Maskable interrupt ISP1 = 0 O × × × × × × × O
ISP0 = 0
ISP1 = 0 O × O × × × × × O
ISP0 = 1
ISP1 = 1 O × O × O × × × O
ISP0 = 0
ISP1 = 1 O × O × O × O × O
ISP0 = 1
Software interrupt O × O × O × O × O
Remarks 1. O: Multiple interrupt servicing enabled

2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for an interrupt acknowledgment (all interrupts are enabled).
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in the PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H, and PR13L registers.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
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Figure 24-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI IE = 0 IE = 0 IE = 0
EI EI
INTxx INTyy INTzz

(PR = 11) (PR = 10) (PR = 01)
RETI
IE = 1
IE = 1 RETI IE = 1 RETI
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
EI IE = 0
EI
INTxx INTyy
(PR = 10) (PR = 11)
RETI
IE = 1
1 instruction execution IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.

IE = 0: Interrupt request acknowledgment is disabled
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Figure 24-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing INTxx servicing INTyy servicing
IE = 0
EI
INTyy
INTxx (PR = 00)
(PR = 11) RETI
IE = 1
IE = 0
1 instruction execution
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request
INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held
pending, and is acknowledged following execution of one main processing instruction.

IE = 0: Interrupt request acknowledgment is disabled
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24.4.4 Interrupt servicing during division instruction

The RL78/I1C handles interrupts during the DIVHU/DIVWU instruction in order to enhance the interrupt response when
a division instruction is executed.
● When an interrupt is generated while the DIVHU/DIVWU instruction is executed, the instruction is suspended
● After the instruction is suspended, the PC indicates the next instruction after DIVHU/DIVWU
● An interrupt is generated by the next instruction
● PC-3 is stacked to execute the DIVHU/DIVWU instruction again
Normal interrupt Interrupts while Executing DIVHU/DIVWU Instruction

(SP-1) ← PSW (SP-1) ← PSW
(SP-2) ← (PC)S (SP-2) ← (PC-3)S
(SP-3) ← (PC)H (SP-3) ← (PC-3)H
(SP-4) ← (PC)L (SP-4) ← (PC-3)L
PCS ← 0000 PCS ← 0000
PCH ← (Vector) PCH ← (Vector)
PCL ← (Vector) PCL ← (Vector)
SP ← SP-4 SP ← SP-4
IE ← 0 IE ← 0
The AX, BC, DE, and HL registers are used for DIVHU/DIVWU. Use these registers by stacking them for interrupt
servicing.
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MOVW AX, #8081H Interrupt1 Interrupt2
MOVW BC, #8080H PUSH AX PUSH AX
MOVW DE, #0002H PUSH BC PUSH BC
MOVW HL, #0000H PUSH DE PUSH DE
PUSH HL PUSH HL
DIVWU
MOVW !addr16, AX
MOVW AX, BC DIVWU DIVWU
MOVW !addr16, AX
MOVW AX, DE
POP HL POP HL
MOVW !addr16, AX
POP DE POP DE
MOVW AX, HL
POP BC POP BC
MOVW !addr16, AX
POP AX POP AX
RETI RETI
Caution Disable interrupts when executing the DIVHU or DIVWU instruction in an interrupt servicing routine.
Alternatively, unless they are executed in the RAM area, note that execution of a DIVHU or DIVWU
instruction is possible even with interrupts enabled as long as a NOP instruction is added
immediately after the DIVHU or DIVWU instruction in the assembly language source code.
The following compilers automatically add a NOP instruction immediately after any DIVHU or DIVWU
instruction output during the build process.
- V. 1.71 and later versions of the CA78K0R (Renesas Electronics compiler), for both C and
assembly language source code
- Service pack 1.40.6 and later versions of the EWRL78 (IAR compiler), for C language source code
- GNURL78 (KPIT compiler), for C language source code
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24.4.5 Interrupt request hold

There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
● MOV PSW, #byte

● MOV PSW, A
● MOV1 PSW. bit, CY
● SET1 PSW. bit
● CLR1 PSW. bit
● RETB
● RETI
● POP PSW
● BTCLR PSW. bit, $addr20
● EI
● DI
● SKC
● SKNC
● SKZ
● SKNZ
● SKH
● SKNH
● MULHU
● MULH
● MACHU
● MACH
● Write instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H,
and PR13L registers
Figure 24-11 shows the timing at which interrupt requests are held pending.
Figure 24-11. Interrupt Request Hold
PSW and PC saved, jump Interrupt servicing

CPU processing Instruction N Instruction M
to interrupt servicing program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction

2. Instruction M: Instruction other than interrupt request hold instruction
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RL78/I1C CHAPTER 25 KEY INTERRUPT FUNCTION
CHAPTER 25 KEY INTERRUPT FUNCTION
The number of key interrupt input channels differs, depending on the product.

Key interrupt input channels 5 ch 8 ch 8 ch
25.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by inputting a rising edge/falling edge to the key interrupt input pins (KR0 to
KR3).
Table 25-1. Assignment of Key Interrupt Detection Pins
Key Interrupt Pins Key Return Mode Register 0 (KRM0)
KR0 KRM00
KR1 KRM01
KR2 KRM02
KR3 KRM03
KR4 KRM04
KR5 KRM05
KR6 KRM06
KR7 KRM07
Remark KR0 to KR4: 64-pin products

KR0 to KR7: 80, 100-pin products
25.2 Configuration of Key Interrupt
The key interrupt includes the following hardware.
Table 25-2. Configuration of Key Interrupt
Item Configuration
Control registers Key return control register (KRCTL)

Key return mode register 0 (KRM0)
Key return flag register (KRF)
Port mode register 7 (PM7)
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Figure 25-1. Block Diagram of Key Interrupt
KREG KRMD
Selector
KR7
KRF7
KREG KRMD
Selector
KR6
KRF6
INTKR
KREG KRMD
Selector
KR1
KRF1
KREG KRMD
Selector
KR0
KRF0
KRM07 KRM06 KRM01 KRM00

Key return mode register (KRM0)
Remark KR0 to KR4: 64-pin products

KR0 to KR7: 80, 100-pin products
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25.3 Register Controlling Key Interrupt
The key interrupt function is controlled by the following registers.

● Key return control register (KRCTL)
● Key return mode register 0 (KRM0)
● Key return flag register (KRF)
25.3.1 Key return control register (KRCTL)

This register controls the usage of the key return flags (KRF0 to KRF7) and sets the detection edge.
The KRCTL register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 25-2. Format of Key Return Control Register (KRCTL)

Symbol <7> 6 5 4 3 2 1 <0>
KRCTL KRMD 0 0 0 0 0 0 KREG
KRMD Usage of key return flags (KRF0 to KRF7)
0 Does not use key return flags

1 Uses key return flags
KREG Selection of detection edge (KR0 to KR7)
0 Falling edge
1 Rising edge
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25.3.2 Key return mode register 0 (KRM0)

The KRM0 register controls the KR0 to KR7 signals.
The KRM0 register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Figure 25-3. Format of Key Return Mode Register 0 (KRM0)

Symbol 7 6 5 4 3 2 1 0
KRM0 KRM07 KRM06 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00
KRM0n Key interrupt mode control
0 Does not detect key interrupt signal

1 Detects key interrupt signal
Cautions 1. The on-chip pull-up resistors can be applied by setting the corresponding key interrupt input
pins (bits) in pull-up resistor register 7 (PU7) to 1.
2. An interrupt will be generated if the target bit of the KRM0 register is set while a low level (KREG
is set to 0) or a high level (KREG is set to 1) is being input to the key interrupt input pin.
To ignore this interrupt, set the KRM0 register after disabling interrupt servicing by using the
interrupt mask flag. Afterward, clear the interrupt request flag and enable interrupt servicing
after waiting for the key interrupt input high-level and low-level widths (see 41.4 AC
Characteristics).
3. The pins not used in the key interrupt mode can be used as normal ports.
Remark n = 0 to 7
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25.3.3 Key return flag register (KRF)

This register controls the key interrupt flags (KRF0 to KRF7).
The KRF register can be set by an 8-bit memory manipulation instruction.
Figure 25-4. Format of Key Return Flag Register (KRF)
Address: FFF35H After reset: 00H R/WNote

Symbol 7 6 5 4 3 2 1 0
KRF KRF7 KRF6 KRF5 KRF4 KRF3 KRF2 KRF1 KRF0
KRFn Key interrupt flag (n = 0 to 7)
0 No key interrupt signal has been detected.

1 A key interrupt signal has been detected.
Note Writing to 1 is invalid. To clear the KRFn bit, write 0 to the corresponding bit and 1 to the other bits using an 8-
bit memory manipulation instruction.
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25.3.4 Port mode register 7 (PM7)

These registers set the input and output of port 7 in 1-bit units.
To use a key interrupt input (KR0 to KR7), set 1 to the bit of port mode register (PM7) corresponding to each port.
The PM7 register can be set by a 1-bit or an 8-bit memory manipulation instruction.
Reset signal generation clears this register to FFH.
Figure 25-5. Format of Port Mode Register 7 (PM7)
Address: FFF27H After reset: FFH R/W

Symbol 7 6 5 4 3 2 1 0
PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70
PM7n I/O mode selection for PM7n pin (n = 0 to 7)

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RL78/I1C CHAPTER 26 STANDBY FUNCTION
CHAPTER 26 STANDBY FUNCTION
26.1 Standby Function
The standby function reduces the operating current of the system, and the following three modes are available.
(1) HALT mode

HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, high-speed on-chip oscillator, middle-speed on-chip oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode

STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator, high-
speed on-chip oscillator, and middle-speed on-chip oscillator stop, stopping the whole system, thereby
considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
(3) SNOOZE mode

In the case of CSI0 or UART0 data reception, an A/D conversion request by the timer trigger signal (the interrupt
request signal (INTRTCPRD/INTRTCALM/INTIT) or ELC event input), and DTC start source, the STOP mode is
exited, the CSI0 or UART0 data is received without operating the CPU, A/D conversion is performed, and DTC start
source. This can only be specified when the high-speed on-chip oscillator or middle-speed on-chip oscillator is
selected for the CPU/peripheral hardware clock (fCLK).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
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Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. Do not
set to the STOP mode while the CPU operates with the subsystem clock. The HALT mode can be
used when the CPU is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with main system clock before executing STOP instruction (except SNOOZE mode setting unit).
3. When using CSI0, UART0, or the A/D converter in the SNOOZE mode, set up serial standby
control register m (SSCm) and A/D converter mode register 2 (ADM2) before switching to the
STOP mode. For details, see 18.3 Registers Controlling Serial Array Unit and 15.3 Registers
Controlling A/D Converter.
4. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter
mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
<R> 5. It can be selected by the WDTON bit of the option byte and the WUTMMCK0 bit of the subsystem
clock supply mode control register (OSMC) whether the low-speed on-chip oscillator continues
oscillating or stops in the HALT or STOP mode. For details, see 6.1 (2) <2> Low-speed on-chip
oscillator.
26.2 Registers Controlling Standby Function
The registers which control the standby function are described below.
● Oscillation stabilization time counter status register (OSTC)
● Oscillation stabilization time select register (OSTS)
Remark For details of registers described above, see CHAPTER 6 CLOCK GENERATOR. For registers which
control the SNOOZE mode, CHAPTER 15 A/D CONVERTER and CHAPTER 18 SERIAL ARRAY UNIT.
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26.3 Standby Function Operation
26.3.1 HALT mode

(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-
chip oscillator clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
Caution Because the interrupt request signal is used to clear the HALT mode, if the interrupt mask flag is
0 (the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request
signal is generated), the HALT mode is not entered even if the HALT instruction is executed in
such a situation.
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Table 26-1. Operating Statuses in HALT Mode (1/4)

HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Main System Clock
When CPU is When CPU is When CPU is When CPU is When CPU is
Operating on High- Operating on Middle- Operating on X1 Operating on Operating on PLL
speed On-chip speed On-chip Clock (fX) External Main Clock Frequency
Item Oscillator Clock (fIH) Oscillator Clock (fIM) System Clock (fEX) (fPLL)
System clock Clock supply to the CPU is stopped
Main system fIH Operation continues Operation disabled Operation disabled Operation continues
clock (cannot be stopped) (cannot be stopped)
fIM Operation disabled Operation continues Operation disabled Operation disabled
(cannot be stopped)
fX Operation disabled Operation continues Cannot operate
(cannot be stopped)
fEX Cannot operate Operation continues
(cannot be stopped)
fPLL Operation disabled Operation continues
(cannot be stopped)
Subsystem clock fXT Status before HALT mode was set is retained.
(Operation disabled when RTC power-on-reset occurs)
fEXS
Low-speed on- fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock
chip oscillator supply option control register (OSMC)
clock WUTMMCK0 = 1 or SELLOSC = 1: Oscillates
(Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited while the sub clock (fSX) operates.)
WUTMMCK0 = 0, SELLOSC = 0, and WDTON = 0: Stop
WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 0: Stop
CPU Operation stopped
Code flash memory
Data flash memory
RAM Operation stopped (Operable while in the DTC is executed)
Port (latch) Status before HALT mode was set is retained. (Rewriting the port register by the DTC can change the port pin
setting.)
Timer array unit Operable
Independent power supply real-time Operable (Operation stopped when RTC power-on-reset occurs)
clock (RTC)
Frequency measurement function Operation disable Operable
High-speed on-chip oscillator clock Operable (when fXT Operation disabled
frequency correction function or fEXS is supplied)
Oscillation stop detection Operable (only when fIL is oscillating)
Battery backup function Operable
Watchdog timer See CHAPTER 14 WATCHDOG TIMER.
Clock output/buzzer output Operable
10-bit resolution A/D converter
24-bit ΔΣ A/D converter
Temperature sensor 2
Serial array unit (SAU)
IrDA
Serial interface (IICA)
Event link controller (ELC) Operable function blocks can be linked
Remark Operation stopped: Operation is automatically stopped before switching to HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
fIM: Middle-speed on-chip oscillator clock fPLL: PLL clock frequency
fEX: External main system clock fX: X1 clock
fEXS: External subsystem clock fXT: XT1 clock
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HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Main System Clock
When CPU is When CPU is When CPU is When CPU is When CPU is
Operating on High- Operating on Middle- Operating on X1 Operating on Operating on PLL
speed On-chip speed On-chip Clock (fX) External Main Clock Frequency
Item Oscillator Clock (fIH) Oscillator Clock (fIM) System Clock (fEX) (fPLL)
32-bit multiplier and multiply accumulator Operation disable
AES circuit Operable
Power-on-reset function
RTC power-on-reset function
Voltage detection Internal power
function supply voltage
(internal VDD)
VDD, VBAT,
VRTC, EXLVD
pin supply
voltage
External interrupt INTP0 to INTP7
RTCIC0 to
RTCIC2
Key interrupt function
CRC operation High-speed CRC
function General-purpose In the calculation of the RAM area, operable when DTC is executed only
CRC
Illegal-memory access detection function Operation stopped (Operable when DTC is executed.)
RAM parity error detection function
RAM guard function
SFR guard function
Remark Operation stopped: Operation is automatically stopped before switching to HALT mode.
fIM: Middle-speed on-chip oscillator clock fPLL: PLL clock frequency
fEX: External main system clock fX: X1 clock
fEXS: External subsystem clock fXT: XT1 clock
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HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Subsystem Clock
When CPU is Operating on XT1 When CPU is Operating on When CPU is Operating on Low-
Clock (fXT) External Subsystem Clock (fEXS) speed On-chip Oscillator Clock
Item (fIL)
System clock Clock supply to the CPU is stopped.
Main system clock fIH Operation disabled
fIM
fX
fEX
fPLL
Subsystem clock fXT Operation continues (cannot be Cannot operate Operation disabled
stopped)
(Operation disabled when RTC
power-on-reset occurs)
fEXS Cannot operate Operation continues (cannot be Operation disabled
stopped)
(Operation disabled when RTC
power-on-reset occurs)
Low-speed on-chip fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of the option byte Operation continues (cannot be
oscillator clock (000C0H) and bit 4 (WUTMMCK0) of the subsystem clock supply stopped)
option control register (OSMC).
● WUTMMCK0 = 1 or SELLOSC = 1: Oscillates
(However, setting the WUTMMCK0 and SELLOSC bits to 1 is
prohibited while the sub clock (fSX) operates.)
● WUTMMCK0 = 0, SELLOSC = 0, and WDTON=0: Stops
● WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON =
1: Oscillates
● WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON =
0: Stops
Code flash memory
Data flash memory
Port (latch) Status before HALT mode was set is retained (rewriting the port register by the DTC can change the
port pin setting).
Timer array unit Operates when the RTCLPC bit is 0 (operation is disabled when the Operable
RTCLPC bit is not 0).
Independent power supply real-time clock (RTC) Operable (Operation stopped when RTC power-on-reset occurs)
Frequency measurement function Operation disabled
High-speed on-chip oscillator clock frequency
correction function
Oscillation stop detection
12-bit Interval timer
8-bit Interval timer
Clock output/buzzer output Operates when the subsystem clock is selected as the clock source for counting.
10-bit resolution A/D converter Operation disabled
Serial array unit (SAU) Operates when the RTCLPC bit is 0 (operation is disabled when the Operable
IrDA Operation disabled
Serial interface (IICA) Operation disabled
LCD controller/driver Operable (However, this depends on the status of the clock selected as the LCD source clock:
operation is possible if the selected clock is operating, but operation will stop if the selected clock is
stopped.)
Data transfer controller (DTC) Operates when the RTCLPC bit is 0 (operation is disabled when the Operable
32-bit multiplier and multiply accumulator Operation disable
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HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Subsystem Clock
When CPU is Operating on XT1 When CPU is Operating on When CPU is Operating on Low-
Clock (fXT) External Subsystem Clock (fEXS) speed On-chip Oscillator Clock
Item (fIL)
AES circuit Operable
Power-on-reset function
Voltage detection function Internal power
supply voltage
(internal VDD)
VDD, VBAT, VRTC,
EXLVD pin supply
voltage
RTCIC0 to RTCIC2
CRC operation function High-speed CRC Operation disabled
General-purpose In the calculation of the RAM area, operable when DTC is executed only
CRC
Illegal-memory access detection function Operable when DTC is executed only
RAM guard function
SFR guard function
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
fIM: Middle-speed on-chip oscillator clock fX: X1 clock
fEX: External main system clock fXT: XT1 clock
fEXS: External subsystem clock fPLL: PLL clock frequency
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(2) HALT mode release

The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is
enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address
instruction is executed.
Figure 26-1. HALT Mode Release by Interrupt Request Generation
Interrupt request
HALT
instruction
Standby release signal Note 1
Operating
Status of CPU HALT mode Wait Note 2 Operating mode
mode
High-speed system clock,

High-speed on-chip oscillator clock, Oscillation
middle-speed on-chip oscillator clock,
or subsystem clock
Notes 1. For details of the standby release signal, see Figure 24-1 Basic Configuration of Interrupt Function.
2. Wait time for HALT mode release
● When vectored interrupt servicing is carried out
Main system clock: 15 to 16 clocks
Subsystem clock (RTCLPC = 0): 10 to 11 clocks
● When vectored interrupt servicing is not carried out
Main system clock: 9 to 10 clocks
Remark The broken lines indicate the case when the interrupt request which has released the standby mode is
acknowledged.
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(b) Release by reset signal generation

When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 26-2. HALT Mode Release by Reset (1/2)
(1) When high-speed on-chip oscillator clock is used as CPU clock
HALT instruction
Reset signal
Normal operation Normal operation

(high-speed on-chip Reset Note (high-speed on-chip
oscillator clock) HALT mode period oscillator clock)
Status of CPU
Oscillation
High-speed on-chip Oscillates stopped Oscillates
oscillator clock
Wait for oscillation
accuracy stabilization
(2) When high-speed system clock is used as CPU clock
HALT instruction
Reset signal
Normal operation
Normal operation Reset (high-speed on-chip
Note
(high-speed system clock) HALT mode period oscillator clock)
Status of CPU
Oscillation Oscillation
High-speed system clock Oscillates stopped stopped Oscillates
(X1 oscillation)
Oscillation stabilization time
(check by using OSTC register)
Starting X1 oscillation is specified by software.
Note For the reset processing time, see CHAPTER 27 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see CHAPTER 28
POWER-ON-RESET CIRCUIT.
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Figure 26-2. HALT Mode Release by Reset (2/2)
(3) When subsystem clock is used as CPU clock
HALT instruction
Reset signal
Normal operation mode
Normal operation Reset (high-speed on-chip
Note
(subsystem clock) HALT mode period oscillator clock)
Status of CPU
Subsystem clock Oscillates stopped stopped Oscillates
(XT1 oscillation)
(check by using OSTC register)
Starting XT1 oscillation is
specified by software.
26.3.2 STOP mode

(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, X1 clock, or external
main system clock.
Caution Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is
generated), the STOP mode is immediately cleared if set when the STOP instruction is executed in
such a situation.
Accordingly, once the STOP instruction is executed, the system returns to its normal operating mode
after the elapse of release time from the STOP mode.
The operating statuses in the STOP mode are shown below.
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Table 26-2. Operating Statuses in STOP Mode (1/2)

STOP Mode Setting When STOP Instruction is Executed While CPU is Operating on Main System Clock
When CPU is Operating on When CPU is Operating on When CPU is Operating on When CPU is Operating on
High-speed On-chip Middle-speed On-chip X1 Clock (fX) External Main System
Item Oscillator Clock (fIH) Oscillator Clock (fIM) Clock (fEX)
Main system fIH Stopped
clock fIM
fX
fEX
fPLL
Subsystem fXT Status before STOP mode was set is retained
clock (Operation disabled when RTC power-on-reset occurs)
fEXS
Low-speed fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock
on-chip supply option control register (OSMC)
oscillator WUTMMCK0 = 1 or SELLOSC = 1: Oscillates
clock (Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited while the sub clock (fSX) operates.)
Code flash memory
Data flash memory Operation stopped (Transition to the STOP mode is not possible while rewriting the data flash memory)
RAM Operation stopped
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
Independent power supply real-time Operable (Operation stopped when RTC power-on-reset occurs)
clock (RTC)
10-bit resolution A/D converter Wakeup operation is enabled (switching to SNOOZE mode)
24-bit ΔΣ A/D converter Operation disabled
Serial array unit (SAU) Wakeup operation is enabled only for CSI00 and UART0 (switching to SNOOZE mode).
Operation is disabled for anything other than CSI00 and UART0.
Serial interface (IICA) Wakeup by address match operable
LCD controller/driver Operable (However, this depends on the status of the clock selected as the LCD source clock: operation is
possible if the selected clock is operating, but operation will stop if the selected clock is stopped.)
Data transfer controller (DTC) Operable
32-bit multiplier and multiply Operation disabled
accumulator
AES circuit
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Table 26-2. Operating Statuses in STOP Mode (2/2)

STOP Mode Setting When STOP Instruction is Executed While CPU is Operating on Main System Clock
When CPU is Operating on When CPU is Operating on When CPU is Operating on When CPU is Operating on
High-speed On-chip Middle-speed On-chip X1 Clock (fX) External Main System
Item Oscillator Clock (fIH) Oscillator Clock (fIM) Clock (fEX)
Power-on-reset function Operable
Voltage detection Internal power
function supply voltage
(internal VDD)
VDD, VBAT, VRTC,
EXLVD pin supply
voltage
RTCIC0 to RTCIC2
CRC operation High-speed CRC Operation stopped
function
General-purpose
CRC
Illegal-memory access detection function
RAM guard function
SFR guard function
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fEXS: External subsystem clock fPLL: PLL clock frequency
(2) STOP mode release

The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 26-3. STOP Mode Release by Interrupt Request Generation (1/2)
(1) When high-speed/middle-speed on-chip oscillator clock is used as CPU clock
Interrupt
STOP request
instruction
Note 2
STOP mode release time Note 3
(high-speed/middle-speed (high-speed/middle-speed
Supply of the
on-chip oscillator clock) on-chip oscillator clock)
STOP mode clock is stopped Wait
Status of CPU
High-speed/middle-speed Oscillates Oscillation stopped Oscillates

Wait for oscillation accuracy
stabilization
(Notes, Caution, and Remarks are listed on the next page.)
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2. STOP mode release time
Supply of the clock is stopped:
When high-speed on-chip oscillator clock: 18 µs to 65 µs
When middle-speed on-chip oscillator clock: 22 µs to 31 µs (in HS mode)
Up to 3.4 µs (during operation at 4 MHz in LS mode)
Up to 5.9 µs (during operation at 1 MHz in LP mode)
Wait:
(common to the high-speed/middle-speed on-chip oscillator clock)
● When vectored interrupt servicing is carried out: 7 clocks
● When vectored interrupt servicing is not carried out: 1 clock
3. Before switching the operating clock from the CPU/peripheral hardware clock (fCLK) to the high-speed on-
chip oscillator clock after using the middle-speed on-chip oscillator clock for the transition from STOP mode
to normal mode, use software to set up waiting for the corresponding period from the list below.
In HS mode: 24 µs
In LS mode: 10 µs
In LP mode: 7 µs
Caution To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with
the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the high-speed on-
chip oscillator clock before the execution of the STOP instruction.
Remarks 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period.
2. The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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Figure 26-3. STOP Mode Release by Interrupt Request Generation (2/2)
(2) When high-speed system clock (X1 oscillation) is used as CPU clock
Interrupt
STOP request
instruction
Normal operation STOP mode release time Note 2 Normal operation

(high-speed Supply of the (high-speed
STOP mode Wait
system clock) clock is stopped system clock)
Status of CPU
High-speed
Oscillates Oscillation stopped Oscillates
system clock
(X1 oscillation)
Supply of the clock is stopped:
18 µs to “whichever is longer 65 µs or the oscillation stabilization time (set by OSTS)”
Wait:
● When vectored interrupt servicing is carried out: 10 to 11 clocks
● When vectored interrupt servicing is not carried out: 4 to 5 clocks
(3) When high-speed system clock (external clock input) is used as CPU clock
Interrupt
STOP request
instruction
Note 2
STOP mode release time
Normal operation
(high-speed Supply of the Normal operation
system clock) STOP mode clock is stopped Wait (high-speed system clock)
Status of CPU
High-speed system clock Oscillates Oscillation stopped Oscillates

(external clock input)
Supply of the clock is stopped: 18 µs to 65 µs
Wait:
● When vectored interrupt servicing is carried out: 7 clocks
● When vectored interrupt servicing is not carried out: 1 clock
Caution To reduce the oscillation stabilization time after release from the STOP mode while CPU operates
based on the high-speed system clock (X1 oscillation), switch the clock to the high-speed on-chip
oscillator clock temporarily before executing the STOP instruction.
Remarks 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period.
2. The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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(b) Release by reset signal generation

When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 26-4. STOP Mode Release by Reset
(1) When high-speed on-chip oscillator clock is used as CPU clock
STOP instruction
Reset signal

(high-speed on-chip
Reset
Note (high-speed on-chip
oscillator clock) STOP mode period oscillator clock)
Status of CPU
Oscillation
High-speed on-chip Oscillates Oscillation stopped stopped Oscillates
oscillator clock
Wait for oscillation accuracy stabilization
(2) When middle-speed on-chip oscillator clock is used as CPU clock
STOP instruction
Reset signal
(middle-speed on-chip Reset (high-speed on-chip
STOP mode Note
oscillator clock) period oscillator clock)
Status of CPU
Oscillation
High-speed on-chip Oscillates Oscillation stopped stopped Oscillates
oscillator clock
Middle-speed on-chip Oscillates Oscillation stopped

oscillator clock
(3) When high-speed system clock is used as CPU clock
STOP instruction
Reset signal
(high-speed Reset (high-speed on-chip
Note
system clock) STOP mode period oscillator clock)
Status of CPU
High-speed system clock Oscillates Oscillation stopped stopped stopped Oscillates
(X1 oscillation)
(Check by using OSTC register)
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26.3.3 SNOOZE mode

(1) SNOOZE mode setting and operating statuses
The SNOOZE mode can only be specified for CSI0, the A/D converter, or DTC. The UART0 can be specified.
Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock or middle-
speed on-chip oscillator clockNote.
When using CSI0 or UART0 in the SNOOZE mode, set up serial standby control register m (SSCm) before
switching to the STOP mode. For details, see 18.3 Registers Controlling Serial Array Unit.
When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2 (ADM2) before
switching to the STOP mode. For details, see 15.3 Registers Controlling A/D Converter.
When DTC transfer is used in SNOOZE mode, before switching to the STOP mode, allow DTC activation by
interrupt to be used. During STOP mode, detecting DTC activation by interrupt enables DTC transit to SNOOZE
mode, automatically. For details, see 22.3 Registers Controlling DTC.
Note When using UART reception to transition from STOP mode to SNOOZE mode, use the high-speed on-chip
oscillator.
In SNOOZE mode transition, wait status to be only following time.

Transition time from STOP mode to SNOOZE mode:
When high-speed on-chip oscillator clock: 18 µs to 65 µs
When middle-speed on-chip oscillator clock: 22 µs to 31 µs (in HS mode)
Up to 5.9 µs (during operation at 1 MHz in LP mode)
Remark Transition time from STOP mode to SNOOZE mode varies depending on the temperature conditions
and the STOP mode period.
Transition time from SNOOZE mode to normal operation:

When high-speed on-chip oscillator clock:
● When vectored interrupt servicing is carried out:
HS (High-speed main) mode: “5.2 µs to 9.4 µs” + 7 clocks
LS (Low-speed main) mode: “1.3 µs to 4.5 µs” + 7 clocks
LV (Low-voltage main) mode: “17.5 µs to 25.2 µs” + 7 clocks
● When vectored interrupt servicing is not carried out:
HS (High-speed main) mode: “5.2 µs to 9.4 µs” + 1 clock
LS (Low-speed main) mode: “1.3 µs to 4.5 µs” + 1 clock
LV (Low-voltage main) mode: “17.5 µs to 25.2 µs” + 1 clock
When middle-speed on-chip oscillator clock:
● When vectored interrupt servicing is carried out:
HS (High-speed main) mode: “6.0 µs to 10.3 µs” + 7 clocks
LS (Low-speed main) mode: “1.8 µs to 4.9 µs” + 7 clocks
LP (Low-power main) mode: “3.8 µs to 4.9 µs” + 7 clocks
● When vectored interrupt servicing is not carried out:
HS (High-speed main) mode: “6.0 µs to 10.3 µs” + 1 clock
LS (Low-speed main) mode: “1.8 µs to 4.9 µs” + 1 clock
LP (Low-power main) mode: “3.8 µs to 4.9 µs” + 1 clock
The operating statuses in the SNOOZE mode are shown next.
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Table 26-3. Operating Statuses in SNOOZE Mode (1/2)

STOP Mode Setting During STOP Mode, Receiving Data Signal from CSI0 and UART0, Inputting Timer Trigger Signal to A/D
Converter, and Generating DTC Activation by Interrupt
When CPU is Operating When CPU is Operating
Item on High-speed On-chip Oscillator Clock (fIH) on Middle-speed On-chip Oscillator Clock (fIM)
Main system fIH Operation started Stopped
clock fIM Stopped Operation started
fX Stopped
fEX
fPLL
Subsystem fXT Status before STOP mode was set is retained (Operation disabled when RTC power-on-reset occurs)
clock
fEXS
Low-speed on- fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem
chip oscillator clock supply option control register (OSMC)
clock WUTMMCK0 = 1 or SELLOSC = 1: Oscillates
(Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited while the sub clock (fSX) operates.)
Code flash memory
Data flash memory
Port (latch) Use of the status while in the STOP mode continues
(rewriting the port register by the DTC can change the port pin setting)
Timer array unit Operation disabled
Independent power supply real-time clock Operable (Operation stopped when RTC power-on-reset occurs)
(RTC)
12-bit interval timer Operable
10-bit resolution A/D converter Operable
24-bit ΔΣ A/D Converter Operation disabled
Serial array unit (SAU) Operable only CSI00 and UART0 only.
Operation disabled other than CSI00 and UART0.
LCD controller/driver Operable (However, this depends on the status of the clock selected as the LCD source clock: operation is
possible if the selected clock is operating, but operation will stop if the selected clock is stopped.)
Data transfer controller (DTC) Operable
32-bit multiplier and multiply accumulator Operation disabled
AES circuit
Power-on-reset function Operable
Voltage detection Internal power supply
function voltage (internal VDD)
VDD, VBAT, VRTC,
EXLVD pin supply
voltage
External interrupt
Detection of tampering (RTCICn)
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Table 26-3. Operating Statuses in SNOOZE Mode (2/2)

STOP Mode Setting During STOP Mode, Receiving Data Signal from CSI0 and UART0, Inputting Timer Trigger Signal to A/D
Converter, and Generating DTC Activation by Interrupt
When CPU is Operating When CPU is Operating
Item on High-speed On-chip Oscillator Clock (fIH) on Middle-speed On-chip Oscillator Clock (fIM)
CRC operation High-speed CRC Operation stopped
function
General-purpose
CRC
Illegal-memory access detection function Operable when executing the DTC
RAM guard function
SFR guard function
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fEXS: External subsystem clock fSX: Sub clock
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(2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode
Figure 26-5. When the Interrupt Request Signal is Generated in the SNOOZE Mode
STOP Trigger
instruction detection Interrupt request
H
Standby release
signal Note 1
L
Normal operation Note 4
SNOOZE mode Normal operation Note 5
(high-speed/middle-speed
STOP mode (A/D conversion, (high-speed/middle-speed
Status of CPU on-chip oscillator clock)
Note 2 Note 3
UART/CSI) on-chip oscillator clock)
High-speed/middle-speed Oscillation
Oscillates stopped Oscillates
2. Transition time from STOP mode to SNOOZE mode
3. Transition time from SNOOZE mode to normal operation
4. Enable the SNOOZE mode (AWC = 1 or SWC = 1) immediately before switching to the STOP mode.
5. Be sure to release the SNOOZE mode (AWC = 0 or SWC = 0) immediately after return to the normal
operation.
(3) Timing diagram when the interrupt request signal is not generated in the SNOOZE mode
Figure 26-6. When the Interrupt Request Signal is not Generated in the SNOOZE Mode
STOP Trigger
instruction detection
Standby release
signal Note 1
L
Normal operation SNOOZE mode
Note 3
(A/D conversion, Note 4 STOP mode
Status of CPU (high-speed/middle-speed STOP mode
on-chip oscillator clock)
Note 2 UART/CSI) (Waiting for a trigger to switch to the SNOOZE mode)
High-speed/
middle-speed
on-chip oscillator Oscillation
Oscillates Oscillates Oscillation stopped
clock stopped
2. Transition time from STOP mode to SNOOZE mode
3. Enable the SNOOZE mode (AWC = 1 or SWC = 1) immediately before switching to the STOP mode.
<R> 4. If a standby release signal is generated in response to an interrupt from a module which is not set to
operate in the SNOOZE mode during a transition of the chip from SNOOZE mode to STOP mode, the high-
speed on-chip oscillator clock may run slowly for up to 15 μs from when the CPU starts to operate. If the
clock frequency accuracy specified in the electrical characteristics is required immediately after release from
standby, wait for the number of cycles at the actual CPU clock frequency that is equivalent to 15 μs.
Remark For details of the SNOOZE mode function, see CHAPTER 15 A/D CONVERTER and CHAPTER 18
SERIAL ARRAY UNIT.
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RL78/I1C CHAPTER 27 RESET FUNCTION
CHAPTER 27 RESET FUNCTION
The following eight operations are available to generate a reset signal.
(1) External reset input via RESET pin

(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuitNote 1
(4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instructionNote 2
(6) Internal reset by RAM parity error
(7) Internal reset by illegal-memory access
(8) Reset of the RTC and XT1 oscillator by comparison of supply voltage of the RTC power-on reset (RTCPOR) circuit
and detection voltage
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD
circuit voltage detection, execution of illegal instructionNote 2, RAM parity error or illegal-memory access, and each item of
hardware is set to the status shown in Table 27-1.
The RTC and XT1 oscillator are reset by the RTC power-on reset (RTCPOR).
Notes 1. If RTC power-on-reset does not occur, independent power supply RTC and XT1 oscillator circuit can be
operated even during the reset period of (3) power-on-reset.
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
To perform an external reset upon power application, input a low level to the RESET pin, turn
power on, continue to input a low level to the pin for 10 µs or more within the operating voltage
range shown in 41.4 AC Characteristics, and then input a high level to the pin.
2. During reset input, the X1 clock, high-speed on-chip oscillator clock, middle-speed on-chip
oscillator clock, and low-speed on-chip oscillator clock stop oscillating.
3. The port pins become the following state because each SFR and 2nd SFR are initialized after
reset.
● P40: High-impedance during the external reset period or reset period by the POR. High level
during other types of reset or after receiving a reset signal (connected to the internal pull-up
resistor).
● P150 to P152: High level during the reset period or after receiving a reset signal (connected to
the internal pull-up resistor).
● Ports other than P40 and P150 to P152: High-impedance during the reset period or after
receiving a reset signal.
Remark VPOR: POR power supply rise detection voltage

VLVD: LVD detection voltage
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Figure 27-1. Block Diagram of Reset Function
Internal bus
RL78/I1C
Aug 31, 2018

Reset control flag Power-on-reset status RTC power-on reset status
register (RESF) register (PORSR) register (RTCPORSR)
TRAP WDTRF RPERF IAWRF LVIRF PORF RTCPORF
Set Set Set Set Set

Watchdog timer reset signal
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Clear Clear Clear Clear Clear Clear
Reset signal by execution of illegal instruction
Reset signal by RAM parity error

Reset signal by illegal-memory access
RESF register read signal
Reset signal to
RESET
LVIM/LVIS register
Power-on reset
circuit reset signal
Voltage detector Reset signal

reset signal
Reset signal to
RTC power-on reset RTC and XT1 oscillator
circuit reset signal
Caution An LVD circuit internal reset does not reset the LVD circuit.
Remarks 1. LVIM: Voltage detection register

2. LVIS: Voltage detection level register
940
27.1 Timing of Reset Operation
This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level
on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the
operating clock starts.
Figure 27-2. Timing of Reset by RESET Input

High-speed on-chip
oscillator clock
(when X1 oscillation is selected)
Reset period Normal operation
CPU status Normal operation
(high-speed on-chip oscillator clock)
RESET Reset processing for release

from the external reset state Note 1
Internal reset signal
Delay
Hi-Z Notes 2, 3
Port pin
The input buffer of the RESET pin is connected to internal VDD. When using the battery backup function, input signal
based on the voltage of the selected power supply source (VDD pin or VBAT pin).
Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow, execution of an
illegal instruction, detection of a RAM parity error, or detection of illegal memory access. After reset processing, program
execution starts with the high-speed on-chip oscillator clock as the operating clock.
(Notes and Caution are listed on the next page.)
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Figure 27-3. Timing of Reset Due to Watchdog Timer Overflow, Execution of Illegal Instruction,
Detection of RAM Parity Error, or Detection of Illegal Memory

High-speed on-chip
oscillator clock
(when X1 oscillation is selected)
Reset period Reset processing
CPU status Normal operation
Normal operation (oscillation stop)
41 to 69 µs (high-speed on-chip oscillator clock)
Execution of Illegal
Instruction/
Watchdog timer
overflow
Hi-Z Notes 2, 3
Port pin
Notes 1. Reset times (times for release from the external reset state)
After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use.
0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.
After the second release of the POR: 0.531 ms (typ.), 0.675 ms (max.) when the LVD is in use.
0.259 ms (typ.), 0.362 ms (max.) when the LVD is off.
After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.)
is required before reset processing starts after release of the external reset.
2. P40 becomes the following state.
● High-impedance during the external reset period or reset period by the POR.
● High level during other types of reset or after receiving a reset signal (connected to the internal pull-up
resistor).
3. P150 to P152 become the following state.
● High level during the reset period or after receiving a reset signal (connected to the internal pull-up
resistor).
Reset by POR and LVD circuit supply voltage detection is automatically released when internal VDD ≥ VPOR or internal
VDD ≥ VLVD after the reset. After reset processing, execution of the program with the high-speed on-chip oscillator clock as
the operating clock starts.
For details, see CHAPTER 28 POWER-ON-RESET CIRCUIT or CHAPTER 29 VOLTAGE DETECTOR.

VLVD: LVD detection voltage
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27.2 States of Operation During Reset Periods
Table 27-1 shows the states of operation during reset periods. Table 27-2 shows the states of the hardware after
receiving a reset signal.
Table 27-1. Operation Statuses During Reset Period (1/2)

Item During Reset Period
System clock Clock supply to the CPU is stopped.
Main system fIH Operation stopped
clock fIM Operation stopped.
fX Operation stopped (the X1 and X2 pins are input port mode)
fEX Clock input invalid (the pin is input port mode)
fPLL Operation stopped.
Subsystem clock fXT Operation possible when RTC power-on-reset does not occur
fEXS Operation possible when RTC power-on-reset does not occur
fIL Operation stopped
CPU
Code flash memory
Data flash memory
RAM
Port (latch) P40 Except pin reset and power-on reset: Pull-up function enable
Pin reset and power-on reset: High impedance
P150 to P152 Pull-up function enable
Other than P40, P150 High impedance (Through-type current does not flow.)
to P152
Timer array unit Operation stopped
Independent Time capture Operation stopped when power-on reset occurs
power supply function
real-time clock Other than time Operation possible when RTC power-on-reset does not occur
(RTC) capture function
Frequency measurement circuit Operation stopped
Oscillation stop detection
Battery backup function During a reset other than the power-on reset: Operation possible
During a power-on reset: Operation stopped
12-bit interval timer Operation stopped
Watchdog timer
Clock output/buzzer output
10-bit resolution A/D converter
Serial array unit (SAU)
IrDA
Power-on-reset function Detection operation possible
(Note and Remark are listed on the next page.)
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Table 27-1. Operation Statuses During Reset Period (2/2)

Item During Reset Period
Voltage Internal power Operation is possible in the case of an LVD reset and stopped in the case of other types of reset.
detection supply voltage
function (internal VDD)
VDD, VBAT, VRTC, Operation stopped
EXLVD pin supply
voltage
External INTP0 to INTP7
interrupt RTCIC0 to RTCIC2
CRC High-speed CRC
operation General-purpose
function CRC
32-bit multiplier and multiply
accumulator
RAM guard function
SFR guard function
Illegal-memory access detection
function
AES circuit
Detection of tampering
Note P40 and P150 to P152 become the following state.

● P40: High-impedance during the external reset period or reset period by the POR. High level during other
types of reset (connected to the internal pull-up resistor).
● P150 to P152: High level during the reset period (connected to the internal pull-up resistor)
Remark fIH: High-speed on-chip oscillator clock

fIM: Middle-speed on-chip oscillator clock
fX: X1 oscillation clock
fEX: External main system clock
fXT: XT1 oscillation clock
fEXS: External subsystem clock
fIL: Low-speed on-chip oscillator clock
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Table 27-2. Hardware Statuses After Reset Acknowledgment
Hardware After Reset

AcknowledgmentNote
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
RAM Data memory Undefined
General-purpose registers Undefined
Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark For the state of the special function register (SFR) after receiving a reset signal, see 3.2.4 Special function
registers (SFRs) and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function
Registers).
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27.3 Register for Confirming Reset Source
27.3.1 Reset control flag register (RESF)

Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used
to store which source has generated the reset request.
The RESF register can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF,
IAWRF, and LVIRF flags.
Figure 27-4. Format of Reset Control Flag Register (RESF)
Address: FFFA8H After reset: UndefinedNote 1 R

Symbol 7 6 5 4 3 2 1 0
RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF
TRAP Internal reset request by execution of illegal instructionNote 2
0 No internal reset request has been generated, or the RESF register has been cleared.
1 An internal reset request has been generated.
WDTRF Internal reset request by watchdog timer (WDT)
RPERF Internal reset request by RAM parity
IAWRF Internal reset request by illegal-memory access
LVIRF Internal reset request by voltage detector (LVD)
Notes 1. The value after reset varies depending on the reset source. See Table 27-3.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.

2. When enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area at
data access or the used RAM area + 10 bytes at execution of instruction from the RAM area.
Reset generation enables RAM parity error resets (RPERDIS = 0). For details, see 32.3.3 RAM
parity error detection function.
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The status of the RESF register when a reset request is generated is shown in Table 27-3.
Table 27-3. RESF Register Status When Reset Request Is Generated
Reset Source RESET Input Reset by Reset by Reset by Reset by Reset by Reset by
Flag POR Execution of WDT RAM parity illegal- LVD
Illegal error memory
Instruction access
TRAP bit Cleared (0) Cleared (0) Set (1) Held Held Held Held
WDTRF bit Held Set (1)
RPERF bit Held Set (1)
IAWRF bit Held Set (1)

LVIRF bit Held Set (1)
The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction.
Figure 27-5 shows the procedure for checking a reset source.
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Figure 27-5. Example of Procedure for Checking Reset Source
After reset acceptance
Read the RESF register (clear the RESF register) and store
Read RESF register
the value of the RESF register in any RAM.
Yes
TRAP of RESF
register = 1?
No
Internal reset request by the
execution of the illegal instruction
generated
Yes
WDTRF of RESF
register = 1?
No
watchdog timer generated
Yes
RPERF of RESF
register = 1?
No
RAM parity error generated
Yes
IAWRF of RESF
register = 1?
No
illegal memory access generated
Yes
LVIRF of RESF
register = 1?
No
Internal reset request
by the voltage detector generated
Power-on-reset/external
reset generated
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27.3.2 Power-on-reset status register (PORSR)

The PORSR register is used to check the occurrence of a power-on reset.
Writing “1” to bit 0 (PORF) of the PORSR register is valid, and writing “0” is ignored.
Write 1 to the PORF bit in advance to enable checking of the occurrence of a power-on reset.
The PORSR register can be set by an 8-bit memory manipulation instruction.
Power-on reset signal generation clears this register to 00H.
Cautions 1. The PORSR register is reset only by a power-on reset; it retains the value when a reset caused by
another factor occurs.
2. If the PORF bit is set to 1, it guarantees that no power-on reset has occurred, but it does not
guarantee that the RAM value is retained.
Figure 27-6. Format of Power-on-Reset Status Register (PORSR)

Symbol 7 6 5 4 3 2 1 0
PORSR 0 0 0 0 0 0 0 PORF
PORF Checking occurrence of power-on reset
0 A value 1 has not been written, or a power-on reset has occurred.

1 No power-on reset has occurred.
27.3.3 RTC power-on-reset status register (RTCPORSR)

The RTCPORSR register is used to check the occurrence of an RTC Power-on reset.
Writing 1 to bit 0 (RTCPORF) of the RTCPORSR register enables this function. Writing 0 disables this function.
Write 1 to the RTCPORF bit in advance to enable checking of the occurrence of an RTC power-on reset.
The RTCPORSR register can be set by an 8-bit memory manipulation instruction.
<R> The RTCPORSR register operates on the VRTC power-supply.
Cautions 1. The RTCPORSR register is reset only by an RTC power-on reset; it retains the value when a reset
<R> 2. The RTCPORSR register is readable and writable while the VRTCEN bit is “1”.
Figure 27-7. Format of RTC Power-on-Reset Status Register (RTCPORSR)

Symbol 7 6 5 4 3 2 1 0
RTCPORSR 0 0 0 0 0 0 0 RTCPORF
RTCPORF Checking occurrence of RTC power-on reset
0 A value 1 has not been written, or an RTC power-on reset has occurred.
1 No RTC power-on reset has occurred.
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Symbol 7 <6> <5> <4> <3> <2> 1 <0>
PRR0n Control resetting of the on-chip peripheral modules

0 Releases the on-chip peripheral modules from the reset state.
1 The on-chip peripheral modules are in the reset state.
Remark n = 0, 2 to 6
Target modules for each of the bits are listed below.
Table 27-4. Target Modules for Each Bit in PRR0
Bit Bit Name Target Module
6 IRDARES IrDA
5 ADCRES A/D converter/temperature sensor 2
4 IICA0RES Serial interface IICA
3 SAU1RES Serial array unit (unit 1)
2 SAU0RES Serial array unit (unit 0)
0 TAU0RES Timer array unit
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Address: F00FBH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 <0>
PRR1 0 0 0 0 0 0 0 DSADRES

Remark n = 0
Target module for bit 0 is listed below.
Table 27-5. Target Module for Bit 0 in PRR1
0 DSADRES 24-bit ΔΣ A/D converter


Symbol <7> <6> 5 4 3 <2> 1 0

Remark n = 2, 6, 7
Target modules for each of the bits are listed below.
Table 27-6. Target Modules for Each Bit in PRR2
7 TMKARES 12-bit interval timer

6 OSDCRES Oscillation stop detection circuit
2 MACRES 32-bit multiplier and accumulator
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RL78/I1C CHAPTER 28 POWER-ON-RESET CIRCUIT
CHAPTER 28 POWER-ON-RESET CIRCUIT
28.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
● Generates internal reset signal at power on.

The reset signal is released when the supply voltage (VDD)Note exceeds the detection voltage (VPOR). However, be
sure to maintain the reset state until the power supply voltage reaches the operating voltage range specified in 41.4
AC Characteristics, by using the voltage detector or external reset pin.
● Compares supply voltage (VDD)Note and detection voltage (VPDR), generates internal reset signal when VDDNote < VPDR.
Note that, after power is supplied, this LSI should be placed in the STOP mode, or in the reset state by utilizing the
voltage detector or externally input reset signal, before the operation voltage falls below the range defined in 41.4
AC Characteristics. When restarting the operation, make sure that the operation voltage has returned within the
range of operation.
Note Internal power supply voltage (internal VDD) when using the battery backup function.
Caution If an internal reset signal is generated in the power-on-reset circuit, the reset control flag register
(RESF) and power-on-reset status register (PORSR) are cleared to 00H.
Remarks 1. The RL78 microcontroller incorporates multiple hardware functions that generate an internal reset
signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for
when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD),
illegal instruction execution, RAM parity error, or illegal-memory access. The RESF register is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by the watchdog timer
(WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory
access.
For details of the RESF register, see CHAPTER 27 RESET FUNCTION.
2. Whether an internal reset has been generated by the power-on reset circuit can be checked by using
the power-on-reset status register (PORSR). For details of the PORSR register, see CHAPTER 27
RESET FUNCTION.
3. VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
For details, see 41.6.4 POR circuit characteristics.
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28.2 Configuration of Power-on-reset Circuit
The block diagram of the power-on-reset circuit is shown in Figure 28-1.
Figure 28-1. Block Diagram of Power-on-reset Circuit
VDD Note
VDD Note
+
-
Reference
Voltage
source
Note Internal power supply voltage (internal VDD) when using the battery backup function.
28.3 Operation of Power-on-reset Circuit
The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below.
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Figure 28-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit

and Voltage Detector (1/3)
(1) When the externally input reset signal on the RESET pin is used
Internal power supply voltage (internal VDD) Note 5
Note 5
Lower limit voltage for guaranteed operation

VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
0V
RESET pin
At least 10 μs
Note 1
Note 1
High-speed on-chip
oscillator clock (fIH )
Starting oscillation Starting oscillation
is specified is specified by software
High-speedsystem by software
clock (fMX )
(when X1 oscillation Reset
is selected)
Reset processing time Normal operation
period (high-speed on-chip
when external reset Normal operation (high-speed (oscillation
is released. Note 3 on-chip oscillator clock)Note 2 stop) oscillator clock)Note 2
CPU Operation stops Operation stops
Voltage stabilization wait Reset processing time when
0.99 ms (TYP.), 2.30 ms (MAX.) external reset is released. Note 4
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
2. The CPU clock can be switched from the high-speed on-chip oscillator clock to the high-speed system
clock, or subsystem clock, or the middle-speed on-chip oscillator clock, or the low-speed on-chip oscillator
clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm
the lapse of the oscillation stabilization time. To use the XT1 clock, or the middle-speed on-chip oscillator
clock, or the low-speed on-chip oscillator clock, please switch from to check the oscillation stabilization time
by using for example the timer function.
3. The time until normal operation starts includes the following reset processing time when the external reset
is released (release from the first external reset following release from the POR state) after the RESET
signal is driven high (1) as well as the voltage stabilization wait time after VPOR (1.51 V, typ.) is reached.
With the LVD circuit in use: 0.672 ms (typ.), 0.832 ms (max.)
With the LVD circuit not in use: 0.399 ms (typ.), 0.519 ms (max.)
4. The reset processing times in the case of the second or subsequent external reset following release from
the POR state are listed below.
With the LVD circuit in use: 0.531 ms (typ.), 0.675 ms (max.)
With the LVD circuit not in use: 0.259 ms (typ.), 0.362 ms (max.)
5. After power is supplied, the reset state must be retained until the operating voltage becomes in the range
defined in 41.4 AC Characteristics. This is done by controlling the externally input reset signal. After
power supply is turned off, this LSI should be placed in the STOP mode, or in the reset state by utilizing the
voltage detector or externally input reset signal, before the voltage falls below the operating range. When
restarting the operation, make sure that the operation voltage has returned within the range of operation.
Caution For power-on reset, be sure to use the externally input reset signal on the RESET pin when the LVD is
off. For details, see CHAPTER 29 VOLTAGE DETECTOR.

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(2) LVD interrupt & reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 0)
Internal power supply voltage (internal V DD)

VLVDH Note 3
VLVDL
0V
Wait for oscillation Wait for oscillation
accuracy stabilization Note 1
accuracy stabilization Note 1
High-speed on-chip
oscillator clock (f IH)
Starting oscillation is specified by software Starting oscillation is specified by software
High-speedsystem
clock
(fMX)(when X1 oscillation
is selected) Normal operation (high-speed
Normal operation (high-speed Reset period on-chip oscillator clock) Note 2
on-chip oscillator clock) Note 2 (oscillation stop)
CPU Operation stops Operation stops
LVD reset processing time Note 4
LVD reset processing time Note 4
Voltage stabilization wait + POR reset processing time Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.) 1.64 ms (TYP.), 3.10 ms (MAX.)
INTLVI
3. After the interrupt request signal (INTLVI) is generated, the LVILV and LVIMD bits of the voltage detection
level register (LVIS) are automatically set to 1. After INTLVI is generated, appropriate settings should be
made according to Figure 29-20 Setting Procedure for Operating Voltage Check and Reset, taking into
consideration that the supply voltage might return to the high voltage detection level (VLVDH) or higher
without falling below the low voltage detection level (VLVDL).
4. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (VLVDH) is reached as well as the voltage stabilization wait + POR reset processing time after
the VPOR (1.51 V, typ.) is reached.
LVD reset processing time: 0 ms to 0.0701 ms (max.)
Remark VLVDH, VLVDL: LVD detection voltage

VPOR: POR power supply rise detection voltage
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(3) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1)
Internal power supply voltage (internal VDD)

VLVD
0V
Wait for oscillation Note 1 Wait for oscillation Note 1
accuracy stabilization accuracy stabilization
High-speed on-chip
oscillator clock (fIH) Starting oscillation Starting oscillation
is specified by software is specified by software
High-speed
system clock (fMX)
(when X1 oscillation
Normal operation Reset period Normal operation Reset period
is selected) (high-speed on-chip (oscillation (high-speed on-chip (oscillation
oscillator clock) Note 2 stop) oscillator clock) Note 2
stop)
CPU Operation stops
LVD reset processing
time Note 3
Voltage stabilization wait + POR reset
processing time 1.64 ms (TYP.), LVD reset processing
3.10 ms (MAX.) time Note 4
3. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (VLVD) is reached as well as the voltage stabilization wait + POR reset processing time after
the VPOR (1.51 V, typ.) is reached.
LVD reset processing time: 0 ms to 0.0701 ms (max.)
4. When the power supply voltage is below the lower limit for operation and the power supply voltage is then
restored after an internal reset is generated only by the voltage detector (LVD), the following LVD reset
processing time is required after the LVD detection level (VLVD) is reached.
LVD reset processing time: 0.0511 ms (typ.), 0.0701 ms (max.)
Remarks 1. VLVDH, VLVDL: LVD detection voltage

VPOR: POR power supply rise detection voltage
2. When the LVD interrupt mode is selected (option byte 000C1H: LVIMD1 = 0, LVIMD0 = 1), the time until
normal operation starts after power is turned on is the same as the time specified in Note 3 of Figure
28-2 (3).
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RL78/I1C CHAPTER 29 VOLTAGE DETECTOR
CHAPTER 29 VOLTAGE DETECTOR
29.1 Functions of Voltage Detector
The operation mode and detection voltages (VLVDH, VLVDL, VLVD) for the voltage detector is set by using the option byte
(000C1H). The detection voltages can be reset using the LVIS register. The voltage detector (LVD) has the following
functions.
● The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL, VLVD), and generates an
internal reset or internal interrupt signal.
● The detection level for the power supply detection voltage (VLVDH, VLVDL) can be selected as one of 14 levels (For
details, see 29.3.2 Voltage detection level register (LVIS) and CHAPTER 35 OPTION BYTE).
● Operable in STOP mode.
● After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in
41.4 AC Characteristics. This is done by utilizing the voltage detector or controlling the externally input reset signal.
After the power supply is turned off, this LSI should be placed in the STOP mode, or placed in the reset state by
utilizing the voltage detector or controlling the externally input reset signal before the voltage falls below the operating
range. The range of operating voltage varies with the setting of the user option byte (000C2H or 010C2H).
(a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0)

The two detection voltages (VLVDH, VLVDL) are selected by the option byte 000C1H. The high-voltage detection level
(VLVDH) is used for releasing resets and generating interrupts. This level is also used for generating resets. The
low-voltage detection level (VLVDL) is used for generating resets.
(b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1)

The detection voltage (VLVD) selected by the option byte 000C1H is used for triggering and ending resets. The
detection voltages can be reset using the LVIS register.
(c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1)

The detection voltage (VLVD) selected by the option byte 000C1H is used for generating interrupts/reset release.
The detection voltages can be reset using the LVIS register.
The reset and internal interrupt signals are generated in each mode as follows.
Interrupt & reset mode Reset mode Interrupt mode

(LVIMDS1, LVIMDS0 = 1, 0) (LVIMDS1, LVIMDS0 = 1, 1) (LVIMDS1, LVIMDS0 = 0, 1)
Generates an interrupt request signal by Releases an internal reset by detecting Immediately after a reset occurs, the
detecting VDD < VLVDH when the operating VDD ≥ VLVD. internal reset state of LVD remains until
voltage falls, and an internal reset by Generates an internal reset by detecting VDD ≥ VLVD. The internal reset of LVD is
detecting VDD < VLVDL. VDD < VLVD. cleared when VDD ≥ VLVD is detected.
Releases an internal reset by detecting After the internal reset of LVD is released,
VDD ≥ VLVDH. an interrupt request signal (INTLVI) is
generated when VDD < VLVD or VDD ≥ VLVD
is detected.
While the voltage detector is operating, whether the supply voltage is more than or less than the detection level can be
checked by reading the voltage detection flag (LVIF: bit 0 of the voltage detection register (LVIM)).
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Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see
CHAPTER 27 RESET FUNCTION.
The RL78/I1C products have voltage detection function for each power supply pin.
While voltage detection function is operating, whether the supply voltage of each pin is more than the detection level
can be checked by interruption or reading the voltage detection flag.
● The LVD circuit compares the VDD pin voltage (VDD) with the detection voltage (VLVDVDD), and generates a one-shot
interrupt request signal (INTLVDVDD) by detecting VDD > VLVDVDD or VDD < VLVDVDD.
● The LVD circuit compares the VBAT pin voltage (VBAT) with the detection voltage (VLVDVBAT), and generates a one-
shot interrupt request signal (INTLVDVBAT) by detecting VBAT > VLVDVBAT or VBAT < VLVDVBAT.
● The LVD circuit compares the VRTC pin voltage (VRTC) with the detection voltage (VLVDVRTC), and generates a
one-shot interrupt request signal (INTLVDVRTC) by detecting VRTC > VLVDVRTC or VRTC < VLVDVRTC.
● The LVD circuit compares the EXLVD pin voltage (EXLVD) with the detection voltage (VLVDEXLVD), and generates a
one-shot interrupt request signal (INTLVDEXLVD) by detecting EXLVD > VLVDEXLVD or EXLVD < VLVDEXLVD.
29.2 Configuration of Voltage Detector
The block diagrams of the voltage detector (LVD) are shown in Figure 29-1 to Figure 29-5.
Figure 29-1. Block Diagram of Voltage Detector (LVD)
VBAT pin Battery backup

function
VDD pin
N-ch
Voltage detection
level selector
Controller
+
VLVDH
Selector
VLVDL/VLVD
INTLVI
Option byte (000C1H) Reference

voltage
LVIS1, LVIS0 source LVIF LVIOMSK LVISEN LVIMD LVILV
VPOC2 to VPOC0 or Voltage detection Voltage detection
LVISEL4 to LVISEL0 of voltage detection level register (LVIS) register (LVIM) level register (LVIS)
Internal bus
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Figure 29-2. Block Diagram of VDD Pin Voltage Detector
VDD Internal power supply voltage (internal VDD)
Voltage detection
level selector
+
INTLVDVDD
VLVDVDD
−
Reference
voltage
source
LVDVDD2 LVDVDD1 LVDVDD0 LVDVDDEN LVDVDDF
VDD pin voltage detection

control register (LVDVDD)
Internal bus
Figure 29-3. Block Diagram of VBAT Pin Voltage Detector
VBAT Internal power supply voltage (internal VDD)

Voltage detection
level selector
+
INTLVDVBAT
VLVDVBAT
−
Reference
voltage
source
LVDVBAT2 LVDVBAT1LVDVBAT0 LVDVBATEN LVDVBATF
VBAT pin voltage detection

control register (LVDVBAT)
Internal bus
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Figure 29-4. Block Diagram of VRTC Pin Voltage Detector
VRTC Internal power supply voltage (internal VDD)
Voltage detection
level selector
+
INTLVDVRTC
VLVDVRTC
−
Reference
voltage
source
LVDVRTC1LVDVRTC0LVDVRTCENLVDVRTCF
VRTC pin voltage detection

control register (LVDVRTC)
Internal bus
Figure 29-5. Block Diagram of EXLVD Pin Voltage Detector
EXLVD
+
INTLVDEXLVD
VLVDEXLVD
−
Reference
voltage
source
LVDEXLVDEN LVDEXLVDF
EXLVD pin voltage detection

control register (LVDEXLVD)
Internal bus
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29.3 Registers Controlling Voltage Detector
The voltage detector is controlled by the following registers.
● Voltage detection register (LVIM)

● Voltage detection level register (LVIS)
● Voltage detection control register for VDD pin (LVDVDD)
● Voltage detection control register for VBAT pin (LVDVBAT)
● Voltage detection control register for VRTC pin (LVDVRTC)
● Voltage detection control register for EXLVD pin (LVDEXLVD)
29.3.1 Voltage detection register (LVIM)

This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well
as to check the LVD output mask status.
Figure 29-6. Format of Voltage Detection Register (LVIM)
Address: FFFA9H After reset: 00HNote 1 R/WNote 2

Symbol <7> 6 5 4 3 2 <1> <0>
LVIM LVISEN 0 0 0 0 0 LVIOMSK LVIF
LVISEN Specification of whether to enable or disable rewriting the voltage detection level register (LVIS)
0 Disabling of rewriting the LVIS register (LVIOMSK = 0 (Mask of LVD output is invalid)
1 Enabling of rewriting the LVIS register (LVIOMSK = 1 (Mask of LVD output is valid)
LVIOMSK Mask status flag of LVD output
0 Mask of LVD output is invalid

1 Mask of LVD output is valid Note 3
LVIF Voltage detection flag
0 Supply voltage (VDD) ≥ detection voltage (VLVD), or when LVD is off

1 Supply voltage (VDD) < detection voltage (VLVD)
Notes 1. The reset value changes depending on the reset source.

If the LVIS register is reset by LVD, it is not reset but holds the current value. In other reset, LVISEN is
cleared to 0.
2. Bits 0 and 1 are read-only.
3. The LVIOMSK bit is automatically set to 1 for the following periods and generation of an LVD reset or
interrupt is masked.
● Period when LVISEN = 1
In either of the following cases, generation of an LVD reset or interrupt is masked only in interrupt & reset
mode.
● Wait time until the LVD detection voltage stabilizes after an LVD interrupt is generated
● Wait time until the LVD detection voltage stabilizes after the value of the LVILV bit is changed
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29.3.2 Voltage detection level register (LVIS)

This register selects the voltage detection level. The minimum supply voltage (LVD detection voltage) and LVD
detection level settings that are set by the user option byte can be changed by software.
Reset signal generation input sets this register to Note 1.
Caution Do not change the detection voltage in interrupt & reset mode.
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Figure 29-7. Format of Voltage Detection Level Register (LVIS)
Address: FFFAAH After reset: Note 1 R/W

Symbol <7> 6 5 4 3 2 1 <0>
Note 2 Note
LVIS LVIMD 0 LVISEL4 LVISEL3 LVISEL2 LVISEL1 LVISEL0 LVILVNote 2
6
Note 2
LVIMD Operation mode of voltage detection
0 Interrupt mode
1 Reset mode
LVISEL4Note 6 LVISEL3 LVISEL2 Minimum operating voltage (typical falling value)Note 5
0 0 1 1.84 V
0 1 0 2.45 V
0 1 1 2.75 V
1 1 1 1.53 V (LVD OFF)
LVISEL1 LVISEL0 LVD detection level settingNote 5

0 0 Setting voltage according to LVISEL4/LVISEL3/LVISEL2 + 1.2 VNote 3
1 1 Setting voltage according to LVISEL4/LVISEL3/LVISEL2Note 4
Note 2
LVILV LVD detection level
0 High-voltage detection level (VLVDH)
1 Low-voltage detection level (VLVDL or VLVD)
Notes 1. The reset value changes depending on the setting of the option byte.
After a reset is released, the values of VPOC2 to VPOC0 and LVIS1 and LVIS0 in the user option byte are
reflected in LVISEL4 to LVISEL2, LVISEL1, and LVISEL0, respectively.
The reset values of LVIMD and LVIVL are set as follows.
When LVIMDS1, LVIMDS0 in the option byte = 1, 0: LVIMD = 0, LVILV = 0
2. Writing “0” can only be allowed in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0). Do
not set LVIMD and LVILV in other cases. The value is switched automatically when reset or interrupt is
generated in the interrupt & reset mode.
3. Indicates an approximate detection value. For details on the actual detection voltage, refer to the LVD
section in Electrical Specifications.
4. Cannot be selected when LVIMDS1 and LVIMDS0 = 1 and 0.
5. When changing LVISEL4 to LVISEL0 to use two or more LVD detection voltages, the setting value that
indicates the highest voltage value among the LVD detection voltages to be used should be set in the
VPOC2 to VPOC0 bits and LVIS1 and LVIS0 bits before using the voltages.
6. Rewriting LVISEL4 is prohibited. Keep the initial value unchanged.
Cautions 1. When rewriting the LVIMD and LVILV bits, use the procedure shown in Figure 29-20.
2. Specify the LVD operation mode and initial detection voltage (VLVDH, VLVDL, VLVD) of each mode by
using the option byte 000C1H. Figure 29-8 shows the format of the user option byte
(000C1H/010C1H). For details about the option byte, see CHAPTER 35 OPTION BYTE.
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<R> Figure 29-8. Format of User Option Byte (000C1H/010C1H) (1/2)
Address: 000C1H/010C1HNote
7 6 5 4 3 2 1 0
VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0
● LVD setting (interrupt & reset mode)

Detection voltage Option byte setting value
VLVDH VLVDL VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting
Rising Falling Falling LVIMDS1 LVIMDS0
edge edge edge
1.98 V 1.94 V 1.84 V 0 0 1 1 0 1 0
2.09 V 2.04 V 0 1
3.13 V 3.06 V 0 0
2.61 V 2.55 V 2.45 V 1 0 1 0
2.71 V 2.65 V 0 1
3.75 V 3.67 V 0 0
2.92 V 2.86 V 2.75 V 1 1 1 0
3.02 V 2.96 V 0 1
4.06 V 3.98 V 0 0
– Setting of values other than above is prohibited.
● LVD setting (reset mode)

VLVD VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0
1.77 V 1.73 V 0 0 0 1 0 1 1
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V 1 1 0 0
Note Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced
by 010C1H.
Remarks 1. For details on the LVD circuit, see CHAPTER 29 VOLTAGE DETECTOR.
2. The detection voltage is a TYP. value. For details, see 41.6.5 LVD circuit characteristics.
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<R> Figure 29-8. Format of User Option Byte (000C1H/010C1H) (2/2)
7 6 5 4 3 2 1 0
● LVD setting (interrupt mode)

1.77 V 1.73 V 0 0 0 1 0 0 1
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V 1 1 0 0
● LVD off setting (external reset input from the RESET pin is used)
VLVD Mode setting
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
— — 1 × × × × × 1
— Settings other than the above are prohibited
by 010C1H.
Cautions 1. Set bit 4 to 1.

2. After power is supplied, the reset state must be retained until the operating voltage becomes in
the range defined in 41.4 AC Characteristics. This is done by utilizing the voltage detector or
controlling the externally input reset signal. After the power supply is turned off, this LSI should
be placed in the STOP mode, or placed in the reset state by utilizing the voltage detector or
controlling the externally input reset signal, before the voltage falls below the operating range.
The range of operating voltage varies with the setting of the user option byte (000C2H or 010C2H).
Remarks 1. ×: Don’t care

2. For details on the LVD circuit, see CHAPTER 29 VOLTAGE DETECTOR.
3. The detection voltage is a TYP. value. For details, see 41.6.5 LVD circuit characteristics.
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29.3.3 VDD pin voltage detection control register (LVDVDD)

This register is used to enable/disable VDD pin voltage detection and select the detection voltage.
Reset signal generation input sets this register to 00H.
Figure 29-9. Format of Voltage Detection Control Register for VDD Pin (LVDVDD)

Symbol <7> <6> 5 4 3 2 1 0
LVDVDD LVDVDDEN LVDVDDF 0 0 0 LVDVDD2 LVDVDD1 LVDVDD0
LVDVDDEN VDD pin voltage detection enable/disable

Note 3
0 Disables detection
1 Enables detection
LVDVDDFNote 2 VDD pin voltage detection flag
0 Supply voltage (VDD) ≥ detection voltage (VLVDVDD), or detection is off

1 Supply voltage (VDD) < detection voltage (VLVDVDD)
Detection voltage (VLVDVDD)

LVDVDD2 LVDVDD1 LVDVDD0
Rising edge Falling edge
0 0 0 2.54 V 2.47 V
0 0 1 2.75 V 2.68 V
0 1 0 2.95 V 2.88 V
0 1 1 3.16 V 3.09 V
1 0 0 3.47 V 3.40 V
1 0 1 3.78 V 3.71 V

2. When the LVDVDDEN bit is set to 1 while voltage of VDD pin < detection voltage (VLVDVDD), the LVDVDDF bit
is undefined until the stabilization time (300 µs) elapses.
3. To disable INTLVDVDD generation, do the following steps.
Figure 29-10. Setting Procedure to Disable VDD Pin Voltage Detection Function
Sets the interrupt mask flag to 1 to disable interrupt

LVDVDMK = 1
acknowledgement.
Sets the LVDVDDEN bit to 0 to stop voltage

LVDVDDEN = 0
detection function operation.
LVDVDIF = 0 Clears the interrupt request flag.
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29.3.4 VBAT pin voltage detection control register (LVDVBAT)

This register is used to enable/disable VBAT pin voltage detection and select the detection voltage.
Figure 29-11. Format of Voltage Detection Control Register for VBAT Pin (LVDVBAT)

Symbol <7> <6> 5 4 3 2 1 0
LVDVBAT LVDVBATEN LVDVBATF 0 0 0 LVDVBAT2 LVDVBAT1 LVDVBAT0
LVDVBATEN VBAT pin voltage detection enable/disable

Note 3
1 Enables detection
LVDVBATFNote 2 VBAT pin voltage detection flag

0 Supply voltage (VBAT) ≥ detection voltage (VLVDVBAT), or detection is off
1 Supply voltage (VBAT) < detection voltage (VLVDVBAT)
Detection voltage (VLVDVBAT)

LVDVBAT2 LVDVBAT1 LVDVBAT0
0 0 0 2.12 V 2.06 V
0 0 1 2.22 V 2.16 V
0 1 0 2.33 V 2.27 V
0 1 1 2.43 V 2.37 V
1 0 0 2.53 V 2.47 V
1 0 1 2.63 V 2.57 V
1 1 0 2.74 V 2.68 V

2. When the LVDVBATEN bit is set to 1 while voltage of VBAT pin < detection voltage (VLVDVBAT), the
LVDVBATF bit is undefined until the stabilization time (500 µs) elapses.
3. To disable INTLVDBAT generation, do the following steps.
Figure 29-12. Setting Procedure to Disable VBAT Pin Voltage Detection Function

LVDVBMK = 1
acknowledgement.
Sets the LVDVBATEN bit to 0 to stop voltage

LVDVBATEN = 0
LVDVBIF = 0 Clears the interrupt request flag.
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29.3.5 VRTC pin voltage detection control register (LVDVRTC)

This register is used to enable/disable VRTC pin voltage detection and select the detection voltage.
Figure 29-13. Format of Voltage Detection Control Register for VRTC Pin (LVDVRTC)

Symbol <7> <6> 5 4 3 2 1 0
LVDVRTC LVDVRTCEN LVDVRTCF 0 0 0 0 LVDVRTC1 LVDVRTC0
LVDVRTCEN VRTC pin voltage detection enable/disable

Note 3
1 Enables detection
LVDVRTCFNote 2 VRTC pin voltage detection flag

0 Supply voltage (VRTC) ≥ detection voltage (VLVDVRTC), or detection is off
1 Supply voltage (VRTC) < detection voltage (VLVDVRTC)
Detection voltage (VLVDVRTC)

LVDVRTC1 LVDVRTC0
0 0 2.22 V 2.16 V
0 1 2.43 V 2.37 V
1 0 2.63 V 2.57 V
1 1 2.84 V 2.78 V

2. When the LVDVRTCEN bit is set to 1 while voltage of VRTC pin < detection voltage (VLVDVRTC), the
LVDVRTCF bit is undefined until the stabilization time (300 µs) elapses.
3. To disable INTLVDVRTC generation, do the following steps.
Figure 29-14. Setting Procedure to Disable VRTC Pin Voltage Detection Function

LVDVRMK = 1
acknowledgement.
Sets the LVDVRTCEN bit to 0 to stop voltage

LVDVRTCEN = 0
LVDVRIF = 0 Clears the interrupt request flag.
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29.3.6 EXLVD pin voltage detection control register (LVDEXLVD)

This register is used to enable/disable EXLVD pin voltage detection and select the detection voltage.
Figure 29-15. Format of Voltage Detection Control for EXLVD Pin Register (LVDEXLVD)

Symbol <7> <6> 5 4 3 2 1 0
LVDEXLVD LVDEXLVDEN LVDEXLVDF 0 0 0 0 0 0
LVDEXLVDEN EXLVD pin voltage detection enable/disable

Note 3
1 Enables detection
LVDEXLVDFNote 2 EXLVD pin voltage detection flag

0 Supply voltage (EXLVD) ≥ detection voltage (VLVDEXLVD), or detection is off
1 Supply voltage (EXLVD) < detection voltage (VLVDEXLVD)
Detection voltage (VLVDEXLVD)

1.33 V (fixed) 1.28 V (fixed)

2. When the LVDEXLVDEN bit is set to 1 while voltage of EXLVD pin < detection voltage (VLVDEXLVD), the
LVDEXLVDF bit is undefined until the stabilization time (300 µs) elapses.
3. To disable INTLVDEXLVD generation, do the following steps.
Figure 29-16. Setting Procedure to Disable EXLVD Pin Voltage Detection Function

LVDEXMK = 1
acknowledgement.
Sets the LVDEXLVDEN bit to 0 to stop voltage

LVDEXLVDEN = 0
LVDEXIF = 0 Clears the interrupt request flag.
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29.4 Operation of Voltage Detector
29.4.1 When used as reset mode

Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the initial detection voltage (VLVD) by
using the option byte 000C1H. The detection voltages can be reset using the LVIS register.
The operation is started in the following initial setting state when the reset mode is set.
- Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level register
(LVIS))
- The initial value of the voltage detection level select register (LVIS) is set to 81H.
See 29.3.2 Voltage detection level register (LVIS) for details on the initial value of the voltage detection level
register (LVIS).
Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD).
● Operation in LVD reset mode

In the reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1), the state of an internal reset by LVD is retained until the
supply voltage (VDD) exceeds the voltage detection level (VLVD) after power is supplied. The internal reset is released
when the supply voltage (VDD) exceeds the voltage detection level (VLVD).
At the fall of the operating voltage, an internal reset by LVD is generated when the supply voltage (VDD) falls below
the voltage detection level (VLVD).
The reset release voltage when an LVD reset is generated is the detection voltage set by the option byte or detection
voltage set by the LVIS register, whichever is higher. The state of an internal reset by the LVD is retained until the
supply voltage exceeds the voltage detection level.
The reset release voltage used for resets other than an LVD reset is the same voltage detection level set by the
option byte.
Figure 29-17 shows the timing of the internal reset signal generated in the LVD reset mode.
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Figure 29-17. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1)
VLVD
Lower limit of operation voltage

Time
Cleared
LVIF flag
LVIMD flag H Not cleared
LVILV flag H Not cleared
Cleared
LVIRF flag
(RESF register)
LVD reset signal

Cleared by software
POR reset signal

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29.4.2 When used as interrupt mode

Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the initial detection voltage (VLVD) by
using the option byte 000C1H. The detection voltages can be reset using the LVIS register.
The operation is started in the following initial setting state when the interrupt mode is set.
(LVIS))
- See 29.3.2 Voltage detection level register (LVIS) for details on the initial value of the voltage detection level
register (LVIS).
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD).
● Operation in LVD interrupt mode

In the interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1), the state of an internal reset by LVD is retained until
the supply voltage (VDD) exceeds the voltage detection level (VLVD) immediately after a reset occurs. The internal
reset is released when the supply voltage (VDD) exceeds the voltage detection level (VLVD).
After the internal reset of LVD is released, an interrupt request signal by LVD (INTLVD) is generated when the supply
voltage (VDD) exceeds the voltage detection level (VLVD). When the voltage falls, this LSI should be placed in the
STOP mode, or placed in the reset state by controlling the externally input reset signal, before the voltage falls below
the operating voltage range defined in 41.4 AC Characteristics. When restarting the operation, make sure that the
operation voltage has returned within the range of operation.
After the LVISEN bit is set to 1 (LVD is masked) by changing the detection level, if the supply voltage (VDD) falls
below the voltage detection level (VLVD) when LVISEN is set to 0, an interrupt request signal by the LVD (INTLVI) is
generated.
Figure 29-18 shows the timing of the interrupt request signal generated in the LVD interrupt mode.
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Figure 29-18. Timing of Voltage Detector Internal Interrupt Signal Generation

(Option Byte LVIMDS1, LVIMDS0 = 0, 1)
Note 2 Note 2
VLVD
Time
LVIMK flag
H Note 1
(interrupt MASK)
(set by software)
Cleared by
software
Cleared
LVIF flag
LVIMD flag
LVILV flag H
INTLVI
LVIIF flag
LVD reset signal
POR reset signal
Notes 1. The LVIMK flag is set to “1” by reset signal generation.

2. When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset state by
controlling the externally input reset signal, before the voltage falls below the operating voltage range
defined in 41.4 AC Characteristics. When restarting the operation, make sure that the operation voltage
has returned within the range of operation.

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29.4.3 When used as interrupt and reset mode

Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVDL)
by using the option byte 000C1H. Do not manipulate the detection voltage using the LVIS register.
The operation is started in the following initial setting state when the interrupt & reset mode is set.
(LVIS))
- See 29.3.2 Voltage detection level register (LVIS) for details on the initial value of the voltage detection level
register (LVIS).
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH).
● Operation in LVD interrupt & reset mode

In the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0), the state of an internal reset by LVD is retained
until the supply voltage (VDD) exceeds the high-voltage detection level (VLVDH) after power is supplied. The internal
reset is released when the supply voltage (VDD) exceeds the high-voltage detection level (VLVDH). An interrupt request
signal by LVD (INTLVI) is generated and arbitrary save processing is performed when the supply voltage (VDD) falls
below the high-voltage detection level (VLVDH). After that, an internal reset by LVD is generated when the supply
voltage (VDD) falls below the low-voltage detection level (VLVDL). After INTLVI is generated, an interrupt request signal
is not generated even if the supply voltage becomes equal to or higher than the high-voltage detection voltage (VLVDH)
without falling below the low-voltage detection voltage (VLVDL). To use the LVD reset & interrupt mode, perform the
processing according to Figure 29-20 Setting Procedure for Operating Voltage Check and Reset.
Figure 29-19 shows the timing of the internal reset signal and interrupt signal generated in the LVD interrupt & reset
mode.
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Figure 29-19. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
If a reset is not generated after releasing the mask,

determine that a condition of VDD becomes VDD VLVDH,
clear LVIMD bit to 0, and the MCU shift to normal operation.

VLVDH
VLVDL
Time
Note 1
LVIMK flag H
(set by software)
Cleared by Cleared by software

software Normal
operation
Normal Save Normal
Operation status RESET operation
RESET operation
RESET
processing
Save
processing
Cleared
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
Cleared by
software Note 2
LVIRF flag
Cleared
LVD reset signal
POR reset signal
INTLVI
LVIIF flag
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2. After an interrupt is generated, perform the processing according to Figure 29-20 Setting Procedure for
Operating Voltage Check and Reset in interrupt and reset mode.

VPOR: POR power supply fall detection voltage
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Figure 29-19. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
When a condition of VDD is VDD < VLVDH after releasing the mask,
a reset is generated because of LVIMD = 1 (reset mode).
VLVDH
VLVDL
Time
LVIMK flag H Note 1
(set by software)
Cleared by software
Cleared by
software
Normal Save Normal

Operation status RESET operation processing RESET operation
RESET
Save processing
Cleared
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
Cleared by
LVIRF flag software Note 2
Cleared
LVD reset signal
POR reset signal
INTLVI
LVIIF flag
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2. After an interrupt is generated, perform the processing according to Figure 29-20 Setting Procedure for
Operating Voltage Check and Reset in interrupt and reset mode.

Figure 29-20. Setting Procedure for Operating Voltage Check and Reset
INTLVI generated
Save processing Perform required save processing.
Set the LVISEN bit to 1 to mask voltage detection

LVISEN = 1
(LVIOMSK = 1).
Set the LVILV bit to 0 to set the high-voltage detection

LVILV = 0
level (VLVDH).
LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection.
LVIOMSK = 0
No
Yes
When an internal reset by voltage detector (LVD) is not

LVD reset generated
generated, a condition of VDD becomes VDD  VLVDH.
Yes
No
Set the LVISEN bit to 1 to mask voltage detection
LVISEN = 1
(LVIOMSK = 1).
LVIMD = 0 Set the LVIMD bit to 0 to set interrupt mode.
LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection.
Internal reset by LVD

Normal operation
is generated
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29.4.4 Each power supply pin voltage detection setting procedure
(1) VDD
The setting procedure of VDD pin voltage detection is shown below.
Figure 29-21. Setting Procedure of VDD Pin Voltage Detection
LVDVDMK = 1 Sets the interrupt mask flag
Sets the LVDVDDEN bit to “0”

LVDVDDEN = 0 to disable voltage detection function
LVDVDD2 to LVDVDD0 = Sets detection voltage with LVDVDD2 to LVDVDD0 bits

(setting value)

LVDVDDEN = 1 to enable voltage detection function
Stabilization wait time count Counts the detect stabilization wait time (300 µs)
Note 2 by software Note 1
LVDVDIF = 0 Clears the interrupt request flag and

interrupt mask flag to enable interrupt
acknowledgment
LVDVDMK = 0
VDD pin voltage > The LVD circuit compares the VDD pin
No
No Detection voltage (VLVDVDD) voltage with the detection voltage (VLVDVDD),
or and generates an interrupt request signal
VDD pin voltage < (INTLVDVDD) by detecting VDD pin voltage >
Detection voltage (VLVDVDD) VLVDVDD or VDD pin voltage < VLVDVDD.
Yes
Yes
INTLVDVDD = 1
Notes 1. Be sure to set the detection voltage level when pin voltage < detection voltage.
<R> 2. If other process operating secures the stabilization wait time after setting the LVDVDDEN bit to 1 to enable
the voltage detect function operation, the count process isn't required.
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(2) VBAT
The setting procedure of VBAT pin voltage detection is shown below.
Figure 29-22. Setting Procedure of VBAT Pin Voltage Detection
LVDVBMK = 1 Sets the interrupt mask flag
LVDVBATEN = 0 Sets the LVDVBATEN bit to “0”

to disable voltage detection function
LVDVBAT2 to LVDVBAT0 Sets detection voltage with LVDVBAT2 to LVDVBAT0 bits

= (setting value)
Sets the LVDVBATEN bit to “1”

LVDVBATEN = 1
to enable voltage detection function
LVDVBIF= 0
Clears the interrupt request flag and
acknowledgment
LVDVBMK = 0
VBAT pin voltage > The LVD circuit compares the VBAT pin voltage
No
No Detection voltage (VLVDVBAT) with the detection voltage (VLVDVBAT), and
or generates an interrupt request signal
VBAT pin voltage < (INTLVDVBAT) by detecting VBAT pin voltage >
Detection voltage (VLVDVBAT) VLVDVBAT or VBAT pin voltage < VLVDVBAT.
Yes
Yes
INTLVDVBAT = 1
<R> 2. If other process operating secures the stabilization wait time after setting the LVDVBATEN bit to 1 to enable
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(3) VRTC
The setting procedure of VRTC pin voltage detection is shown below.
Figure 29-23. Setting Procedure of VRTC Pin Voltage Detection
LVDVRMK = 1 Sets the interrupt mask flag
LVDVRTCEN = 0 Sets the LVDVRTCEN bit to “0”

LVDVRTC2 to LVDVRTC0 Sets detection voltage with LVDVRTC2 to LVDVRTC0 bits

= (setting value)
Sets the LVDVRTCEN bit to “1”

LVDVRTCEN = 1
LVDVRIF = 0 Clears the interrupt request flag and

acknowledgment
LVDVRMK = 0
VRTC pin voltage > The LVD circuit compares the VRTC pin
No
No Detection voltage (VLVDVRTC) voltage with the detection voltage
or (VLVDVRTC), and generates an interrupt
VRTC pin voltage < request signal (INTLVDVRTC) by detecting
Detection voltage (VLVDVRTC) VRTC pin voltage > VLVDVRTC or VRTC pin
voltage < VLVDVRTC.
Yes
Yes
INTLVDVRTC = 1
<R> 2. If other process operating secures the stabilization wait time after setting the LVDVRTCEN bit to 1 to enable
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(4) EXLVD
The setting procedure of EXLVD pin voltage detection is shown below.
Figure 29-24. Setting Procedure of EXLVD Pin Voltage Detection
LVDEXMK = 1 Sets the interrupt mask flag
LVDEXLVDEN = 0 Sets the LVDEXLVDEN bit to “0”

LVDEXLVD2 to LVDEXLVD0 Sets detection voltage

= (setting value) with LVDEXLVD2 to LVDEXLVD0 bits
Sets the LVDEXLVDEN bit to “1”

LVDEXLVDEN = 1
LVDEXIF = 0
Clears the interrupt request flag and
acknowledgment
LVDEXMK = 0
EXLVD pin voltage > The LVD circuit compares the EXLVD pin
No
No Detection voltage (VLVDEXLVD) voltage with the detection voltage
or (VLVDEXLVD), and generates an interrupt
EXLVD pin voltage < request signal (INTLVDEXLVD) by detecting
Detection voltage (VLVDEXLVD) EXLVD pin voltage > VLVDEXLVD or EXLVD
pin voltage < VLVDEXLVD.
Yes
Yes
INTLVDEXLVD = 1
<R> 2. If other process operating secures the stabilization wait time after setting the LVDEXLVDEN bit to 1 to
enable the voltage detect function operation, the count process isn't required.
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29.5 Changing of LVD Detection Voltage Setting
To change the LVD detection voltage by software, use the following procedure.
The LVD detection voltage can be changed in interrupt mode and reset mode.
In interrupt & reset mode, the value of the LVD detection voltage cannot be changed. Keep the initial value (set value
in the option byte) unchanged.
To use two or more LVD detection voltages by changing LVISEL4 to LVISEL0 in the LVIS register by software, the
highest voltage value of the used LVD detection voltages must be specified in the VPOC2 to VPOC0, LVIS1, and LVIS0
bits in the option byte (000C1H).
Figure 29-25. Changing of LVD Detection Voltage Setting
Program
LVISEN = 1
LVIS5 to LVIS1 = (setting value)
Wait for stabilization by software (400 µs or 5 clocks of fIL)
LVISEN = 0
Note
Program
Note After LVISEN is set to 0, LVD is detected if VLVD > VDD, and a reset/interrupt is generated.
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29.5.1 Changing of LVD detection voltage setting in LVD reset mode

Figure 29-26 shows an example of timing for changing LVD detection voltage setting in LVD reset mode.
Figure 29-26. Example of Timing for Changing LVD Detection Voltage Setting in LVD Reset Mode
(1) (2) (3) (4) (5)
Option byte initial value
Detection voltage
VDD
LVD reset
LVISEN
(set by software)
LVIOMSK flag
Operation
(1) When the supply voltage rises, the detection voltage set by the option byte is used to release the reset.
(2) The value of the LVIS register is changed.
(3) Waiting for stabilization by software is completed (400 µs or five fIL clock cycles after (2))
(4) At LVD detection (falling), the detection voltage set by the LVIS register
(5) At the LVD reset release (rising), the detection voltage set by the option byte
When changing the LVD detection voltage setting, note the following.
Caution The value of the reset release voltage in LVD reset mode is set to the set value in the option byte.
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29.5.2 Changing of LVD detection voltage setting in LVD interrupt mode

Figure 29-27 shows an example of timing for changing LVD detection voltage setting in LVD interrupt mode.
Figure 29-27. Example of Timing for Changing LVD Detection Voltage Setting in LVD Interrupt Mode
(1) (2) (3) (3) (4) (5)
Detection voltage
VDD
LVIF flag
LVISEN
(set by software)
LVIOMSK flag
INTLVI
Operation
(3) At LVD detection (falling and rising), the detection voltage set by the LVIS register
(4) An internal reset is generated.
(5) The voltage value is changed to the set value in the option byte again when the internal reset is released.
When changing the LVD detection voltage setting, note the following.
Cautions 1. Immediately after all resets are generated, the LVD internal reset retains its reset state until VDD ≥
VLVD (set value in the option byte). The LVD internal reset is released when VDD ≥ VLVD is detected
(set value in the option byte).
After that, an interrupt request signal (INTLVI) is generated when VDD < VLVD or VDD ≥ VLVD is
detected.
2. If the LVD set voltage is changed by setting LVISEL4 to LVISEL0 in the LVIS register while VDD <
VLVD, an LVD interrupt is generated when the masking is released (LVISEN = 0). See Figure 29-28.
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Figure 29-28. Example of Timing for Changing LVD Detection Voltage Using LVIS When VDD < VLVD
(1) (2) (3) (4)
Detection voltage
VDD
LVIF flag
LVISEN
(set by software)
LVIOMSK flag
INTLVI
Operation
(2) At LVD detection (falling), the detection voltage set by the option byte
(4) If VDD < VLVD at the same time the masking is released, an interrupt is generated.
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29.5.3 Changing of each power supply pin LVD detection voltage setting
To change the LVD detection voltage during voltage detection, use the following procedure.
Figure 29-29. Changing of LVD Detection Voltage Setting (VDD pin)
LVDVDMK = 1 Sets the interrupt mask flag to disable

interrupt acknowledgment
LVDVDDEN = 0 Sets the LVDVDDEN bit to “0”

LVDVDIF = 0 Clears the interrupt request flag
LVDVDD2 to LVDVDD0 = Sets detection voltage with LVDVDD2 to LVDVDD0 bits

(setting value)

LVDVDDEN = 1
LVDVDIF = 0 Clears the interrupt request flag
Clears the interrupt mask flag to enable

LVDVDMK = 0 interrupt acknowledgment
VDD pin voltage > The LVD circuit compares the VDD pin
No
No Detection voltage (VLVDVDD) voltage (VDD) with the detection voltage
or (VLVDVDD), and generates a interrupt request
VDD pin voltage < signal (INTLVDVDD) by detecting VDD >
Detection voltage (VLVDVDD) VLVDVDD or VDD < VLVDVDD.
Yes
Yes
INTLVDVDD = 1
<R> 2. If other process operating secures the stabilization wait time after setting the LVDVDDEN bit to 1 to enable
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29.6 Cautions for Voltage Detector
(1) Voltage fluctuation when power is supplied

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVD detection voltage,
the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset
to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 29-30. Example of Software Processing If Supply Voltage Fluctuation is 50 ms or Less in Vicinity of LVD
Detection Voltage
Reset
Initialization processing <1> Refer to Figure 27-5 Example of Procedure for

Checking Reset Source.
; e.g. fCLK = High-speed on-chip oscillator clock (4.04 MHz (MAX.))

Setting timer array unit Source: fMCK = (4.04 MHz (MAX.))/28,
(to measure 50 ms) where comparison value = 789:  50 ms
Timer starts (TSmn = 1).
Clearing WDT
Note
No 50 ms have passed?
(TMIFmn = 1?)
Yes
; Initial setting for port.
Initialization processing <2>
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Note If reset is generated again during this period, initialization processing <2> is not started.
Remark m=0
n = 0 to 3
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(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has
been generated.
In the same way, there is also some delay from the time LVD detection voltage (VLVD) ≤ supply voltage (VDD) until
the time LVD reset has been released (see Figure 29-31).
Figure 29-31. Delay from the Time LVD Reset Source Is Generated until the Time LVD Reset has Been Generated
or Released
VLVD
Time
LVIF flag
<1> <1>
LVD reset signal
<1>: Detection delay (300 µs (MAX.))
(3) Power on when LVD is off

Use the external rest input via the RESET pin when the LVD is off.
For an external reset, input a low level for 10 µs or more to the RESET pin. To perform an external reset upon
power application, input a low level to the RESET pin, turn power on, continue to input a low level to the pin for 10
µs or more within the operating voltage range shown in 41.4 AC Characteristics, and then input a high level to
the pin.
(4) Operating voltage fall when LVD is off or LVD interrupt mode is selected
When the operating voltage falls with the LVD is off or with the LVD interrupt mode is selected, this LSI should be
placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before the
voltage falls below the operating voltage range defined in 41.4 AC Characteristics. When restarting the operation,
make sure that the operation voltage has returned within the range of operation.
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(5) When supply voltage from the pins is shut off

When supply voltage from the pins selected with VBATEN and VBATSEL is shut off, the voltage detection function
of VDD, VBAT, VRTC, and EXLVD pins cannot be used.
(6) When supply voltage output to the VDDOUT pin is shut off
When source supply voltage (VDD and VBAT) of the VDDOUT pin is shut off, the voltage detection function of the
VRTC pin cannot be used, even if supply voltage from the VRTC pin is not shut off.
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RL78/I1C CHAPTER 30 BATTERY BACKUP FUNCTION
CHAPTER 30 BATTERY BACKUP FUNCTION
30.1 Functions of Battery Backup
This function monitors the supply voltage at the VDD pin, and switches the internal power supply and the power supply
for ΔΣ A/D converter from the dedicated battery backup power pin (VBAT pin) when the voltage at the VDD pin falls below
the detection voltage. The mode used to supply the internal power and the power supply for ΔΣ A/D converter from the
VBAT pin is referred to as battery backup mode. Even if power supply from the VDD pin is cut off due to a power outage,
operation of battery backup mode can be continued by switching to battery backup mode by hardware.
Table 30-1. Peripheral Circuit Operation State during Battery Backup (1/2)
Item When operating CPU with the When operating CPU with the
power of VDD pin supplied power of VBAT pin supplied
System clock Clock supply operation to CPU
Main system clock Operable
Subsystem clock Operable when RTCPOR does not occur
fIL Operable
CPU Continuous operation
Code flash memory Continuous operation Continuous operationNote 1
Data flash memory Operable Operation disabledNote 6
RAM Continuous operation
Port Internal VDD P20 to P25, P150 to P152Note 5 Operable
port
P137, P121, P122 Operable
EVDD port Other than P20 to P25, P137, Operable Operable when the power of EVDD
P121 to P124, P150 to P152 pin is suppliedNote 2
Not operable when the power of
EVDD pin is shut downNote 3
VRTC port P123, P124 Operable when RTCPOR does not occur
Timer array unit Operable
Independent power supply RTC Operable when RTCPOR does not occur
Frequency measurement circuit Operable

Battery backup function Continuous operation
12-bit interval timer Operable
Watchdog timer
Clock output/buzzer output
10-bit A/D converter
24-bit ΔΣ A/D converter Operable OperableNote 4
Temperature sensor Operable
Serial array unit
IrDA
(Notes are listed on the next page.)
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Table 30-1. Peripheral Circuit Operation State during Battery Backup (2/2)
Item When operating CPU with the When operating CPU with the
power of VDD pin supplied power of VBAT pin supplied
LCD controller/driver Operable

Power-on-reset function Continuous operation
RTC power-on-reset function Continuous operation
Voltage detection function Internal power supply voltage Operable
(Internal VDD)
VDD, VBAT, VRTC, EXLVD Operable
Pin voltage
External interrupt INTP0 Operable
INTP1 to INTP7 Operable Operable when the power of
EVDD pin is suppliedNote 2.
Not operable when the power of
EVDD pin is shut down.
RTCIC0 to RTCIC2 Operable
Key interrupt input Operable
CRC operation function
32-bit multiplier and multiplyaccumulator
RAM guard function
SFR guard function
Illegal-memory access detection function
AES function
Notes 1. The self-programming function cannot be used.
2. When supplying the power from outside to the EVDD pin, it is recommended to backup the VDD and VBAT
pins or the VRTC pin with the diode ORing.
3. When the power of EVDD is not supplied, set GDIDIS0 to 1.
4. The ΔΣ A/D converter operable in the backup mode is limited up to 3 channels.
5. RTCIC0, RTCIC1, and RTCIC2 pins are included.
6. When power supply switching by the battery backup function occurs, access to the data flash memory is
prohibited.
● The power is supplied from the VDD pin at startup of the power supply. MCU remains reset even when the power is
supplied to the VBAT pin earlier than the VDD pin.
● The battery backup function is stopped by default. The battery backup mode must be set by the software after
startup of the power supply.
● If the VDD pin voltage is lower than the detection voltage, the internal power and the power supply for ΔΣ A/D
converter can be switched from the VDD supply to the VBAT supply. When the VDD pin voltage is recovered higher
than the detection voltage, the internal power and the power supply for ΔΣ A/D converter can be switched from the
VBAT supply to the VDD supply.
● Under the condition of VBAT ≥ VDD, the software enables to switch the internal power and the power supply for ΔΣ
A/D converter from the VDD supply to the VBAT supply.
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Figure 30-1 shows the block diagram of the battery backup function.
Figure 30-1. Block Diagram of Battery Backup Function
Power supply switch
VBAT pin
Internal power supply voltage
VDD pin (internal VDD)
VDETBAT A/D Converter power supply
Internal VDD I/O
Switch
controller
Sync
circuit
BUPCTL0 BUPCTL1
VBATCMPM VBATEN VBATSEL BUPPTR
register register
Data bus
30.1.1 Pin configuration

Table 30-2 lists the pin configuration of battery backup function.
Table 30-2. Pin Configuration of Battery Backup Function
Name Function
VDD Positive power from the pin
VBAT Power for battery backup
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30.2 Registers
Table 30-3 lists the registers used for battery backup.
Battery backup power switching control register 0 BUPCTL0

Battery backup power switching control register 1 BUPCTL1
Global digital input disable register GDIDIS
30.2.1 Battery backup power switching control register 0 (BUPCTL0)

The BUPCTL0 register is used to select the power supply pin.
The BUPCTL0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
VBATEN (bit 7) and VBATSEL (bit 0) are cleared to 0 only when a power-on reset is generated. Other bits are cleared
to 0 when a reset signal is generated.
Figure 30-2. Format of Battery Backup Power Switching Control Register 0 (BUPCTL0) (1/2)
Address: F0330H After reset: 00HNote 1 R/W

Symbol <7> 6 5 4 <3> 2 1 <0>
BUPCTL0 VBATEN 0 0 0 VBATCMPM 0 0 VBATSEL
VBATENNotes 2, 4 Battery backup function control

Note 3
0 Battery backup function stops
1 Battery backup function operates
Notes 1. VBATEN (bit 7) and VBATSEL (bit 0) are cleared to 0 only when a power-on reset is generated.
2. To set the VBATEN bit to 1, write 0 and then write 1 to this bit. If a value is written to an SFR other than
BUPCTL0 after 0 has been written, the VBATEN bit cannot be set to 1.
To set the VBATEN bit to 0, write 1 and then write 0 to this bit. If a value is written to an SFR other than
BUPCTL0 after 1 has been written, the VBATEN bit cannot be set to 0.
3. Making the setting to stop the battery backup function (VBATEN = 0) while the internal power supply is
supplying power through the VBAT pin causes the power supply to be switched to that from the VDD pin.
To forcibly shut down the power supply from the VBAT pin when the VDD voltage is not supplied, clear the
VBATEN bit to 0. The power is not supplied (power-on-reset status) since the power supply from VDD pin is
forcibly switched. After that, this status is recovered by the VDD power supply.
4. The minimum operating voltage of this product varies according to the VBATEN setting value.
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Figure 30-2. Format of Battery Backup Power Switching Control Register 0 (BUPCTL0) (2/2)
Address: F0330H After reset: 00HNote 1 R/W

Symbol <7> 6 5 4 <3> 2 1 <0>
BUPCTL0 VBATEN 0 0 0 VBATCMPM 0 0 VBATSEL
VBATCMPMNote 1 Battery backup comparator output monitor
0 VDD pin voltage ≥ power switching detection voltage (VDETBAT2)

or power switching function stopped (VBATEN = 0)
1 VDD pin voltage < power switching detection voltage (VDETBAT1)
VBATSELNote 2 Power supply pin selection
0 The supply source is switched by hardware depending on the potential of VDD pin.
1 Power is supplied from VBAT pin.
Notes 1. Bit 3 is Read only.

2. To set the VBATSEL bit to 1, write 0 and then write 1 to this bit. If a value is written to an SFR other than
BUPCTL0 after 0 has been written, the VBATSEL bit cannot be set to 1.
To set the VBATSEL bit to 0, write 1 and then write 0 to this bit. If a value is written to an SFR other than
BUPCTL0 after 1 has been written, the VBATSEL bit cannot be set to 0.
Cautions 1. Setting VBATSEL = 1 is prohibited when VDD > 4.0 V and VBAT < 2.4 V, or VBAT > 4.0 V and VDD < 2.4
V.
2. Be sure to clear bits 6 to 4, 2, and 1 to “0”.
Remark Set the operation/stop of the battery backup function according to Figure 30-7 Procedure for Setting
Battery Backup Function Operation, Figure 30-8 Procedure for Battery Backup Function Stop, and
30.3.2 Using the battery backup function.
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30.2.2 Battery backup power switching control register 1 (BUPCTL1)

The BUPCTL1 register is used to disable or enable rewriting of the BUPCTL0 register. Since rewriting of the BUPCTL0
register is disabled when the BUPPRT bit is 0, the BUPCTL0 register can be prevented from being written inadvertently.
The BUPCTL1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 30-3. Format of Battery Backup Power Switching Control Register 1 (BUPCTL1)

Symbol <7> 6 5 4 3 2 1 0
BUPCTL1 BUPPRT 0 0 0 0 0 0 0
BUPPRT BUPCTL0 register write protection control
0 The BUPCTL0 register cannot be written, but it can be read.

1 The BUPCTL0 register can be written and read.
30.2.3 Global digital input disable register (GDIDIS)

When EVDD and VDD are used at the same potential, if power supply from the VDD pin is stopped due to power outage,
EVDD supply will also stop and drop to 0 V. The GDIDIS register prevents through-current to the input buffer when EVDD =
0 V. Setting the GDIDIS0 bit to 1 disables input to all input buffersNote connected to EVDD, and prevents shoot-through
current when the power connected to EVDD is turned off. When using the GDIDIS register, set GDIDIS0 to 1 before turning
off the power for EVDD, and then set GDIDIS0 to 0 after turning on the power for EVDD.
The GDIDIS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Note Port pin other than the I/O buffer (P20 to P25, P121 to P124, P137 and P150 to P152) that is driven by internal VDD
or VRTC.
Because the power supply of the I/O buffer switches to VDD or VBAT pin with the battery backup function, I/O that is
driven by internal VDD can be used even when GDIDIS is set to 1.
See Table 2-1 Pin I/O Buffer Power Supplies for the I/O buffer power of the pins.
Figure 30-4. Format of Global Digital Input Disable Register (GDIDIS)
Address: F007DH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
GDIDIS 0 0 0 0 0 0 0 GDIDIS0
GDIDIS0 Setting of input buffers using EVDD power supply
0 Input to input buffers permitted (default)

1 Input to input buffers prohibited. No through-current flows to the input buffers.
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30.3 Operation
30.3.1 Battery backup function

When the voltage from the VDD pin falls below the detection voltage, the power supply from the dedicated battery
backup power pin (VBAT pin) can be switched to the internal power supply and the power supply for ΔΣ A/D converter.
When the voltage supplied from the VDD pin falls below the detection voltage (VDETBAT1), the internal power and the power
supply for ΔΣ A/D converter are switched from VDD supply to VBAT supply.
At power on, the internal power and the power supply for ΔΣ A/D converter are fixed to be always supplied from the VDD
pin. When a power-on reset is generated, the VBATEN bit in the BUPCTL0 register is reset to 0. When the VBATEN bit
in the BUPCTL0 register is 0, the power switching function is stopped, and the internal power and the power supply for ΔΣ
A/D converter are supplied from the VDD pin. When the VBATEN bit in the BUPCTL0 register is set to 1, the power
switching function operates. When the power switching function is operating, the internal power supply and the power
supply for ΔΣ A/D converter are switched from VDD supply to VBAT supply when the supply voltage from the VDD pin
becomes lower than the detection voltage (VDETBAT1). The internal power supply and the power supply for ΔΣ A/D
converter are switched from VBAT supply to VDD supply when the VDD voltage rises to or above the detection voltage
(VDETBAT2) again while the power is supplied from the VBAT pin.
In addition, the power supply from the VDD pin can be switched to the power supply from the VBAT pin by software.
When the VBATEN bit in the BUPCTL0 register is 1 (power switching function operates), the power supply is switched to
the power supply from the VBAT pin by setting the VBATSEL bit in the BUPCTL0 register to 1 (power is supplied from
the VBAT pin).
Table 30-4 lists the specifications of battery backup operation and Figure 30-5 and Figure 30-6 show battery backup
operation.
Table 30-4. Specifications of Battery Backup Operation
Power VBATEN VBATSEL Condition Internal Power and Power Supply for ΔΣ
A/D Converter Connection
At power on × × – Power supplied from the VDD pin

After power on 0 × – Power supplied from the VDD pin
1 0 VDD ≥ VDETBAT2 Power supplied from the VDD pin
VDETBAT1 < VDD < VDETBAT2 Power supplied from the VDD pin
or power supplied from the VBAT pin
(Has hysteretic characteristics)
VDD ≤ VDETBAT1 Power supplied from the VBAT pin
1 – Power supplied from the VBAT pin
Remark ×: Don't care
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Figure 30-5. Battery Backup Operation (1) with VBATEN = 1 and VBATSEL = 0
Switch to the power supply from Switch to the power supply from
the VBAT pin when the voltage falls the VDD pin when the voltage rises
below the detection voltage (VDETBAT1) above the detection voltage (VDETBAT2)
VDD
VBAT
VDETBAT2
VDETBAT1
Note Note
VBATEN
Set VBATEN = 1
by software
VBATSEL
VDD electric Internal power

potential
VBAT electric
potential VDETBAT2
VDETBAT1
Internal power
POR signal
Power Power supplied Power supplied

Power supplied from the VDD pin
connection from the VBAT pin from the VDD pin
Note For details about the power rising and falling slopes, see CHAPTER 41 ELECTRICAL SPECIFICATIONS.
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Figure 30-6. Battery Backup Operation (2) with VBATEN = 1 and VBATSEL = 1
VDD
VBAT
VDETBAT1
VBATEN
Set VBATEN = 1
by software
VBATSEL Forcibly switch to the power supply from the

VBAT pin by setting VBATSEL = 1 by software
VDD electric Internal power
potential
VBAT electric
potential
Internal power
POR signal
Power Power supplied from the VDD pin Power supplied from the VBAT pin
connection
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Figure 30-7 shows the procedure for setting the battery backup function operation, and Figure 30-8 shows the
procedure for setting the battery backup function stop.
Figure 30-7. Procedure for Setting Battery Backup Function Operation
VDD/VBAT power supply ON
Set the BUPPRT bit, and enable read/write of the

BUPPRT = 1 BUPCTL0 register.
SetNote the VBATEN bit and enable the battery backup

VBATEN = 1
function operation.
Stabilization wait time count Count the wait time (500 µs) for stabilization of the
battery backup function by using the software.
Clear the BUPPRT bit, and disable read/write of the

BUPPRT = 0
BUPCTL0 register.
Note Write 1 after writing 0 to set the VBATEN bit to 1.
Figure 30-8. Procedure for Setting Battery Backup Function Stop
Set the BUPPRT bit, and enable read/write of the

BUPPRT = 1
BUPCTL0 register.
ClearNote the VBATEN bit, and stop the battery

VBATEN = 0
backup function operation.
Clear the BUPPRT bit, and disable read/write of

BUPPRT = 0
the BUPCTL0 register.
Note Write 0 after writing 1 to clear the VBATEN bit to 0.
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30.3.2 Using the battery backup function

When power supply switching is performed with hardware (VBATEN = 1 and VBATSEL = 0), the following phenomena
occur due to sudden fluctuations of the internal power supply when the supply voltage from the VDD pin becomes lower
than the detection voltage (VDETBAT1) and the internal power supply is switched from VDD supply to VBAT supply, or when
the VDD voltage recovers to the detection voltage (VDETBAT2) or higher while the power is supplied from the VBAT pin and
the internal power supply is switched from VBAT supply to VDD supply. This also applies when power supply switching is
performed with software (VBATSEL = 0 to 1, or VBATSEL = 1 to 0).
<1> High-speed on-chip oscillator clock (fIH) may change its frequency or stop.
<2> Instructions may not be read out correctly at the moment of power supply switching when HS (high-speed main)
mode is used.
When using the battery backup function to prevent the CPU from operating with the high-speed on-chip oscillator clock
when power supply switching occurs and prevent readout of the flash memory in HS (high-speed main) mode when power
supply switching occurs, make sure to use it as described below.
<1> Power supply switching with software (VBATSEL)

Figure 30-9 shows the operation when power supply switching is performed with software (VBATSEL).
Power failure
Perform power failure detection by using a voltage detection interrupt (INTLVDVDD) of the VDD pin, and switch
the internal power supply to the VBAT pin supply by using the setting procedure in Figure 30-10 before power
supply switching by the battery backup circuit occurs.
In battery backup mode (VBAT pin supply)

Operation is available according to Table 30-1.
Power recovery
Perform power recovery detection by using a voltage detection interrupt (INTLVDVDD) of the VDD pin, and
switch the internal power supply to the VDD pin supply by using the setting procedure in Figure 30-10.
Cautions 1. When VDD > 4.0 V and VBAT < 2.4 V, or VBAT > 4.0 V and VDD < 2.4 V, power supply switching by
rewriting VBATSEL is prohibited.
2. When voltage over VBAT +0.3 V is applied to the VDD system ports (P20 to P25, P121, P122,
P137, P150 to P152) when VBATSEL = 1, through current is generated for I/O protection in the
path as shown in Figure 30-11.
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Figure 30-9. Power Supply Switching Operation with Software (VBATSEL)
VDD
VBAT
VLVDVDD
VSS
Internal VDD
VDD potential
VBAT potential
VSS
Power supply
connection VDD pin supply VBAT pin supply VDD pin supply
INTLVDVDD
VBATSEL
CSS
Sub-clock Main clock Main clock Sub-clock
Main clock operation STOP STOP Main clock operation
CPU operation operation operation operation
Main clock
operation
RTCIC0
Figure 30-10. Setting Procedure for Power Supply Switching with Software (VBATSEL)
INTLVDVDD
interrupt generation
LVDVDDF = 1?
No
Yes
Power failure Power recovery
Stop the peripheral functions to be
Peripheral functions stopped
stopped in battery backup mode
CSS = 1 Sw itch to sub-system clock CSS = 1 Sw itch to sub-system clock
CLS = 1? CLS = 1?
No No
Yes Yes
BUPPRT = 1 Enable w riting to BUPCTL0 register
BUPPRT = 1 Enable w riting to BUPCTL0 register
VBATSEL = 0 Set VBATSEL bit to sw itch to sw itch to VBAT

pin supply VBATSEL = 1 Clear VBATSEL bit to sw itch to switch to V DD
VBATSEL = 1 VBATSEL = 0 pin supply
BUPPRT = 0 Disable w riting to BUPCTL0 register BUPPRT = 0 Disable w riting to BUPCTL0 register
Wait 500 μs for pow er supply stability until the Wait 500 μs for pow er supply stability until the
Wait for pow er supply stability internal pow er supply is switched to VBAT Wait for pow er supply stability internal pow er supply is switched to V DD
CSS=0 Sw itch to main system clock CSS = 0 Sw itch to main system clock
CLS = 0? CLS = 0?
No No
Yes Yes
CPU operating w ith VBAT Sw itch to battery backup mode operation CPU operating w ith V DD
pin supply Sw itch to normal operation
pin supply
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Figure 30-11. Conditions for Follow-through Current Generation When VBATSEL = 1
I/O power supply (EVDD system)

3.3 V EVDD
Pxx
I/O power supply (VDD system)

2.5 V
PxxNote
VDD
2.5 V 3.3 V
Internal power supply (internal VDD)
ΔΣ A/D converter power supply (AVDD)
VBAT
VBATSEL = 1 2.5 V
Note VDD power supply I/O (P20 to P25, P121, P122, P137, P150 to P152)
<2> Power supply switching with hardware (VBATSEL = 0)

Figure 30-12 shows the operation when power supply switching is performed with hardware.
Power failure
Perform power failure detection by using a voltage detection interrupt (INTLVDVDD) of the VDD pin, and switch
to sub-system clock operation by using the procedure in Figure 30-13 before power supply switching by the
battery backup circuit occurs.

Operation is available only with the sub-system clock or in HALT. Operation with the main system clock is
prohibited. When operation with the main system clock is required in battery backup mode, perform power
supply switching by software (VBATSEL).
Power recovery
switch to main system clock operation by using the procedure in Figure 30-13.
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Figure 30-12. Power Supply Switching Operation with Hardware (VBATSEL = 0)
VDD
VBAT
VLVDVDD
VDETBAT2
VDETBAT1
VSS
Internal VDD
VDD potential
VBAT potential
VSS
Power supply VDD pin supply VBAT pin supply VDD pin supply
connection
VBATCMPM
INTLVDVDD
CSS
Sub-clock Sub-clock Sub-clock
Main clock operation Sub-clock HALT Sub-clock HALT Main clock operation
CPU operation operation operation
RTCIC0
Figure 30-13. Setting Procedure for Power Supply Switching with Hardware
INTLVDVDD
LVDVDDF = 1?
No
Yes
Peripheral functions stopped stopped in battery backup mode
CSS = 0 Sw itch to main system clock

CSS = 1 Sw itch to sub-system clock
CLS = 1? CLS = 0?
No No
Yes Yes
CPU operating w ith VBAT Sw itch to battery backup mode operation CPU operating w ith V DD
Sw itch to normal operation
pin supply pin supply
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<3> Stopping (only independent power supply RTC operates) in battery backup mode
Figure 30-14 shows the operation when only the independent power supply RTC operates and the CPU maintains
the STOP state in battery backup mode.
Power failure
Perform power failure detection by using a voltage detection interrupt (INTLVDVDD) of the VDD pin, and
transition to STOP mode before power supply switching by the battery backup circuit occurs.

Put the system in the STOP state. Clearing of STOP due to any cause other than a voltage detection interrupt
(INTLVDVDD) of the VDD pin is prohibited.
Power recovery
clear STOP.
Caution During power recovery, make sure to keep the power supply rising slope at maximum of 0.06 V/ms.
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Figure 30-14. Operation When the CPU can Maintain the STOP State in Battery Backup Mode
VDD
VBAT
VLVDVDD
VDETBAT2
VDETBAT1
VSS
Internal VDD
VDD potential
VBAT potential
VSS
Power supply VDD pin supply VBAT pin supply VDD pin supply
connection
VBATCMPM
INTLVDVDD
Main clock operation STOP Main clock operation

CPU
Figure 30-15. Setting Procedure When the CPU can Maintain the STOP State in Battery Backup Mode
INTLVDVDD
LVDVDDF = 1?
No
Yes
Peripheral functions stopped stopped in battery backup mode
STOP command Transition to STOP

mode
STOP mode w ith VBAT * Maintain the STOP state in battery CPU operating w ith V DD
backup mode. pin supply Switch to normal operation
pin supply
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30.4 Usage Notes
(1) When not using the battery backup function, connect the VBAT and Vss pins to the same potential.
(2) Setting VBATSEL = 1 is prohibited when VDD > 4.0 V and VBAT < 2.4 V, or VBAT > 4.0 V and VDD < 2.4 V.
(3) Be sure VBAT does not drop below 1.9 V when VBATSEL = 1.
(4) Do not set VBATEN and VBATSEL at the same time.
(5) Do not set VBATEN to 0 while VBATSEL is 1.
(6) For details about the power rising and falling slopes, see CHAPTER 41 ELECTRICAL SPECIFICATIONS.
(7) The self-programming function cannot be used when the internal power is supplied from the VBAT pin.
(8) When switching the power supply by hardware (VBATEN = 1, VBATSEL = 0), disable the input buffer with the
GDIDIS register (GDIDIS = 01H) to prevent leak current at the EVDD port pin when the power is switched to VBAT.
(9) When switching the power supply by hardware (VBATEN = 1, VBATSEL = 0), input signal must be designed so
that it does not exceed the EVDD voltage because the input buffer of the EVDD port pin is controlled by the EVDD
voltage when the power is switched to VBAT.
(10) The I/O buffer that is driven by the internal VDD power is operable in the battery backup mode. However, the
internal VDD voltage is lowered when the I/O outputs the large current. Therefore, extreme care must be taken
when designing so that the VDD I/O does not output the high-level current in the battery backup mode as much as
possible.
Drive the I/O in the battery backup mode if required according to the following procedure.
● When using the internal VDD I/O, control it only by the combination of the current draw by the low-level output
and the external pull-up by the Hi-Z output.
● Connect the diode ORings of the VBAT and VDD pins to the EVDD pin to use EVDD I/O after backing up the
VDD power by the backup power supply voltage that was connected to the VBAT pin when shutting down the
VDD power.
(11) When VBATEN is set to 1, use of the LV mode is forbidden.
(12) Set the product operation mode (HS/LS/LV/LP) depending on the internal VDD power source setting (VBATEN and
VBATSEL) and internal VDD voltage status.
Internal Power Supply Voltage Operating Voltage Range

Source
VDD pin HS mode: 2.1 V to 5.5 V
LS mode: 1.9 V to 5.5 V
LP mode: 1.9 V to 5.5 V
LV mode: 1.7 V to 5.5 V
VBAT pin HS mode: 2.1 V to 5.5 V
LS mode: 1.9 V to 5.5 V
LP mode: 1.9 V to 5.5 V
LV mode: Setting prohibited
(13) Before switching of the voltage supply, check and set supply voltage that is suitable for the operation mode of each
product.
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RL78/I1C CHAPTER 31 OSCILLATION STOP DETECTOR
CHAPTER 31 OSCILLATION STOP DETECTOR
31.1 Functions of Oscillation Stop Detector
The oscillation stop detection circuit monitors the sub clock (fSx) operating status with a low-speed on-chip oscillator
clock (fIL). If it detects that operation is stopped longer than a predefined interval, it assumes that an XT1 oscillator circuit
error has occurred and outputs an oscillation stop interrupt signal.
When the system is reset, operation of the oscillation stop detector must be enabled by software after the reset period
ends.
Operation of the oscillation stop detector is stopped by software. Or, oscillation stop detection operation is stopped by
reset from the RESET pin or internal reset due to execution of an invalid instructionNote. Furthermore, after a reset, enable
oscillation stop detection operation with software.
Note Occurs when instruction code for FFH is executed.

Reset due to invalid instruction does not occur during emulation with in-circuit emulator or on-chip debug
emulator.
The period used by the oscillation stop detector to judge that oscillation is stopped (oscillation stop judgment time) can
be set by using the OSDCCMP11 to OSDCCMP0 bits of the oscillation stop detection control register (OSDC).
Oscillation stop judgment time = Low-speed on-chip oscillator clock (fIL) cycle × ((value of OSDCCMP11 to OSDCCMP0)
+ 1)
● OSDCCMP11 to OSDCCMP0 = 003H: 232 µs (MIN.), 267 µs (TYP.), 314 µs (MAX.)
● OSDCCMP11 to OSDCCMP0 = FFFH: 237 ms (MIN.), 273 ms (TYP.), 322 ms (MAX.)
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31.2 Configuration of Oscillation Stop Detector
The oscillation stop detector includes the following hardware.
Table 31-1. Configuration of Oscillation Stop Detector
Item Configuration

Oscillation stop detection control register (OSDC)
Figure 31-1. Block Diagram of Oscillation Stop Detector
Clear Clear
fSX
Count clock
fIL
12-bit counter
Oscillation stop
Oscillation stop
detection interrupt signal
detection signal INTOSDC
output controller
Match
Clear
Oscillation stop
detection control OSDCE OSDCCMP11 to OSDCCMP0 OSDCEN Peripheral enable
register (OSDC) register 2 (PER2)
Internal bus
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31.3 Registers Used by Oscillation Stop Detector

This register is used to enable or disable clock supply to the peripheral hardware. Use this register to stop clock supply
to unused hardware to reduce power consumption and noise.
When using the oscillation stop detector, be sure to set bit 6 (OSDCEN) to 1.

Symbol <7> <6> 5 4 3 <2> 1 <0>
OSDCEN Control of oscillation stop detection circuit input clock supply

● SFR used by the oscillation stop detection circuit cannot be written. The read value is 00H.
However, the SFR is not initialized. Note
● SFR used by the oscillation stop detection circuit can be read and written.
Note To initialize the oscillation stop detection circuit and the SFR used by the oscillation stop detection
circuit, use bit 6 (OSDCRES) of PRR2.
Cautions 1. When using the oscillation stop detector, be sure to set the OSDCEN bit to 1. If OSDCEN
= 0, writing to a control register of the oscillation stop detector is ignored, and, even if
the register is read, only the default value is read.
2. Be sure to set bits 5 to 3 and 1 to “0”.
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To reset the oscillation stop detection circuit, be sure to set bit 6 (OSDCRES) to 1.

Symbol <7> <6> 5 4 3 <2> 1 0
OSDCRES Control resetting of the oscillation stop detection circuit
0 Releases the oscillation stop detection circuit from the reset state.
1 The oscillation stop detection circuit is in the reset state.
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Figure 31-4. Format of Subsystem clock supply option control register (OSMC)

Symbol <7> 6 5 <4> 3 2 1 0
RTCLPC Setting in STOP mode or HALT mode while sub clock (fSX) is selected as CPU clock
Note4
0 Enables supply of sub clock (fSX) to peripheral functions

1 Stops supply of sub clock (fSX) to peripheral functions other than the independent power
supply RTC, 12-bit interval timer,8-bit interval timer, clock output/buzzer output controller,
LCD controller/driver, oscillation stop detection circuit, and frequency measurement
circuit.
WUTMMCK0 Selection of the operating Selection of the count Selection of the output
clock for the 12-bit interval operation/stop trigger clock for clock for the clock
timer, 8-bit interval timer, the frequency measurement output/buzzer output
LCD controller/driver, and circuit controller
frequency measurement
circuit
0 Sub clock (fSX) Sub clock (fSx) selected. Sub clock (fSX)
1 Low-speed on-chip oscillator Low-speed on-chip oscillator Clock output is
clock (fIL) Notes 2, 3, 6, 7 clock (fIL) selected Note 6 prohibited. Note 5
Notes 1. Be sure to set bits 0 to 3, 5, and 6 to 0.

3. Switching between the sub clock (fSX) and the low-speed on-chip oscillator clock (fIL) can be
enabled by the WUTMMCK0 bit only when all of the 12-bit interval timer, 8-bit interval timer,
clock output/buzzer output controller, LCD controller/driver, and frequency measurement circuit
are stopped.
4. When the sub clock (fSX) is selected (SELLOSC = 0) by bit 0 (SELLOSC) of the CKSEL register
and RTCLPC is set to 1, the subsystem clock (fSUB) is stopped. However, when the low-speed
on-chip oscillator clock is selected (SELLOSC = 1) and RTCLPC is set to 1, the subsystem
clock (fSUB) is not stopped.
7. When the WUTMMCK0 bit is set to 1, internal voltage boosting cannot be used for the LCD
drive voltage generator of the LCD controller/driver.
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31.3.4 Oscillation stop detection control register (OSDC)

This register is used to control the oscillation stop detector. Use this register to start and stop operation of the
oscillation stop detector. This register can also be used to specify the oscillation stop judgment time.
Operation of the oscillation stop detector cannot be started while the OSDCE bit is 0.
The OSDC register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0FFFH.
Figure 31-5. Format of Oscillation Stop Detection Control Register (OSDC)
Address: F02D0H After reset: 0FFFH R/W

Symbol 15 14 13 12 11 10 9 8
OSDC OSDCE 0 0 0 OSDCCMP OSDCCMP OSDCCMP OSDCCMP

11 10 9 8
Symbol 7 6 5 4 3 2 1 0
OSDC OSDCCMP OSDCCMP OSDCCMP OSDCCMP OSDCCMP OSDCCMP OSDCCMP OSDCCMP

7 6 5 4 3 2 1 0
OSDCE Control of oscillation stop detector operation
0 Stop operation of the oscillation stop detector.

1 Start operation of the oscillation stop detector.
OSDCCMP11 to
Oscillation stop judgment time
OSDCCMP0
000H Setting prohibited

...
002H
003H These bits specify the oscillation stop judgment time.
... It is judged that oscillation has stopped when oscillation has been stopped for (A-2) to
FFFH (A+1) clock cycles, where A refers to the time specified by these bits.
Oscillation stop judgment time = Low-speed on-chip oscillator clock (fIL) cycle ×
((value of OSDCCMP11 to OSDCCMP0) + 1)
Cautions 1. Be sure to set the OSDCE bit to “0” (to stop operation of the oscillation stop detector) before
changing the setting of the OSDCCMP11 to OSDCCMP0 bits.
2. The oscillation stop detector stops oscillation stop detection by setting the OSDCE bit to 0 by
software or by reset from the RESET pin or internal reset due to execution of an invalid
instructionNote.
Furthermore, since the oscillation of XT1 oscillator clock is also stopped with an internal reset,
after a reset, enable oscillation stop detection operation after resuming oscillation of the XT1
oscillation clock with software.
3. Be sure to set bits 14 to 12 to “0”.
Note Occurs when instruction code for FFH is executed.

Reset due to invalid instruction does not occur during emulation with in-circuit emulator or on-chip debug
emulator.
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31.4 Operation of Oscillation Stop Detector
31.4.1 How the oscillation stop detector operates
1. The sub clock (fSX) starts operating after the external reset ends.
2. A value is written to the oscillation stop detection control register (OSDC) and the oscillation stop detector starts
operating.
3. While the oscillation stop detector is operating, if the sub clock (fSX) stops oscillating continuously for a period equal
to the oscillation stop judgment time or longer, the oscillation stop detector outputs the oscillation stop detection
interrupt signal (INTOSDC).
Figure 31-6. Timing of Oscillation Stop Detection by Oscillation Stop Detector
Reset state
OSDCEN
OSDCE
fSX
12-bit counter
Oscillation stop
judgment timeNote
INTOSDC
Oscillation stop can be detected Oscillation stop

can be detected
Note It is judged that oscillation has stopped when oscillation has been stopped for (A-2) to (A+1) clock cycles, where
A refers to the time specified by these bits.
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31.5 Cautions on Using the Oscillation Stop Detector
The oscillation stop detector should be used in conjunction with the watchdog timer.
Oscillation stop detection can be used under either of the following conditions:
● When bit 0 (WDSTBYON) and bit 4 (WDTON) of the option byte (000C0H) are set to 1 and bit 4 (WUTMMCK0) of the
OSMC register is set to 0
● When bit 4 (WUTMMCK0) of the OSMC register is set to 1
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RL78/I1C CHAPTER 32 SAFETY FUNCTIONS
CHAPTER 32 SAFETY FUNCTIONS
32.1 Overview of Safety Functions
The following safety functions are provided in the RL78/I1C to comply with the IEC60730 and IEC61508 safety
standards.
These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is
detected.
(1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC)
This detects data errors in the flash memory by performing CRC operations.
Two CRC functions are provided in the RL78/I1C that can be used according to the application or purpose of use.
● High-speed CRC: The CPU can be stopped and a high-speed check executed on its entire code flash
memory area during the initialization routine.
● General CRC: This can be used for checking various data in addition to the code flash memory area while
the CPU is running.
(2) RAM parity error detection function

This detects parity errors when the RAM is read as data.
(3) RAM guard function

This prevents RAM data from being rewritten when the CPU freezes.
(4) SFR guard function

This prevents SFRs from being rewritten when the CPU freezes.
(5) Invalid memory access detection function

This detects illegal accesses to invalid memory areas (such as areas where no memory is allocated and areas to
which access is restricted).
(6) Frequency detection function

This function allows a self-check of the CPU/peripheral hardware clock frequencies using the timer array unit.
(7) A/D test function

This is used to perform a self-check of the A/D converter by performing A/D conversion of the A/D converter’s
positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and
internal reference voltage.
(8) Digital output signal level detection function for I/O pins
When the I/O pins are output mode, the output level of the pin can be read.
Remark For usage examples of the safety functions complying with the IEC60730 safety standards, refer to RL78
MCU series IEC60730/60335 self test library application note (R01AN1062, R01AN1296).
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32.2 Registers Used by Safety Functions
The safety functions use the following registers for each function.
Register Each Function of Safety Function
● Flash memory CRC control register (CRC0CTL) Flash memory CRC operation function
● Flash memory CRC operation result register (PGCRCL) (high-speed CRC)
● CRC input register (CRCIN) CRC operation function

● CRC data register (CRCD) (general-purpose CRC)
● RAM parity error control register (RPECTL) RAM parity error detection function
● Invalid memory access detection control register (IAWCTL) RAM guard function
SFR guard function
Invalid memory access detection function
● Timer input select register 0 (TIS0) Frequency detection function
● A/D test register (ADTES) A/D test function
● Port mode select register (PMS) Digital output signal level detection function for I/O
ports
The content of each register is described in 32.3 Operation of Safety Functions.
32.3 Operation of Safety Functions
32.3.1 Flash memory CRC operation function (high-speed CRC)

The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The
high-speed CRC provided in the RL78/I1C can be used to check the entire code flash memory area during the initialization
routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of
the main system clock.
The high-speed CRC performs an operation by reading 32-bit data per clock from the flash memory while stopping the
CPU. This function therefore can finish a check in a shorter time (for example, 341 µs@24 MHz with 32 KB flash memory).
The CRC generator polynomial used complies with “X16 + X12 + X5 + 1” of CRC-16-CCITT.
The high-speed CRC operates in MSB first order from bit 31 to bit 0.
Caution The CRC operation result might differ during on-chip debugging because the monitor program is
allocated.
Remark The operation result is different between the high-speed CRC and the general CRC, because the general
CRC operates in LSB first order.
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32.3.1.1 Flash memory CRC control register (CRC0CTL)

This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range.
The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 32-1. Format of Flash Memory CRC Control Register (CRC0CTL)

Symbol <7> 6 5 4 3 2 1 0
Note 1 Note 2
CRC0CTL CRC0EN 0 0 0 FEA3 FEA2 FEA1 FEA0
CRC0EN Control of CRC ALU operation
0 Stop the operation.

1 Start the operation according to HALT instruction execution.
FEA3Note 1 FEA2Note 2 FEA1 FEA0 High-speed CRC operation range

0 0 0 0 0000H to 3FFBH (16 K-4 bytes)
0 0 0 1 0000H to 7FFBH (32 K-4 bytes)
0 0 1 0 0000H to BFFBH (48 K-4 bytes)
0 0 1 1 0000H to FFFBH (64 K-4 bytes)
0 1 0 0 00000H to 13FFBH (80 K-4 bytes)
0 1 0 1 00000H to 17FFBH (96 K-4 bytes)
0 1 1 0 00000H to 1BFFBH (112 K-4 bytes)
0 1 1 1 00000H to 1FFFBH (128 K-4 bytes)
1 0 0 0 00000H to 23FFBH (144 K-4 bytes)
1 0 0 1 00000H to 27FFBH (160 K-4 bytes)
1 0 1 0 00000H to 2BFFBH (176 K-4 bytes)
1 0 1 1 00000H to 2FFFBH (192 K-4 bytes)
1 1 0 0 00000H to 33FFBH (208 K-4 bytes)
1 1 0 1 00000H to 37FFBH (224 K-4 bytes)
1 1 1 0 00000H to 3BFFBH (240 K-4 bytes)
1 1 1 1 00000H to 3FFFBH (256 K-4 bytes)
Notes 1. For R5F10NMG, R5F10NLG, R5F10NME, and R5F10NLE be sure to set the FEA3 bit to 0.
2. For products with 64 Kbytes of code flash memory (R5F10NME, R5F10NLE), be sure to set the FEA2 bit
to 0.
Remark Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash
memory. Note that the operation range will thereby be reduced by 4 bytes.
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32.3.1.2 Flash memory CRC operation result register (PGCRCL)

This register is used to store the high-speed CRC operation results.
The PGCRCL register can be set by a 16-bit memory manipulation instruction.
Figure 32-2. Format of Flash Memory CRC Operation Result Register (PGCRCL)

Symbol 15 14 13 12 11 10 9 8
PGCRCL PGCRC15 PGCRC14 PGCRC13 PGCRC12 PGCRC11 PGCRC10 PGCRC9 PGCRC8
7 6 5 4 3 2 1 0
PGCRC7 PGCRC6 PGCRC5 PGCRC4 PGCRC3 PGCRC2 PGCRC1 PGCRC0
PGCRC15 to 0 High-speed CRC operation results
0000H to FFFFH Store the high-speed CRC operation results.
Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 32-3 shows the flowchart of flash memory CRC operation function (high-speed CRC).
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<Operation flow>
Figure 32-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC)
Start ; Store the expected CRC operation result

; value in the lowest 4 bytes.
Set FEA5 to FEA0 bits

; Set CRC operation range.
Copy HALT and RET instructions to ; Copy the HALT and RET instructions to the
; RAM to execute in the RAM.
RAM, initialize 10 bytes
; Initialize the 10 bytes after the RET instruction.
All xxMKx = 1 ; Masks all interrupt
CRC0EN = 1
; Enable CRC operation
PGCRCL = 0000H
; Initialize the CRC operation result register
; Call the address of the HALT instruction

Execute CALL instruction ; copied to the RAM.
; CRC operation starts by HALT instruction

Execute HALT instruction. ; execution
CRC operation
completed? No
Yes
; When the CRC operation is complete, the HALT
Execute RET instruction. ; mode is released and control is returned from RAM
CRC0EN = 0 ; Prohibit CRC operation
Read the value of PGCRCL. ; Read CRC operation result

; Compare the value with the stored expected
; value.
Compare the value with
the expected CRC value. Not match
Match Abnormal complete
Correctly complete
Cautions 1. The CRC operation is executed only on the code flash.

2. Store the expected CRC operation value in the area below the operation range in the code flash.
3. The CRC operation is enabled by executing the HALT instruction in the RAM area.
Be sure to execute the HALT instruction in RAM area.
The expected CRC value can be calculated by using the Integrated Development Environment CubeSuite+. See
Integrated Development Environment CubeSuite+ user’s manual for details.
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32.3.2 CRC operation function (general-purpose CRC)

In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the
CPU is operating.
In the RL78/I1C, a general CRC operation can be executed as a peripheral function while the CPU is operating. The
general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked
can be specified by using software (a user-created program). CRC calculation function in the HALT mode can be used
only during the DTC transmission.
The general CRC operation can be executed in the main system clock operation mode as well as the subsystem clock
operation mode.
The CRC generator polynomial used is “X16 + X12 + X5 + 1” of CRC-16-CCITT. The data to be input is inverted in bit
order and then calculated to allow for LSB-first communication. For example, if the data 12345678H is sent from the LSB,
values are written to the CRCIN register in the order of 78H, 56H, 34H, and 12H, enabling a value of 08F6H to be
obtained from the CRCD register. This is the result obtained by executing a CRC operation on the bit rows shown below,
which consist of the data 12345678H inverted in bit order.
CRCIN setting data 78H 56H 34H 12H

Bit representation data 0111 1000 0101 0110 0011 0100 0001 0010
Bit reverse
Bit reverse data 0001 1110 0110 1010 0010 1100 0100 1000
Operation with polynomial
Result data 0110 1111 0001 0000
Bit reverse
CRCD data 0000 1000 1111 0110 Obtained result

(08F6H)
Caution Because the debugger rewrites the software break setting line to a break instruction during
program execution, the CRC operation result differs if a software break is set in the CRC operation
target area.
32.3.2.1 CRC input register (CRCIN)

CRCIN register is an 8-bit register that is used to set the CRC operation data of general-purpose CRC.
The possible setting range is 00H to FFH.
The CRCIN register can be set by an 8-bit memory manipulation instruction.
Figure 32-4. Format of CRC Input Register (CRCIN)
Address: FFFACH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
CRCIN
Bits 7 to 0 Function
00H to FFH Data input.
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32.3.2.2 CRC data register (CRCD)

This register is used to store the CRC operation result of the general-purpose CRC.
The setting range is 0000H to FFFFH.
After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC
operation result is stored to the CRCD register.
The CRCD register can be set by a 16-bit memory manipulation instruction.
Figure 32-5. Format of CRC Data Register (CRCD)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCD
Cautions 1. Read the value written to CRCD register before writing to CRCIN register.
2. If conflict between writing and storing operation result to CRCD register occurs, the writing is
ignored.
<Operation flow>
Figure 32-6. CRC Operation Function (General-purpose CRC)
START
; Store the start and end addresses in a

Specify the start and end addresses
; general-purpose register.
Write CRCD register to 0000H ; Initialize CRCD register
Read data ; Read 8-bit data of corresponding address
; Execute CRC calculation for 8-bit data

Store data to CRCIN register
Address+1
Last address?
Yes
No
1 clock wait (fCLK)
Read CRCD register ; Get CRC result
; Compare the value

End ; with the stored
; expected value and
; make sure that the
; values match.
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32.3.3 RAM parity error detection function

The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data
in the RL78/I1C’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written,
and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error
occurs.
32.3.3.1 RAM parity error control register (RPECTL)

This register is used to control parity error generation check bit and reset generation due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 32-7. Format of RAM Parity Error Control Register (RPECTL)

Symbol <7> 6 5 4 3 2 1 <0>
RPECTL RPERDIS 0 0 0 0 0 0 RPEF
RPERDIS Parity error reset mask flag
0 Enable parity error resets.

1 Disable parity error resets.
RPEF Parity error status flag
0 No parity error has occurred.

1 A parity error has occurred.
Caution The parity bit is appended when data is written, and the parity is checked when the data is read.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas
where data access is to proceed before reading data.
The RL78’s CPU executes look-ahead due to the pipeline operation, the CPU might read an
uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM
area + 10 bytes when instructions are fetched from RAM areas.
Remarks 1. The parity error reset is enabled by default (RPERDIS = 0).

2. Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error
occurs. If parity error resets are enabled (RPERDIS = 0) with RPEF set to 1, a parity error reset is
generated when the RPERDIS bit is cleared to 0.
3. The RPEF flag in the RPECTL register is set (1) when the RAM parity error occurs and cleared (0) by
writing 0 to it or by any reset source. When RPEF = 1, the value is retained even if RAM for which no
parity error has occurred is read.
4. The general registers are not included for RAM parity error detection.
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Figure 32-8. Flowchart of RAM Parity Check
Start of check
Note Yes
RPERF = 1
No
RPERDIS = 1 Disable parity error reset.
Check RAM.
Check RAM. Read RAM.
Yes
Parity error No RPEF = 1 Parity error
generated? generation
No checked
Yes
Enable parity
RPERDIS = 0
error reset.
Internal reset Normal RAM failure

generated operation processing
Note To check internal reset status using a RAM parity error, see CHAPTER 27 RESET FUNCTION.
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32.3.4 RAM guard function

In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM
be protected, even if the CPU freezes.
This RAM guard function is used to protect data in the specified memory space.
If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can
be carried out as usual.
32.3.4.1 Invalid memory access detection control register (IAWCTL)

This register is used to control the detection of invalid memory access and RAM/SFR guard function.
GRAM1 and GRAM0 bits are used in RAM guard function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Figure 32-9. Format of Invalid Memory Access Detection Control Register (IAWCTL)

Symbol 7 6 5 4 3 2 1 0
IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC
GRAM1 GRAM0 RAM guard spaceNote
0 0 Disabled. RAM can be written to.

0 1 The 128 bytes of space starting at the start address in the RAM
Note The RAM start address differs depending on the size of the RAM provided with the product.
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32.3.5 SFR guard function

In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from
being overwritten, even if the CPU freezes.
This SFR guard function is used to protect data in the control registers used by the port function, interrupt function,
clock control function, voltage detection function, and RAM parity error detection function.
If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be
carried out as usual.

GPORT, GINT and GCSC bits are used in SFR guard function.

Symbol 7 6 5 4 3 2 1 0
GPORT Control registers of port function guard
0 Disabled. Control registers of port function can be read or written to.

1 Enabled. Writing to control registers of port function is disabled. Reading is enabled.
[Guarded SFR] PMxx, PUxx, PIMxx, POMxx, ADPC, PIOR, PFSEGxx, ISCLCDNote
GINT Registers of interrupt function guard
0 Disabled. Registers of interrupt function can be read or written to.

1 Enabled. Writing to registers of interrupt function is disabled. Reading is enabled.
[Guarded SFR] IFxx, MKxx, PRxx, EGPx, EGNx
GCSC Control registers of clock control function, voltage detector and RAM parity error detection function guard
0 Disabled. Control registers of clock control function, voltage detector and RAM parity error detection
function can be read or written to.
1 Enabled. Writing to control registers of clock control function, voltage detector and RAM parity error
detection function is disabled. Reading is enabled.
[Guarded SFR] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL, PRRx (x = 0, 1),
PMMC, MOCODIV, FMCKS, DSCCTL, MCKC
Note Pxx (Port register) is not guarded.
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32.3.6 Invalid memory access detection function

The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly.
The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is
accessed.
The illegal memory access detection function applies to the areas indicated by NG in Figure 32-11.
Figure 32-11. Invalid Access Detection Area
Possibility access
Fetching
instructions
Read Write (execute)
FFFFFH
256 byte
NG
FFF00H
32 byte OK
F F E E 0H
FFEDFH
RAMNote
OK
zzzzzH
Mirror
OK
F20 00H
Reserved NG NG
F17FFH
Data flash memory
F 1 0 0 0H
F0FFFH
Reserved OK
F 0 8 0 0H
F07FFH
OK
Special function register (2nd SFR) NG
2 Kbyte
F 0 0 0 0H
E F F F FH
OK
EE000H
EDFFFH
NG NG NG
Reserved
yyyyyH
xxxxxH
OK OK
Flash memory Note
00000H
Note Code flash memory and RAM address of each product are as follows.
Products Code flash memory RAM Detected lowest address
(00000H to xxxxxH) (zzzzzH to FFEFFH) for read/instruction fetch
(execution) (yyyyyH)
R5F10NME, R5F10NLE 65536 × 8 bits (00000H to 0FFFFH) 6144 × 8 bits (FE700H to FFEFFH) 10000H
R5F10NPG, R5F10NMG, 131072 × 8 bits (00000H to 1FFFFH) 8192 × 8 bits (FDF00H to FFEFFH) 20000H
R5F10NLG
R5F10NMJ, R5F10NPJ 262144 × 8 bits (00000H to 3FFFFH) 16384 × 8 bits (FBF00H to FFEFFH) 40000H
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IAWEN bit is used in invalid memory access detection function.

Symbol 7 6 5 4 3 2 1 0
IAWENNote Control of invalid memory access detection
0 Disable the detection of invalid memory access.

1 Enable the detection of invalid memory access.
Note Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1.
Remark By specifying WDTON = 1 (watchdog timer operation enable) for the option byte (000C0H), the invalid
memory access function is enabled even IAWEN = 0.
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32.3.7 Frequency detection function

The IEC60730 standard mandates checking that the oscillation frequency is correct.
By using the CPU/peripheral hardware clock frequency (fCLK) and measuring the pulse width of the input signal to
channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is
correct can be determined. Note that, however, if one or both clock operations are stopped, the proportional relationship
between the clocks cannot be determined.
<Clocks to be compared>
<1> CPU/peripheral hardware clock frequency (fCLK):
● High-speed on-chip oscillator clock (fIH)
● High-speed system clock (fMX)
<2> Input to channel 5 of the timer array unit
● Timer input to channel 5 (TI05)
● Low-speed on-chip oscillator clock (fIL: 15 kHz (typ.))
● Middle-speed on-chip oscillator clock (fIM)
● Subsystem clock (fSUB)
Figure 32-13. Configuration of Frequency Detection Function
High-speed on-chip
oscillator clock (fIH)
fCLK
Selector
High-speed system
clock (fMX)
<1>
TI05
Channel 5 of timer
Selector
<2>
array unit 0
Subsystem clock (fSUB) (TAU0)
oscillator clock (fIM)
fIL Watchdog timer

Low-speed on-chip
oscillator clock (15 kHz (typ.)) (WDT)
If input pulse interval measurement results in an abnormal value, it can be concluded that the clock frequency is
abnormal.
For how to execute input pulse interval measurement, see 8.8.3 Operation as input pulse interval measurement.
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32.3.7.1 Timer input select register 0 (TIS0)

The TIS0 register is used to select the timer input of channels 0, 1, 5, 6, and 7 of the timer array unit 0 (TAU0).
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Figure 32-14. Format of Timer Input Select Register 0 (TIS0)

Symbol 7 6 5 4 3 2 1 0

0 1 1 Middle-speed on-chip oscillator clock (fIM)
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32.3.8 A/D test function

The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D
converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference
voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage. For details of
the check method, see Safety Function (A/D Test) Application Note (R01AN0955).
The analog multiplexer can be checked using the following procedure.
<1> Select the ANIx pin for A/D conversion using the ADTES register (ADTES1 = 0, ADTES0 = 0).
<2> Perform A/D conversion for the ANIx pin (conversion result 1-1).
<3> Select the A/D converter’s negative reference voltage for A/D conversion using the ADTES register (ADTES1 = 1,
ADTES0 = 0)
<4> Perform A/D conversion of the negative reference voltage of the A/D converter (conversion result 2-1).
<7> Select the A/D converter’s positive reference voltage for A/D conversion using the ADTES register (ADTES1 = 1,
ADTES0 = 1)
<8> Perform A/D conversion of the positive reference voltage of the A/D converter (conversion result 2-2).
<11> Check that the conversion results 1-1, 1-2, and 1-3 are equal.
<12> Check that the A/D conversion result 2-1 is all zero and conversion result 2-2 is all one.
Using the procedure above can confirm that the analog multiplexer is selected and all wiring is connected.
Remarks 1. If the analog input voltage is variable during A/D conversion in steps <1> to <10> above, use another
method to check the analog multiplexer.
2. The conversion results might contain an error. Consider an appropriate level of error when comparing
the conversion results.
Figure 32-15. Configuration of A/D Test Function
ADISS
ADS4 to ADS0
ANI0/AVREFP
ANI1/AVREFM
ANIxx ADTES1, ADTES0
ANIxx
Temperature
sensor 2Note
Internal reference
voltage (1.45 V)Note
Positive reference voltage
of A/D converter
VDD
ADREFP1, A/D converter

ADREFP0
Negative reference voltage

VSS of A/D converter
ADREFM
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32.3.8.1 A/D test register (ADTES)

This register is used to select the A/D converter’s positive reference voltage, A/D converter’s negative reference
voltage, analog input channel (ANIxx), temperature sensor output voltage, or internal reference voltage (1.45 V) as
the target of A/D conversion.
When using the A/D test function, specify the following settings:
● Select negative reference voltage as the target of A/D conversion for zero-scale measurement.
● Select positive reference voltage as the target of A/D conversion for full-scale measurement.
The ADTES register can be set by an 8-bit memory manipulation instruction.

Figure 32-16. Format of A/D Test Register (ADTES)

Symbol 7 6 5 4 3 2 1 0
ADTES 0 0 0 0 0 0 ADTES1 ADTES0
ADTES1 ADTES0 A/D conversion target
0 0 ANIxx/temperature sensor output voltageNote/internal reference voltage (1.45 V)Note (This

is specified using the analog input channel specification register (ADS).)
1 0 Negative reference voltage (selected with the ADREFM bit in ADM2)
1 1 Positive reference voltage (selected with the ADREFP1 or ADREFP0 bit in ADM2)
Note Temperature sensor output voltage/internal reference voltage (1.45 V) can be used only in HS (high-
speed main) mode.
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32.3.8.2 Analog input channel specification register (ADS)

This register specifies the input channel of the analog voltage to be A/D converted.
Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference
voltage (1.45 V).
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 32-17. Format of Analog Input Channel Specification Register (ADS)

Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0
ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input Input source
channel
0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin
0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin
0 0 0 0 1 0 ANI2 P22/ANI2 pin
0 0 0 0 1 1 ANI3 P23/ANI3 pin
0 0 0 1 0 0 ANI4 P24/ANI4 pin
0 0 0 1 0 1 ANI5 P25/ANI5 pin
0 1 1 1 0 1 – Temperature sensor 2
output voltageNote
1 0 0 0 0 1 – Internal reference voltage
(1.45 V)Note

2. Select input mode for the ports which are set to analog input with the ADPC register, using the
port mode register 2 (PM2).
3. Do not use the ADS register to set the pins which should be set as digital I/O with the A/D port
configuration register (ADPC).
4. Only rewrite the value of the ADISS bit while conversion operation is stopped (ADCE = 0, ADCS =
0).
5. If using AVREFP as the positive reference voltage of the A/D converter, do not select ANI0 as an
6. If using AVREFM as the negative reference voltage of the A/D converter, do not select ANI1 as an
7. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the positive
reference voltage. In addition, the first conversion result obtained after setting ADISS to 1 is not
available.
8. If a transition is made to STOP mode or a transition is made to HALT mode during CPU operation
with subsystem clock, do not set ADISS to 1. When ADISS is 1, the A/D converter reference
voltage current (IADREF) shown in 41.3.2 Supply current characteristics is added.
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32.3.9 Digital output signal level detection function for I/O ports
In the IEC60730, it is required to check that the I/O function correctly operates.
By using the digital output signal level detection function for I/O pins, the digital output level of the pin can be read when
the pin is set to output mode.
32.3.9.1 Port mode select register (PMS)

This register is used to select the output level from output latch level or pin output level when the port is output mode
in which PMm bit of port mode register (PMm) is 0.
Figure 32-18. Format of Port Mode Select Register (PMS)
Address: F007BH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0
PMS 0 0 0 0 0 0 0 PMS0
PMS0 Method for selecting output level to be read when port is output mode (PMmn = 0)
0 Pmn register value is read.

1 Digital output level of the pin is read.
Remark m = 0 to 8, 12
n = 0 to 7
Cautions 1. While the PMS0 bit of the PMS register is “1”, do not change the value of the Px register
by using a read-modify instruction. To change the value of the Px register, use an 8-bit
2. PMS control cannot be used for the dedicated LCD pins and the input-only pins (P121 to
P124 and P137).
3. PMS control cannot be used for alternate-function pins being used as segment output
pins. (“L” is always read when this register is read.)
4. PMS control cannot be used for P61 and P60 when IICA0EN (bit 4 of the PER0 register) is
0.
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RL78/I1C CHAPTER 33 AES FUNCTIONS
CHAPTER 33 AES FUNCTIONS
33. 1 AES Functions
The RL78/I1C microcontrollers are provided with the AES function based on AES-GCM Standards, which is used in the
smart meter market, for enhanced security.
Feature overview
• Cipher modes of operation: GCM/ECB/CBC
• Encryption key length: 128/192/256 bits
• Number of interrupt sources: 2
• Interrupt source name: INTAES, INTAESF
For functional details, ask our sales representative.
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RL78/I1C CHAPTER 34 REGULATOR
CHAPTER 34 REGULATOR
34.1 Regulator Overview
The RL78/I1C contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the
regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Also, use a capacitor with good
characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
The regulator output voltage, see Table 34-1.
Table 34-1. Regulator Output Voltage Conditions
Mode Output Voltage Condition
LV (low-voltage main) mode 1.8 V —

LP (Low-power main) mode
LS (low-speed main) mode

HS (high-speed main) mode 1.8 V In STOP mode
When both the high-speed system clock (fMX) and the high-speed on-chip oscillator
clock (fIH) are stopped during CPU operation with the subsystem clock (fSUB)
When both the high-speed system clock (fMX) and the high-speed on-chip oscillator
clock (fIH) are stopped during the HALT mode when the CPU operation with the
subsystem clock (fSUB) has been set
2.1 V Other than above (include during OCD mode)Note
Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator
output voltage is kept at 2.1 V (not decline to 1.8 V).
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RL78/I1C CHAPTER 34 REGULATOR
34.2 Register Controlling Regulator
The following register is used to control the regulator.

34.2.1 Regulator mode control register (PMMC)

The PMMC register is an 8-bit register used to control the mode of the on-chip regulator.
Figure 34-1. Format of Regulator Mode Control Register (PMMC)

Symbol 7 <6> 5 4 3 2 1 0
PMMC 0 MCSEL 0 0 0 0 0 0
MCSEL Control of regulator mode
0 Normal setting
1 Low-power consumption setting
Cautions 1. Do not change the flash operation mode select register (FLMODE) when MCSEL is 1.
2. Do not set MCSEL to 1 in HS (high-speed main) mode and LV (low-voltage main) mode.
3. In LS (low-speed main) mode, transitions to the STOP mode are prohibited while MCSEL is 1.
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RL78/I1C CHAPTER 35 OPTION BYTE
CHAPTER 35 OPTION BYTE
35.1 Functions of Option Bytes
Addresses 000C0H to 000C3H of the flash memory of the RL78/I1C form an option byte area.
Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is
set. When using the product, be sure to set the following functions by using the option bytes. For bits for which no
function is assigned, do not change their initial values.
To use the boot swap operation during self programming, 000C0H to 000C3H are replaced by 010C0H to 010C3H.
Therefore, set the same values as 000C0H to 000C3H to 010C0H to 010C3H.
Caution The option bytes should always be set regardless of whether each function is used.
35.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)
(1) 000C0H/010C0H
O Operation of watchdog timer
● Enabling or disabling of counter operation
● Enabling or disabling of counter operation in the HALT or STOP mode
O Setting of overflow time of watchdog timer
O Setting of window open period of watchdog timer
O Setting of interval interrupt of watchdog timer
● Whether or not to use the interval interrupt is selectable.
Caution Set the same value as 000C0H to 010C0H when the boot swap operation is used because
000C0H is replaced by 010C0H.
(2) 000C1H/010C1H
O Setting of LVD operation mode
● Interrupt & reset mode.
● Reset mode.
● Interrupt mode.
● LVD off (by controlling the externally input reset signal on the RESET pin)
O Setting of LVD detection level (VLVDH, VLVDL, VLVD)
Cautions 1. After power is supplied, the reset state must be retained until the operating voltage
becomes in the range defined in 41.4 AC Characteristics. This is done by utilizing the
voltage detector or controlling the externally input reset signal. After the power supply is
turned off, this LSI should be placed in the STOP mode, or placed in the reset state by
utilizing the voltage detector or controlling the externally input reset signal, before the
voltage falls below the operating range. The range of operating voltage varies with the
setting of the user option byte (000C2H or 010C2H).
2. Set the same value as 000C1H to 010C1H when the boot swap operation is used because
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(3) 000C2H/010C2H
O Setting of flash operation mode
It should be set, depending on the main system clock frequency (fMAIN) and power supply (VDD) to be used.
● LV (low-voltage main) mode
● LS (low speed main) mode
● HS (high speed main) mode
O Setting of the frequency of the high-speed on-chip oscillator
● Select from 1 MHz to 24 MHz
35.1.2 On-chip debug option byte (000C3H/ 010C3H)
O Control of on-chip debug operation

● On-chip debug operation is disabled or enabled.
O Handling of data of flash memory in case of failure in on-chip debug security ID authentication
● Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication.
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35.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 35-1. Format of User Option Byte (000C0H/010C0H)
Address: 000C0H/010C0HNote 1
7 6 5 4 3 2 1 0
WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON
WDTINIT Use of interval interrupt of watchdog timer

0 Interval interrupt is not used.
1 Interval interrupt is generated when 75% + 1/2fIL of the overflow time is reached.
WINDOW1 WINDOW0 Watchdog timer window open periodNote 2

0 1 50%
1 0 75%Note 3
1 1 100%
WDTON Operation control of watchdog timer counter

0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time

(fIL = 17.25 kHz (MAX.))
0 0 0 26/fIL (3.71 ms)
0 0 1 27/fIL (7.42 ms)
0 1 0 28/fIL (14.84 ms)
0 1 1 29/fIL (29.68 ms)
1 0 0 211/fIL (118.72 ms)
1 0 1 213/fIL (474.89 ms)
1 1 0 214/fIL (949.79 ms)
1 1 1 216/fIL (3799.18 ms)
WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode)

0 Counter operation stopped in HALT/STOP modeNote 2
1 Counter operation enabled in HALT/STOP mode
Notes 1. Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
2. The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
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<R> Notes 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to
WDTE) must proceed outside the corresponding period from among those listed below, over which clearing
of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of
the watchdog timer is set).
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time Period over which clearing the
(fIL = 17.25 kHz (MAX.)) counter is prohibited when the
window open period is set to 75%
0 0 0 26/fIL (3.71 ms) 1.85 ms to 2.51 ms
0 0 1 27/fIL (7.42 ms) 3.71 ms to 5.02 ms
8
0 1 0 2 /fIL (14.84 ms) 7.42 ms to 10.04 ms
9
0 1 1 2 /fIL (29.68 ms) 14.84 ms to 20.08 ms
11
1 0 0 2 /fIL (118.72 ms) 56.36 ms to 80.32 ms
13
1 0 1 2 /fIL (474.89 ms) 237.44 ms to 321.26 ms
14
1 1 0 2 /fIL (949.79 ms) 474.89 ms to 642.51 ms
16
1 1 1 2 /fIL (3799.18 ms) 1899.59 ms to 2570.04 ms
Remark fIL: Low-speed on-chip oscillator clock frequency
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Figure 35-2. Format of User Option Byte (000C1H/010C1H) (1/2)
7 6 5 4 3 2 1 0
● LVD setting (interrupt & reset mode)

VLVDH VLVDL VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting
Rising Falling Falling LVIMDS1 LVIMDS0
edge edge edge
1.98 V 1.94 V 1.84 V 0 0 1 1 0 1 0
2.09 V 2.04 V 0 1
3.13 V 3.06 V 0 0
2.61 V 2.55 V 2.45 V 1 0 1 0
2.71 V 2.65 V 0 1
3.75 V 3.67 V 0 0
2.92 V 2.86 V 2.75 V 1 1 1 0
3.02 V 2.96 V 0 1
4.06 V 3.98 V 0 0
● LVD setting (reset mode)

1.77 V 1.73 V 0 0 0 1 0 1 1
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V 1 1 0 0
by 010C1H.
Caution Be sure to set bit 4 to “1”.
Remarks 1. For LVD setting, see 29.1 Functions of Voltage Detector.

2. The detection voltage is a typical value. For details, see 41.6.5 LVD circuit characteristics.
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Figure 35-2. Format of User Option Byte (000C1H/010C1H) (2/2)
7 6 5 4 3 2 1 0
● LVD setting (interrupt mode)

1.77 V 1.73 V 0 0 0 1 0 0 1
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V 1 1 0 0
● LVD off setting (use of external reset input via RESET pin)
– – 1 × × × × × 1
by 010C1H.
Cautions 1. Be sure to set bit 4 to “1”.

2. After power is supplied, the reset state must be retained until the operating voltage becomes in
the range defined in 41.4 AC Characteristics. This is done by utilizing the voltage detector or
controlling the externally input reset signal. After the power supply is turned off, this LSI
should be placed in the STOP mode, or placed in the reset state by utilizing the voltage detector
or controlling the externally input reset signal, before the voltage falls below the operating
range. The range of operating voltage varies with the setting of the user option byte (000C2H or
010C2H).

2. For LVD setting, see 29.1 Functions of Voltage Detector.
3. The detection voltage is a typical value. For details, see 41.6.5 LVD circuit characteristics.
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Figure 35-3. Format of Option Byte (000C2H/010C2H)
Address: 000C2H/010C2HNote 1
7 6 5 4 3 2 1 0
CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
CMODE1 CMODE0 Setting of flash operation mode

Operating Operating voltage
frequency range (fMAIN) range (VDD)
1 0 LS (low speed main) mode 1 to 8 MHz 1.9 to 5.5 V
1 1 HS (high speed main) mode 1 to 6 MHz 2.1 to 5.5 V
1 to 12 MHz 2.4 to 5.5 V
1 to 16 MHz 2.5 to 5.5 V
1 to 24 MHz 2.7 to 5.5 V
Note 2
1 to 32 MHz 2.8 to 5.5 V
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator clock (fIH)
0 0 0 0 24 MHzNote 2 Setting prohibitedNote 2
0 0 0 1 12 MHz 16 MHz
0 0 1 0 6 MHz 8 MHz
0 0 1 1 3 MHz 4 MHz
0 1 0 0 1.5 MHz 2 MHz
1 1 0 1 Setting prohibited 1 MHz
Notes 1. Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is
replaced by 010C2H.
2. When the PLL clock (32 MHz) is selected as the main system clock, select 24 MHz for the high-speed
on-chip oscillator clock.
3. This setting is prohibited when the high-speed on-chip oscillator clock (fIH) is selected as the operating
clock for the 24-bit ΔΣ A/D converter.
Cautions 1. Be sure to set bits 5 and 4 to 10B.

2. The ranges of operation frequency and operation voltage vary depending on the flash operation
mode. For details, see 41.4 AC Characteristics.
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35.3 Format of On-chip Debug Option Byte
The format of on-chip debug option byte is shown below.
Figure 35-4. Format of On-chip Debug Option Byte (000C3H/010C3H)
7 6 5 4 3 2 1 0
OCDENSET 0 0 0 0 1 0 OCDERSD
OCDENSET OCDERSD Control of on-chip debug operation

0 0 Disables on-chip debug operation.
1 0 Enables on-chip debugging.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
1 1 Enables on-chip debugging.
Does not erases data of flash memory in case of failures in authenticating on-chip
debug security ID.
by 010C3H.
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set bits 6 to 1 to 000010B.
Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become
unstable after the setting.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
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35.4 Setting of Option Byte
The user option byte and on-chip debug option byte can be set using the link option, in addition to describing to the
source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source,
as mentioned below.
A software description example of the option byte setting is shown below.
OPT CSEG OPT_BYTE

DB 36H ; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
; Overflow time of watchdog timer is 29/fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB 5AH ; Select 2.45 V for VLVDL
; Select rising edge 2.61 V, falling edge 2.55 V for VLVDH
; Select the interrupt & reset mode as the LVD operation mode
DB A3H ; Select the LS (low speed main) mode as the flash operation mode
and 3 MHz as the frequency of the high-speed on-chip oscillator
DB 85H ; Enables on-chip debug operation, does not erase flash memory
data when security ID authorization fails
When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 010C0H to 010C3H.
Describe to 010C0H to 010C3H, therefore, the same values as 000C0H to 000C3H as follows.
OPT2 CSEG AT 010C0H

DB 36H ; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
; Overflow time of watchdog timer is 210/fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB 5AH ; Select 2.45 V for VLVDL
; Select rising edge 2.61 V, falling edge 2.55 V for VLVDH
; Select the interrupt & reset mode as the LVD operation mode
DB A3H ; Select the LS (low speed main) mode as the flash operation mode
and 3 MHz as the frequency of the high-speed on-chip oscillator
DB 85H ; Enables on-chip debug operation, does not erase flash memory
data when security ID authorization fails
Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute
name of the CSEG pseudo instruction. To specify the option byte to 010C0H to 010C3H in order to
use the boot swap function, use the relocation attribute AT to specify an absolute address.
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RL78/I1C CHAPTER 36 FLASH MEMORY
CHAPTER 36 FLASH MEMORY
The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten
while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed,
and the “data flash memory”, an area for storing data.
FFFFFH
256 bytes
FFF00H
FFEFFH General-purpose register
FFEE0H 32 bytes
FFEDFH
RAM
6 to 16 KB
Mirror area
Data flash memory

2 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Extended special function register
(2nd SFR)
2 KB
F0000H
EFFFFH
Reserved
Code flash memory

64 to 256 KB
00000H
The following methods for programming the flash memory are available.
The code flash memory can be rewritten to through serial programming using a flash memory programmer or an
external device (UART communication), or through self-programming.
● Serial Programming Using Flash Memory Programmer (see 36.1)
Data can be written to the flash memory on-board or off-board by using a dedicated flash memory programmer.
● Serial Programming Using External Device (that Incorporates UART) (see 36.2)
Data can be written to the flash memory on-board through UART communication with an external device
(microcontroller or ASIC).
● Self-Programming (see 36.6)
The user application can execute self-programming of the code flash memory by using the flash self-programming
library.
Caution When rewriting the flash memory, stop the middle-speed on-chip oscillator (MIOEN = 0) and select
the high-speed on-chip oscillator (MCM1 = 0) as the main on-chip oscillator clock (fOCO).
Do not change the flash operation mode register (FLMODE). Rewrite the flash memory when the
MCSEL bit in the regulator mode control register (PMMC) is 0.
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The data flash memory can be rewritten to by using the data flash library during user program execution (background
operation). For access and writing to the data flash memory, see 36.8 Data Flash.
36.1 Serial Programming Using Flash Memory Programmer
The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78
microcontroller.
● PG-FP5, FL-PR5
● E1 on-chip debugging emulator
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming

The contents of the flash memory can be rewritten after the RL78 microcontroller has been mounted on the target
system. The connectors that connect the dedicated flash memory programmer must be mounted on the target
system.
(2) Off-board programming

Data can be written to the flash memory with a dedicated program adapter (FA series) before the RL78
microcontroller is mounted on the target system.
Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd.
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Table 36-1. Wiring Between RL78/I1C and Dedicated Flash Memory Programmer
Pin No.
Pin Configuration of Dedicated Flash Memory Programmer
Signal Name LFQFP LFQFP LFQFP

Pin Name
(10 × 10) (12 × 12) (14 × 14)
E1 On-chip
PG-FP5, I/O Pin Function
Debugging
FL-PR5
Emulator
Transmit/
— TOOL0 I/O
receive signal TOOL0/
5 3 9
Transmit/ P40
SI/RxD — I/O
receive signal
— RESET Output
Reset signal RESET 6 7 13
/RESET — Output
VDD voltage generation/
VDD I/O VDD 15 16 22
power monitoring
VSS/EVSS0 21
14 15
GND — Ground EVSS1 54
Note
REGC 13 14 20
VDD — —
Driving power for
FLMD1 EMVDD — EVDD0 15 23
TOOL0 pin 17
EVDD1 63
Note Connect REGC pin to ground via a capacitor (0.47 to 1 µF).
Remark Pins that are not indicated in the above table can be left open when using the flash memory programmer for
flash programming.
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36.1.1 Programming environment

The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below.
Figure 36-1. Environment for Writing Program to Flash Memory
VDD
PG-FP5, FL-PR5 E1
VSS
RS-232C
RESET
USB
TOOL0 (dedicated single-line UART) RL78
Dedicated flash
microcontroller
memory programmer
Host machine
A host machine that controls the dedicated flash memory programmer is necessary.
To interface between the dedicated flash memory programmer and the RL78 microcontroller, the TOOL0 pin is used for
manipulation such as writing and erasing via a dedicated single-line UART.
36.1.2 Communication mode

Communication between the dedicated flash memory programmer and the RL78 microcontroller is established by serial
communication using the TOOL0 pin via a dedicated single-line UART of the RL78 microcontroller.
Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps
Figure 36-2. Communication with Dedicated Flash Memory Programmer
VDD VDD
PG-FP5, FL-PR5 E1 EMVDDNote 1 VDD
FLMD1Note 2
GND VSS/REGCNote 3
RESETNote 1,
RESET
/RESETNote 2 RL78
Dedicated flash microcontroller
memory programmer TOOL0Note 1,
TOOL0
SI/RxDNote 2
Notes 1. When using E1 on-chip debugging emulator.

2. When using PG-FP5 or FL-PR5.
3. Connect REGC pin to ground via a capacitor (0.47 to 1 µF).
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The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manual
of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details.
Table 36-2. Pin Connection
Dedicated Flash Memory Programmer RL78 Microcontroller

Signal Name
I/O Pin Function Pin NameNote 2
PG-FP5, FL-PR5 E1 On-chip Debugging Emulator
VDD I/O VDD voltage generation/power monitoring VDD

GND — Ground VSS, EVSS, REGCNote 1
FLMD1 EMVDD — Driving power for TOOL0 pin VDD
/RESET — Output
Reset signal RESET
— RESET Output
— TOOL0 I/O Transmit/receive signal
TOOL0
SI/RxD — I/O Transmit/receive signal
Notes 1. Connect REGC pin to ground via a capacitor (0.47 to 1 µF).

2. Pins to be connected differ with the product. For details, see Table 36-1.
36.2 Serial Programming Using External Device (that Incorporates UART)
On-board data writing to the internal flash memory is possible by using the RL78 microcontroller and an external device
(a microcontroller or ASIC) connected to a UART.
On the development of flash memory programmer by user, refer to RL78 Microcontrollers (RL78 Protocol A)
Programmer Edition Application Note (R01AN0815).
36.2.1 Programming environment

The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below.
Figure 36-3. Environment for Writing Program to Flash Memory
VDD
VSS
RESET
External device UART (TOOLTxD, TOOLRxD) RL78 microcontroller

(such as microcontroller and ASIC)
TOOL0
Processing to write data to or delete data from the RL78 microcontroller by using an external device is performed on-
board. Off-board writing is not possible.
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36.2.2 Communication mode

Communication between the external device and the RL78 microcontroller is established by serial communication using
the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller.
Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps
Figure 36-4. Communication with External Device
VDD VDD
GND VSS/REGCNote
<R> RESETOUT RESET
External device RxD TOOLTxD RL78 microcontroller

(such as microcontroller and ASIC)
TxD TOOLRxD
PORT TOOL0
The external device generates the following signals for the RL78 microcontroller.
Table 36-3. Pin Connection
External Device RL78 Microcontroller

Signal Name I/O Pin Function Pin Name
VDD I/O VDD voltage generation/power monitoring VDD
GND — Ground VSS, REGCNote
RESETOUT Output Reset signal output RESET
RxD Input Receive signal TOOLTxD
TxD Output Transmit signal TOOLRxD
PORT Output Mode signal TOOL0
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36.3 Connection of Pins on Board
To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated
flash memory programmer must be provided on the target system. First provide a function that selects the normal
operation mode or flash memory programming mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the
same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after
reset, the pins must be handled as described below.
Remark For details on flash memory programming mode, refer to 36.4.2 Flash memory programming mode.
36.3.1 P40/TOOL0 pin

In the flash memory programming mode, connect this pin to the dedicated flash memory programmer via an external 1
kΩ pull-up resistor.
When this pin is used as the port pin, use that by the following method.
When used as an input pin: Input of low-level is prohibited for tHD period after external reset release. However, when
this pin is used via pull-down resistors, use the 500 kΩ or more resistors.
When used as an output pin: When this pin is used via pull-down resistors, use the 500 kΩ or more resistors.
Remarks 1. tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end for
setting of the flash memory programming mode (see 41.12 Timing Specs for Switching Flash Memory
Programming Modes).
2. The SAU and IICA pins are not used for communication between the RL78 microcontroller and dedicated
flash memory programmer, because single-line UART (TOOL0 pin) is used.
36.3.2 RESET pin

Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are
connected to the RESET pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate
the connection with the reset signal generator.
The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash
memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory
programmer and external device.
Figure 36-5. Signal Conflict (RESET Pin)
RL78 microcontroller
Dedicated flash memory programmer

Signal conflict connection pin
Input pin
Another device
Output pin
In the flash memory programming mode, a signal output by another device

will conflict with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of another device.
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36.3.3 Port pins

Example When the flash memory programming mode is set, all the pins not used for flash memory programming enter
the same status as that immediately after reset. If external devices connected to the ports do not recognize
the port status immediately after reset, the port pin must be connected to VDD, or VSS via a resistor
36.3.4 REGC pin

Connect the REGC pin to GND via a capacitor having excellent characteristics (0.47 to 1 µF) in the same manner as
during normal operation. Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
36.3.5 X1 and X2 pins

Connect X1 and X2 in the same status as in the normal operation mode.
Remark In the flash memory programming mode, the high-speed on-chip oscillator clock (fIH) is used.
36.3.6 Power supply

To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory
programmer, and the VSS pin to GND of the flash memory programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
However, when writing to the flash memory by using the flash memory programmer and using the on-board supply
voltage, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power
monitor function with the flash memory programmer.
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36.4 Programming Method
36.4.1 Serial programming procedure

The following figure illustrates a flow for rewriting the code flash memory through serial programming.
Figure 36-6. Code Flash Memory Manipulation Procedure
Start
Flash memory programming

Controlling TOOL0 pin and RESET pin mode is set
Manipulate code flash memory
No
End?
Yes
End
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36.4.2 Flash memory programming mode

To rewrite the contents of the code flash memory through serial programming, specify the flash memory programming
mode. To enter the mode, set as follows.
<When serial programming by using the dedicated flash memory programmer>

Connect the RL78 microcontroller to a dedicated flash memory programmer. Communication from the dedicated flash
memory programmer is performed to automatically switch to the flash memory programming mode.
<When serial programming by using an external device>

Set the TOOL0 pin to the low level, and then cancel the reset (see Table 36-4). After that, enter flash memory
programming mode according to the procedures <1> to <4> shown in Figure 36-7. For details, refer to RL78
microcontrollers (RL78 Protocol A) Programmer Edition Application Note (R01AN0815).
Table 36-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release
TOOL0 Operation Mode

EVDD0 Normal operation mode
0V Flash memory programming mode
Figure 36-7. Setting of Flash Memory Programming Mode
<1> <2> <3> <4>
RESET
723 µs + tHD
processing
time 1-byte data for setting mode
TOOL0
tSU tSUINIT
<1> The low level is input to the TOOL0 pin.

<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the external resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends.
tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (the flash
firmware processing time is excluded).
For details, see 41.12 Timing Specs for Switching Flash Memory Programming Modes.
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There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value
applied to the microcontroller during write operations and the setting information of the user option byte for setting of the
flash memory programming mode determine which mode is selected.
When a dedicated flash memory programmer is used for serial programming, setting the voltage on GUI selects the
mode automatically.
Table 36-5. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified
User Option Byte Setting for Switching to Flash Memory

Power Supply Voltage (VDD) Programming Mode Flash Programming Mode
Flash Operation Mode Operating Frequency (fCLK)
2.7 V ≤ VDD ≤ 5.5 V Blank state Full speed mode
HS (high-speed main) mode 1 MHz to 32 MHz Full speed mode
LS (low-speed main) mode 1 MHz to 8 MHz Wide voltage mode
LV (low-voltage main) mode 1 MHz to 4 MHz Wide voltage mode
2.4 V ≤ VDD < 2.7 V Blank state Full speed mode
HS (high-speed main) mode 1 MHz to 16 MHz Full speed mode
1.8 V ≤ VDD < 2.4 V Blank state Wide voltage mode
Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, erasing, or
verification.
2. For details about communication commands, see 36.4.4 Communication commands.
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36.4.3 Selecting communication mode

Communication mode of the RL78 microcontroller as follows.
Table 36-6. Communication Modes
Standard SettingNote 1
Communication Mode Pins Used
Port SpeedNote 2 Frequency Multiply Rate
1-line mode
115200 bps,
(when flash memory
250000 bps,
programmer is used, or UART — — TOOL0
500000 bps,
when external device is
1 Mbps
used)
Dedicated UART
115200 bps,
(when external device is
250000 bps, TOOLTxD,
used) UART — —
500000 bps, TOOLRxD
1 Mbps
Notes 1. Selection items for Standard settings on GUI of the flash memory programmer.
2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
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36.4.4 Communication commands

The RL78 microcontroller executes serial programming through the commands listed in Table 36-7.
The signals sent from the dedicated flash memory programmer or external device to the RL78 microcontroller are
called commands, and programming functions corresponding to the commands are executed. For details, refer to RL78
microcontroller (RL78 Protocol A) Programmer Edition Application Note (R01AN0815).
Table 36-7. Flash Memory Control Commands
Classification Command Name Function

Verify Verify Compares the contents of a specified area of the flash memory with data
transmitted from the programmer.
Erase Block Erase Erases a specified area in the flash memory.
Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased
Write Programming Writes data to a specified area in the flash memoryNote.
Getting information Silicon Signature Gets the RL78 microcontroller information (such as the part number, flash
memory configuration, and programming firmware version).
Checksum Gets the checksum data for a specified area.
Security Security Set Sets security information.
Security Get Gets security information.
Security Release Release setting of prohibition of writing.
Others Reset Used to detect synchronization status of communication.
Baud Rate Set Sets baud rate when UART communication mode is selected.
Note Confirm that no data has been written to the write area. Because data cannot be erased after block erase is
prohibited, do not write data if the data has not been erased.
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Product information (such as product name and firmware version) can be obtained by executing the “Silicon Signature”
command.
Tables 36-8 and 36-9 show signature data list and example of signature data list.
Table 36-8. Signature Data List
Field Name Description Number of Transmit Data

Device code The serial number assigned to the device 3 bytes
Device name Device name (ASCII code) 10 bytes
Code flash memory area last address Last address of code flash memory area 3 bytes
(Sent from lower address.
Example. 00000H to 0FFFFH (64 KB) → FFH, FFH, 00H)
Data flash memory area last address Last address of data flash memory area 3 bytes
(Sent from lower address.
Example. F1000H to F17FFH (2 KB) → FFH, 17H, 0FH)
Firmware version Version information of firmware for programming 3 bytes
(Sent from upper address.
Example. From Ver. 1.23 → 01H, 02H, 03H)
Table 36-9. Signature Data List
Field Name Description Number of Transmit Data Data (Hexadecimal)

Device code RL78 protocol A 3 bytes 10 00 06
Device name R5F10NPJ 10 bytes 52 = “R”
35 = “5”
46 = “F”
31 = “1”
30 = “0”
4E = “N”
50 = “P”
4A = “J”
20 = “ ”
20 = “ ”
Code flash memory area last address Code flash memory area 3 bytes FFH FFH 03H
00000H to 3FFFFH (256 KB)
Data flash memory area last address Data flash memory area 3 bytes FFH 17H 0FH
F1000H to F17FFH (2 KB)
Firmware version Ver.1.23 3 bytes 01 02 03
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36.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)
The following shows the processing time for each command (reference value) when PG-FP5 is used as a dedicated
flash memory programmer.
Table 36-10. Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)
Port: TOOL0 (UART)

Speed: 1M bps
PG-FP5 Command
64 128 256
Kbytes Kbytes Kbytes
Erasing 1.5 s 2s 2.5 s
Writing 2.5 s 3.5 s 6s
Verification 2s 3.5 s 5.5 s
Writing after erasing 3s 4.5 s 8s
Remark The command processing times (reference values) shown in the table are typical values under the following
conditions.
Port: TOOL0 (single-line UART)
Speed: 1,000,000 bps
Mode: Full speed mode (flash operation mode: HS (high speed main) mode)
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36.6 Self-Programming
The RL78 microcontroller supports a self-programming function that can be used to rewrite the flash memory via a user
program. Because this function allows a user application to rewrite the flash memory by using the RL78 microcontroller
self-programming library, it can be used to upgrade the program in the field.
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock
(fSUB).
2. To prohibit an interrupt during self-programming, in the same way as in the normal operation
mode, execute the flash self-programming library in the state where the IE flag is cleared (0) by
the DI instruction. To enable an interrupt, clear (0) the interrupt mask flag to accept in the state
where the IE flag is set (1) by the EI instruction, and then execute the flash self-programming
library.
3. The high-speed on-chip oscillator should be kept operating during self-programming. If it is
stopped, its clock should be operated (HIOSTOP = 0), and the flash self-programming library
should be executed after 30 µs have elapsed. Stop the middle-speed on-chip oscillator (MIOEN =
0) and select the high-speed on-chip oscillator (MCM1 = 0) as the main on-chip oscillator clock
(fOCO).
4. When rewriting the flash memory, do not change the flash operation mode register (FLMODE).
Rewrite the flash memory when the MCSEL bit in the regulator mode control register (PMMC) is 0.
5. The self-programming function cannot be used when the internal power is supplied from the
VBAT pin.
Remarks 1. For details of the self-programming function, refer to RL78 microcontroller Flash Self-Programming
Library Type01 User’s Manual (R01US0050).
2. For details of the time required to execute self-programming, see the notes on use that accompany the
flash self-programming library tool.
The self-programming function has two flash memory programming modes; wide voltage mode and full speed mode.
Specify the mode that corresponds to the flash operation mode specified in bits CMODE1 and CMODE0 in option byte
000C2H.
Specify the full speed mode when the HS (high-speed main) mode is specified. Specify the wide voltage mode when
the LS (low-speed main) mode or LV (low-voltage main) mode is specified.
If the argument fsl_flash_voltage_u08 is 00H when the FSL_Init function of the flash self-programming library provided
by Renesas Electronics is executed, full speed mode is specified. If the argument is other than 00H, the wide voltage
mode is specified.
Remark Using both the wide voltage mode and full speed mode imposes no restrictions on writing, erasing, or
verification.
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36.6.1 Self-programming procedure

The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library.
Figure 36-8. Flow of Self-Programming (Rewriting Flash Memory)
Code flash memory control start
Initialize flash environment
Flash shield window setting
Erase
Write • Inhibit access to flash memory

• Inhibit shifting STOP mode
• Inhibit clock stop
Verify
Flash information getting
Flash information setting
Close flash environment
End
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36.6.2 Boot swap function

If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or
overwriting is disabled due to data destruction in the boot area.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot
cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot
cluster 0 by using the set information function of the firmware of the RL78 microcontroller, so that boot cluster 1 is used as
a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure
occurs while the area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be
swapped when the program is reset and started next.
Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Figure 36-9. Boot Swap Function
XXXXXH
Self-programming Execution of boot Self-programming

User program to boot cluster 1 User program swap by firmware User program to boot cluster 0 User program
02000H
New boot program Boot program New user program
User program
(boot cluster 1) (boot cluster 0) (boot cluster 0)
01000H
Boot program Boot program New boot program New boot program
(boot cluster 0) (boot cluster 0) (boot cluster 1) (boot cluster 1)
00000H Boot Boot Boot Boot
In an example of above figure, it is as follows.

Boot cluster 0: Boot area before boot swap
Boot cluster 1: Boot area after boot swap
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Figure 36-10. Example of Executing Boot Swapping
Block number
Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7
7 User program 7 User program 7 User program 7 User program 7

Boot 6 User program 6 User program 6 User program 6 6
cluster 1 5 User program 5 User program 5 5 5
4 User program 01000H 4 4 4 4
3 Boot program 3 Boot program 3 Boot program 3 Boot program 3 Boot program
Boot 2 Boot program 2 Boot program 2 Boot program 2 Boot program 2 Boot program
cluster 0 1 Boot program 1 Boot program 1 Boot program 1 Boot program 1 Boot program
0 Boot program 00000H 0 Boot program 0 Boot program 0 Boot program 0 Boot program
Booted by boot cluster 0
Writing blocks 4 to 7 Erasing block 4 Erasing block 5

Boot swap
7 New boot program 7 Boot program 7 Boot program 7 Boot program
6 New boot program 6 Boot program 6 Boot program 6 Boot program
5 New boot program
5 Boot program 5 Boot program 5
4 New boot program
4 Boot program 01000H 4 4
3 Boot program
3 New boot program 3 New boot program 3 New boot program
2 Boot program
1 Boot program 1 New boot program 1 New boot program 1 New boot program
0 Boot program
0 New boot program 00000H 0 New boot program 0 New boot program
Booted by boot cluster 1
Erasing block 6 Erasing block 7 Writing blocks 4 to 7

7 Boot program 7 7 New user program
6 6 6 New user program
5 5 5 New user program
4 4 4 New user program 01000H
0 New boot program 0 New boot program 0 New boot program 00000H
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36.6.3 Flash shield window function

The flash shield window function is provided as one of the security functions for self-programming. It disables writing to
and erasing areas outside the range specified as a window only during self-programming.
The window range can be set by specifying the start and end blocks. The window range can be set or changed during
both serial programming and self-programming.
Writing to and erasing areas outside the window range are disabled during self-programming. During serial
programming, however, areas outside the range specified as a window can be written and erased.
Figure 36-11. Flash Shield Window Setting Example

(Target Devices: R5F10NLE, R5F10NME Start Block: 04H, End Block: 06H)
0FFFFH Methods by which writing can be performed

Block 3FH
Flash shield Block 3EH : Serial programming

range ×: Self-programming
01C00H
01BFFH Block 06H
(end block)
Window range Block 05H : Serial programming
Flash memory : Self-programming
area Block 04H
01000H (start block)
00FFFH
Block 03H
Block 02H
Flash shield : Serial programming
range ×: Self-programming
Block 01H
Block 00H
00000H
Cautions 1. If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range,
prohibition to rewrite the boot cluster 0 takes priority.
2. The flash shield window can only be used for the code flash memory (and is not supported for
the data flash memory).
Table 36-11. Relationship between Flash Shield Window Function Setting/Change Methods and Commands
Window Range Setting/ Execution Commands

Programming Conditions
Change Methods Block Erase Write
Self-programming Specify the starting and ending Block erasing is enabled only Writing is enabled only within
blocks by the flash self- within the window range. the range of window range.
programming library.
Serial programming Specify the starting and ending Block erasing is enabled also Writing is enabled also
blocks on GUI of dedicated flash outside the window range. outside the window range.
memory programmer, etc.
Remark See 36.7 Security Settings to prohibit writing/erasing during serial programming.
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36.7 Security Settings
The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal
flash memory, so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed using the Security Set command.
● Disabling block erase

Execution of the block erase command for a specific block in the flash memory is prohibited during serial
programming. However, blocks can be erased by means of self-programming.
● Disabling write
Execution of the write command for entire blocks in the flash memory is prohibited during serial programming.
However, blocks can be written by means of self-programming.
After the setting of prohibition of writing is specified, releasing the setting by the Security Release command is
enabled by a reset.
● Disabling rewriting boot cluster 0

Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the flash
memory is prohibited by this setting.
The block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash
memory is shipped. Security can be set by serial programming and self-programming. Each security setting can be used
in combination.
Table 36-11 shows the relationship between the erase and write commands when the RL78 microcontroller security
function is enabled.
After the security settings are specified, releasing the security settings by the Security Release command is enabled by
a reset.
Caution The security function of the flash programmer does not support self-programming.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function (see 36.6.3 for
detail).
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Table 36-12. Relationship Between Enabling Security Function and Command
(1) During serial programming

Executed Command
Valid Security
Block Erase Write
Prohibition of block erase Blocks cannot be erased. Can be performed. Note
Prohibition of writing Blocks can be erased. Cannot be performed.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after block erase is
prohibited, do not write data if the data has not been erased.
(2) During self-programming

Executed Command
Valid Security
Block Erase Write
Prohibition of block erase Blocks can be erased. Can be performed.
Prohibition of writing
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function (see 36.6.3 for
detail).
Table 36-13. Setting Security in Each Programming Mode
(1) During serial programming

Security Security Setting How to Disable Security Setting
Prohibition of block erase Set via GUI of dedicated flash memory Cannot be disabled after set.
programmer, etc. Set via GUI of dedicated flash memory
programmer, etc.
Prohibition of rewriting boot cluster 0 Cannot be disabled after set.
Caution Releasing the setting of prohibition of writing is enabled only when the security is not set as the
block erase prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and
data flash memory area being blanks.
(2) During self-programming

Security Security Setting How to Disable Security Setting
Prohibition of block erase Set by using flash self-programming Cannot be disabled after set.
library. Cannot be disabled during self-
programming
(set via GUI of dedicated flash memory
programmer, etc. during serial
programming).
Prohibition of rewriting boot cluster 0 Cannot be disabled after set.
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36.8 Data Flash
36.8.1 Data flash overview

An overview of the data flash memory is provided below.
● The user program can rewrite the data flash memory by using the flash data library. For details, refer to RL78 Family
Flash Data Library User’s Manual.
● The data flash memory can also be rewritten to through serial programming using the dedicated flash memory
programmer or an external device.
● The data flash can be erased in 1-block (1 KB) units.
● The data flash can be accessed only in 8-bit units.
● The data flash can be directly read by CPU instructions.
● Instructions can be executed from the code flash memory while rewriting the data flash memory (that is, background
operation (BGO) is supported).
● Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions.
● Accessing the data flash memory is not possible while rewriting the code flash memory (during self-programming).
● Manipulating the DFLCTL register is not possible while rewriting the data flash memory.
● Transition to the STOP mode is not possible while rewriting the data flash memory.
Cautions 1. The data flash memory is stopped after a reset is canceled. The data flash control register
(DFLCTL) must be set up in order to use the data flash memory.
2. The high-speed on-chip oscillator should be kept operating during data flash rewrite. If it is
stopped, its clock should be operated (HIOSTOP = 0), and the data flash library should be
executed after 65 µs have elapsed.
Remark For the flash programming mode, see 36.6 Self-Programming.
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36.8.2 Register controlling data flash memory
36.8.2.1 Data flash control register (DFLCTL)

This register is used to enable or disable accessing to the data flash.
The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 36-12. Format of Data Flash Control Register (DFLCTL)

Symbol 7 6 5 4 3 2 1 <0>
DFLCTL 0 0 0 0 0 0 0 DFLEN
DFLEN Data flash access control

0 Disables data flash access
1 Enables data flash access
Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory.
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36.8.3 Procedure for accessing data flash memory

The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access
the memory, perform the following procedure:
<1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
<2> Wait for the setup to finish for software timer, etc.
The time setup takes differs for each main clock mode.
<Setup time for each main clock mode>
● HS (high-speed main) mode: 5 ms
● LS (low-speed main) mode: 720 ns
● LP (low-power main) mode: 720 ns
● LV (low-voltage main) mode: 10 ms
<3> After the wait, the data flash memory can be accessed.
Cautions 1. Accessing the data flash memory is not possible during the setup time.
2. Transition to the STOP mode is not possible during the setup time. To enter the STOP mode
during the setup time, clear DFLEN to 0 and then execute the STOP instruction.
3. The high-speed on-chip oscillator should be kept operating during data flash rewrite. If it is kept
stopped, its clock should be operated (HIOSTOP = 0), and the data flash library should be
executed after 65 µs have elapsed.
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RL78/I1C CHAPTER 37 ON-CHIP DEBUG FUNCTION
CHAPTER 37 ON-CHIP DEBUG FUNCTION
37.1 Connecting E1 On-chip Debugging Emulator
The RL78 microcontroller uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1
on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin.
Caution The RL78 microcontroller has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
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Figure 37-1. Example of Connections with the E1 On-chip Debugging Emulator (when the Battery Backup
Function is in Use)
Note 4
Target connector VDD RL78 microcontroller
Notes 3, 4
8 VDD VDD
Note 4
EVDD
9 EMVDD EVDD0, EVDD1
2 GND Note 5
12 GND EVDD VSS, EVSS0, EVSS1

14 GND
1 kΩ
5 TOOL0 TOOL0
Note 6 Note 1
10 Reset_out RESET
13 Reset_out 470 to 510 Ω
Note 2
4 RSTPU
1 kΩ Reset circuit
6 Reset_in Reset signal
1, 3, 7, 11 R.F.U
Notes 1. We recommend a BAT54 series diode from NXP Semiconductors.

2. Need to connecting during to using the on-chip debug. Flash programming will operate in either connected or
not.
3. If the battery backup function is to be used, connect VDD of the E1 emulator to EVDD of the microcontroller.
Do not connect VDD of the microcontroller to the E1 emulator. Do not turn off power to EVDD during
debugging in the battery-backup mode.
4. Depending on the number of pins the microcontroller has, VDD and EVDD may be multiplexed on the same
pin.
In this case, connect both VDD and EMVDD of the E1 emulator to the power supply pin of the microcontroller.
Do not turn off power to these pins during debugging in the battery-backup mode.
5. Be sure to connect pins 2, 12, and 14 of the E1 emulator to the ground pins on the user system.
As well as being used as electrical ground pins, these pins are used for monitoring connection of an E1 or
E20 emulator to the user system, for checking whether the battery backup function is or is not in use, and for
other purposes.
6. Pins 10 and 13 of the E1 emulator must be connected.
Caution The values in the connection example are for reference. Before proceeding with flash programming
for mass production, sufficiently evaluate the values in use to confirm that they satisfy the
specifications of the target device.
Remark With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or
replace EVSS0 and EVSS1 with VSS.
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Figure 37-2. Example of Connections with the E1 On-chip Debugging Emulator (when the Battery Backup
Function is Not in Use)
Note 2
Target connector VDD Target device
8 VDD VDD
Note 2
EVDD
9 EMVDD EVDD0, EVDD1

Note 3
2 GND
GND
12 GND
EVDD
14 GND
1 kΩ
5 TOOL0 TOOL0
Note 4
10 Reset_out RESET
13 Reset_out Note 1 470 to 510 Ω
4 RSTPU
1 kΩ Reset circuit
6 Reset_in Reset signal
1, 3, 11 R.F.U
7 RSTSEL
Notes 1. These connections must be made if the on-chip debugging function is to be used. Flash programming can
proceed whether or not these connections are made.
2. Depending on the number of pins the microcontroller has, VDD and EVDD may be multiplexed on the same
pin.
In this case, connect both VDD and EMVDD of the E1 emulator to the power supply pin of the microcontroller.
3. Be sure to connect pins 2, 12, and 14 of the E1 emulator to the ground pins on the user system.
As well as being used as electrical ground pins, these pins are used for monitoring connection of an E1 or
E20 emulator to the user system.
4. Pins 10 and 13 of the E1 emulator must be connected.
Caution The values in the connection example are for reference. Before proceeding with flash programming
for mass production, sufficiently evaluate the values in use to confirm that they satisfy the
specifications of the target device. Do not use the battery backup function when the circuits for the
connection are as shown in the figure.
Remark With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or
replace EVSS0 and EVSS1 with VSS.
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37.2 On-Chip Debug Security ID
The RL78 microcontroller has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER
35 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from
reading memory content.
When the boot swap function is used, also set a value that is the same as that of 010C3H and 010C4H to 010CDH in
advance, because 000C3H, 000C4H to 000CDH and 010C3H, and 010C4H to 010CDH are switched.
Table 37-1. On-Chip Debug Security ID
Address On-Chip Debug Security ID
000C4H to 000CDH Any ID code of 10 bytes
010C4H to 010CDH
37.3 Securing of User Resources
To perform communication between the RL78 microcontroller and E1 on-chip debugging emulator, as well as each
debug function, the securing of memory space must be done beforehand.
If Renesas Electronics assembler or compiler is used, the items can be set by using link options.
(1) Securement of memory space

The shaded portions in Figure 37-3 are the areas reserved for placing the debug monitor program, so user
programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces must
be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user
program.
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Figure 37-3. Memory Spaces Where Debug Monitor Programs Are Allocated
Code flash memory Internal RAM
Use prohibited SFR area
Note 1
(512 bytes or
256 bytes Note 2) Stack area for debugging Internal RAM
(4 bytes) Note 4 area
Mirror area
Code flash
area
: Area used for on-chip debugging

01000H
000D8H
Debug monitor area

000CEH (10 bytes)
Security ID area
On-chip debug option byte area
000C4H (10 bytes)
(1 byte)
000C3H
Debug monitor area

00002H (2 bytes)
00000H Note 3
Notes 1. Address differs depending on products as follows.

Products (code flash memory capacity) Address of Note 1
R5F10NME, R5F10NLE 0FFFFH
R5F10NPG, R5F10NMG, R5F10NLG 1FFFFH
R5F10NMJ, R5F10NPJ 3FFFFH
2. When real-time RAM monitor (RRM) function and dynamic memory modification (DMM) function are not
used, it is 256 bytes.
3. In debugging, reset vector is rewritten to address allocated to a monitor program.
4. Since this area is allocated immediately before the stack area, the address of this area varies depending on
the stack increase and decrease. That is, 4 extra bytes are consumed for the stack area used.
When using self-programming, 12 extra bytes are consumed for the stack area used.
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RL78/I1C CHAPTER 38 BCD CORRECTION CIRCUIT
CHAPTER 38 BCD CORRECTION CIRCUIT
38.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/subtracting the BCD correction result register (BCDADJ).
38.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
● BCD correction result register (BCDADJ)
38.2.1 BCD correction result register (BCDADJ)

The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through add/subtract
instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of
the CY and AC flags.
The BCDADJ register is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 38-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH After reset: undefined R

Symbol 7 6 5 4 3 2 1 0
BCDADJ
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38.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD
code value
<1> The BCD code value to which addition is performed is stored in the A register.
<2> By adding the value of the A register and the second operand (value of one more BCD code to be added) as
are in binary, the binary operation result is stored in the A register and the correction value is stored in the
BCD correction result register (BCDADJ).
<3> Decimal correction is performed by adding in binary the value of the A register (addition result in binary) and
the BCDADJ register (correction value), and the correction result is stored in the A register and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction <3>
after the instruction <2> instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
Examples 1: 99 + 89 = 188
Instruction A Register CY Flag AC Flag BCDADJ

Register
MOV A, #99H ; <1> 99H – – –
ADD A, #89H ; <2> 22H 1 1 66H
ADD A, !BCDADJ ; <3> 88H 1 0 –
Examples 2: 85 + 15 = 100

Register
MOV A, #85H ; <1> 85H – – –
ADD A, #15H ; <2> 9AH 0 0 66H
ADD A, !BCDADJ ; <3> 00H 1 1 –
Examples 3: 80 + 80 = 160

Register
MOV A, #80H ; <1> 80H – – –
ADD A, #80H ; <2> 00H 1 0 60H
ADD A, !BCDADJ ; <3> 60H 1 0 –
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(2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using
a BCD code value
<1> The BCD code value from which subtraction is performed is stored in the A register.
<2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is
in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the
BCD correction result register (BCDADJ).
<3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A
register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction <3>
after the instruction <2> instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
Example: 91 – 52 = 39

Register
MOV A, #91H ; <1> 91H – – –
SUB A, #52H ; <2> 3FH 0 1 06H
SUB A, !BCDADJ ; <3> 39H 0 0 –
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RL78/I1C CHAPTER 39 32-BIT MULTIPLY-ACCUMULATOR
CHAPTER 39 32-BIT MULTIPLY-ACCUMULATOR
39.1 Function of 32-bit Multiply-accumulator
The 32-bit multiply-accumulator has the following function.
● 32 bits × 32 bits = 64 bits (Unsigned multiply)

● 32 bits × 32 bits = 64 bits (Signed multiply)
● 32 bits × 32 bits + 64 bits = 64 bits (Unsigned multiply-accumulate)
● 32 bits × 32 bits + 64 bits = 64 bits (Signed multiply-accumulate)
● Fixed point mode supported
● Interrupt output for the multiply-accumulation result in the case of overflow/underflow
The data format is 2’s complement form.

● Signed (The highest-order bit is the signed bit.)
7FFF (hexadecimal digit) = 32767 (decimal digit)
0001 (hexadecimal digit) = 1 (decimal digit)
FFFF (hexadecimal digit) = –1 (decimal digit)
8000 (hexadecimal digit) = -32768 (decimal digit)
● Unsigned
FFFF (hexadecimal digit) = 65535 (decimal digit)
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39.2 Configuration of 32-bit Multiply-accumulator
The 32-bit multiply-accumulator consists of the following hardware.
Table 39-1. Configuration of 32-bit Multiply-accumulator
Item Configuration
Registers Multiplication data register B (L) (MULBL)

Multiplication data register B (H) (MULBH)
Multiplication data register A (L) (Unsigned) (MUL32UL)
Multiplication data register A (H) (Unsigned) (MUL32UH)
Multiplication data register A (L) (Signed) (MUL32SL)
Multiplication data register A (H) (Signed) (MUL32SH)
Multiply-accumulation data register A (L) (Unsigned) (MAC32UL)
Multiply-accumulation data register A (H) (Unsigned) (MAC32UH)
Multiply-accumulation data register A (L) (Signed) (MAC32SL)
Multiply-accumulation data register A (H) (Signed) (MAC32SH)
Multiplication result register 0 (MULR0)
Multiplication control register (MULC)
Peripheral enable register 2 (PER2)
Figure 39-1 shows a block diagram of 32-bit multiply-accumulator.
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Figure 39-1. Block Diagram of 32-bit Multiply-accumulator
Internal bus
Multiplier Multiplicand
Multiplication data register B Multiplication data register A Multiplication control register

MULBH MULBL MUL32UH MUL32UL MACMODE MULSM MULFRAC MACOF MACSF MULST
MUL32SH MUL32SL
MAC32UH MAC32UL
MAC32SH MAC32SL Control circuit
Multiplier
Multiplier Multiplicand Multiplicand
MULBH write signal
operation control signal Counter
0 Accumulation value
Operation
mode change
Selector Selector Multiplication Multiply-
accumulation (Multiply/
Multiply-
accumulation)
Selector
16-bit Multiplier
Operation mode
change
(Signed/Unsigned)
INTMACLOF
64-bit adder
Multiplication result register 3/2 Multiplication result register 1/0

MULR3 MULR2 MULR1 MULR0
Result of multiply/multiply-
accumulation
(accumulation value)
Fixed point mode control
Data flow during multiplication and
multiply-accumulation
Internal bus
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39.2.1 Multiplication data register A (MUL32UH, MUL32UL, MUL32SH, MUL32SL, MAC32UH, MAC32UL, MAC32SH,
MAC32SL)
Multiplication data register A specifies the multiplicand used for multiplication and multiply-accumulation.
Multiplication data register A can be set by a 16-bit manipulation instruction.
Figure 39-2. Format of Multiplication Data Register A

(MUL32UH, MUL32UL, MUL32SH, MUL32SL, MAC32UH, MAC32UL, MAC32SH, MAC32SL)
Address: F0282H (MUL32UH), F0286H (MUL32SH), F028AH (MAC32UH), F028EH (MAC32SH)

F0280H (MUL32UL), F0284H (MUL32SL), F0288H (MAC32UL), F028CH (MAC32SL)
After reset: 0000H R/W
Symbol F0283H F0282H
MUL32UH
MUL32SH
MAC32UH
MAC32SH
MUL32UL
MUL32SL
MAC32UL
MAC32SL
Caution Do not rewrite the values of the multiplication data register A (MUL32UH, MUL32UL,
MUL32SH, MUL32SL, MAC32UH, MAC32UL, MAC32SH, MAC32SL) during the operation
processing (when the bit 0 (MULST) of the multiplication control register (MULC) = 1). If this
is done, the operation result will be an undefined value.
Multiplication data register A stores the written value. The MACMODE and MULSM bits of
the MULC register are also rewritten with the values of the supported operation mode.
For the multiplication data register A, the operation mode can be switched by the register that specifies the
multiplicand since the different register name and register address are set for each operation mode. The MACMODE
and MULSM bits of the MULC register are also rewritten with the values of the supported operation mode.
For the MUL32UL, MUL32UH, MUL32SL, MUL32SH, MAC32UL, MAC32UH, MAC32SL, and MAC32SH registers,
all the register values are rewritten when rewriting one register value since a common register is used for these
registers.
The following table shows the relationship between the operation mode and register name.
Table 39-2. Relationship between Operation Mode and Register Name

Operation Mode Register Name of Multiplication Data Register A
Bits 31 to 16 (MULAH) Bits 15 to 0 (MULAL)
Multiplication mode (unsigned) MUL32UH MUL32UL
Multiplication mode (signed) MUL32SH MUL32SL
Multiply-accumulation mode (unsigned) MAC32UH MAC32UL
Multiply-accumulation mode (signed) MAC32SH MAC32SL
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39.2.2 Multiplication data register B (MULBL, MULBH)

Multiplication data register B specifies the multiplier used for multiplication and multiply-accumulation.
Multiplication data register B can be set by a 16-bit manipulation instruction.
Figure 39-3. Format of Multiplication Data Register B (MULBH, MULBL)
Address: FFF3EH (MULBH), FFF3CH (MULBL) After reset: 0000H R/W
Symbol FFF3FH FFF3EH
MULBH
Symbol FFF3DH FFF3CH
MULBL
Cautions 1. Do not rewrite the values of the multiplication data register B with software during the
operation (when bit 0 (MULST) of the multiplication control register (MULC) = 1). If this is
done, the operation result will be an undefined value.
2. The operation starts by writing to the higher 16 bit (MULBH) of the multiplication data
register B. Be sure to set the multiplier in the order from MULBL to MULBH.
(The operation processing exits after the 5th cycle from writing of the MULBH register.)
The multiplication data register B is used as a common register in all the operation modes.
Operation Mode Register Name of Multiplication Data Register B
Bits 31 to 16 (MULBH) Bits 15 to 0 (MULBL)
Multiplication mode (unsigned) MULBH MULBL
Multiplication mode (signed)

Multiply-accumulation mode (unsigned)
Multiply-accumulation mode (signed)
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39.2.3 Multiplication result register (MULR0, MULR1, MULR2, MULR3)

Multiplication result register is the register where the operation result values are stored.
Multiplication result register can be set by a 16-bit manipulation instruction.
Figure 39-4. Format of Multiplication Result Register (MULR0, MULR1, MULR2, MULR3)
Address: F0290H (MULR0), F0292H (MULR1), F0294H (MULR2), F0296H (MULR3) After reset: 0000H R/W
MULR3
F0295H F0294H
MULR2
F0293H F0292H
MULR1
F0291H F0290H
MULR0
Cautions 1. Do not rewrite the value of the multiplication result register during the operation
processing (when bit 0 (MULST) of the multiplication control register (MULC) = 1). If this
is done, the operation result will be an undefined value.
2. When the value of the multiplication result register is read out during the operation
processing (MULST = 1), the value is not guaranteed. The values of the MULR3 to
MULR0 registers can be read out even during the operation processing if the number of
clocks required for the operation (refer to 39.4.2 Number of clocks for result availability)
has been met in each multiplication result register since the operation results are stored
in the MULR0, MULR1, MULR2, and MULR3 registers in this order (results are stored in
the MULR2 and MULR3 registers simultaneously).
The multiplication result register is used as a common register in all the operation modes.
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Operation Mode Multiplication Result Register Name
Bits 63 to 48 Bits 47 to 32 Bits 31 to 16 Bits 15 to 0
Multiplication mode (unsigned) MULR3 MULR2 MULR1 MULR0
Multiplication mode (signed)

Multiply-accumulation mode (unsigned)
Multiply-accumulation mode (signed)
The operation result (multiplication) is stored for the multiplication, and the operation result (accumulation) is stored
for the multiply-accumulation. Additionally, the accumulation initial value can be set for the multiply-accumulation.
Table 39-5. Details of Storing of Operation Modes and Multiplication Result Registers
Operation Mode Setting Operation Result
Multiplication mode (unsigned) – MULR3 to MULR0:

Multiplication (unsigned)
Multiplication mode (signed) – MULR3 to MULR0:
Multiplication (signed)
Multiply-accumulation mode (unsigned) MULR3 to MULR0: MULR3 to MULR0:
Accumulation initial value (unsigned) Accumulation value (unsigned)
Multiply-accumulation mode (signed) MULR3 to MULR0: MULR3 to MULR0:
Accumulation initial value (signed) Accumulation value (signed)
If exceeding the maximum value of the value range that can be handled in 64 bit (= overflow), or if dropping below
the minimum value (= underflow), the value is reversed, and the values plus overflow/underflow values are stored in
the MULR3 to MULR0 registers.
■ Unsigned
• In case of overflow
Processing) 264 + MULR[63:0]
Example)
FFFF FFFF FFFF FFFFh + 0000 0000 0000 0001h = 0000 0000 0000 0000h
■ Signed
• In case of overflow
Processing) 263 + MULR[62:0]
Example)
7FFF FFFF FFFF FFFFh + 0000 0000 0000 0001h = 8000 0000 0000 0000h
• In case of underflow
Processing) –263 + MULR[62:0]
Example)
8000 0000 0000 0000h + FFFF FFFF FFFF FFFFh = 7FFF FFFF FFFF FFFFh
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39.3 Register Controlling 32-bit Multiply-accumulator
32-bit multiply-accumulator is controlled by the following registers.
• Peripheral enable register 2 (PER2)

• Peripheral reset control register 2 (PRR2)
• Multiplication control register (MULC)

This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
When the 32-bit multiply-accumulator is used, be sure to set bit 2 (MACEN) of this register to 1.
Figure 39-5. Format of Peripheral enable register 2 (PER2)

Symbol <7> <6> 5 4 3 <2> 1 <0>
MACEN Control of 32-bit multiplier and accumulator input clock supply

• SFR used by the 32-bit multiplier and accumulator cannot be written. The read value is 00H.
However, the SFR is not initialized. Note
• SFR used by the 32-bit multiplier and accumulator can be read and written.
Note To initialize the 32-bit multiply-accumulator and the SFR used by the 32-bit multiply-accumulator, use
bit 2 (MACRES) of PRR2.

This register is used for individual reset control of each peripheral hardware.
This MCU controls reset and reset release of each peripheral hardware supported by the PRR2 register.
To reset the 32-bit multiply-accumulator, be sure to set bit 2 (MACRES) to 1.

Symbol <7> <6> 5 4 3 <2> 1 0
MACRES Reset control of 32-bit multiply-accumulator

0 32-bit multiply-accumulator reset release
1 32-bit multiply-accumulator reset state
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39.3.3 Multiplication control register (MULC)

MULC register is the 8-bit register that controls the operation of the 32-bit multiply-accumulator.
MULC register is set by 1-bit or 8-bit memory manipulation instruction.
However, for the overflow/underflow flag (MACOF) of the multiply-accumulation result (accumulation value), sign
flag (MACSF) of the multiply-accumulation result (accumulation value), and the operation status flag (MULST), only
the read-out operation is enabled.
Figure 39-7. Format of Multiplication Control Register (MULC) (1/2)
Address: F029AH After reset: 00H R/WNote

Symbol <7> <6> 5 <4> 3 <2> <1> <0>
MULC MACMODE MULSM 0 MULFRAC 0 MACOF MACSF MULST
MACMODE MULSM Selection of operation mode

<R> 0 0 Multiplication mode (unsigned) (default)
0 1 Multiplication mode (signed)
1 0 Multiply-accumulation mode (unsigned)
1 1 Multiply-accumulation mode (signed)
The operation mode is automatically switched by the address of the multiplication data register A to be
specified.
Reading out this bit enables to check the operation mode.
Writing in this bit enables to specify the operation mode as well.
MULFRAC Selection of fixed point mode

0 Disabled
1 Enabled
For details of the fixed point mode, refer to 39.4.6 Fixed point mode.
MACOF Overflow/underflow flag of multiply-accumulation result (accumulation value)

0 No overflow/underflow occurred.
1 Overflow/underflow occurred.
[Conditions for setting]
● Multiply-accumulation mode (unsigned)
If exceeding the accumulation value FFFF FFFF FFFF FFFFh
● Multiply-accumulation mode (signed)
If the result is the negative value exceeding 7FFF FFFF FFFF FFFFh after adding the positive
multiplication value to the positive accumulation value
If the result is the positive value exceeding 8000 0000 0000 0000h after adding the negative multiplication
value to the negative accumulation value
[Timing of setting/clearing]
● At finish of operation (MULST = 1 → 0)
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Figure 39-7. Format of Multiplication Control Register (MULC) (2/2)
Address: F029AH After reset: 00H R/WNote

Symbol <7> <6> 5 <4> 3 <2> <1> <0>
MULC MACMODE MULSM 0 MULFRAC 0 MACOF MACSF MULST
MACSF Sign flag of multiply-accumulation result (accumulation value)
0 Positive accumulation value

1 Negative accumulation value
Multiply-accumulation mode (unsigned): Always 0

Multiply-accumulation mode (signed): Displays the sign bit of the accumulation value.
MULST Operation processing status bit
0 Completion of operation processing

1 During operation processing
The operation starts by writing to the higher 16 bit (MULBH) of the multiplication data register B.
The MULST bit is set (1) at start of the operation, and cleared (0) at completion of 5 cycles.
Note Bits 0 to 2 are Read only.
Caution Do not rewrite the value of the multiplication control register (MULC) during the operation
processing (MULST = 1). Otherwise, the MACOF and MACSF bits of the multiplication result
register will be undefined values.
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39.4 Operations of 32-bit Multiply-accumulator
39.4.1 Basic operation

The register configuration shows as follow when multiplication or multiply-accumulation is executed.
■ Register configuration during unsigned multiplication

<Multiplier A> <Multiplier B> <Product>
32-bit 32-bit 64-bit
Unsigned Unsigned Unsigned
[MUL32UH, MUL32UL] × [MDBH, MDBL] = [MULR3, MULR2, MULR1, MULR0]
■ Register configuration during signed multiplication

<Multiplier A> <Multiplier B> <Product>
32-bit 32-bit 64-bit
Signed Signed Signed
[MUL32SH, MUL32SL] × [MDBH, MDBL] = [MULR3, MULR2, MULR1, MULR0]
■ Register configuration during unsigned multiply-accumulation

<Multiplier A> <Multiplier B> <Accumulated value> <Product>
32-bit 32-bit 64-bit 64-bit
Unsigned Unsigned Unsigned Unsigned
[MAC32UH, MAC32UL] × [MDBH, MDBL] + [MULR3, MULR2, MULR1, MULR0] = [MULR3, MULR2, MULR1, MULR0]
■ Register configuration during signed multiply-accumulation

<Multiplier A> <Multiplier B> <Accumulated value> <Product>
32-bit 32-bit 64-bit 64-bit
Signed Signed Signed Signed
[MAC32SH, MAC32SL] × [MDBH, MDBL] + [MULR3, MULR2, MULR1,MULR0] = [MULR3, MULR2, MULR1, MULR0]
39.4.2 Number of clocks for result availability

In case of multiplication or multiply-accumulation, the calculation is started automatically by setting upper 16-bit of
the multiplier data (MULBH). Table 39-6 gives the number of clocks necessary to calculation.
Table 39-6. Number of Clocks Necessary to Calculation
Operation Mode Operation The Number of Clocks Necessary to Calculation

MULR0 MULR1 MULR2 MULR3 MACOF
MACSF
Unsigned multiply 32 bits × 32 bits 2 4 5 5 5

Signed multiply 32 bits × 32 bits 2 4 5 5 5
Unsigned multiply- 32 bits × 32 bits + 2 4 5 5 5
accumulate 64 bits
Signed multiply-accumulate 32 bits × 32 bits + 2 4 5 5 5
64 bits
Remark There is no difference in the clock number between the enabled and disabled fixed point modes.
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39.4.3 Switch of operation mode

Writing the multiplicand in the multiplication data register A switches the operation mode. MACMODE (bit 7) and
MULSM (bit 6) of the multiplication control register (MULC) enable to switch the modes and to check the operation
mode. Hold the lastly-written mode so that the multiplication processing can be executed consecutively when writing
in the multiplication data register B (H). The initial vale is "Unsigned multiplication mode".
39.4.4 Multiplication operation

● The multiplication automatically starts when setting the multiplier in the MULBH register. The operation does not
start even when setting the MULBL register.
● By setting the multiplicand in the multiplication data register A, the operation mode is switched automatically.
However, the operation does not start at this time.
● The MULST bit is set to 1 after starting the operation, and the bit is cleared to 0 after completion of the operation.
● Interrupt does not occur after completion of the operation. Note
<R> Note In the case where multiplication mode (signed) is selected and the value of the multiplication result register
(MULR3 to MULR0) before the operation is negative, a multiply-accumulation operation overflow/underflow
interrupt (INTMACLOF) may be generated. If the multiplication mode (signed) is selected, set a “1” in the
interrupt flag mask register (MACMK) to disable INTMACLOF or set the multiplication result register
(MULR3) to “0000H” or a positive value before starting the operation by setting the values for multiplication in
the MULBH register.
39.4.5 Multiply-accumulation operation

● The multiply-accumulation automatically starts when setting the multiplier in the MULBH register. The operation
does not start even when setting the MULBL register.
● By setting the multiplicand in the multiplication data register A, the operation mode is switched automatically.
However, the operation does not start at this time.
● The MULST bit is set to 1 after starting the operation, and the bit is cleared to 0 after completion of the operation.
● In case of overflow/underflow of the accumulation result after completion of the operation, interrupt is output.
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39.4.6 Fixed point mode

Fixed point mode supports the Q format.
(Example) Q31 format –1.0 to 0.999999999534 ≈ 1.0
│←――――――――31 bits――――――――――――――――――――→│
S 1/2 1/4 1/8 ...
↑ ●
│ ↑
│ Point
Sign flag
(Example) Q30 format –2.0 to 1.999999999069 ≈ 2.0

│←―――30 bits―――――――――――――――――→│
S X 1/2 1/4 1/8 ...
↑ ●
│ ↑
│ Point
Sign flag
When executing multiplication of two 32-bit fixed points in the Q31 format, the operation result is stored in the
multiplication result registers (MULR3 to MULR0) as the Q62 format. To manually covert into the Q31 format, the
lower 31 bit of the operation result and extended sign bit must be removed. When the CPU reads the multiplication
result registers (MULR3 and MULR2) with the fixed point mode enabled (MULFRAC = 1), the value of the operation
result shifted to the left for 1 bit can be read out. By shifting the operation result to the left for 1 bit, the redundant sign
bit is automatically removed, and the operation result in the Q31 format can be obtained.
In the fixed point mode, the value of the multiplication result register itself is not rewritten. Therefore, change of the
fixed point mode flag value enables to read out both the Q31-format value shifted to the left for 1 bit and the operation
result that is not shifted to the left.
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39.4.7 Operation of fixed point mode

The operation is executed in the same way as the normal operation. The result of reading the multiplication result
register only when the fixed point mode is enabled is shown below:
In case of MULFRAC = 1 Value at reading MULR3 = {MULR3[15], MULR3[13:0], MULR2[15]}

Value at reading MULR2 = {MULR2[14:0], MULR1[15]}
Value at reading MULR1 = {MULR1[15:0]}
Value at reading MULR0 = {MULR0[15:0]}
MULFRAC = 0
Multiplication result 63 62 61 48 47 46
3
31 16 15 0
2
register
MULFRAC = 1
Multiplication result 63 62 61 48 47 46 32 31 16 15 0
register
In case of the fixed point mode (MULFRAC = 1), fill MULA and MULB in the Q31 format. For multiply-accumulation,
enter the accumulation initial value in the Q62 format (= 31 (31 format of MULA) + 31 (31 format of MULB)). At this
time, MULR3 to MULR0 in the Q62 format must be filled since MULR3 to MULR0 must be filled according to the
format output from MULA × MULB. An example is shown below:
Example) For multiply-accumulation {MULAH, MULAL} × {MULBH, MULBL} + {MULR3, MULR2, MULR1, MULR0}
<1> <2>
MULAH MULAL
31 30 16 15 0 (Q31 format)
MULBH MULBL
Operation of
× 31 30 16 15 0 (Q31 format)
<1>
63 62 48 47 32 31 30 16 15 0 (Q62 format)

+ 63 62 48 47 32 31 30 16 15 0 (Q62 format)
Operation of
<2>
63 62 48 47 32 31 30 16 15 0 (Q63 format)
Caution The values of the MULR1 and MULR0 registers in the fixed point mode (MULFRAC = 1) is the
lower 32 bit of the Q62 format that is not shifted to the left. Unless carry/borrow occurs from bit
62 of the multiplication result register with the fixed point mode disabled, interrupt of
overflow/underflow does not occur even in the fixed point mode (MULFRAC = 1).
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39.4.8 Interrupt
In case of overflow/underflow of the multiply-accumulation result, interrupt signal is generated.
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39.5 Operation of 32-bit Multiply-accumulator
Execute the MACL operation according to the following setting procedure.
<1> An example of executing during multiplication

● Enables input clock supply
The MACEN bit of the PER2 register is set (1), and supplying the clock starts.
● Initial setting
<STEP-1> MULC writing (Enabling/Disabling fixed point mode)
<STEP-2> Multiplication data register A (L) writing (MUL32UL or MUL32SL)
<STEP-3> Multiplication data register A (H) writing (MUL32UH or MUL32SH)
<STEP-4> Multiplication data register B (L) writing (MULBL)
<STEP-5> Multiplication data register B (H) writing (MULBH)
● MULST = 1
● Multiplication operation
When a series of processing shown below finishes, the operation finishes.
● When all operations (5 cycles) of the multiplication operation process are finished, MULST is cleared to 0.
(The sign flag MACSF is fixed to 0.)
● The 2nd cycle after start of operation and subsequent cycles
<STEP-6> Multiplication result register 0 (MULR0) can be read out.
● The 4th cycle after start of operation and subsequent cycles
● When executing the operation continuously

(1) When switching the fixed point mode, execute <STEP-1>. For the other cases, proceed to (2).
(2) When rewriting the multiplicand, execute <STEP-2> and <STEP-3>. For the other cases, proceed to (3).
(3) Execute from <STEP-4>.
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The operation flow when executing the multiplication is shown below:
Figure 39-8. MACL Operation Flow (for Multiplication)
START
Multiplication control register (MULC) If the fixed point mode is not

<STEP-1> (Fixed point mode) rewritten, rewriting is not required.
Write to the multiplication data register A (L)

<STEP-2> (MUL32UL or MUL32SL)
(Multiplicand lower 16 bit writing) If the multiplicand is not rewritten,
rewriting is not required. (Set the
multiplication data register A in the
Write to the multiplication data register A (H)
desired order.)
<STEP-3> (MUL32UH or MUL32SH)
(Multiplicand upper 16 bit writing)
Write to the multiplication data register B (L)

<STEP-4> (MULBL)
(Multiplier writing)
Write to the multiplication data register B (H) MULBH writing starts the
<STEP-5> (MULBH) operation.
2 cycles or more elapse
Read from the multiplication result

<STEP-6> register 0 (MULR0)
1 cycle or more elapse


MULST is set to 1, and the MACSF value is
not fixed.

END
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<2> An example when executing the multiply-accumulation

● Enables input clock supply
The MACEN bit of the PER2 register is set (1), and supplying the clock starts.
● Initial setting
<STEP-1> MULC writing (Enabling/Disabling fixed point mode)
<STEP-2> Multiplication result register 0 writing (MULR0) (accumulation initial setting)
<STEP-6> Multiplication data register A (L) writing (MAC32UL or MAC32SL)
<STEP-7> Multiplication data register A (H) writing (MAC32UH or MAC32SH)
<STEP-8> Multiplication data register B (L) writing (MULBL)
<STEP-9> Multiplication data register B (H) writing (MULBH)
● MULST = 1
● During multiply-accumulation
When a series of processing shown below finishes, the operation finishes.
● In case of overflow/underflow, MACOF is set to 1, and interrupt (INTMACLOF = 1) occurs.
● When all cycles (5 cycles) of the multiply-accumulation processing operation have been completed, MULST is
cleared to 0, and the sign flag MACSF is set or cleared.
(However, the MACSF flag is not set but fixed to 0 when MULSM is cleared to 0.)
● The 2nd cycle after start of operation and subsequent cycles
● The 4th cycle or after
● When executing the operation continuously

(1) When switching the fixed point mode, execute <STEP-1>. For the other cases, proceed to (2).
(2) When rewriting accumulation initial value (multiplication result registers MULR0 to MULR3)
Execute <STEP-2>, <STEP-3>, <STEP-4>, and <STEP-5>. For the other cases, proceed to (3).
(3) When rewriting the multiplicand, execute <STEP-6> and <STEP-7>. For the other cases, proceed to (4).
(4) Execute from <STEP-8>.
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The operation flow when executing the multiply-accumulation is shown below:
Figure 39-9. MACL Operation Flow (for Multiply-accumulation)
START
Multiplication control register (MULC) If the fixed point mode is not

<STEP-1> (Fixed point mode) rewritten, rewriting is not required.
Write to the multiplication result register 0

<STEP-2> (MULR0)
(Accumulation initial value setting)

<STEP-3> (MULR1)
If the accumulation initial value is
not rewritten, rewriting is not
required. (At the accumulation
Write to the multiplication result register 2 initial value setting, set MULR0 to
<STEP-4> (MULR2) MULR3 in the desired order.)

<STEP-5> (MULR3)
Write to the multiplication data register A (L)

<STEP-6> (MAC32UL or MAC32SL)
(Multiplicand lower 16 bit writing) If the multiplicand is not rewritten,
rewriting is not required. (Set the
Write to the multiplication data register A (H) multiplication data register A in the
desired order.)
<STEP-7> (MAC32UH or MAC32SH)
(Multiplicand upper 16 bit writing)
Write to the multiplication data register B (L)

<STEP-8> (MULBL)
Write to the multiplication data register B (H) MULBH writing starts the
<STEP-9> (MULBH) operation.
2 cycles or more elapse

1 cycle or more elapse

MULST is set to 1, and the MACSF value is
Read from the multiplication result not fixed.
<STEP-11> In case of overflow/underflow of the multiply-
register 1 (MULR1)
accumulation, MACOF is set to 1, and
interrupt (INTMACLOF = 1) occurs.
<STEP-12>
register 2 (MULR2)

END
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39.6 Precautions for 32-bit Multiply-accumulator
39.6.1 Precautions during operation (MULST = 1)

Rewriting of the multiplication data register A (L)/(H), multiplication data register B (L)/(H), multiplication result
register 0/1/2/3, and multiplication control register is prohibited during the operation. Otherwise, the operation result
will be an undefined value.
Before rewriting to the multiplication data register B (H) as the operation start, rewriting the multiplication data
register A (L)/(H), multiplication data register B (L), multiplication result register 0/1/2/3, and multiplication control
register must be completed.
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RL78/I1C CHAPTER 40 INSTRUCTION SET
CHAPTER 40 INSTRUCTION SET
This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and
operation code, refer to the separate document RL78 Family User’s Manual: software (R01US0015).
40.1 Conventions Used in Operation List
40.1.1 Operand identifiers and specification methods

Operands are described in the “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and
are described as they are. Each symbol has the following meaning.
● #: Immediate data specification

● !: 16-bit absolute address specification
● !!: 20-bit absolute address specification
● $: 8-bit relative address specification
● $!: 16-bit relative address specification
● [ ]: Indirect address specification
● ES:: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, !!, $, $!, [ ], and ES: symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 40-1. Operand Identifiers and Specification Methods
Identifier Description Method
r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

rp AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr Special-function register symbol (SFR symbol) FFF00H to FFFFFH
sfrp Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses onlyNote) FFF00H to
FFFFFH
saddr FFE20H to FFF1FH Immediate data or labels
saddrp FFE20H to FF1FH Immediate data or labels (even addresses onlyNote)
addr20 00000H to FFFFFH Immediate data or labels
addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructionsNote)
addr5 0080H to 00BFH Immediate data or labels (even addresses only)
word 16-bit immediate data or label
byte 8-bit immediate data or label
bit 1-bit immediate data or label
RBn RB0 to RB3
Note Bit 0 = 0 when an odd address is specified.
Remark The special function registers can be described to operand sfr as symbols. See Table 3-5 SFR List for the
symbols of the special function registers. The extended special function registers can be described to
operand !addr16 as symbols. See Table 3-6 Extended SFR (2nd SFR) List for the symbols of the extended
special function registers.
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40.1.2 Description of operation column

The operation when the instruction is executed is shown in the “Operation” column using the following symbols.
Table 40-2. Symbols in “Operation” Column
Symbol Function
A A register; 8-bit accumulator

X X register
B B register
C C register
D D register
E E register
H H register
L L register
ES ES register
CS CS register
AX AX register pair; 16-bit accumulator
BC BC register pair
DE DE register pair
HL HL register pair
PC Program counter
SP Stack pointer
PSW Program status word
CY Carry flag
AC Auxiliary carry flag
Z Zero flag
RBS Register bank select flag
IE Interrupt request enable flag
() Memory contents indicated by address or register contents in parentheses
X H, X L 16-bit registers: XH = higher 8 bits, XL = lower 8 bits
XS, XH, XL 20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
 Logical product (AND)
 Logical sum (OR)
 Exclusive logical sum (exclusive OR)
– Inverted data
addr5 16-bit immediate data (even addresses only in 0080H to 00BFH)
addr16 16-bit immediate data
addr20 20-bit immediate data
jdisp8 Signed 8-bit data (displacement value)
jdisp16 Signed 16-bit data (displacement value)
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40.1.3 Description of flag operation column

The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols.
Table 40-3. Symbols in “Flag” Column
Symbol Change of Flag Value
(Blank) Unchanged
0 Cleared to 0
1 Set to 1
× Set/cleared according to the result
R Previously saved value is restored
40.1.4 PREFIX instruction

Instructions with “ES:” have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space
(00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX
operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation
code is executed as the addresses with the ES register value added.
A interrupt and DTC transfer are not acknowledged between a PREFIX instruction code and the instruction immediately
after.
Table 40-4. Use Example of PREFIX Operation Code
Instruction Opcode
1 2 3 4 5
MOV !addr16, #byte CFH !addr16 #byte –

MOV ES:!addr16, #byte 11H CFH !addr16 #byte
MOV A, [HL] 8BH – – – –
MOV A, ES:[HL] 11H 8BH – – –
Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction.
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40.2 Operation List
Table 40-5. Operation List (1/18)
Instruction Mnemonic Operands Bytes Clocks Clocks Flag

Group
Note 1 Note 2 Z AC CY
8-bit data MOV r, #byte 2 1 – r ← byte
transfer × × ×
PSW, #byte 3 3 – PSW ← byte
CS, #byte 3 1 – CS ← byte
ES, #byte 2 1 – ES ← byte
!addr16, #byte 4 1 – (addr16) ← byte
ES:!addr16, #byte 5 2 – (ES, addr16) ← byte
saddr, #byte 3 1 – (saddr) ← byte
sfr, #byte 3 1 – sfr ← byte
[DE+byte], #byte 3 1 – (DE+byte) ← byte
ES:[DE+byte],#byte 4 2 – ((ES, DE)+byte) ← byte
[HL+byte], #byte 3 1 – (HL+byte) ← byte
ES:[HL+byte],#byte 4 2 – ((ES, HL)+byte) ← byte
[SP+byte], #byte 3 1 – (SP+byte) ← byte
word[B], #byte 4 1 – (B+word) ← byte
ES:word[B], #byte 5 2 – ((ES, B)+word) ← byte
word[C], #byte 4 1 – (C+word) ← byte
ES:word[C], #byte 5 2 – ((ES, C)+word) ← byte
word[BC], #byte 4 1 – (BC+word) ← byte
ES:word[BC], #byte 5 2 – ((ES, BC)+word) ← byte
Note 3
A, r 1 1 – A←r
Note 3
r, A 1 1 – r←A
A, PSW 2 1 – A ← PSW
PSW, A 2 3 – PSW ← A × × ×
A, CS 2 1 – A ← CS
CS, A 2 1 – CS ← A
A, ES 2 1 – A ← ES
ES, A 2 1 – ES ← A
A, !addr16 3 1 4 A ← (addr16)
A, ES:!addr16 4 2 5 A ← (ES, addr16)
!addr16, A 3 1 – (addr16) ← A
ES:!addr16, A 4 2 – (ES, addr16) ← A
A, saddr 2 1 – A ← (saddr)
saddr, A 2 1 – (saddr) ← A
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the code flash area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Group
8-bit data MOV A, sfr 2 1 – A ← sfr

transfer
sfr, A 2 1 – sfr ← A
A, [DE] 1 1 4 A ← (DE)
[DE], A 1 1 – (DE) ← A
A, ES:[DE] 2 2 5 A ← (ES, DE)
ES:[DE], A 2 2 – (ES, DE) ← A
A, [HL] 1 1 4 A ← (HL)
[HL], A 1 1 – (HL) ← A
A, ES:[HL] 2 2 5 A ← (ES, HL)
ES:[HL], A 2 2 – (ES, HL) ← A
A, [DE+byte] 2 1 4 A ← (DE + byte)
[DE+byte], A 2 1 – (DE + byte) ← A
A, ES:[DE+byte] 3 2 5 A ← ((ES, DE) + byte)
ES:[DE+byte], A 3 2 – ((ES, DE) + byte) ← A
A, [HL+byte] 2 1 4 A ← (HL + byte)
[HL+byte], A 2 1 – (HL + byte) ← A
A, ES:[HL+byte] 3 2 5 A ← ((ES, HL) + byte)
ES:[HL+byte], A 3 2 – ((ES, HL) + byte) ← A
A, [SP+byte] 2 1 – A ← (SP + byte)
[SP+byte], A 2 1 – (SP + byte) ← A
A, word[B] 3 1 4 A ← (B + word)
word[B], A 3 1 – (B + word) ← A
A, ES:word[B] 4 2 5 A ← ((ES, B) + word)
ES:word[B], A 4 2 – ((ES, B) + word) ← A
A, word[C] 3 1 4 A ← (C + word)
word[C], A 3 1 – (C + word) ← A
A, ES:word[C] 4 2 5 A ← ((ES, C) + word)
ES:word[C], A 4 2 – ((ES, C) + word) ← A
A, word[BC] 3 1 4 A ← (BC + word)
word[BC], A 3 1 – (BC + word) ← A
A, ES:word[BC] 4 2 5 A ← ((ES, BC) + word)
ES:word[BC], A 4 2 – ((ES, BC) + word) ← A
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Group
8-bit data MOV A, [HL+B] 2 1 4 A ← (HL + B)

transfer
[HL+B], A 2 1 – (HL + B) ← A
A, ES:[HL+B] 3 2 5 A ← ((ES, HL) + B)
ES:[HL+B], A 3 2 – ((ES, HL) + B) ← A
A, [HL+C] 2 1 4 A ← (HL + C)
[HL+C], A 2 1 – (HL + C) ← A
A, ES:[HL+C] 3 2 5 A ← ((ES, HL) + C)
ES:[HL+C], A 3 2 – ((ES, HL) + C) ← A
X, !addr16 3 1 4 X ← (addr16)
X, ES:!addr16 4 2 5 X ← (ES, addr16)
X, saddr 2 1 – X ← (saddr)
B, !addr16 3 1 4 B ← (addr16)
B, ES:!addr16 4 2 5 B ← (ES, addr16)
B, saddr 2 1 – B ← (saddr)
C, !addr16 3 1 4 C ← (addr16)
C, ES:!addr16 4 2 5 C ← (ES, addr16)
C, saddr 2 1 – C ← (saddr)
ES, saddr 3 1 – ES ← (saddr)

Note 3
XCH A, r 1 (r = X) 1 – A ←→ r
2 (other
than r =
X)
A, !addr16 4 2 – A ←→ (addr16)
A, ES:!addr16 5 3 – A ←→ (ES, addr16)
A, saddr 3 2 – A ←→ (saddr)
A, sfr 3 2 – A ←→ sfr
A, [DE] 2 2 – A ←→ (DE)
A, ES:[DE] 3 3 – A ←→ (ES, DE)
A, [HL] 2 2 – A ←→ (HL)
A, ES:[HL] 3 3 – A ←→ (ES, HL)
A, [DE+byte] 3 2 – A ←→ (DE + byte)
A, ES:[DE+byte] 4 3 – A ←→ ((ES, DE) + byte)
A, [HL+byte] 3 2 – A ←→ (HL + byte)
A, ES:[HL+byte] 4 3 – A ←→ ((ES, HL) + byte)
3. Except r = A
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Group
8-bit data XCH A, [HL+B] 2 2 – A ←→ (HL+B)

transfer
A, ES:[HL+B] 3 3 – A ←→ ((ES, HL)+B)
A, [HL+C] 2 2 – A ←→ (HL+C)
A, ES:[HL+C] 3 3 – A ←→ ((ES, HL)+C)
ONEB A 1 1 – A ← 01H
X 1 1 – X ← 01H
B 1 1 – B ← 01H
C 1 1 – C ← 01H
!addr16 3 1 – (addr16) ← 01H
ES:!addr16 4 2 – (ES, addr16) ← 01H
saddr 2 1 – (saddr) ← 01H
CLRB A 1 1 – A ← 00H
X 1 1 – X ← 00H
B 1 1 – B ← 00H
C 1 1 – C ← 00H
!addr16 3 1 – (addr16) ← 00H
ES:!addr16 4 2 – (ES,addr16) ← 00H
saddr 2 1 – (saddr) ← 00H
MOVS [HL+byte], X 3 1 – (HL+byte) ← X × ×
ES:[HL+byte], X 4 2 – (ES, HL+byte) ← X × ×
16-bit MOVW rp, #word 3 1 – rp ← word

data
saddrp, #word 4 1 – (saddrp) ← word
transfer
sfrp, #word 4 1 – sfrp ← word
Note 3
AX, rp 1 1 – AX ← rp
Note 3
rp, AX 1 1 – rp ← AX
AX, !addr16 3 1 4 AX ← (addr16)
!addr16, AX 3 1 – (addr16) ← AX
AX, ES:!addr16 4 2 5 AX ← (ES, addr16)
ES:!addr16, AX 4 2 – (ES, addr16) ← AX
AX, saddrp 2 1 – AX ← (saddrp)
saddrp, AX 2 1 – (saddrp) ← AX
AX, sfrp 2 1 – AX ← sfrp
sfrp, AX 2 1 – sfrp ← AX
3. Except rp = AX
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Group
16-bit MOVW AX, [DE] 1 1 4 AX ← (DE)

data
[DE], AX 1 1 – (DE) ← AX
transfer
AX, ES:[DE] 2 2 5 AX ← (ES, DE)
ES:[DE], AX 2 2 – (ES, DE) ← AX
AX, [HL] 1 1 4 AX ← (HL)
[HL], AX 1 1 – (HL) ← AX
AX, ES:[HL] 2 2 5 AX ← (ES, HL)
ES:[HL], AX 2 2 – (ES, HL) ← AX
AX, [DE+byte] 2 1 4 AX ← (DE+byte)
[DE+byte], AX 2 1 – (DE+byte) ← AX
AX, ES:[DE+byte] 3 2 5 AX ← ((ES, DE) + byte)
ES:[DE+byte], AX 3 2 – ((ES, DE) + byte) ← AX
AX, [HL+byte] 2 1 4 AX ← (HL + byte)
[HL+byte], AX 2 1 – (HL + byte) ← AX
AX, ES:[HL+byte] 3 2 5 AX ← ((ES, HL) + byte)
ES:[HL+byte], AX 3 2 – ((ES, HL) + byte) ← AX
AX, [SP+byte] 2 1 – AX ← (SP + byte)
[SP+byte], AX 2 1 – (SP + byte) ← AX
AX, word[B] 3 1 4 AX ← (B + word)
word[B], AX 3 1 – (B+ word) ← AX
AX, ES:word[B] 4 2 5 AX ← ((ES, B) + word)
ES:word[B], AX 4 2 – ((ES, B) + word) ← AX
AX, word[C] 3 1 4 AX ← (C + word)
word[C], AX 3 1 – (C + word) ← AX
AX, ES:word[C] 4 2 5 AX ← ((ES, C) + word)
ES:word[C], AX 4 2 – ((ES, C) + word) ← AX
AX, word[BC] 3 1 4 AX ← (BC + word)
word[BC], AX 3 1 – (BC + word) ← AX
AX, ES:word[BC] 4 2 5 AX ← ((ES, BC) + word)
ES:word[BC], AX 4 2 – ((ES, BC) + word) ← AX
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Group
16-bit MOVW BC, !addr16 3 1 4 BC ← (addr16)

data
BC, ES:!addr16 4 2 5 BC ← (ES, addr16)
transfer
DE, !addr16 3 1 4 DE ← (addr16)
DE, ES:!addr16 4 2 5 DE ← (ES, addr16)
HL, !addr16 3 1 4 HL ← (addr16)
HL, ES:!addr16 4 2 5 HL ← (ES, addr16)
BC, saddrp 2 1 – BC ← (saddrp)
DE, saddrp 2 1 – DE ← (saddrp)
HL, saddrp 2 1 – HL ← (saddrp)

Note 3
XCHW AX, rp 1 1 – AX ←→ rp
ONEW AX 1 1 – AX ← 0001H
BC 1 1 – BC ← 0001H
CLRW AX 1 1 – AX ← 0000H
BC 1 1 – BC ← 0000H
8-bit ADD A, #byte 2 1 – A, CY ← A + byte × × ×

operation
saddr, #byte 3 2 – (saddr), CY ← (saddr)+byte × × ×
Note 4
A, r 2 1 – A, CY ← A + r × × ×
r, A 2 1 – r, CY ← r + A × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16) × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16) × × ×
A, saddr 2 1 – A, CY ← A + (saddr) × × ×
A, [HL] 1 1 4 A, CY ← A+ (HL) × × ×
A, ES:[HL] 2 2 5 A,CY ← A + (ES, HL) × × ×
A, [HL+byte] 2 1 4 A, CY ← A + (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A + ((ES, HL)+byte) × × ×
A, [HL+B] 2 1 4 A, CY ← A + (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A+((ES, HL)+B) × × ×
A, [HL+C] 2 1 4 A, CY ← A + (HL+C) × × ×
A, ES:[HL+C] 3 2 5 A,CY ← A + ((ES, HL) + C) × × ×
3. Except rp = AX
4. Except r = A
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Group
8-bit ADDC A, #byte 2 1 – A, CY ← A+byte+CY × × ×

operation
saddr, #byte 3 2 – (saddr), CY ← (saddr) +byte+CY × × ×
Note 3
A, rv 2 1 – A, CY ← A + r + CY × × ×
r, A 2 1 – r, CY ← r + A + CY × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16)+CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16)+CY × × ×
A, saddr 2 1 – A, CY ← A + (saddr)+CY × × ×
A, [HL] 1 1 4 A, CY ← A+ (HL) + CY × × ×
A, ES:[HL] 2 2 5 A,CY ← A+ (ES, HL) + CY × × ×
A, [HL+byte] 2 1 4 A, CY ← A+ (HL+byte) + CY × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A+ ((ES, HL)+byte) + CY × × ×
A, [HL+B] 2 1 4 A, CY ← A+ (HL+B) +CY × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A+((ES, HL)+B)+CY × × ×
A, [HL+C] 2 1 4 A, CY ← A+ (HL+C)+CY × × ×
A, ES:[HL+C] 3 2 5 A,CY ← A+ ((ES, HL)+C)+CY × × ×
SUB A, #byte 2 1 – A, CY ← A – byte × × ×
saddr, #byte 3 2 – (saddr), CY ← (saddr) – byte × × ×

Note 3
A, r 2 1 – A, CY ← A – r × × ×
r, A 2 1 – r, CY ← r – A × × ×
A, !addr16 3 1 4 A, CY ← A – (addr16) × × ×
A, ES:!addr16 4 2 5 A, CY ← A – (ES, addr16) × × ×
A, saddr 2 1 – A, CY ← A – (saddr) × × ×
A, [HL] 1 1 4 A, CY ← A – (HL) × × ×
A, ES:[HL] 2 2 5 A,CY ← A – (ES, HL) × × ×
A, [HL+byte] 2 1 4 A, CY ← A – (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A – ((ES, HL)+byte) × × ×
A, [HL+B] 2 1 4 A, CY ← A – (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A – ((ES, HL)+B) × × ×
A, [HL+C] 2 1 4 A, CY ← A – (HL+C) × × ×
A, ES:[HL+C] 3 2 5 A,CY ← A – ((ES, HL)+C) × × ×
3. Except r = A
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Group
8-bit SUBC A, #byte 2 1 – A, CY ← A – byte – CY × × ×

operation
saddr, #byte 3 2 – (saddr), CY ← (saddr) – byte – CY × × ×
Note 3
A, r 2 1 – A, CY ← A – r – CY × × ×
r, A 2 1 – r, CY ← r – A – CY × × ×
A, !addr16 3 1 4 A, CY ← A – (addr16) – CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A – (ES, addr16) – CY × × ×
A, saddr 2 1 – A, CY ← A – (saddr) – CY × × ×
A, [HL] 1 1 4 A, CY ← A – (HL) – CY × × ×
A, ES:[HL] 2 2 5 A,CY ← A – (ES, HL) – CY × × ×
A, [HL+byte] 2 1 4 A, CY ← A – (HL+byte) – CY × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A – ((ES, HL)+byte) – CY × × ×
A, [HL+B] 2 1 4 A, CY ← A – (HL+B) – CY × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A – ((ES, HL)+B) – CY × × ×
A, [HL+C] 2 1 4 A, CY ← A – (HL+C) – CY × × ×
A, ES:[HL+C] 3 2 5 A, CY ← A – ((ES:HL)+C) – CY × × ×
AND A, #byte 2 1 – A ← A  byte ×
saddr, #byte 3 2 – (saddr) ← (saddr)  byte ×
A, r Note 3
2 1 – A←Ar ×
r, A 2 1 – R←rA ×
A, !addr16 3 1 4 A ← A  (addr16) ×
A, ES:!addr16 4 2 5 A ← A  (ES:addr16) ×
A, saddr 2 1 – A ← A  (saddr) ×
A, [HL] 1 1 4 A ← A  (HL) ×
A, ES:[HL] 2 2 5 A ← A  (ES:HL) ×
A, [HL+byte] 2 1 4 A ← A  (HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A  ((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A  (HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A  ((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A  (HL+C) ×
A, ES:[HL+C] 3 2 5 A ← A  ((ES:HL)+C) ×
3. Except r = A
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Group
8-bit OR A, #byte 2 1 – A ← Abyte ×

operation
saddr, #byte 3 2 – (saddr) ← (saddr)byte ×
Note 3
A, r 2 1 – A ← Ar ×
r, A 2 1 – r ← rA ×
A, !addr16 3 1 4 A ← A(addr16) ×
A, ES:!addr16 4 2 5 A ← A(ES:addr16) ×
A, saddr 2 1 – A ← A(saddr) ×
A, [HL] 1 1 4 A ← A(H) ×
A, ES:[HL] 2 2 5 A ← A(ES:HL) ×
A, [HL+byte] 2 1 4 A ← A(HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A(HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A(HL+C) ×
A, ES:[HL+C] 3 2 5 A ← A((ES:HL)+C) ×
XOR A, #byte 2 1 – A ← Abyte ×
saddr, #byte 3 2 – (saddr) ← (saddr)byte ×

Note 3
A, r 2 1 – A ← Ar ×
r, A 2 1 – r ← rA ×
A, !addr16 3 1 4 A ← A(addr16) ×
A, ES:!addr16 4 2 5 A ← A(ES:addr16) ×
A, saddr 2 1 – A ← A(saddr) ×
A, [HL] 1 1 4 A ← A(HL) ×
A, ES:[HL] 2 2 5 A ← A(ES:HL) ×
A, [HL+byte] 2 1 4 A ← A(HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A(HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A(HL+C) ×
A, ES:[HL+C] 3 2 5 A ← A((ES:HL)+C) ×
3. Except r = A
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Group
8-bit CMP A, #byte 2 1 – A – byte × × ×

operation
!addr16, #byte 4 1 4 (addr16) – byte × × ×
ES:!addr16, #byte 5 2 5 (ES:addr16) – byte × × ×
saddr, #byte 3 1 – (saddr) – byte × × ×

Note3
A, r 2 1 – A–r × × ×
r, A 2 1 – r–A × × ×
A, !addr16 3 1 4 A – (addr16) × × ×
A, ES:!addr16 4 2 5 A – (ES:addr16) × × ×
A, saddr 2 1 – A – (saddr) × × ×
A, [HL] 1 1 4 A – (HL) × × ×
A, ES:[HL] 2 2 5 A – (ES:HL) × × ×
A, [HL+byte] 2 1 4 A – (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A – ((ES:HL)+byte) × × ×
A, [HL+B] 2 1 4 A – (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A – ((ES:HL)+B) × × ×
A, [HL+C] 2 1 4 A – (HL+C) × × ×
A, ES:[HL+C] 3 2 5 A – ((ES:HL)+C) × × ×
CMP0 A 1 1 – A – 00H × 0 0
X 1 1 – X – 00H × 0 0
B 1 1 – B – 00H × 0 0
C 1 1 – C – 00H × 0 0
!addr16 3 1 4 (addr16) – 00H × 0 0
ES:!addr16 4 2 5 (ES:addr16) – 00H × 0 0
saddr 2 1 – (saddr) – 00H × 0 0
CMPS X, [HL+byte] 3 1 4 X – (HL+byte) × × ×
X, ES:[HL+byte] 4 2 5 X – ((ES:HL)+byte) × × ×
3. Except r = A
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Group
16-bit ADDW AX, #word 3 1 – AX, CY ← AX+word × × ×

operation
AX, AX 1 1 – AX, CY ← AX+AX × × ×
AX, BC 1 1 – AX, CY ← AX+BC × × ×
AX, DE 1 1 – AX, CY ← AX+DE × × ×
AX, HL 1 1 – AX, CY ← AX+HL × × ×
AX, !addr16 3 1 4 AX, CY ← AX+(addr16) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX+(ES:addr16) × × ×
AX, saddrp 2 1 – AX, CY ← AX+(saddrp) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX+(HL+byte) × × ×
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX+((ES:HL)+byte) × × ×
SUBW AX, #word 3 1 – AX, CY ← AX – word × × ×
AX, BC 1 1 – AX, CY ← AX – BC × × ×
AX, DE 1 1 – AX, CY ← AX – DE × × ×
AX, HL 1 1 – AX, CY ← AX – HL × × ×
AX, !addr16 3 1 4 AX, CY ← AX – (addr16) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX – (ES:addr16) × × ×
AX, saddrp 2 1 – AX, CY ← AX – (saddrp) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX – (HL+byte) × × ×
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX – ((ES:HL)+byte) × × ×
CMPW AX, #word 3 1 – AX – word × × ×
AX, BC 1 1 – AX – BC × × ×
AX, DE 1 1 – AX – DE × × ×
AX, HL 1 1 – AX – HL × × ×
AX, !addr16 3 1 4 AX – (addr16) × × ×
AX, ES:!addr16 4 2 5 AX – (ES:addr16) × × ×
AX, saddrp 2 1 – AX – (saddrp) × × ×
AX, [HL+byte] 3 1 4 AX – (HL+byte) × × ×
AX, ES: [HL+byte] 4 2 5 AX – ((ES:HL)+byte) × × ×
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Instruction Mnemonic Operands Bytes Clocks Operation Flag

Group Note 1 Note 2 Z AC CY
Multiply, MULU X 1 1 – AX ← A × X
Divide,
MULHU 3 2 – BCAX ← AX × BC (unsigned)
Multiply &
accumu- MULH 3 2 – BCAX ← AX × BC (signed)
late
DIVHU 3 9 – AX (quotient), DE (remainder) ←
AX ÷ DE (unsigned)
DIVWU 3 17 – BCAX (quotient), HLDE (remainder) ←
BCAX ÷ HLDE (unsigned)
MACHU 3 3 – MACR ← MACR + AX × BC (unsigned) × ×
MACH 3 3 – MACR ← MACR + AX × BC(signed) × ×
Caution Disable interrupts when executing the DIVHU or DIVWU instruction in an interrupt servicing routine.
Alternatively, unless they are executed in the RAM area, note that execution of a DIVHU or DIVWU
instruction is possible even with interrupts enabled as long as a NOP instruction is added immediately
after the DIVHU or DIVWU instruction in the assembly language source code. The following compilers
automatically add a NOP instruction immediately after any DIVHU or DIVWU instruction output during
the build process.
- V. 1.71 and later versions of the CA78K0R (Renesas Electronics compiler), for both C and
assembly language source code
- Service pack 1.40.6 and later versions of the EWRL78 (IAR compiler), for C language source
code
- GNURL78 (KPIT compiler), for C language source code
Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the
instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
2. MACR indicates the multiplication and accumulation register (MACRH, MACRL).
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Group
Increment/ INC r 1 1 – r ← r+1 × ×

decrement
!addr16 3 2 – (addr16) ← (addr16)+1 × ×
ES:!addr16 4 3 – (ES, addr16) ← (ES, addr16)+1 × ×
saddr 2 2 – (saddr) ← (saddr)+1 × ×
[HL+byte] 3 2 – (HL+byte) ← (HL+byte)+1 × ×
ES: [HL+byte] 4 3 – ((ES:HL)+byte) ← ((ES:HL)+byte)+1 × ×
DEC r 1 1 – r←r–1 × ×
!addr16 3 2 – (addr16) ← (addr16) – 1 × ×
ES:!addr16 4 3 – (ES, addr16) ← (ES, addr16) – 1 × ×
saddr 2 2 – (saddr) ← (saddr) – 1 × ×
[HL+byte] 3 2 – (HL+byte) ← (HL+byte) – 1 × ×
ES: [HL+byte] 4 3 – ((ES:HL)+byte) ← ((ES:HL)+byte) – 1 × ×
INCW rp 1 1 – rp ← rp+1
!addr16 3 2 – (addr16) ← (addr16)+1
ES:!addr16 4 3 – (ES, addr16) ← (ES, addr16)+1
saddrp 2 2 – (saddrp) ← (saddrp)+1
[HL+byte] 3 2 – (HL+byte) ← (HL+byte)+1
ES: [HL+byte] 4 3 – ((ES:HL)+byte) ← ((ES:HL)+byte)+1
DECW rp 1 1 – rp ← rp – 1
!addr16 3 2 – (addr16) ← (addr16) – 1
ES:!addr16 4 3 – (ES, addr16) ← (ES, addr16) – 1
saddrp 2 2 – (saddrp) ← (saddrp) – 1
[HL+byte] 3 2 – (HL+byte) ← (HL+byte) – 1
ES: [HL+byte] 4 3 – ((ES:HL)+byte) ← ((ES:HL)+byte) – 1
Shift SHR A, cnt 2 1 – (CY ← A0, Am-1 ← Am, A7 ← 0) ×cnt ×
SHRW AX, cnt 2 1 – (CY ← AX0, AXm-1 ← AXm, AX15 ← 0) ×cnt ×
SHL A, cnt 2 1 – (CY ← A7, Am ← Am-1, A0 ← 0) ×cnt ×
B, cnt 2 1 – (CY ← B7, Bm ← Bm-1, B0 ← 0) ×cnt ×
C, cnt 2 1 – (CY ← C7, Cm ← Cm-1, C0 ← 0) ×cnt ×
SHLW AX, cnt 2 1 – (CY ← AX15, AXm ← AXm-1, AX0 ← 0) ×cnt ×
BC, cnt 2 1 – (CY ← BC15, BCm ← BCm-1, BC0 ← 0) ×cnt ×
SAR A, cnt 2 1 – (CY ← A0, Am-1 ← Am, A7 ← A7) ×cnt ×
SARW AX, cnt 2 1 – (CY ← AX0, AXm-1 ← AXm, AX15 ← AX15) ×cnt ×
Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
2. cnt indicates the bit shift count.
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Group
Rotate ROR A, 1 2 1 – (CY, A7 ← A0, Am-1 ← Am)×1 ×
ROL A, 1 2 1 – (CY, A0 ← A7, Am+1 ← Am)×1 ×
RORC A, 1 2 1 – (CY ← A0, A7 ← CY, Am-1 ← Am)×1 ×
ROLC A, 1 2 1 – (CY ← A7, A0 ← CY, Am+1 ← Am)×1 ×
ROLWC AX,1 2 1 – (CY ← AX15, AX0 ← CY, AXm+1 ← AXm) ×1 ×
BC,1 2 1 – (CY ← BC15, BC0 ← CY, BCm+1 ← BCm) ×1 ×
Bit MOV1 CY, A.bit 2 1 – CY ← A.bit ×

manipulate
A.bit, CY 2 1 – A.bit ← CY
CY, PSW.bit 3 1 – CY ← PSW.bit ×
PSW.bit, CY 3 4 – PSW.bit ← CY × ×
CY, saddr.bit 3 1 – CY ← (saddr).bit ×
saddr.bit, CY 3 2 – (saddr).bit ← CY
CY, sfr.bit 3 1 – CY ← sfr.bit ×
sfr.bit, CY 3 2 – sfr.bit ← CY
CY,[HL].bit 2 1 4 CY ← (HL).bit ×
[HL].bit, CY 2 2 – (HL).bit ← CY
CY, ES:[HL].bit 3 2 5 CY ← (ES, HL).bit ×
ES:[HL].bit, CY 3 3 – (ES, HL).bit ← CY
AND1 CY, A.bit 2 1 – CY ← CY  A.bit ×
CY, PSW.bit 3 1 – CY ← CY  PSW.bit ×
CY, saddr.bit 3 1 – CY ← CY  (saddr).bit ×
CY, sfr.bit 3 1 – CY ← CY  sfr.bit ×
CY,[HL].bit 2 1 4 CY ← CY  (HL).bit ×
CY, ES:[HL].bit 3 2 5 CY ← CY  (ES, HL).bit ×
OR1 CY, A.bit 2 1 – CY ← CY  A.bit ×
CY, PSW.bit 3 1 – CY ← CY  PSW.bit ×
CY, saddr.bit 3 1 – CY ← CY  (saddr).bit ×
CY, sfr.bit 3 1 – CY ← CY  sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY  (HL).bit ×
CY, ES:[HL].bit 3 2 5 CY ← CY  (ES, HL).bit ×
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Group
Bit XOR1 CY, A.bit 2 1 – CY ← CY  A.bit ×

manipulate
CY, PSW.bit 3 1 – CY ← CY  PSW.bit ×
CY, saddr.bit 3 1 – CY ← CY  (saddr).bit ×
CY, sfr.bit 3 1 – CY ← CY  sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY  (HL).bit ×
CY, ES:[HL].bit 3 2 5 CY ← CY  (ES, HL).bit ×
SET1 A.bit 2 1 – A.bit ← 1
PSW.bit 3 4 – PSW.bit ← 1 × × ×
!addr16.bit 4 2 – (addr16).bit ← 1
ES:!addr16.bit 5 3 – (ES, addr16).bit ← 1
saddr.bit 3 2 – (saddr).bit ← 1
sfr.bit 3 2 – sfr.bit ← 1
[HL].bit 2 2 – (HL).bit ← 1
ES:[HL].bit 3 3 – (ES, HL).bit ← 1
CLR1 A.bit 2 1 – A.bit ← 0
PSW.bit 3 4 – PSW.bit ← 0 × × ×
!addr16.bit 4 2 – (addr16).bit ← 0
ES:!addr16.bit 5 3 – (ES, addr16).bit ← 0
saddr.bit 3 2 – (saddr.bit) ← 0
sfr.bit 3 2 – sfr.bit ← 0
[HL].bit 2 2 – (HL).bit ← 0
ES:[HL].bit 3 3 – (ES, HL).bit ← 0
SET1 CY 2 1 – CY ← 1 1
CLR1 CY 2 1 – CY ← 0 0
NOT1 CY 2 1 – CY ← CY ×
when no data is accessed
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Group
Call/ CALL rp 2 3 – (SP – 2) ← (PC+2)S, (SP – 3) ← (PC+2)H,

return (SP – 4) ← (PC+2)L, PC ← CS, rp,
SP ← SP – 4
$!addr20 3 3 – (SP – 2) ← (PC+3)S, (SP – 3) ← (PC+3)H,

(SP – 4) ← (PC+3)L, PC ← PC+3+jdisp16,
SP ← SP – 4
!addr16 3 3 – (SP – 2) ← (PC+3)S, (SP – 3) ← (PC+3)H,

(SP – 4) ← (PC+3)L, PC ← 0000, addr16,
SP ← SP – 4
!!addr20 4 3 – (SP – 2) ← (PC+4)S, (SP – 3) ← (PC+4)H,

(SP – 4) ← (PC+4)L, PC ← addr20,
SP ← SP – 4
CALLT [addr5] 2 5 – (SP – 2) ← (PC+2)S , (SP – 3) ← (PC+2)H,

(SP – 4) ← (PC+2)L , PCS ← 0000,
PCH ← (0000, addr5+1),
PCL ← (0000, addr5),
SP ← SP – 4
BRK – 2 5 – (SP – 1) ← PSW, (SP – 2) ← (PC+2)S,

(SP – 3) ← (PC+2)H, (SP – 4) ← (PC+2)L,
PCS ← 0000,
PCH ← (0007FH), PCL ← (0007EH),
SP ← SP – 4, IE ← 0
RET – 1 6 – PCL ← (SP), PCH ← (SP+1),

PCS ← (SP+2), SP ← SP+4
RETI – 2 6 – PCL ← (SP), PCH ← (SP+1), R R R

PCS ← (SP+2), PSW← (SP+3),
SP ← SP+4
RETB – 2 6 – PCL ← (SP), PCH ← (SP+1), R R R

PCS ← (SP+2), PSW ← (SP+3),
SP ← SP+4
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Group
Stack PUSH PSW 2 1 – (SP – 1) ← PSW, (SP – 2) ← 00H,

manipulate SP ← SP–2
rp 1 1 – (SP – 1) ← rpH, (SP – 2) ← rpL,

SP ← SP – 2
POP PSW 2 3 – PSW ← (SP+1), SP ← SP + 2 R R R
rp 1 1 – rpL ←(SP), rpH ← (SP+1), SP ← SP + 2
MOVW SP, #word 4 1 – SP ← word
SP, AX 2 1 – SP ← AX
AX, SP 2 1 – AX ← SP
HL, SP 3 1 – HL ← SP
BC, SP 3 1 – BC ← SP
DE, SP 3 1 – DE ← SP
ADDW SP, #byte 2 1 – SP ← SP + byte
SUBW SP, #byte 2 1 – SP ← SP – byte
Un- BR AX 2 3 – PC ← CS, AX
conditional
$addr20 2 3 – PC ← PC + 2 + jdisp8
branch
$!addr20 3 3 – PC ← PC + 3 + jdisp16
!addr16 3 3 – PC ← 0000, addr16
!!addr20 4 3 – PC ← addr20
Conditional BC $addr20 2 2/4 Note3 – PC ← PC + 2 + jdisp8 if CY = 1

branch
BNC $addr20 2 2/4 Note3 – PC ← PC + 2 + jdisp8 if CY = 0
Note3
BZ $addr20 2 2/4 – PC ← PC + 2 + jdisp8 if Z = 1
Note3
BNZ $addr20 2 2/4 – PC ← PC + 2 + jdisp8 if Z = 0
Note3
BH $addr20 3 2/4 – PC ← PC + 3 + jdisp8 if (ZCY) = 0
Note3
BNH $addr20 3 2/4 – PC ← PC + 3 + jdisp8 if (ZCY) = 1
Note3
BT saddr.bit, $addr20 4 3/5 – PC ← PC + 4 + jdisp8 if (saddr).bit = 1
sfr.bit, $addr20 4 3/5 Note3 – PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr20 3 3/5 Note3 – PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr20 4 3/5 Note3 – PC ← PC + 4 + jdisp8 if PSW.bit = 1

Note3
[HL].bit, $addr20 3 3/5 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 1
Note3
ES:[HL].bit, 4 4/6 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
$addr20
3. This indicates the number of clocks “when condition is not met/when condition is met”.
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Group
Note3
Condition BF saddr.bit, $addr20 4 3/5 – PC ← PC + 4 + jdisp8 if (saddr).bit = 0
al branch Note3
sfr.bit, $addr20 4 3/5 – PC ← PC + 4 + jdisp8 if sfr.bit = 0
Note3
A.bit, $addr20 3 3/5 – PC ← PC + 3 + jdisp8 if A.bit = 0
Note3
PSW.bit, $addr20 4 3/5 – PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr20 3 3/5 Note3 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 0
ES:[HL].bit, 4 4/6 Note3 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0

$addr20
BTCLR saddr.bit, $addr20 4 3/5 Note3 – PC ← PC + 4 + jdisp8 if (saddr).bit = 1

then reset (saddr).bit
sfr.bit, $addr20 4 3/5 Note3 – PC ← PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit
A.bit, $addr20 3 3/5 Note3 – PC ← PC + 3 + jdisp8 if A.bit = 1

then reset A.bit
Note3
PSW.bit, $addr20 4 3/5 – PC ← PC + 4 + jdisp8 if PSW.bit = 1 × × ×
then reset PSW.bit
Note3
[HL].bit, $addr20 3 3/5 – PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
Note3
ES:[HL].bit, 4 4/6 – PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
$addr20 then reset (ES, HL).bit
Conditional SKC – 2 1 – Next instruction skip if CY = 1

skip
SKNC – 2 1 – Next instruction skip if CY = 0
SKZ – 2 1 – Next instruction skip if Z = 1
SKNZ – 2 1 – Next instruction skip if Z = 0
SKH – 2 1 – Next instruction skip if (ZCY)=0
SKNH – 2 1 – Next instruction skip if (ZCY)=1
CPU SEL Note4 RBn 2 1 – RBS[1:0] ← n

control
NOP – 1 1 – No Operation
EI – 3 4 – IE ← 1 (Enable Interrupt)
DI – 3 4 – IE ← 0 (Disable Interrupt)
HALT – 2 3 – Set HALT Mode
STOP – 2 3 – Set STOP Mode
3. This indicates the number of clocks “when condition is not met/when condition is met”.
4. n indicates the number of register banks (n = 0 to 3).
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RL78/I1C CHAPTER 41 ELECTRICAL SPECIFICATIONS
CHAPTER 41 ELECTRICAL SPECIFICATIONS
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for
each product.
Remarks 1. In the descriptions in this chapter, read EVDD as EVDD0 and EVDD1, and EVSS as EVSS0 and EVSS1.
2. For 64-pin products, read EVDD as VDD and EVSS as VSS.
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41.1 Absolute Maximum Ratings
Absolute Maximum Ratings (1/3)

Parameter Symbols Conditions Ratings Unit
Supply voltage VDD –0.5 to +6.5 V

EVDD –0.5 to +6.5 V
VBAT –0.5 to +6.5 V
VRTC –0.5 to +6.5 V
REGC pin input voltage VIREGC REGC –0.3 to +2.8 V
and –0.3 to VDDNote 4 +0.3Note 1
Input voltage VI1 P02 to P07, P10 to P17, P30 to P37, P40 to P43, –0.3 to EVDD +0.3 V
P50 to P57, P70 to P77, P80 to P85, and –0.3 to VDDNote 4 +0.3Note 2
P125 to P127
VI2 P60 to P62 (N-ch open-drain) –0.3 to +6.5 V
Note 4 Note 2
VI3 P20 to P25, P121 to P122, P137, P150 to 152, –0.3 to VDD +0.3 V
EXCLK
VI4 RESET –0.3 to +6.5 V
VI5 P123, P124, EXCLKS –0.3 to VRTC +0.3Note 2 V
Output voltage VO1 P02 to P07, P10 to P17, P30 to P37, P40 to P43, –0.3 to EVDD +0.3 V
P50 to P57, P60 to P62, P70 to P77, P80 to P85, and –0.3 to VDDNote 4 +0.3Note 2
P125 to P127
VO2 P20 to P25, P150 to P152 –0.3 to VDDNote 4 +0.3 Note 2 V
Note 4
Analog input voltage VAI1 ANI0 to ANI5 –0.3 to VDD +0.3 V
and –0.3 to AVREF(+) +0.3Notes 2, 3
VAI2 ANIP0 to ANIP3, ANIN0 to ANIN3 –0.6 to +2.8 V
and –0.6 to AREGC +0.3Note 5
Reference supply VIDSAD AREGC, AVCM, AVRT –0.3 to +2.8 V
voltage and –0.3 to VDDNote 4 +0.3Note 6
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin.
4. Either V DD or VBAT is selected by the battery backup function.
5. The ΔΣ A/D conversion target pin must not exceed AREGC +0.3 V.
6. Connect AREGC, AVCM, and AVRT terminals to V SS via capacitor (0.47 µF).
This value defines the absolute maximum rating of AREGC, AVCM, and AVRT terminal. Do not use
with voltage applied.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. VSS: Reference voltage
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Note 1
LCD voltage VLI1 VL1 voltage –0.3 to 2.8 V
and –0.3 to VL4 +0.3
VLI2 VL2 voltageNote 1 –0.3 to VL4 +0.3Note 2 V
VLI3 VL3 voltageNote 1 –0.3 to VL4 +0.3Note 2 V
VLI4 VL4 voltageNote 1 –0.3 to +6.5 V
Note 1 Note 2
VLCAP CAPL, CAPH voltage –0.3 to VL4 +0.3 V
Note 3 Note 2
VOUT COM0 to COM7, External resistance division –0.3 to VDD +0.3 V
SEG0 to SEG41, method
output voltage Capacitor split method –0.3 to VDDNote 3 +0.3Note 2 V
Note 2
Internal voltage boosting method –0.3 to VL4 +0.3 V
Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the V L1 , VL2 , V L3 ,
and V L4 pins; it does not mean that applying voltage to these pins is recommended. When using
the internal voltage boosting method or capacitance split method, connect these pins to V SS via a
capacitor (0.47 µF ± 30%) and connect a capacitor (0.47 µF ± 30%) between the CAPL and CAPH
pins.
2. Must be 6.5 V or lower.
3. Either VDD or VBAT is selected by the battery backup function.
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark VSS: Reference voltage
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Output current, high IOH1 Per pin P02 to P07, P10 to P17, P30 to –40 mA
P37, P40 to P43, P50 to P57, P70
to P77, P80 to P85, P125 to P127
Total of all pins P02 to P07, P40 to P43 –70 mA
–170 mA P10 to P17, P30 to P37, P50 to –100 mA
P57, P70 to P77, P80 to P85,
P125 to P127
IOH2 Per pin P20 to P25, P150 to P152 –0.5 mA
Total of all pins –2 mA
Output current, low IOL1 Per pin P02 to P07, P10 to P17, P30 to 40 mA
P37, P40 to P43, P50 to P57, P70
to P77, P80 to P85, P125 to P127
Total of all pins P02 to P07, P40 to P43 70 mA
170 mA P10 to P17, P30 to P37, P50 to 100 mA
P57, P60 to P62, P70 to P77, P80
to P85, P125 to P127
IOL2 Per pin P20 to P25, P150 to P152 1 mA
Total of all pins 5 mA
Operating ambient TA In normal operation mode –40 to +85 °C
temperature In flash memory programming mode
Storage temperature Tstg –65 to +150 °C
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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41.2 Oscillator Characteristics
41.2.1 X1, XT1 oscillator characteristics
(TA = –40 to +85°C, 1.7 V ≤ VDDNote 2 ≤ 5.5 V, VSS = 0 V)

Parameter Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation Ceramic resonator/ 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
frequency (fX)Notes 1, 2 crystal resonator 2.5 V ≤ VDD < 2.7 V 1.0 16.0 MHz
2.4 V ≤ VDD < 2.5 V 1.0 12.0 MHz
1.9 V ≤ VDD < 2.4 V 1.0 8.0 MHz
1.7 V ≤ VDD < 1.9 V 1.0 4.0 MHz
XT1 clock oscillation Crystal resonator 32 32.768 35 kHz
frequency (fXT)Notes 1, 2
Notes 1. Indicates only permissible oscillator frequency ranges. See 41.4 AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, see 6.4 System Clock Oscillator.
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41.2.2 On-chip oscillator characteristics

Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator fIH 1.5 24 MHz

clock frequencyNotes 1, 2
High-speed on-chip oscillator –20 to +85°C 1.9 V ≤ VDDNote 3 ≤ 5.5 V –1.0 +1.0 %
clock frequency accuracy 1.7 V ≤ VDD Note 3
≤ 1.9 V –5.0 +5.0 %
–40 to –20°C 1.9 V ≤ VDDNote 3 ≤ 5.5 V –1.5 +1.5 %
1.7 V ≤ VDDNote 3 ≤ 1.9 V –5.5 +5.5 %
Middle-speed on-chip oscillator fIM 1 4 MHz
clock frequencyNote 2
Middle-speed on-chip oscillator 1.9 V ≤ VDDNote 3 ≤ 5.5 V –12 +12 %
clock frequency accuracy
Low-speed on-chip oscillator fIL 15 kHz
clock frequency
Low-speed on-chip oscillator –15 +15 %
clock frequency accuracy
Notes 1. The high-speed on-chip oscillator frequency is selected by using bits 0 to 3 of option byte (000C2H/010C2H)
and bits 0 to 2 of the HOCODIV register.
2. This indicates the oscillator characteristics only. See 41.4 AC Characteristics for the instruction execution
time.
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41.2.3 PLL oscillator characteristics

Oscillators Parameters Conditions MIN. TYP. MAX. Unit
Note 1
PLL input frequency fPLLIN fIH 4 MHz
Note 1
PLL output frequency fPLL 32 MHz
Lockup wait time Wait time from PLL output enable to frequency 40 µs
stabilization
Interval wait time Wait time from PLL stop to PLL restart setting 4 µs
Setting wait time Wait time from PLL input clock stabilization and 1 µs
PLL setting fixedness to start-up setting
Notes 1. Indicates only permissible oscillator frequency ranges.

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41.3 DC Characteristics
41.3.1 Pin characteristics
(TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
<R> Output current, IOH1 Per pin for P02 to P07, P10 to P17, P30 to 1.9 V ≤ EVDD ≤ 5.5 V –10.0Note 2 mA
highNote 1 P37, P40 to P43, P50 to P57, P70 to P77,
P80 to P85, P125 to P127
Total of P02 to P07, P40 to P43 4.0 V ≤ EVDD ≤ 5.5 V –55.0 mA
(When duty ≤ 70%Note 3) 2.7 V ≤ EVDD < 4.0 V –10.0 mA
1.9 V ≤ EVDD < 2.7 V –5.0 mA
1.7 V ≤ EVDD < 1.9 V –2.5 mA
Total of P10 to P17, P30 to P37, P50 to 4.0 V ≤ EVDD ≤ 5.5 V –80.0 mA
P57, P70 to P77, P80 to P85, P125 to 2.7 V ≤ EVDD < 4.0 V –19.0 mA
P127
1.9 V ≤ EVDD < 2.7 V –10.0 mA
(When duty ≤ 70%Note 3)
1.7 V ≤ EVDD < 1.9 V –5.0 mA
Total of all pins –100.0 mA
IOH2 Per pin for P20 to P25, P150 to P152 1.7 V ≤ VDDNote 4 ≤ 5.5 V –0.1Note 2 mA
Note 4
Total of all pins 1.7 V ≤ VDD ≤ 5.5 V –0.9 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD and
VDD pins to an output pin.
2. Do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = –10.0 mA
Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 do not output high level in N-ch
open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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<R> Output current, IOL1 Per pin for P02 to P07, P10 to P17, 20.0Note 2 mA
lowNote 1 P30 to P37, P40 to P43, P50 to P57,
P70 to P77, P80 to P85, P125 to
P127
Per pin for P60 to P62 15.0Note 2 mA
Total of P02 to P07, P40 to P43 4.0 V ≤ EVDD ≤ 5.5 V 70.0 mA
(When duty ≤ 70%Note 3) 2.7 V ≤ EVDD < 4.0 V 15.0 mA
1.9 V ≤ EVDD < 2.7 V 9.0 mA
1.7 V ≤ EVDD < 1.9 V 4.5 mA
Total of P10 to P17, P30 to P37, 4.0 V ≤ EVDD ≤ 5.5 V 80.0 mA
P50 to P57, P60 to P62, P70 to P77, 2.7 V ≤ EVDD < 4.0 V 35.0 mA
P80 to P85, P125 to P127
(When duty ≤ 70%Note 3) 1.9 V ≤ EVDD < 2.7 V 20.0 mA
1.7 V ≤ EVDD < 1.9 V 10.0 mA
Total of all pins 150.0 mA
IOL2 Per pin for P20 to P25, P150 to P152 1.7 V ≤ VDDNote 4 ≤ 5.5 V 0.4Note 2 mA
Note 4
Total of all pins 1.7 V ≤ VDD ≤ 5.5 V 3.6 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the EVSS and VSS pins.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
pins.
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(TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Input voltage, VIH1 P02 to P07, P10 to P17, P30 to P37, Normal input buffer 0.8EVDD EVDD V
high P40 to P43, P50 to P57, P70 to P77,
P80 to P85, P125 to P127
VIH2 P02, P03, P05, P06, P12, P13, P15, TTL input buffer 2.2 EVDD V
P16, P30, P55, P57, P80, P81, P84 4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer 2.0 EVDD V
3.3 V ≤ EVDD < 4.0 V
TTL input buffer 1.5 EVDD V
1.7 V ≤ EVDD < 3.3 V
VIH3 P20 to P25 0.7VDDNote VDDNote V
VIH4 P60 to P62 0.7EVDD 6.0 V
Note Note
VIH5 P121 to P122, P137, P150 to P152, EXCLK 0.8VDD VDD V
Note
VIH6 RESET 0.8VDD 6.0 V
VIH7 P123, P124, EXCLKS 0.8VRTC VRTC V
Input voltage, VIL1 P02 to P07, P10 to P17, P30 to P37, Normal input buffer 0 0.2EVDD V
low P40 to P43, P50 to P57, P70 to P77,
P80 to P85, P125 to P127
VIL2 P02, P03, P05, P06, P12, P13, P15, TTL input buffer 0 0.8 V
P16, P30, P55, P57, P80, P81, P84 4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer 0 0.5 V
3.3 V ≤ EVDD < 4.0 V
TTL input buffer 0 0.32 V
1.7 V ≤ EVDD < 3.3 V
VIL3 P20 to P25 0 0.3VDDNote V
VIL4 P60 to P62 0 0.3EVDD V
Note
VIL5 P121, P122, P137, P150 to P152, EXCLK, RESET 0 0.2VDD V
VIL6 P123, P124, EXCLKS 0 0.2VRTC V
Note Either V DD or VBAT is selected by the battery backup function.
Caution The maximum value of VIH of pins P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 is
EVDD, even in the N-ch open-drain mode.
pins.
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Output voltage, VOH1 P02 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD ≤ 5.5 V, EVDD – 1.5 V
high P40 to P43, P50 to P57, P70 to P77, IOH1 = –10.0 mA
P80 to P85, P125 to P127 4.0 V ≤ EVDD ≤ 5.5 V, EVDD – 0.7 V
IOH1 = –3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V, EVDD – 0.6 V
IOH1 = –2.0 mA
1.9 V ≤ EVDD ≤ 5.5 V, EVDD – 0.5 V
IOH1 = –1.5 mA
1.7 V ≤ EVDD ≤ 5.5 V, EVDD – 0.5 V
IOH1 = –1.0 mA
VOH2 P20 to P25, P150 to P152 1.7 V ≤ VDDNote ≤ 5.5 V, VDD – 0.5 V
IOH2 = –100 µA
Output voltage, VOL1 P02 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD ≤ 5.5 V, 1.3 V
low P40 to P43, P50 to P57, P70 to P77, IOL1 = 20 mA
P80 to P85, P125 to P127 4.0 V ≤ EVDD ≤ 5.5 V, 0.7 V
IOL1 = 8.5 mA
2.7 V ≤ EVDD ≤ 5.5 V, 0.6 V
IOL1 = 3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL1 = 1.5 mA
1.9 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL1 = 0.6 mA
1.7 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL1 = 0.3 mA
VOL2 P20 to P25, P150 to P152 1.7 V ≤ VDDNote ≤ 5.5 V, 0.4 V
IOL2 = 400 µA
VOL3 P60 to P62 4.0 V ≤ EVDD ≤ 5.5 V, 2.0 V
IOL3 = 15.0 mA
4.0 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL3 = 5.0 mA
2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL3 = 3.0 mA
1.9 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL3 = 2.0 mA
1.7 V ≤ EVDD ≤ 5.5 V, 0.4 V
IOL3 = 1.0 mA
Caution P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 do not output high level in N-ch
open-drain mode.
pins.
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Input leakage ILIH1 P02 to P07, P10 to P17, P30 to P37, VI = EVDD 1 µA
current, high P40 to P43, P50 to P57, P60 to P62,
P70 to P77, P80 to P85, P125 to P127
ILIH2 P20 to P25, P137, P150 to P152, VI = VDDNote 1 µA
RESET
ILIH3 P121, P122 VI = VDDNote In input port or external 1 µA
(X1, X2, EXCLK) clock input
In resonator connection 10 µA
ILIH4 P123, P124 VI = VRTC In input port or external 1 µA
(EXCLKS) clock input
In resonator connection 10 µA
Input leakage ILIL1 P02 to P07, P10 to P17, P30 to P37, VI = EVSS –1 µA
current, low P40 to P43, P50 to P57, P70 to P77,
P80 to P85, P125 to P127
ILIL2 P20 to P25, P137, P150 to P152, VI = VSS –1 µA
RESET
ILIL3 P121, P122 VI = VSS In input port or external –1 µA
(X1, X2, EXCLK) clock input
In resonator connection –10 µA
ILIL4 P123, P124 VI = VSS In input port or external –1 µA
(EXCLKS) clock input
In resonator connection –10 µA
On-chip pull- RU1 P10 to P17, P30 to P37, P50 to P57, VI = EVSS 2.4 V ≤ EVDD ≤ 5.5 V 10 20 100 kΩ
up resistance P70 to P77, P80 to P85, P125 to P127 1.7 V ≤ EVDD ≤ 5.5 V 10 30 100 kΩ
RU2 P02 to P07, P40 to P43, P150 to P152 VI = EVSS 10 20 100 kΩ
pins.
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41.3.2 Supply current characteristics
(TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 8 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Note 3
Supply IDD1 Operating HS (high- fCLK = 32 MHz Normal VDD = 5.0 V 5.2 8.5 mA
currentNote 1 mode speed main) PLL operation operation VDD = 3.0 V 5.2 8.5 mA
modeNote 5 Note 3
fIH = 24 MHz Basic VDD = 5.0 V 1.7 mA
operation VDD = 3.0 V 1.7 mA
Normal VDD = 5.0 V 3.9 6.6 mA
operation VDD = 3.0 V 3.9 6.6 mA
fIH = 12 MHzNote 3 Normal VDD = 5.0 V 2.4 3.8 mA
Note 3
LS (low- fIH = 8 MHz Normal VDD = 3.0 V 1.3 2.2 mA
speed main) operation VDD = 2.0 V 1.3 2.2 mA
modeNote 5
Note 6
fIM = 4 MHz Normal VDD = 3.0 V 0.70 1.20 mA
LV (low- fIH = 4 MHzNote 3 Normal VDD = 3.0 V 1.3 1.9 mA
voltage main) operation VDD = 2.0 V 1.3 1.9 mA
modeNote 5
LP (low- fIH = 1 MHzNote 3 Normal VDD = 3.0 V 315 530 µA
power main) operation VDD = 2.0 V 315 530 µA
modeNote 5
fIM = 1 MHzNote 6 Normal VDD = 3.0 V 160 300 µA
operation VDD = 2.0 V 160 300 µA
(Notes and Remarks are listed on the page after the next page.)
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Note 2
Supply IDD1 Operating HS (high- fMX = 20 MHz , Normal Square wave input 3.3 5.5 mA
currentNote 1 mode speed main) VDD = 5.0 V operation Resonator connection 3.5 5.7 mA
modeNote 5
fMX = 20 MHzNote 2, Normal Square wave input 3.3 5.5 mA
VDD = 3.0 V operation Resonator connection 3.5 5.7 mA
LS (low- fMX = 8 MHzNote 2, Normal Square wave input 1.1 2.0 mA
speed main) VDD = 3.0 V operation Resonator connection 1.2 2.1 mA
modeNote 5
LP (low- fIH = 1 MHzNote 2, Normal Square wave input 140 240 µA
power main) VDD = 3.0 V operation Resonator connection 190 300 µA
modeNote 5
fIH = 1 MHzNote 2, Normal Square wave input 140 240 µA
VDD = 2.0 V operation Resonator connection 190 300 µA
Subclock fSUB = 32.768 kHzNote 4, Normal Square wave input 5.1 6.6 µA
operation TA = –40°C operation Resonator connection 5.2 6.7 µA
fSUB = 32.768 kHzNote 4, Normal Square wave input 5.4 7.1 µA
TA = +25°C operation Resonator connection 5.5 7.2 µA
fIL = 15 kHz, Normal 2.5 7.0 µA
TA = +85°C Note 7 operation
TA = –40°C Note 7 operation
TA =+ 25°C Note 7 operation
(Notes and Remarks are listed on the next page.)
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Notes 1. Total current flowing into VDD, EVDD, and VRTC including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, ΔΣ
A/D converter, LVD circuit, battery backup circuit, I/O port, and on-chip pull-up/pull-down resistors. When the
VBAT pin (pin for battery backup) is selected, current flowing into VBAT.
2. When high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and
subsystem clock are stopped.
3. When high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem
clock are stopped.
4. When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped.
When setting ultra-low current consumption (AMPHS1 = 1). However, not including the current flowing into
Independent power supply RTC, 12-bit interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.8 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.5 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 12 MHz
2.1 V ≤ VDD ≤ 5.5 V@1 MHz to 6 MHz
LS (low-speed main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LP (low-power main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz
LV (low-voltage main) mode: 1.7 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
6. When high-speed on-chip oscillator, low-speed on-chip oscillator, high-speed system clock, and subsystem
clock are stopped.
7. When high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem
clock are stopped.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fIM: Middle-speed on-chip oscillator clock frequency
4. fIL: Low-speed on-chip oscillator clock frequency
5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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Note 2 Note 4
Supply I
DD2 HALT HS (high- fCLK = 32 MHz , VDD = 5.0 V 0.80 2.0 mA
currentNote 1 mode speed main) PLL operation VDD = 3.0 V 0.80 2.0 mA
modeNote 7
fIH = 24 MHzNote 4 VDD = 5.0 V 0.48 1.45 mA
VDD = 3.0 V 0.48 1.45 mA
VDD = 3.0 V 0.37 0.91 mA
VDD = 3.0 V 0.32 0.63 mA
VDD = 3.0 V 0.29 0.49 mA
Note 4
LS (low- fIH = 8 MHz VDD = 3.0 V 280 740 µA
speed main) VDD = 2.0 V 280 740 µA
modeNote 7
fIH = 6 MHzNote 4 VDD = 3.0 V 230 620 µA
VDD = 2.0 V 230 620 µA
Note 4
fIH = 4 MHz VDD = 3.0 V 220 440 µA
VDD = 2.0 V 220 440 µA
Note 9
fIM = 4 MHz VDD = 3.0 V 55 300 µA
VDD = 2.0 V 55 300 µA
Note 4
fIH = 3 MHz VDD = 3.0 V 200 534 µA
VDD = 2.0 V 200 534 µA
LV (low- fIH = 4 MHzNote 4 VDD = 3.0 V 450 825 µA
voltage VDD = 2.0 V 450 825 µA
main)
modeNote 7
LP (low- fIH = 1 MHzNote 4 VDD = 3.0 V 195 400 µA
power main) VDD = 2.0 V 195 400 µA
modeNote 7
fIM = 1 MHzNote 9 VDD = 3.0 V 33 100 µA
VDD = 2.0 V 33 100 µA
HS (high- fMX = 20 MHzNote 3, Square wave input 0.31 1.08 mA
speed main) VDD = 5.0 V Resonator connection 0.48 1.28 mA
modeNote 7
fMX = 20 MHzNote 3, Square wave input 0.31 1.08 mA
VDD = 3.0 V Resonator connection 0.48 1.28 mA
(Notes and Remarks are listed on the page after the next page.)
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Note 2 Note 3
Supply I
DD2 HALT LS (low- fMX = 8 MHz , Square wave input 110 360 µA
currentNote 1 mode speed main) VDD = 3.0 V Resonator connection 160 420 µA
modeNote 7
fMX = 8 MHzNote 3, Square wave input 110 360 µA
VDD = 2.0 V Resonator connection 160 420 µA
Note 3
fMX = 4 MHz , Square wave input 39 200 µA
Note 3
fMX = 4 MHz , Square wave input 39 200 µA
LP (low- fMX = 1 MHzNote 3, Square wave input 14 100 µA
power main) VDD = 3.0 V Resonator connection 70 200 µA
modeNote 7
fMX = 1 MHzNote 3, Square wave input 14 100 µA
Subsystem fSUB = 32.768 kHzNote 5, Square wave input 0.80 1.60 µA
clock TA = –40°C Resonator connection 1.00 1.80 µA
operation
fSUB = 32.768 kHzNote 5, Square wave input 0.93 1.70 µA
TA = +25°C Resonator connection 1.13 1.90 µA
fIL = 15 kHzNote 9, 0.78 1.60 µA
TA = –40°C µA
fIL = 15 kHzNote 9, 1.01 1.76 µA
TA = +25°C µA
fIL = 15 kHzNote 9, 2.25 8.45 µA
TA = +85°C µA
IDD3Note 6 STOP TA = –40°C 0.47 0.90 µA
modeNote 8 TA = +25°C 0.65 1.20 µA
TA = +50°C 0.84 2.80 µA
TA = +70°C 1.21 4.70 µA
TA = +85°C 1.82 9.00 µA
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Notes 1. Total current flowing into VDD, EVDD, and VRTC including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, ΔΣ
A/D converter, LVD circuit, battery backup circuit, I/O port, and on-chip pull-up/pull-down resistors. When the
VBAT pin (pin for battery backup) is selected, current flowing into VBAT.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and
subsystem clock are stopped.
4. When high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem
clock are stopped.
5. When operating independent power supply RTC and setting ultra-low current consumption (AMPHS1 = 1).
When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. However, not
including the current flowing into independent power supply RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.8 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.5 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 12 MHz
2.1 V ≤ VDD ≤ 5.5 V@1 MHz to 6 MHz
LS (low-speed main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LP (low-power main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz
LV (low-voltage main) mode: 1.7 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
8. If operation of the subsystem clock when STOP mode, same as when HALT mode of subsystem clock
operation.
9. When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fIM: Middle-speed on-chip oscillator clock frequency
4. fIL: Low-speed on-chip oscillator clock frequency
6. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
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Notes 3
Independent IRTC fSUB = 32.768 kHz 0.70 µA
power supply
RTC operating
current
12-bit interval ITMKANotes 1, 2, 4 fSUB = 32.768 kHz, fMAIN is stopped 0.04 µA
timer operating
current
8-bit interval ITMTNotes 1, 2, 5 fSUB = 32.768 kHz, 8-bit counter mode × 2 ch operation 0.12 µA
timer operating fMAIN is stopped,
16-bit counter mode operation 0.10 µA
current per unit
Watchdog timer IWDTNotes 1, 2, 6 fIL = 15 kHz, fMAIN is stopped 0.22 µA
operating current
LVD operating ILVDNotes 1, 7 0.10 µA
current
LVDVDD ILVDVDD Current flowing to VDD 0.05 µA
operating current Current flowing to VDD or VBAT Note 1
0.04 µA
LVDVBAT ILVDVBAT Current flowing to VBAT 0.04 µA
0.04 µA
LVDVRTC ILVDVRTC Current flowing to VRTC 0.04 µA
operating current Current flowing to VDD or VBATNote 1 0.04 µA
LVDEXLVD ILVDEXLVD Current flowing to EXLVD 0.16 µA
0.04 µA
Note 1
Oscillation stop IOSDC 0.02 µA
detection circuit
operating current
Battery backup IBUPNote 1 0.05 µA
circuit operating
current
A/D converter IADCNotes 1, 8 When Normal mode, AVREFP = VDD = 5.0 V 1.3 2.4 mA
operating current conversion at Low voltage mode, AVREFP = VDD = 3.0 V 0.5 1.0 mA
maximum
speed
A/D converter IADREFNote 1 75.0 µA
reference voltage
current
Temperature ITMPSNote 1 105 µA
sensor operating
current
BGO operating IBGONotes 1, 9 2.00 12.20 mA
current
Self- IFSPNotes 1, 10 2.00 12.20 mA
programming
operating current
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Notes 1, 11
24-Bit ΔΣ A/D IDSAD In 4 ch ΔΣ A/D converter operation 1.45 2.30 mA
Converter
In 3 ch ΔΣ A/D converter operation 1.14 1.85 mA
operating
current In 1 ch ΔΣA/D converter operation 0.52 0.94 mA
SNOOZE ISNOZNotes 1, 12 ADC operation The mode is performed 0.50 0.80 mA

operating
The A/D conversion operations are 1.20 1.80 mA
current
performed, low voltage mode, AVREFP =
VDD = 3.0 V
CSI/UART operation 0.70 1.05 mA
DTC operation 2.20 mA
LCD ILCD1Notes 1, 13, 14 External fLCD = fSUB VDD = 5.0 V, 0.06 µA

operating resistance LCD clock = 128 Hz VL4 = 5.0 V
current division method 1/3 bias, four-time-slices
Notes 1, 13
I LCD2 Internal voltage fLCD = fSUB VDD = 3.0 V, 0.85 µA
boosting method LCD clock = 128 Hz VL4 = 3.0 V
1/3 bias, four-time-slices (VLCD = 04H)
VDD = 5.0 V, 1.55 µA
VL4 = 5.1 V
(VLCD = 12H)
Notes 1, 13
I LCD3 Capacitor split fLCD = fSUB VDD = 3.0 V, 0.20 µA
method LCD clock = 128 Hz VL4 = 3.0 V
1/3 bias, four-time-slices
Notes 1. Current flowing to VDD. When the VBAT pin (battery backup power supply pin) is selected, current flowing to
the VBAT.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing to VRTC pin, including RTC power supply, subsystem clock oscillator circuit, and RTC.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and XT1 oscillator). The value of the current value of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and XT1 oscillator). The value of the current value of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and ITMT, when the 8-bit interval timer operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added.
6. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer
operates.
7 Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ILVD when the LVD circuit operates.
8. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
9. Current flowing only during rewrite of 1 KB data flash memory.
10.Current flowing only during self programming.
11.Current flowing only to the 24-bit ΔΣ A/D converter. The current value of the RL78 microcontrollers is the sum
of IDD1 or IDD2, and IDSAD when the 24-bit ΔΣ A/D converter operates.
12.For shift time to the SNOOZE mode, see 26.3.3 SNOOZE mode.
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Notes 13. Current flowing only to the LCD controller/driver. The current value of the RL78 microcontrollers is the sum of
the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or IDD2) when the LCD
controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the
LCD panel. Conditions of the TYP. value and MAX. value are as follows.
● Setting 20 pins as the segment function and blinking all
● Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H)
● Setting four time slices and 1/3 bias
14. Not including the current flowing into the external division resistor when using the external resistance division
method.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency

3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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41.4 AC Characteristics
Note 1
Instruction cycle (minimum TCY Main system HS (high-speed 2.8 V ≤ VDD ≤ 5.5 V 0.03125 1 µs
instruction execution time) clock (fMAIN) main) mode Note 1
2.7 V ≤ VDD < 2.8 V 0.04167 1 µs
operation
Note 1
2.5 V ≤ VDD < 2.7 V 0.0625 1 µs
Note 1
2.4 V ≤ VDD < 2.5 V 0.08333 1 µs
Note 1
2.1 V ≤ VDD < 2.4 V 0.16667 1 µs
Note 1
LS (low-speed 1.9 V ≤ VDD ≤ 5.5 V 0.125 1 µs
main) mode
LS (low-speed 1.9 V ≤ VDDNote 1 ≤ 5.5 V 0.25 1 µs

main) mode
@4 MHz
LP (low-power 1.9 V ≤ VDDNote 1 ≤ 5.5 V 1 2 µs
main) mode
LV (low-voltage 1.7 V ≤ VDDNote 1 ≤ 5.5 V 0.25 1 µs

main) mode
Subsystem clock (fSUB) 1.9 V ≤ VDDNote 1 ≤ 5.5 V 28.5 30.5 31.3 µs
operation
In the self HS (high-speed 2.8 V ≤ VDDNote 1 ≤ 5.5 V 0.03125 1 µs
programming main) mode 2.7 V ≤ VDD Note 1
< 2.8 V 0.04167 1 µs
mode
2.5 V ≤ VDDNote 1 < 2.7 V 0.0625 1 µs
2.4 V ≤ VDDNote 1 < 2.5 V 0.08333 1 µs
Note 1
2.1 V ≤ VDD < 2.4 V 0.16667 1 µs
Note 1
LS (low-speed 1.9 V ≤ VDD ≤ 5.5 V 0.125 1 µs
main) mode
LV (low-voltage 1.7 V ≤ VDDNote 1 ≤ 5.5 V 0.25 1 µs
main) mode
External system clock fEX 2.7 V ≤ VDDNote 1 ≤ 5.5 V 1 20 MHz
frequency 2.5 V ≤ VDD Note 1
< 2.7 V 1 16 MHz
Note 1
2.4 V ≤ VDD < 2.5 V 1 12 MHz
1.9 V ≤ VDDNote 1 < 2.4 V 1 8 MHz
1.7 V ≤ VDDNote 1 < 1.9 V 1 4 MHz
fEXS 32 35 kHz
Note 1
External system clock input tEXH, 2.7 V ≤ VDD ≤ 5.5 V 24 ns
high-level width, low-level tEXL 2.5 V ≤ VDD Note 1
< 2.7 V 30 ns
width
Note 1
2.4 V ≤ VDD < 2.5 V 40 ns
Note 1
1.9 V ≤ VDD < 2.4 V 60 ns
Note 1
1.7 V ≤ VDD < 1.9 V 120 ns
tEXHS, 13.7 µs
tEXLS
TI00 to TI07 input high-level tTIH, 1/fMCK+10 nsNote 2
width, low-level width tTIL
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TO00 to TO07 output fTO HS (high-speed main) 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz
frequency mode 2.7 V ≤ EVDD < 4.0 V 8 MHz
2.4 V ≤ EVDD < 2.7 V 4 MHz
2.1 V ≤ EVDD < 2.4 V 4 MHz
LS (low-speed main) 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz
mode
LP (low-power main) 1.9 V ≤ EVDD ≤ 5.5 V 0.5 MHz
mode
LV (low-voltage main) 1.7 V ≤ EVDD ≤ 5.5 V 2 MHz
mode
PCLBUZ0, PCLBUZ1 output fPCL HS (high-speed main) 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz
frequency mode 2.7 V ≤ EVDD < 4.0 V 8 MHz
2.4 V ≤ EVDD < 2.7 V 4 MHz
2.1 V ≤ EVDD < 2.4 V 4 MHz
LS (low-speed main) 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz
mode
LP (low-power main) 1.9 V ≤ EVDD ≤ 5.5 V 1 MHz
mode
LV (low-voltage main) 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz
mode 1.7 V ≤ EVDD < 1.9 V 2 MHz
Note 1
Interrupt input high-level tINTH, INTP0 1.7 V ≤ VDD ≤ 5.5 V 1 µs
width, low-level width tINTL INTP1 to INTP7 1.7 V ≤ EVDD ≤ 5.5 V 1 µs
Key interrupt input low-level tKR KR0 to KR7 1.9 V ≤ EVDD ≤ 5.5 V 250 ns
width 1.7 V ≤ EVDD < 1.9 V 1 µs
RESET low-level width tRSL 10 µs
Notes 1. Either V DD or VBAT is selected by the battery backup function.
2. The following conditions are required for low voltage interface:
1.9 V ≤ VDD < 2.7 V: MIN. 125 ns
Remark fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn)
m: Unit number (m = 0), n: Channel number (n = 0 to 7))
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AC Timing Test Points
VIH/VOH VIH/VOH
Test points
VIL/VOL VIL/VOL
External System Clock Timing
1/fEX
tEXL tEXH
0.7VDD (MIN.)
EXCLK
0.3VDD (MAX.)
1/fEXS
tEXLS tEXHS
0.7VRTC (MIN.)
EXCLKS
0.3VRTC (MAX.)
TI/TO Timing
tTIL tTIH
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
tINTL tINTH
INTP0 to INTP7
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Key interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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41.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH VIH/VOH
Test points
VIL/VOL VIL/VOL
41.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage Unit
main) Mode main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Note 2 Note Note 2
Transfer 2.4 V ≤ VDD ≤ 5.5 V fMCK/6 fMCK/6 fMCK/6 fMCK/6Note 2 bps
Note 1 2
rate
Theoretical value of the 4.0 1.3 0.1 0.6 Mbps
maximum transfer rate
fMCK = fCLKNote 3
1.9 V ≤ VDD ≤ 5.5 V fMCK/6Note 2 fMCK/6Note fMCK/6Note 2 fMCK/6Note 2 bps
2

fMCK = fCLKNote 3
1.8 V ≤ VDD ≤ 5.5 V fMCK/6Note 2 fMCK/6Note fMCK/6Note 2 fMCK/6Note 2 bps
2

fMCK = fCLKNote 3
1.7 V ≤ VDD ≤ 5.5 V fMCK/6Note 2 bps
Theoretical value of the 0.6 Mbps
fMCK = fCLKNote 3
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. The following conditions are required for low voltage interface.
2.4 V ≤ EVDD < 2.7 V: MAX. 2.6 Mbps
1.9 V ≤ EVDD < 2.4 V: MAX. 1.3 Mbps
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.8 V ≤ EVDD ≤ 5.5 V), 24 MHz (2.7 V ≤ EVDD ≤ 5.5 V),
16 MHz (2.5 V ≤ EVDD ≤ 5.5 V), 12 MHz (2.4 V ≤ EVDD ≤ 5.5 V),
6 MHz (2.1 V ≤ EVDD ≤ 5.5 V),
LS (low-speed main) mode: 8 MHz (1.9 V ≤ EVDD ≤ 5.5 V), 4 MHz (1.9 V ≤ EVDD ≤ 5.5 V)
LP (low-power main) mode: 1 MHz (1.9 V ≤ EVDD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.7 V ≤ EVDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
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UART mode connection diagram (during communication at same potential)
TxDq Rx
RL78/I1C
User’s device
microcontrollers
RxDq Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8)

2. fMCK: Serial array unit operation clock frequency
(Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
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(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 125 500 4000 1000 ns
2.4 V ≤ EVDD ≤ 5.5 V 250 500 4000 1000 ns
1.9 V ≤ EVDD ≤ 5.5 V 500 500 4000 1000 ns
1.8 V ≤ EVDD ≤ 5.5 V 1000 1000 4000 1000 ns
1.7 V ≤ EVDD ≤ 5.5 V 1000 4000 1000 ns
SCKp tKH1, 4.0 V ≤ EVDD ≤ 5.5 V tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
high-/low-level tKL1 2 – 12 2 – 50 2 – 50 2 – 50
width 2.7 V ≤ EVDD ≤ 5.5 V tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
2 – 18 2 – 50 2 – 50 2 – 50
2.4 V ≤ EVDD ≤ 5.5 V tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
2 – 38 2 – 50 2 – 50 2 – 50
2 – 50 2 – 50 2 – 50 2 – 50
1.8 V ≤ EVDD ≤ 5.5 V tKCY1/ tKCY1/ tKCY1/ ns
2 – 100 2 – 100 2 – 100
2 – 100 2 – 100 2 – 100
SIp setup time (to tSIK1 4.0 V ≤ EVDD ≤ 5.5 V 44 110 110 110 ns
SCKp↑)Note 1 2.7 V ≤ EVDD ≤ 5.5 V 44 110 110 110 ns
2.4 V ≤ EVDD ≤ 5.5 V 75 110 110 110 ns
1.9 V ≤ EVDD ≤ 5.5 V 110 110 110 110 ns
1.8 V ≤ EVDD ≤ 5.5 V 220 220 220 220 ns
1.7 V ≤ EVDD ≤ 5.5 V 220 220 220 ns
SIp hold time tKSI1 1.8 V ≤ EVDD ≤ 5.5 V 19 19 19 19 ns
(from SCKp↑)Note 2 1.7 V ≤ EVDD ≤ 5.5 V 19 19 19 ns
Delay time from tKSO1 C = 30 1.8 V ≤ EVDD 25 25 25 25 ns
SCKp↓ to SOp pFNote 3 ≤ 5.5 V
outputNote 3 1.7 V ≤ EVDD 25 25 25 ns
≤ 5.5 V
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↑”
3. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10, 30), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 0, 1, 8)
m: Unit number, n: Channel number (mn = 00, 10, 30))
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(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Parameter Symb Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage Unit
ol main) Mode main) Mode main) Mode main) Mode
SCKp cycle tKCY2 4.0 V ≤ 20 MHz < fMCK 8/fMCK – – – ns

timeNote 4 EVDD ≤ fMCK ≤ 20 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK ns
5.5 V
2.7 V ≤ 16 MHz < fMCK 8/fMCK – – – ns
EVDD ≤ fMCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK ns
5.5 V
2.4 V ≤ EVDD ≤ 5.5 V 6/fMCK 6/fMCK 6/fMCK 6/fMCK ns
and 500 and 500 and 500 and 500
and 750 and 750 and 750 and 750
and 1500 and 1500 and 1500 and 1500
1.7 V ≤ EVDD ≤ 5.5 V 6/fMCK 6/fMCK 6/fMCK ns
and 1500 and 1500 and 1500
SCKp tKH2, 4.0 V ≤ EVDD ≤ 5.5 V tKCY2/ tKCY2/ tKCY2/ tKCY2/ ns
high-/low- tKL2 2–7 2–7 2–7 2–7
level width 2.7 V ≤ EVDD ≤ 5.5 V tKCY2/ tKCY2/ tKCY2/ tKCY2/ ns
2–8 2–8 2–8 2–8
2 – 18 2 – 18 2 – 18 2 – 18
2 – 66 2 – 66 2 – 66 2 – 66
2 – 66 2 – 66 2 – 66
SIp setup tSIK2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK+20 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns
time (to 1.9 V ≤ EVDD ≤ 5.5 V 1/fMCK+30 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns
SCKp↑)Note 1
1.8 V ≤ EVDD ≤ 5.5 V 1/fMCK+40 1/fMCK+40 1/fMCK+40 1/fMCK+40 ns
1.7 V ≤ EVDD ≤ 5.5 V 1/fMCK+40 1/fMCK+40 1/fMCK+40 ns
SIp hold tKSI2 2.1 V ≤ EVDD ≤ 5.5 V 1/fMCK+31 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns
time (from 1.9 V ≤ EVDD ≤ 5.5 V 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns
SCKp↑)Note 1
1.7 V ≤ EVDD ≤ 5.5 V 1/fMCK+250 ns
Delay time tKSO2 C = 30 2.7 V ≤ EVDD ≤ 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ ns
from SCKp↓ pFNote 3 5.5 V 44 110 110 110
to SOp
2.4 V ≤ EVDD ≤ 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ ns
outputNote 2
5.5 V 75 110 110 110

5.5 V 100 110 110 110
5.5 V 220 220 220 220
1.7 V ≤ EVDD ≤ 2/fMCK+ 2/fMCK+ 2/fMCK+ ns

5.5 V 220 220 220
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Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
3. C is the load capacitance of the SOp output lines.
4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10, 30), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM number (g = 0, 1, 8)
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CSI mode connection diagram (during communication at same potential)
SCKp SCK
RL78/I1C SIp SO User’s device

microcontrollers
SOp SI
CSI mode serial transfer timing (during communication at same potential)

(when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
tKCY1, 2
tKL1, 2 tKH1, 2
SCKp
tSIK1, 2 tKSI1, 2
SIp Input data
tKSO1, 2
SOp Output data
CSI mode serial transfer timing (during communication at same potential)

tKCY1, 2
tKH1, 2 tKL1, 2
SCKp
tSIK1, 2 tKSI1, 2
SIp Input data
tKSO1, 2
SOp Output data
Remarks 1. p: CSI number (p = 00, 10, 30)

2. m: Unit number, n: Channel number (mn = 00, 10, 30)
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(4) During communication at same potential (simplified I2C mode)

Parameter Symbol Conditions HS (high-speed main) LS (low-speed LP (low-power LV (low-voltage Unit
Mode main) Mode main) Mode main) Mode
SCLr clock fSCL 2.7 V ≤ EVDD ≤ 5.5 V, 1000 400 400 400Note 1 kHz
frequency Cb = 50 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD ≤ 5.5 V, 400Note 1 400Note 1 400Note 1 400Note 1 kHz
Cb = 100 pF, Rb = 3 kΩ
1.9 V ≤ EVDD < 2.7 V, 300Note 1 300Note 1 300Note 1 300Note 1 kHz
Cb = 100 pF, Rb = 5 kΩ
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD < 1.9 V, 250Note 1 250Note 1 250Note 1 kHz
Cb = 100 pF, Rb = 5 kΩ
Hold time tLOW 2.7 V ≤ EVDD ≤ 5.5 V, 475 1150 1150 1150 ns
when SCLr = Cb = 50 pF, Rb = 2.7 kΩ
“L” 1.9 V ≤ EVDD ≤ 5.5 V, 1150 1150 1150 1150 ns
Cb = 100 pF, Rb = 3 kΩ
1.9 V ≤ EVDD < 2.7 V, 1550 1550 1550 1550 ns
Cb = 100 pF, Rb = 5 kΩ
1.8 V ≤ EVDD < 1.9 V, 1850 1850 1850 1850 ns
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD < 1.9 V, 1850 1850 1850 ns
Cb = 100 pF, Rb = 5 kΩ
Hold time tHIGH 2.7 V ≤ EVDD ≤ 5.5 V, 475 1150 1150 1150 ns
when SCLr = Cb = 50 pF, Rb = 2.7 kΩ
“H” 1.9 V ≤ EVDD ≤ 5.5 V, 1150 1150 1150 1150 ns
Cb = 100 pF, Rb = 3 kΩ
1.9 V ≤ EVDD < 2.7 V, 1550 1550 1550 1550 ns
Cb = 100 pF, Rb = 5 kΩ
1.8 V ≤ EVDD < 1.9 V, 1850 1850 1850 1850 ns
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD < 1.9 V, 1850 1850 1850 ns
Cb = 100 pF, Rb = 5 kΩ
Data setup tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
time Cb = 50 pF, Rb = 2.7 kΩ 85Notes 1, 2 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2
(reception)
1.9 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
Cb = 100 pF, Rb = 3 kΩ 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2
1.9 V ≤ EVDD < 2.7 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns

1.7 V ≤ EVDD < 1.9 V, 1/fMCK + 1/fMCK + 1/fMCK + ns

Cb = 100 pF, Rb = 5 kΩ 290Notes 1, 2 290Notes 1, 2 290Notes 1, 2
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Data hold tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V, 0 305 0 305 0 305 0 305 ns
time Cb = 50 pF, Rb = 2.7 kΩ
(transmission)
1.9 V ≤ EVDD ≤ 5.5 V, 0 355 0 355 0 355 0 355 ns
Cb = 100 pF, Rb = 3 kΩ
1.9 V ≤ EVDD < 2.7 V, 0 405 0 405 0 405 0 405 ns
Cb = 100 pF, Rb = 5 kΩ
1.8 V ≤ EVDD < 1.9 V, 0 405 0 405 0 405 0 405 ns

Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD < 1.9 V, 0 405 0 405 0 405 ns

Cb = 100 pF, Rb = 5 kΩ
Notes 1. The value must also be equal to or less than fMCK/4.

2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Simplified I2C mode connection diagram (during communication at same potential)

VDD
Rb
SDAr SDA
RL78/I1C
User’s device
microcontrollers
SCLr SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW tHIGH
SCLr
SDAr
tHD:DAT tSU:DAT
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 10, 30), g: PIM and POM number (g = 0, 1, 8)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12))
R01UH0587EJ0200 Rev.2.00 1153

Aug 31, 2018
(5) Communication at different potential (1.9 V, 2.5 V, 3 V) (UART mode) (1/2)

Transfer 4.0 V ≤ EVDD ≤ 5.5 V, fMCK/6 fMCK/6 fMCK/6 fMCK/6Note 1 bps
Reception
rate 2.7 V ≤ Vb ≤ 4.0 V

Theoretical value of 5.3 1.3 0.1 0.6 Mbps
the maximum
transfer rate
fMCK = fCLKNote 4
2.7 V ≤ EVDD < 4.0 V, fMCK/6Note 1 fMCK/6Note 1 fMCK/6Note 1 fMCK/6Note 1 bps
2.3 V ≤ Vb ≤ 2.7 V
the maximum
transfer rate
fMCK = fCLKNote 4
1.9 V ≤ EVDD < 3.3 V, fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps
Notes 1 to 3 Notes 1, 2 Notes 1, 2 Notes 1, 2
1.8 V ≤ Vb ≤ 2.0 V
the maximum
transfer rate
fMCK = fCLKNote 4
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. Use it with EVDD ≥ Vb.
3. The following conditions are required for low voltage interface.
2.4 V ≤ EVDD < 2.7 V: MAX. 2.6 Mbps
1.9 V ≤ EVDD < 2.4 V: MAX. 1.3 Mbps
6 MHz (2.1 V ≤ EVDD ≤ 5.5 V),
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Vb[V]: Communication line voltage

2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8)
R01UH0587EJ0200 Rev.2.00 1154

Aug 31, 2018
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)

Transfer 4.0 V ≤ EVDD ≤ 5.5 V, Notes Notes Notes Notes bps

Transmission
rate 2.7 V ≤ Vb ≤ 4.0 V 1, 2 1, 2 1, 2 1, 2

Theoretical value of 2.8Note 3 2.8Note 3 2.8Note 3 2.8Note 3 Mbps
the maximum
transfer rateNote 9
Cb = 50 pF, Rb = 1.4 kΩ,
Vb = 2.7 V
2.7 V ≤ EVDD < 4.0 V, Notes Notes Notes Notes bps
2.3 V ≤ Vb ≤ 2.7 V 2, 4 2, 4 2, 4 2, 4

the maximum
transfer rateNote 9
Cb = 50 pF, Rb = 2.7 kΩ,
Vb = 2.3 V
1.9 V ≤ EVDD < 3.3 V, Notes Notes Notes Notes bps
1.6 V ≤ Vb ≤ 2.0 V 2, 6, 7 2, 6, 7 2, 6, 7 2, 6, 7
the maximum
transfer rateNote 9
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate = [bps]
2.2
{–Cb × Rb × ln (1 – Vb )} × 3
1 2.2
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) = × 100 [%]
1
( Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. Transfer rate in the SNOOZE mode is 4800 bps only.
3. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
2.0
{–Cb × Rb × ln (1 – Vb )} × 3
1 2.0
1
R01UH0587EJ0200 Rev.2.00 1155
Aug 31, 2018
Notes 5. This value as an example is calculated when the conditions described in the “Conditions” column are met.
7. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 1.9 V ≤ EVDD < 2.7 V and 1.6 V ≤ Vb ≤ 2.0 V
1
1.5
{–Cb × Rb × ln (1 – Vb )} × 3
1 1.5
1
8. This value as an example is calculated when the conditions described in the “Conditions” column are met.
6 MHz (2.1 V ≤ EVDD ≤ 5.5 V),
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the
TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance,

Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq Rx
RL78/I1C
User’s device
microcontrollers
RxDq Tx
R01UH0587EJ0200 Rev.2.00 1156

Aug 31, 2018
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
TxDq
1/Transfer rate
High-/Low-bit width
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the
TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
R01UH0587EJ0200 Rev.2.00 1157

Aug 31, 2018
(6) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (1/2)
SCKp cycle tKCY1 tKCY1 ≥ 4.0 V ≤ EVDD ≤ 5.5 V, 200 1150 1150 1150 ns
time 2/fCLK 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 300 1150 1150 1150 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high- tKH1 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
level width 2.7 V ≤ Vb ≤ 4.0 V, 2 – 50 2 – 50 2 – 50 2 – 50
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
2.3 V ≤ Vb ≤ 2.7 V, 2 – 120 2 – 120 2 – 120 2 – 120
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low- tKL1 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
level width 2.7 V ≤ Vb ≤ 4.0 V, 2–7 2 – 50 2 – 50 2 – 50
Cb = 20 pF, Rb = 1.4 kΩ
2.3 V ≤ Vb ≤ 2.7 V, 2 – 10 2 – 50 2 – 50 2 – 50
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 58 479 479 479 ns
time (to 2.7 V ≤ Vb ≤ 4.0 V,
SCKp↑)Note 1 Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 121 479 479 479 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 10 10 10 10 ns
time (from 2.7 V ≤ Vb ≤ 4.0 V,
2.7 V ≤ EVDD < 4.0 V, 10 10 10 10 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 60 60 60 60 ns
from SCKp↓ 2.7 V ≤ Vb ≤ 4.0 V,
to SOp Cb = 20 pF, Rb = 1.4 kΩ
outputNote 1 2.7 V ≤ EVDD < 4.0 V, 130 130 130 130 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
time (to 2.7 V ≤ Vb ≤ 4.0 V,
SCKp↓)Note 2 Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 33 110 110 110 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
R01UH0587EJ0200 Rev.2.00 1158

Aug 31, 2018
(6) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (2/2)

2.7 V ≤ EVDD < 4.0 V, 10 10 10 10 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
from SCKp↑ 2.7 V ≤ Vb ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
<Master> Vb Vb
Rb Rb
SCKp SCK

microcontrollers
SOp SI
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1, 8)
4. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
R01UH0587EJ0200 Rev.2.00 1159

Aug 31, 2018
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (1/2)
SCKp cycle tKCY1 tKCY1 ≥ 4.0 V ≤ EVDD ≤ 5.5 V, 300 1150 1150 1150 ns
time 4/fCLK 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 500 1150 1150 1150 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 1150 1150 1150 1150 ns
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high- tKH1 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
level width 2.7 V ≤ Vb ≤ 4.0 V, 2 – 75 2 – 75 2 – 75 2 – 75
Cb = 30 pF, Rb = 1.4 kΩ
2.3 V ≤ Vb ≤ 2.7 V, 2 – 170 2 – 170 2 – 170 2 – 170
Cb = 30 pF, Rb = 2.7 kΩ
1.9 VNote 4 ≤ EVDD < 3.3 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
1.6 V ≤ Vb ≤ 2.0 V Note 3
, 2 – 458 2 – 458 2 – 458 2 – 458
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low- tKL1 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
level width 2.7 V ≤ Vb ≤ 4.0 V, 2 – 12 2 – 50 2 – 50 2 – 50
Cb = 30 pF, Rb = 1.4 kΩ
2.3 V ≤ Vb ≤ 2.7 V, 2 – 18 2 – 50 2 – 50 2 – 50
Cb = 30 pF, Rb = 2.7 kΩ
1.9 VNote 4 ≤ EVDD < 3.3 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns
1.6 V ≤ Vb ≤ 2.0 V Note 3
, 2 – 50 2 – 50 2 – 50 2 – 50
Cb = 30 pF, Rb = 5.5 kΩ
time (to 2.7 V ≤ Vb ≤ 4.0 V,
2.7 V ≤ EVDD < 4.0 V, 177 479 479 479 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 479 479 479 479 ns
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the page after the next page.)
R01UH0587EJ0200 Rev.2.00 1160

Aug 31, 2018
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)

2.7 V ≤ EVDD < 4.0 V, 19 19 19 19 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 19 19 19 19 ns
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
from SCKp↓ 2.7 V ≤ Vb ≤ 4.0 V,
to Cb = 30 pF, Rb = 1.4 kΩ
SOp 2.7 V ≤ EVDD < 4.0 V, 195 195 195 195 ns
outputNote 1 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 483 483 483 483 ns
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
time (to 2.7 V ≤ Vb ≤ 4.0 V,
2.7 V ≤ EVDD < 4.0 V, 44 110 110 110 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 110 110 110 110 ns
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
2.7 V ≤ EVDD < 4.0 V, 19 19 19 19 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 19 19 19 19 ns
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
from SCKp↑ 2.7 V ≤ Vb ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 25 25 25 25 ns

1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the next page.)

R01UH0587EJ0200 Rev.2.00 1161
Aug 31, 2018
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
2. p: CSI number (p = 00, 10, 30), m: Unit number , n: Channel number (mn = 00, 02, 10),
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
<Master> Vb Vb
Rb Rb
SCKp SCK

microcontrollers
SOp SI
CSI mode serial transfer timing (master mode) (during communication at different potential)
tKCY1
tKL1 tKH1
SCKp
tSIK1 tKSI1
SIp Input data
tKSO1
SOp Output data
R01UH0587EJ0200 Rev.2.00 1162

Aug 31, 2018
CSI mode serial transfer timing (master mode) (during communication at different potential)
tKCY1
tKH1 tKL1
SCKp
tSIK1 tKSI1
SIp Input data
tKSO1
SOp Output data
Remark p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10),
R01UH0587EJ0200 Rev.2.00 1163

Aug 31, 2018
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp ... external clock input)
Parameter Symb Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage Unit
ol main) Mode main) Mode main) Mode main) Mode
SCKp cycle tKCY2 4.0 V ≤ 24 MHz < fMCK 14/fMCK – – – ns

timeNote 1 EVDD ≤ 20 MHz < fMCK ≤ 12/fMCK – – – ns
5.5 V, 24 MHz
2.7 V ≤
8 MHz < fMCK ≤ 20 10/fMCK – – – ns
Vb ≤ 4.0
MHz
V
4 MHz < fMCK ≤ 8 8/fMCK 16/fMCK – – ns
MHz
fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns
2.7 V ≤ 24 MHz < fMCK 20/fMCK – – – ns
EVDD < 20 MHz < fMCK ≤ 16/fMCK – – – ns
4.0 V, 24 MHz
2.3 V ≤
16 MHz < fMCK ≤ 14/fMCK – – – ns
Vb ≤ 2.7
20 MHz
V
8 MHz < fMCK ≤ 16 12/fMCK – – – ns
MHz
MHz
1.9 V ≤ 24 MHz < fMCK 48/fMCK – – – ns
EVDD 20 MHz < fMCK ≤ 36/fMCK – – – ns
< 3.3 V, 24 MHz
1.6 V ≤
16 MHz < fMCK ≤ 32/fMCK – – – ns
Vb ≤ 2.0
20 MHz
VNote 2
8 MHz < fMCK ≤ 16 26/fMCK – – – ns
MHz
MHz
SCKp high- tKH2, 4.0 V ≤ EVDD ≤ 5.5 V, tKCY2/ tKCY2/ tKCY2/ tKCY2/ ns
/low-level tKL2 2.7 V ≤ Vb ≤ 4.0 V 2 – 12 2 – 50 2 – 50 2 – 50
width 2.7 V ≤ EVDD < 4.0 V, tKCY2/ tKCY2/ tKCY2/ tKCY2/ ns
2.3 V ≤ Vb ≤ 2.7 V 2 – 18 2 – 50 2 – 50 2 – 50
1.6 V ≤ Vb ≤ 2.0 VNote 2 2 – 50 2 – 50 2 – 50 2 – 50
SIp setup tSIK2 2.7 V ≤ EVDD ≤ 5.5 V, 1/fMCK 1/fMCK 1/fMCK + 1/fMCK + ns
time (to 2.3 V ≤ Vb ≤ 4.0 VNote 2 + 20 + 30 30 30
SCKp↑)Note 3 1.9 V ≤ EVDD < 3.3 V, 1/fMCK 1/fMCK 1/fMCK + 1/fMCK + ns
1.6 V ≤ Vb ≤ 2.0 VNote 2 + 30 + 30 30 30
SIp hold tKSI2 2.7 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
time (from 2.3 V ≤ Vb ≤ 4.0 VNote 2 31 31 31 31
SCKp↑)Note 3 1.9 V ≤ EVDD < 3.3 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
1.6 V ≤ Vb ≤ 2.0 VNote 2 31 31 31 31
R01UH0587EJ0200 Rev.2.00 1164

Aug 31, 2018
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp ... external clock input)
Delay time tKSO2 4.0 V ≤ EVDD ≤ 5.5 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK ns
from 2.7 V ≤ Vb ≤ 4.0 V, + 120 + 573 + 573 + 573
SCKp↓ to Cb = 30 pF, Rb = 1.4 kΩ
SOp
2.7 V ≤ EVDD < 4.0 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK ns
outputNote 4
2.3 V ≤ Vb ≤ 2.7 V, + 214 + 573 + 573 + 573
Cb = 30 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK ns

1.6 V ≤ Vb ≤ 2.0 VNote 2, + 573 + 573 + 573 + 573
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g
<Slave> Vb
Rb
SCKp SCK

microcontrollers
SOp SI
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10),
R01UH0587EJ0200 Rev.2.00 1165

Aug 31, 2018
CSI mode serial transfer timing (slave mode) (during communication at different potential)
tKCY2
tKL2 tKH2
SCKp
tSIK2 tKSI2
SIp Input data
tKSO2
SOp Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2 tKL2
SCKp
tSIK2 tKSI2
SIp Input data
tKSO2
SOp Output data
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g
Remark p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 12),
R01UH0587EJ0200 Rev.2.00 1166

Aug 31, 2018
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
Note 1 Note 1
SCLr clock fSCL 4.0 V ≤ EVDD ≤ 5.5 V, 1000 300 300 Note 1
300Note 1 kHz
frequency 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 400Note 1 300Note 1 300Note 1 300Note 1 kHz
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time tLOW 4.0 V ≤ EVDD ≤ 5.5 V, 475 1550 1550 1550 ns
when SCLr = 2.7 V ≤ Vb ≤ 4.0 V,
“L”
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD < 4.0 V, 475 1550 1550 1550 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 1150 1150 1150 1150 ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD < 4.0 V, 1150 1150 1150 1150 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 1150 1150 1150 1150 ns
Note 2
1.6 V ≤ Vb ≤ 2.0 V ,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time tHIGH 4.0 V ≤ EVDD ≤ 5.5 V, 245 610 610 610 ns
when SCLr = 2.7 V ≤ Vb ≤ 4.0 V,
“H”
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD < 4.0 V, 200 610 610 610 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 675 610 610 610 ns

2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD < 4.0 V, 600 610 610 610 ns

2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 610 610 610 610 ns
Note 2
1.6 V ≤ Vb ≤ 2.0 V ,
Cb = 100 pF, Rb = 5.5 kΩ
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Aug 31, 2018
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
Data setup tSU:DAT 4.0 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
time 2.7 V ≤ Vb ≤ 4.0 V, 135Note 3 190Note 3 190Note 3 190Note 3
(reception) Cb = 50 pF, Rb = 2.7 kΩ
2.3 V ≤ Vb ≤ 2.7 V, 135Note 3 190Note 3 190Note 3 190Note 3
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + ns
Cb = 100 pF, Rb = 2.8 kΩ
Cb = 100 pF, Rb = 2.7 kΩ
1.6 V ≤ Vb ≤ 2.0 VNote 2, 190Note 3 190Note 3 190 Note 3
190 Note 3
Cb = 100 pF, Rb = 5.5 kΩ

Data hold tHD:DAT 4.0 V ≤ EVDD ≤ 5.5 V, 0 305 0 305 0 305 0 305 ns
time 2.7 V ≤ Vb ≤ 4.0 V,
(transmission) Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD < 4.0 V, 0 305 0 305 0 305 0 305 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 0 355 0 355 0 355 0 355 ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD < 4.0 V, 0 355 0 355 0 355 0 355 ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.9 V ≤ EVDD < 3.3 V, 0 405 0 405 0 405 0 405 ns
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 100 pF, Rb = 5.5 kΩ
Notes 1. The value must also be equal to or less than fMCK/4.

3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and
the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
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Simplified I2C mode connection diagram (during communication at different potential)
Vb Vb
Rb Rb
SDAr SDA
RL78/I1C
User’s device
microcontrollers
SCLr SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW tHIGH
SCLr
SDAr
tHD:DAT tSU:DAT
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and
the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
2. r: IIC number (r = 00, 10, 30), g: PIM, POM number (g = 0, 1, 8)
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41.5.2 Serial interface IICA
(1) I2C standard mode (1/2)

SCLA0 clock fSCL Standard 2.7 V ≤ EVDD 0 100 0 100 0 100 0 100 kHz
mode: ≤ 5.5 V
frequency
fCLK ≥ 1 1.9 V ≤ EVDD 0 100 0 100 0 100 0 100 kHz
MHz
≤ 5.5 V
1.8 V ≤ EVDD 0 100 0 100 0 100 0 100 kHz
≤ 5.5 V
1.7 V ≤ EVDD – – 0 100 0 100 0 100 kHz
≤ 5.5 V
Setup time of tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
restart 1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
condition
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.7 4.7 4.7 µs
Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.0 4.0 4.0 µs
Hold time tLOW 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
when SCLA0 1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
= “L”
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.7 4.7 4.7 µs
Hold time tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
when SCLA0 1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
= “H”
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.0 4.0 4.0 µs
Data setup tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs
time 1.9 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs
(reception)
1.8 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 250 250 250 µs
Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs
(transmission) 1.9 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs
Note 2
1.8 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs

1.7 V ≤ EVDD ≤ 5.5 V – – 0 3.45 0 3.45 0 3.45 µs
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(1) I2C standard mode (2/2)

Setup time of tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
stop condition 1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.0 4.0 4.0 µs
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs
1.7 V ≤ EVDD ≤ 5.5 V – – 4.7 4.7 4.7 µs

Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
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(2) I2C fast mode

SCLA0 clock fSCL Fast 2.7 V ≤ EVDD 0 400 0 400 – – 0 400 kHz
frequency mode: ≤ 5.5 V
fCLK ≥ 3.5 1.9 V ≤ EVDD 0 400 0 400 – – 0 400 kHz
MHz
≤ 5.5 V
Setup time of tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
restart 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
condition
Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
Hold time tLOW 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs
when SCLA0 1.9 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs
= “L”
Hold time tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
when SCLA0 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
= “H”
Data setup tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 100 100 – – 100 ns
time 1.9 V ≤ EVDD ≤ 5.5 V 100 100 – – 100 ns
(reception)
Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 – – 0 0.9 µs
(transmission) 1.9 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 – – 0 0.9 µs
Note 2
Setup time of tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs

stop condition 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs
1.9 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
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(3) I2C fast mode plus

SCLA0 clock fSCL Fast 2.7 V ≤ EVDD 0 1000 – – – – – – kHz

frequency mode ≤ 5.5 V
plus:
fCLK ≥
10 MHz
Setup time of restart tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs
condition
Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs
Hold time when tLOW 2.7 V ≤ EVDD ≤ 5.5 V 0.5 – – – – – – µs
SCLA0 = “L”
Hold time when tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs
SCLA0 = “H”
Data setup time tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 50 – – – – – – ns
(reception)
Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.5 – – – – – – µs
Note 2
(transmission)
Setup time of stop tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs
condition
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 0.5 – – – – – – µs
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW tR
SCL0
tHD:DAT tHIGH tF tSU:STA tHD:STA tSU:STO

tHD:STA tSU:DAT
SDA0
tBUF
Stop Start Restart Stop

condition condition condition condition
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41.6 Analog Characteristics
41.6.1 A/D converter characteristics
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pins: ANI2 to ANI5 and internal reference voltage
(TA = –40 to +85°C, 1.9 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (–) = AVREFM
= 0 V)
Resolution RES 8 10 bit

<R> Overall error Note 1
AINL 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB
AVREFP = VDD
Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs
1.9 V ≤ VDD ≤ 5.5 V 17 39 µs
Zero-scale error Notes 1, 2
EZS 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
AVREFP = VDD
Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
AVREFP = VDD
Integral linearity errorNote 1 ILE 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB
AVREFP = VDD
Differential linearity errorNote 1 DLE 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB
AVREFP = VDD
Reference voltage (+) AVREFP 1.9 VDD V
Analog input voltage VAIN 0 AVREFP V
VBGR Select internal reference voltage output 1.38 1.45 1.5 V
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.
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(2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0),
target pins: ANI0 to ANI5 and internal reference voltage
(TA = –40 to +85°C, 1.9 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VDDNote 3, reference voltage (–) = VSS)
Resolution RES 8 10 bit

<R> Overall error Note 1
AINL 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V 1.2 ±10.5 LSB
Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs
1.9 V ≤ VDD ≤ 5.5 V 17 39 µs
Zero-scale error Notes 1, 2
EZS 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±0.85 %FSR
Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±0.85 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±4.0 LSB
Note 1
Differential linearity error DLE 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN 0 VDD V
VBGR Select internal reference voltage output, 1.38 1.45 1.5 V
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode

Caution When using reference voltage (+) = VDD, taking into account the voltage drop due to the effect of the
power switching circuit of the battery backup function and use the A/D conversion result. In addition,
enter HALT mode during A/D conversion and set VDD port to input.
(3) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) =
AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI2 to ANI5
(TA = –40 to +85°C, 2.4 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VBGR, reference voltage (–) = AVREFM =
0 V, HS (high-speed main) mode)
Resolution RES 8 bit

Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs
Notes 1, 2
Zero-scale error EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Note 1
Integral linearity error ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Differential linearity errorNote 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB
Reference voltage (+) VBGR 1.38 1.45 1.5 V
Analog input voltage VAIN 0 VBGR V

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41.6.2 24-bit ΔΣ A/D converter characteristics
(1) Reference voltage
(TA = –40 to +85°C, 2.4 V ≤ VDDNote 1 ≤ 5.5 V, VSS = AVSS = 0 V)

Internal reference voltage VAVRTO 0.8 V
<R> Temperature coefficient for TCBOX 0.47 µF capacitor connected to AREGC, AVRT, 10 ppm/°C
internal reference voltage and AVCM pins
Note 2

<R> 2. This is as stipulated by the BOX method.
1 Vmax – Vmin
TCBOX =
Vmin Ta
VBGR
Vmax
Vmin
Box
Ta
-40°C 85°C T
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(2) Analog input
(TA = –40 to +85°C, 2.4 V ≤ VDDNote ≤ 5.5 V, VSS = AVSS = 0 V)

Input voltage range VAIN x1 gain –500 500 mV
(differential voltage) x2 gain –250 250
x4 gain –125 125
x8 gain –62.5 62.5
x16 gain –31.25 31.25
<R> x32 gain –15.625 15.625
<R> Input gain ainGAIN x1 gain 1 Times
x2 gain 2
x4 gain 4
x8 gain 8
x16 gain 16
<R> x32 gain 32

Input impedance ainRIN Differential voltage 150 360 kΩ
Single-ended voltage 100 240
Note Either VDD or VBAT is selected by the battery backup function.
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(3) 4 kHz sampling mode

Operation clock fDSAD fX oscillation clock, input external clock or high- 12 MHz
speed on-chip oscillator clock is used
Sampling frequency fS 3906.25 Hz
Oversampling frequency fOS 1.5 MHz
Output data rate TDATA 256 µs
Data width RES 24 bit
SNDR SNDR x1 gain 80 dB
High-speed system clock is selected as
operating clock of 24-bit ΔΣ A/D converter (bit 0
of PCKC register (DSADCK) = 1)
x16 gain 69 74
High-speed system clock is selected as operating
clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC
register (DSADCK) = 1)
x32 gain 65 69
Passband (low pass band) fChpf At –3 dB (phase in high pass filter not adjusted) 0.607 Hz
Bits 7 and 6 of DSADHPFCR register
(DSADCOF1, DSADCOF0) = 00
At –3 dB (phase in high pass filter not adjusted) 1.214 Hz
In-band ripple 1 rp1 45 Hz to 55 Hz @50 Hz –0.01 0.01 dB
54 Hz to 66 Hz @60 Hz
In-band ripple 2 rp2 45 Hz to 275 Hz @50 Hz –0.1 0.1
54 Hz to 330 Hz @60 Hz
54 Hz to 1320 Hz @60 Hz
Passband (high pass band) fClpf –3 dB 1672 Hz
Stopband (high pass band) fatt –80 dB 2545 Hz
Out-band attenuation ATT1 fS –80 dB
ATT2 2 fS –80 dB
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(4) 2 kHz sampling mode

Operation clock fDSAD fX oscillation clock, input external clock or high- 12 MHz
speed on-chip oscillator clock is used
<R> Sampling frequency fS 1953.125 Hz

Oversampling frequency fOS 0.75 MHz
Output data rate TDATA 512 µs
Data width RES 24 bit
SNDR SNDR x1 gain 80 dB
High-speed system clock is selected as
operating clock of 24-bit ΔΣ A/D converter (bit 0
of PCKC register (DSADCK) = 1)
x16 gain 69 74
x32 gain 65 69
Passband (low pass band) fChpf At –3 dB (phase in high pass filter not adjusted) 0.303 Hz
In-band ripple 1 rp1 45 Hz to 55 Hz @50 Hz –0.01 0.01 dB
54 Hz to 66 Hz @60 Hz
54 Hz to 330 Hz @60 Hz
54 Hz to 550 Hz @60 Hz
Passband (high pass band) fClpf –3 dB 836 Hz
Stopband (high pass band) fatt –80 dB 1273 Hz
Out-band attenuation ATT1 fS –80 dB
ATT2 2 fS –80 dB
41.6.3 Temperature sensor 2 characteristics
(TA = –40 to +85°C, 2.4 V ≤ VDDNote 2 ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Temperature sensor 2 output voltage VOUT 0.67 V
Temperature coefficient FVTMPS2 Temperature sensor that depends on –11.7 –10.7 –9.7 mV/°C
the temperature
Operation stabilization wait timeNote 1 tTMPON Operable 15 50 µs
tTMPCHG Switching mode 5 15 µs
Notes 1. Time to drop to output stable value ±5LSB (±7 mV) or less.
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41.6.4 POR circuit characteristics
(TA = –40 to +85°C, VSS = 0 V)

Note 1
Detection voltage VPOR When power supply rises 1.47 1.51 1.55 V
Note 2
VPDR When power supply falls 1.46 1.50 1.54 V
Notes 1. Be sure to maintain the reset state until the power supply voltage rises over the minimum VDD value in the
operating voltage range specified in 41.4 AC Characteristics, by using the voltage detector or external reset
pin.
2. If the power supply voltage falls while the voltage detector is off, be sure to either shift to STOP mode or
execute a reset by using the voltage detector or external reset pin before the power supply voltage falls below
the minimum operating voltage specified in 41.4 AC Characteristics.
41.6.5 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode

(TA = –40 to +85°C, VPDR ≤ VDDNote ≤ 5.5 V, VSS = 0 V)
Detection Supply voltage level VLVD0 When power supply rises 3.98 4.06 4.24 V
voltage When power supply falls 3.90 3.98 4.16 V
VLVD1 When power supply rises 3.68 3.75 3.92 V
When power supply falls 3.60 3.67 3.84 V
Minimum pulse width tLW 300 µs
Detection delay time 300 µs
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LVD Detection Voltage of Interrupt & Reset Mode

(TA = –40 to +85°C, VPDR ≤ VDDNote ≤ 5.5 V, VSS = 0 V)
Interrupt & reset VLVD8 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V 1.80 1.84 1.97 V
mode VLVD7 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.12 V
(+0.1 V) Falling interrupt voltage 1.90 1.94 2.08 V
VLVD6 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.23 V
VLVD8 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.60 V
Falling interrupt voltage 2.50 2.55 2.70 V
VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.91 V
41.6.6 Power supply voltage rising slope characteristics
(TA = –40 to +85°C, VSS = 0 V)

Power supply voltage rising slope SVDDR 54 V/ms

SVRTCR
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 41.4 AC Characteristics.
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41.7 Battery Backup Function
41.7.1 Power supply switching characteristics
(TA = –40 to +85°C, VSS = 0 V)

Power switching detection voltage VDETBAT1 VDD → VBAT 2.09 2.18 2.26 V
VBAT ≤ 3.6 V
VDETBAT2 VBAT → VDD 2.19 2.28 2.36 V
VBAT ≤ 3.6 V
VDD fall slope SVDDF -0.06 V/ms
Response time of power switch detector tcmp VBAT ≤ 3.6 V 500 µs
Min -0.06 V/ms
VBAT
Internal voltage
VDETBAT2
VDETBAT1
VDD
Power switching
signal
tcmp tcmp
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41.7.2 VDD pin voltage detection characteristics
(TA = –40 to +85°C, 1.9 V ≤ VDDNote ≤ 5.5 V, VSS = 0 V)

Parameter Symbol LVDVDD[2:0] Conditions MIN. TYP. MAX. Unit
Detection voltage VLVDVDD0 000 Rising 2.40 2.53 2.65 V

Falling 2.33 2.46 2.58 V
VLVDVDD1 001 Rising 2.60 2.74 2.86 V
Falling 2.53 2.67 2.79 V
VLVDVDD2 010 Rising 2.79 2.94 3.07 V
Falling 2.73 2.87 2.99 V
VLVDVDD3 011 Rising 3.00 3.15 3.28 V
Falling 2.93 3.08 3.21 V
VLVDVDD4 100 Rising 3.30 3.46 3.60 V
Falling 3.23 3.39 3.52 V
VLVDVDD5 101 Rising 3.59 3.77 3.91 V
Falling 3.53 3.70 3.84 V
Minimum pulse width tpw_lvdvdd – – 300 µs
Detection delay time tdly_lvdvdd – – 300 µs
tpw_lvdvdd
Detected voltage VDD→__
Detection voltage
VLVDVDD*
VDD
tdly_lvdvdd tdly_lvdvdd
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41.7.3 VBAT pin voltage detection characteristics

Detection voltage VLVDVBAT0 000 Rising 1.99 2.11 2.22 V

Falling 1.94 2.05 2.16 V
VLVDVBAT1 001 Rising 2.09 2.21 2.32 V
Falling 2.03 2.15 2.26 V
Falling 2.14 2.26 2.37 V
Falling 2.23 2.36 2.47 V
Falling 2.33 2.46 2.58 V
Falling 2.42 2.56 2.68 V
Falling 2.53 2.67 2.79 V
Minimum pulse width tpw_lvdvbat – – 300 µs
Detection delay time tdly_lvdvbat – – 300 µs
tpw_lvdvbat
Detected voltage VBAT →__
Detection voltage
VLVDVBAT*
VBAT
tdly_lvdvbat tdly_lvdvbat
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41.7.4 VRTC pin voltage detection characteristics

Detection voltage VLVDVRTC0 000 Rising 2.16 2.22 2.28 V

Falling 2.10 2.16 2.22 V
VLVDVRTC1 001 Rising 2.36 2.43 2.50 V
Falling 2.30 2.37 2.44 V
Falling 2.50 2.57 2.64 V
Falling 2.70 2.78 2.86 V
Minimum pulse width tpw_lvdvrtc – – 300 µs
Detection delay time tdly_lvdvrtc – – 300 µs
tpw_lvdvrtc
Detected voltage VRTC →__
Detection voltage
VLVDVRTC*
VRTC
tdly_lvdvrtc tdly_lvdvrtc
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41.7.5 EXLVD pin voltage detection

Detection voltage VLVDEXLVD Rising 1.25 1.33 1.41 V

Falling 1.20 1.28 1.36 V
Minimum pulse width tpw_lvdexlvd – 300 µs
Detection delay time tdly_lvdexlvd – 300 µs
Pin resistor rin_exlvd LVDEXLVDEN = 1 34 MΩ
tpw_lvdexlvd
__
Detected voltage EXLVD →
Detection voltage
VLVDEXLVD
EXLVD
tdly_lvdexlvd tdly_lvdexlvd
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41.8 LCD Characteristics
41.8.1 Resistance division method
(1) Static display mode

(TA = –40 to +85°C, VL4 (MIN.) ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Note
LCD drive voltage VL4 2.0 VDD V
(2) 1/2 bias method, 1/4 bias method

Note
(3) 1/3 bias method

Note
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41.8.2 Internal voltage boosting method
(1) 1/3 bias method

Note 1
LCD output voltage variation range VL1 C1 to C4 VLCD = 04H 0.90 1.00 1.08 V
= 0.47 µFNote 2 VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
VLCD = 0BH 1.25 1.35 1.43 V
VLCD = 0CH 1.30 1.40 1.48 V
VLCD = 0DH 1.35 1.45 1.53 V
VLCD = 0EH 1.40 1.50 1.58 V
VLCD = 0FH 1.45 1.55 1.63 V
VLCD = 10H 1.50 1.60 1.68 V
VLCD = 11H 1.55 1.65 1.73 V
VLCD = 12H 1.60 1.70 1.78 V
VLCD = 13H 1.65 1.75 1.83 V
Note 1
Doubler output voltage VL2 C1 to C4 = 0.47 µF 2 VL1–0.10 2 VL1 2 VL1 V
Note 1
Tripler output voltage VL4 C1 to C4 = 0.47 µF 3 VL1–0.15 3 VL1 3 VL1 V
Note 2
Reference voltage setup time tVWAIT1 5 ms
Note 3 Note 1
Voltage boost wait time tVWAIT2 C1 to C4 = 0.47 µF 500 ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C1 = C2 = C3 = C4 = 0.47 µF±30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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(2) 1/4 bias method

Note 1
LCD output voltage variation range VL1 C1 to C5 VLCD = 04H 0.90 1.00 1.08 V
= 0.47 µFNote 2 VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
Doubler output voltage VL2 C1 to C5Note 1 = 0.47 µF 2 VL1–0.08 2 VL1 2 VL1 V
Note 1
Tripler output voltage VL3 C1 to C5 = 0.47 µF 3 VL1–0.12 3 VL1 3 VL1 V
Note 1
Quadruply output voltage VL4 C1 to C5 = 0.47 µF 4 VL1–0.16 4 VL1 4 VL1 V
Note 2
Reference voltage setup time tVWAIT1 5 ms
Note 3 Note 1
Voltage boost wait time tVWAIT2 C1 to C5 = 0.47 µF 500 ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1 = C2 = C3 = C4 = C5 = 0.47 µF±30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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41.8.3 Capacitor split method
(1) 1/3 bias method

Note 2 Note 3
VL4 voltage VL4 C1 to C4 = 0.47 µF VDD V
Note 2
VL2 voltage VL2 C1 to C4 = 0.47 µF 2/3 VL4– 2/3 VL4 2/3 VL4 + V
0.1 0.1
VL1 voltage VL1 C1 to C4 = 0.47 µFNote 2 1/3 VL4– 1/3 VL4 1/3 VL4 + V
0.1 0.1
Capacitor split wait timeNote 1 tVWAIT 100 ms
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1 = C2 = C3 = C4 = 0.47 µF±30%
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41.9 RAM Data Retention Characteristics
(TA = –40 to +85°C)
Data retention supply voltage VDDDR 1.46Note 5.5 V
Note The value depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a
POR is applied, but are not retained following a POR.
STOP mode Operation mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal

(interrupt request)
41.10 Flash Memory Programming Characteristics

Note 4
System clock frequency fCLK 1.9 V ≤ VDD ≤ 5.5 V 1 24 MHz
Notes 1, 2, 3
Number of code flash rewrites Cerwr Retained for 20 years 1,000 Times
TA = 85°C
Number of data flash rewritesNotes 1, 2, 3 Retained for 1 year 1,000,000
TA = 25°C
Retained for 5 years 100,000
TA = 85°C
Retained for 20 years 10,000
TA = 85°C
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.
41.11 Dedicated Flash Memory Programmer Communication (UART)
Transfer rate During serial programming 115,200 1,000,000 bps
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41.12 Timing Specs for Switching Flash Memory Programming Modes
Time to complete the tSUINIT POR and LVD reset must be released before 100 ms
communication for the initial setting the external reset is released.
after the external reset is released
Time to release the external reset tSU POR and LVD reset must be released before 10 µs
after the TOOL0 pin is set to the the external reset is released.
low level
Time to hold the TOOL0 pin at the tHD POR and LVD reset must be released before 1 ms
low level after the external reset is the external reset is released.
released
(excluding the processing time of
the firmware to control the flash
memory)
<1> <2> <3> <4>
RESET
723 µs + tHD
processing
time 1-byte data for setting mode
TOOL0
tSU tSUINIT
<1> The low level is input to the TOOL0 pin.

<2> The external reset is released (POR and LVD reset must be released before the external
reset is released.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100
ms from when the resets end.
tSU: Time to release the external reset after the TOOL0 pin is set to the low level.
tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
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RL78/I1C
Aug 31, 2018

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-LFQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g
42.1 64-pin Products
R01UH0587EJ0200 Rev.2.00
HD
R5F10NLEDFB, R5F10NLGDFB
*1
D
48 33
NOTE)
1. DIMENSIONS " *1" AND " *2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION " *3" DOES NOT
49 32 INCLUDE TRIM OFFSET.
bp
b1
E
HE
Reference Dimension in Millimeters
c1
*2
Symbol
Min Nom Max
D 9.9 10.0 10.1
64
E 9.9 10.0 10.1
17 Terminal cross section
ZE
A2 1.4
HD 11.8 12.0 12.2
1 1 6 HE 11.8 12.0 12.2
Index mark
ZD A 1.7
A1 0.05 0.1 0.15
F
bp 0.15 0.20 0.25
CHAPTER 42 PACKAGE DRAWINGS
b1 0.18
S
c
A
A2
0.09 0.145 0.20
c1 0.125
0° 8°
y S
A1
*3 L e 0.5
e bp
x L1 x 0.08
y 0.08
Detail F
ZD 1.25
ZE 1.25
L 0.35 0.5 0.65
L1 1.0
1193
RL78/I1C CHAPTER 42 PACKAGE DRAWINGS
R5F10NMEDFB, R5F10NMGDFB, R5F10NMJDFB
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RL78/I1C
Aug 31, 2018

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-LFQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV 0.6g
R01UH0587EJ0200 Rev.2.00
HD
*1
D
R5F10NPJDFB, R5F10NPGDFB
75 51
NOTE)
1. DIMENSIONS " *1" AND " *2"
76 50 DO NOT INCLUDE MOLD FLASH.
2. DIMENSION " *3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
E
HE
Reference Dimension in Millimeters
*2
c
c1
Symbol
Min Nom Max
D 13.9 14.0 14.1
E 13.9 14.0 14.1
Terminal cross section A2 1.4
HD 15.8 16.0 16.2
100
26 HE 15.8 16.0 16.2
ZE
A 1.7
1 2 5 A1 0.05 0.1 0.15
Index mark bp 0.15 0.20 0.25
ZD
F b1 0.18
S
c 0.09 0.145 0.20
c1 0.125
A
A2
c
0° 8°
e 0.5
y S *3 L
A1
e bp x 0.08
x
L1 y 0.08
ZD 1.0
Detail F
ZE 1.0
L 0.35 0.5 0.65
L1 1.0
1195
RL78/I1C APPENDIX A REVISION HISTORY
APPENDIX A REVISION HISTORY
A.1 Major Revisions in This Edition

(1/3)
Page Description Classification
CHAPTER 1 OUTLINE
p.14 Modification of table in 1.6 Outline of Functions (b)
CHAPTER 6 CLOCK GENERATOR
p.150 Addition of caution in 6.1 (2) <1> XT1 clock oscillator (b)
p.152 Modification of figure and addition of note 3 in Figure 6-1 Block Diagram of Clock Generator (b)
p.154 Modification of caution 2 in Figure 6-2 Format of Clock operation mode control register (CMC) (b)
p.159 Addition of description in 6.3.4 Sub clock operation mode control register (SCMC) (c)
p.160 Addition of caution 7 in Figure 6-5 Format of Sub clock operation mode control register (SCMC) (b)
p.161 Addition of description in 6.3.5 Sub clock operation status control register (SCSC) (c)
p.179 Addition of description in 6.4.2 XT1 oscillator (c)
p.181, 182 Modification of Figure 6-22 Examples of Incorrect Resonator Connection (b)
p.183 Modification of description in 6.4.5 Low-speed on-chip oscillator (c)
p.186 Modification of initial setting in 6.6.1 Example of setting high-speed on-chip oscillator (b)
p.190, 191 Modification of description and caution in 6.6.3 Example of setting XT1 oscillation clock (b)
CHAPTER 9 Realtime Clock with Independent Power Supply
p.321 Addition of note in Table 9-1 RTC Specifications (b)
p.324 Addition of description in 9.2 Register Descriptions (b)
p.324 to p.326 Addition of Table 9-3 Registers that Control the RTC (b)
p.327 Modification of address in Figure 9-2 Format of Peripheral enable register 2 (PER2) (b)
p.343 Addition of note and modification of caution in Figure 9-31 Format of RTC Control Register 1 (b)
(RCR1)
p.344 to p.346 Addition of description, note, and note 1, and modification of note 2 in Figure 9-32 Format of RTC (b)
Control Register 2 (RCR2) (In calendar count mode)
p.347, 348 Addition of description, note, and note 1, and modification of note 2 in Figure 9-33 Format of RTC (b)
Control Register 2 (RCR2) (In binary count mode)
p.359, 360 Modification of description and addition of cautions 1 to 3 in Figure 9-49 Format of RTC Status (c) (b)
Register (RSR)
p.361 Addition of description in 9.2.32 Sub clock operation mode control register (SCMC) (c)
p.363 Addition of description in 9.2.33 Sub clock operation status control register (SCSC) (c)
p.364 Addition of description and caution 2 in 9.2.34 RTC power-on-reset status register (RTCPORSR) (c) (b)
p.368 Addition of note 4 in Figure 9-56 Clock and Count Mode Setting Procedure (b)
p.369 Addition of note 2 in Figure 9-57 Setting the Time (b)
p.370 Addition of note in Figure 9-58 30-Second Adjustment Procedure (b)
p.371 Addition of note in Figure 9-59 Reading Time (b)
p.372 Addition of cautions 1 and 2 in Figure 9-60 Using Alarm Function (b)
p.372 Modification of description in 9.3.7 Alarm function (c)
p.378 Addition of cautions 1 and 2 in Figure 9-65 Timing Chart for the Alarm Interrupt (ALM) (b)
p.379 Addition of cautions 1 and 2 in 9.4 (2) Periodic interrupt (PRD) (b)
Remark “Classification” in the above table classifies revisions as follows.

(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
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p.382 Deletion of 9.6.4 Transitions to standby mode after setting registers (b)
p.382 Modification of description in 9.6.4 Notes when writing to and reading from registers (b)
p.383 Modification of description in 9.6.6 Stop procedure (b)
p.383 Modification of Figure 9-67 Stop Setting Procedure (b)
CHAPTER 14 WATCHDOG TIMER
p.426 Addition of note in Table 14-3 Setting of Overflow Time of Watchdog Timer (b)
p.428 Addition of note in Table 14-4 Setting Window Open Period of Watchdog Timer (b)
CHAPTER 17 24-BIT ΔΣ A/D CONVERTER
p.491 Modification of Table 17-1 Configuration of 24-bit ΔΣ A/D Converter (b)
p.505 Modification of description in 17.2.7 ΔΣ A/D converter interrupt status register (DSADISR) (c)
p.522 Addition of 17.4.6 Input range (b)
CHAPTER 18 SERIAL ARRAY UNIT
p.658 Modification of Figure 18-99 Transmission Operation of LIN (b)
p.659 Modification of Figure 18-100 Flowchart for LIN Transmission (b)
p.661 Modification of Figure 18-101 Reception Operation of LIN (b)
p.662 Modification of Figure 18-102 Flowchart for LIN Reception (b)
CHAPTER 22 DATA TRANSFER CONTROLLER (DTC)
p.850 Modification of Table 22-1 DTC Specifications (b)
CHAPTER 24 INTERRUPT FUNCTIONS
p.907 Modification of description in 24.4.3 Multiple interrupt servicing (b)
CHAPTER 26 STANDBY FUNCTION
p.921 Modification of caution 5 in 26.1 Standby Function (c)
p.938 Addition of note 4 in Figure 26-6 When the Interrupt Request Signal is not Generated in the (b)
SNOOZE Mode
p.949 Modification of description and addition of caution 2 in 27.3.3 RTC power-on-reset status register (b)
(RTCPORSR)
CHAPTER 29 VOLTAGE DETECTOR
p.964, 965 Modification of Figure 29-8 Format of User Option Byte (000C1H/010C1H) (b)
p.979 Addition of note 2 in Figure 29-21 Setting Procedure of VDD Pin Voltage Detection (c)
p.980 Addition of note 2 in Figure 29-22 Setting Procedure of VBAT Pin Voltage Detection (c)
p.981 Addition of note 2 in Figure 29-23 Setting Procedure of VRTC Pin Voltage Detection (c)
p.982 Addition of note 2 in Figure 29-24 Setting Procedure of EXLVD Pin Voltage Detection (c)
p.987 Addition of note 2 in Figure 29-29 Changing of LVD Detection Voltage Setting (VDD pin) (c)
CHAPTER 35 OPTION BYTE
p.1041 Addition of note 3 in Figure 35-1 Format of User Option Byte (000C0H/010C0H) (b)
CHAPTER 36 FLASH MEMORY
p.1052 Modification of Figure 36-4 Communication with External Device (c)
CHAPTER 39 32-BIT MULTIPLY-ACCUMULATOR
p.1088 Modification of Figure 39-7 Format of Multiplication Control Register (MULC) (b)
p.1091 Addition of note in 39.4.4 Multiplication operation (b)

documents
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CHAPTER 41 ELECTRICAL SPECIFICATIONS
p.1128, 1129 Modification of description in 41.3.1 Pin characteristics (b)
p.1174 Modification of table in 41.6.1 (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, (c)
ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI2 to ANI5 and
internal reference voltage
p.1175 Modification of table in 41.6.1 (2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), (c)
reference voltage (–) = VSS (ADREFM = 0), target pins: ANI0 to ANI5 and internal reference
voltage
p.1176 Modification of parameter and symbol, and addition of note 2 in 41.6.2 (1) Reference voltage (b)
p.1177 Modification of condition and unit in 41.6.2 (2) Analog input (b)
p.1179 Modification of typical value in 41.6.2 (4) 2 kHz sampling mode (b)

documents
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A.2 Revision History of Preceding Editions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
(1/7)
Edition Description Chapter
Rev.0.50 Newly created.
Rev.1.00 Addition of product (R5F10NPG) Throughout
Modification of 1.1 Features, addition of Note 1, and modification of Note CHAPTER 1 OUTLINE
Modification of 1.2 List of Part Numbers
Addition of “RL78I1C (Top View)” to each figure in 1.3 Pin Configuration (Top View)
Modification of 1.4 Pin Identification
Modification of 1.6 Outline of Functions
Modification of 2.1.1 64-pin products CHAPTER 2 PIN
Modification of 2.1.2 80-pin products FUNCTIONS
Modification of 2.1.3 100-pin products
Addition of KR0 to KR7 of function to 2.2.1 With functions for each product
Modification of Remarks in 2.2.2 Description of Functions
Addition of Caution to Figure 2-11. Pin Block Diagram for Pin Type 7-5-10
Addition of Cautions to Figure 2-13. Pin Block Diagram for Pin Type 8-5-10
Addition of Caution and Remarks to Figure 2-14. Pin Block Diagram for Pin Type 12-1-1
Addition of Caution and Remarks to Figure 2-15. Pin Block Diagram for Pin Type 12-1-2
Modification of Note of Figure 3-1. Memory Map (R5F10NLE, R5F10NME) CHAPTER 3 CPU
Modification of title of Figure 3-2. Memory Map (R5F10NLG, R5F10NMG, R5F10NPG) and ARCHITECTURE
Note in it
Modification of Note of Figure 3-3. Memory Map (R5F10NMJ, R5F10NPJ)
Modification of Remark of Table 3-1. Correspondence Between Address Values and
Block Numbers in Flash Memory
Modification of Table 3-2. Internal ROM Capacity
Modification of Table 3-3. Vector Table
Modification of 3.1.2 Mirror area
Modification of Table 3-4. Internal RAM Capacity and Caution in it
Modification of Cautions of Figure 3-8. Format of Stack Pointer
Modification of Table 3-5. SFR List and addition of Note to it
Modification of Table 3-6. Extended SFR (2nd SFR) List and addition of Notes to it
Modification of Figure 4-5. Format of Port Input Mode Register CHAPTER 4 PORT
Modification of Figure 4-9. Format of LCD port function registers 0 to 5 (PFSEG0 to FUNCTIONS
PFSEG5) and Note in it
Modification of Table 5-2. Features of Each Flash Operation Mode and Note in it CHAPTER 5
Modification of 5.3 Initial Setting of Flash Operation Modes OPERATION STATE
Modification Figure 5-6. State Transitions between Flash Operation Modes and addition of CONTROL
Note 7 to it
Modification of 5.5.1 Details of HS (high-speed main) mode
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Rev.1.00 Modification of 6.1 Functions of Clock Generator and Note in it CHAPTER 6 CLOCK
Modification of Note of Table 6-1. Configuration of Clock Generator GENERATOR
Modification of Figure 6-1. Block Diagram of Clock Generator
Modification of Figure 6-3. Format of System clock control register (CKC) and Note 2 in it
Modification of Note and Caution of Figure 6-4. Format of Clock operation status control
register (CSC)
Modification of 6.3.10 Subsystem clock supply option control register (OSMC)
Modification of Figure 6-18. Format of Main clock control register (MCKC), addition of
Note, and modification of Remark
Addition of Caution to 6.6.2 Example of setting X1 oscillation clock
Modification of Note of Figure 6-24. CPU Clock Status Transition Diagram
Modification of Table 6-4. Changing CPU Clock
Modification of 6.6.8 Conditions before clock oscillation is stopped
Modification of Table 6-9. Conditions Before the Clock Oscillation Is Stopped and Flag
Settings
Modification of Figure 7-1. Block Diagram of High-speed On-chip Oscillator Clock CHAPTER 7 HIGH-
Frequency Correction Function SPEED ON-CHIP
Modification of Table 7-3. High-Speed On-Chip Oscillator Input Frequency and Correction OSCILLATOR CLOCK
FREQUENCY
Cycle
CORRECTION
FUNCTION
Modification of Figure 8-15. Format of Timer Mode Register mn (TMRmn) CHAPTER 8 TIMER
Deletion of Caution from Figure 8-41. TO0n Pin Statuses by Collective Manipulation of ARRAY UNIT
TO0n Bit
Modification of Caution of 8.9.1 Operation as one-shot pulse output function
Modification of Table 9-1. RTC Specifications CHAPTER 9
Modification of Figure 9-1. Block Diagram of RTC REALTIME CLOCK
Modification of 9.2 Register Descriptions WITH INDEPENDENT
POWER SUPPLY
Deletion of Caution 2 of Figure 9-2. Format of Peripheral enable register 2 (PER2)
Addition of explanation to 9.2.9 Year Counter (RYRCNT)
Modification of Figure 9-14. Format of Year Counter (RYRCNT)
Addition of explanation to (1) In calendar count mode in 9.2.16 Year Alarm Register
(RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER)
Addition of explanation to (2) In binary count mode in 9.2.16 Year Alarm Register
(RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER)
Addition of Caution to Figure 9-31. Format of RTC Control Register 1 (RCR1)
Modification of Figure 9-32. Format of RTC Control Register 2 (RCR2) (In calendar count
mode) and addition of Caution
Addition of Caution to Figure 9-33. Format of RTC Control Register 2 (RCR2) (In binary
count mode)
Addition of Caution to Figure 9-34. Format of RTC Control Register 3 (RCR3)
Modification of Caution of Figure 9-35. Format of RTC control register 4 (RCR4)
Modification of Figure 9-39. Format of Timer Capture Control Register y (RTCCRy) (y = 0
to 2)
Modification of 9.2.34 RTC power-on-reset status register (RTCPORSR)
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Rev.1.00 Modification of Figure 9-52. Format of RTC power-on-reset status register (RTCPORSR) CHAPTER 9
Addition of Caution to Figure 9-53. Format of Time Capture Event Input Noise Filter REALTIME CLOCK
Enable Register (RTCICNFEN) WITH INDEPENDENT
POWER SUPPLY
Addition of Remark to 9.3.1 Outline of Initial Settings of Registers after Power On
Modification of Figure 9-56. Clock and Count Mode Setting Procedure
Modification of Figure 9-59. Reading Time
Modification of Note in 9.5.1 Interrupt Handling and Event Linking
Modification of 9.6.4 Transitions to Low Power Consumption Modes after Setting
Registers
Modification of 9.6.5 Notes When Writing to and Reading from Registers
Addition of 9.6.8 Caution of shortwave detection function
Modification of 10.3.2 Subsystem clock supply option control register (OSMC) CHAPTER 10
Modification of Figure 10-10. Frequency Measurement Circuit Operation Timing FREQUENCY
MEASURE CIRCUIT
Modification of Caution to Figure 11-5 Format of 12-bit interval timer control register CHAPTER 11 12-BIT
(ITMC) INTERVAL TIMER
Modification of 13.5 Cautions of clock output/buzzer output controller CHAPTER 13 CLOCK
OUTPUT/BUZZER
OUTPUT ONTROLLER
Modification of Figure 15-1. Block Diagram of A/D Converter CHAPTER 15 A/D
Modification of Figure 15-3. Format of Peripheral reset control Register 0 (PRR0) CONVERTER
Modification of Figure 15-5. Timing Chart When A/D Voltage Comparator Is Used
Modification of Figure 15-7. Format of A/D Converter Mode Register 1 (ADM1) and
Caution 3 in it
Modification of Caution and Remark in 15.8 SNOOZE Mode Function
Modification of Figure 16-4. Format of Temperature sensor control test register CHAPTER 16
(TMPCTL) TEMPERATURE
Modification of Figure 16-5. Format of Peripheral reset control register 0 (PRR0) SENSOR 2
Addition of Caution to 17.1 Functions of 24-bit ΔΣ A/D Converter CHAPTER 17 24-BIT
ΔΣ A/D CONVERTER
Modification of Figure 18-1. Block Diagram of Serial Array Unit 0 CHAPTER 18 SERIAL
Modification of Figure 18-1. Block Diagram of Serial Array Unit 1 ARRAY UNIT
Addition of Note of 18.2.1 Shift register
Modification of Notes and Cautions of Figure 18-9. Format of Serial Data Register mn
(SDRmn)
Modification of Figure 18-16. Format of Serial Output Register m (SOm) and Caution in it
Modification of Figure 18-18. Examples of Reverse Transmit Data
Modification of Note of Figure 18-22. Format of Noise Filter Enable Register 0 (NFEN0)
Modification of Figure 18-25. Each Register Setting When Stopping the Operation by
Channels and deletion of Note
Modification of Figure 18-26. Example of Contents of Registers for Master Transmission of
3-Wire Serial I/O (CSI00, CSI10, CSI30) and deletion of Note
Modification of Figure 18-34. Example of Contents of Registers for Master Reception of
3-Wire Serial I/O (CSI00, CSI10, CSI30)
Modification of Figure 18-42. Example of Contents of Registers for Master
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
Modification of Figure 18-50. Example of Contents of Registers for Slave Transmission of 3-
Wire Serial I/O (CSI00, CSI10, CSI30) and deletion of Note
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Rev.1.00 Modification of Figure 18-58. Example of Contents of Registers for Slave Reception of 3- CHAPTER 18 SERIAL
Wire Serial I/O (CSI00, CSI10, CSI30) ARRAY UNIT
Modification of Figure 18-64. Example of Contents of Registers for Slave
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI10, CSI30)
Modification of 18.5.7 SNOOZE mode function and Caution
Modification of Figure 18-72. Timing Chart of SNOOZE Mode Operation (Once Startup)
(Type 1: DAPm0 = 0, CKPm0 = 0)
Modification of Figure 18-73. Flowchart of SNOOZE Mode Operation (Once Startup)
Modification of Figure 18-74. Timing Chart of SNOOZE Mode Operation (Continuous
Startup) (Type 1: DAPm0 = 0, CKPm0 = 0)
Modification of Figure 18-75. Flowchart of SNOOZE Mode Operation (Continuous
Startup)
Modification of Figure 18-77. Example of Contents of Registers for UART Transmission
of UART (UART0 to UART3) and Notes
Modification of Figure 18-85. Example of Contents of Registers for UART Reception of
UART (UART0 to UART3) and Notes, and deletion of Note
Addition of Caution to 18.6.3 SNOOZE mode function
Modification of Figure 18-91. Timing Chart of SNOOZE Mode Operation (EOCm1 = 0,
SSECm = 0/1)
SSECm = 0)
Modification of Figure 18-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm
= 0/1 or EOCm1 = 1, SSECm = 0)
SSECm = 1)
Modification of Figure 18-95. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm
= 1)
Modification of Figure 18-100. Flowchart for LIN Transmission
Modification of Figure 18-101. Reception Operation of LIN
Modification of Figure 18-104. Example of Contents of Registers for Address Field
Transmission of Simplified I2C (IIC00, IIC10, IIC30) and deletion of Note
Deletion of Note from Figure 18-111. Example of Contents of Registers for Data
Reception of Simplified I2C (IIC00, IIC10, IIC30)
Addition of explanation to 19.3.7 IICA low-level width setting register n (IICWLn) CHAPTER 19 SERIAL
INTERFACE IICA
Addition of explanation to Table 21-1. Number of LCD Display Function Pins of Each CHAPTER 21 LCD
Product CONTROLLER/DRIVER
Modification of Figure 21-1. Block Diagram of LCD Controller/Driver
Modification of Figure 21-3. Format of LCD Mode Register 1 (LCDM1)
Modification of 21.3.3 Subsystem clock supply option control register (OSMC)
Modification of Figure 21-10. Format of LCD port function registers 0 to 5 (PFSEG0 to
PFSEG5) and Note in it
Modification of 21.5.2 Blinking display (Alternately displaying A-pattern and B-pattern
area data)
Modification of Figure 21-14. Switching Operation from A-Pattern Display to Blinking
Display
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Rev.1.00 Modification of Figure 21-15. Switching Operation from Blinking Display to A-Pattern CHAPTER 21 LCD
Display CONTROLLER/DRIVER
Addition of explanation to CHAPTER 22 DATA TRANSFER CONTROLLER (DTC) CHAPTER 22 DATA
Modification of Figure 22-2. Memory Map Example When DTCBAR Register Is Set to FBH TRANSFER
(R5F10NPGDFB, R5F10NMGDFB, R5F10NLGDFB) and Cautions in it CONTROLLER (DTC)
Figure 22-3. Control Data Allocation and addition of Remark

Addition of Table 22-4. Start Address of Control Data
Addition of Figure 22-4. Start Address of Control Data and Vector Table
Modification of Figure 22-5. Format of Peripheral Enable Register 1 (PER1)
Modification of 22.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4)
Modification of (1) Example 1 of using normal mode: Consecutively capturing A/D
conversion results in 22.4.2 Normal mode
Modification of Figure 22-16. Example 1 of Using Normal Mode: Consecutively Capturing
A/D Conversion Results
Modification of 22.5.2 Allocation of DTC control data area and DTC vector table area
Modification of Notes in 22.5.8 Operation in standby mode status
Modification of Table 23-2. Correspondence Between ELSELRn (n = 00 to 21) Registers CHAPTER 23 EVENT
and Peripheral Functions LINK CONTROLLER
Modification of Figure 23-3. Format of Timer Input Select Register 0 (TIS0) (ELC)
Modification of Figure 23-4. Format of A/D Converter Mode Register 1 (ADM1)

Modification of Table 24-1. Interrupt Source List and Notes CHAPTER 24
Modification of Figure 24-1. Basic Configuration of Interrupt Function and Remark in it INTERRUPT
Modification of Table 24-2. Flags Corresponding to Interrupt Request Sources FUNCTIONS
Modification of Figure 24-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H, IF3L)
Modification of Figure 24-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H,
MK1L, MK1H, MK2L, MK2H, MK3L)
Modification of 24.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H,
PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L)
Modification of Figure 24-4. Format of Priority Specification Flag Registers (PR00L,
PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H, PR13L)
Modification of Figure 24-5. Format of External Interrupt Rising Edge Enable Register
(EGP0, EGP1) and External Interrupt Falling Edge Enable Register (EGN0, EGN1)
Addition of 24.4.4 Interrupt servicing during division instruction
Addition of explanation to 24.4.5 Interrupt request hold
Modification of (3) SNOOZE mode in 26.1 Standby Function CHAPTER 26
Modification of Table 26-1. Operating Statuses in HALT Mode and addition of explanation to STANDBY FUNCTION
Remark in it
Modification of (1) STOP mode setting and operating statuses in 26.3.2 STOP mode
Modification of Table 26-2. Operating Statuses in STOP Mode and Remark in it
Modification of Table 26-3. Operating Statuses in SNOOZE Mode and Remark in it
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Rev.1.00 Addition of Note to CHAPTER 27 RESET FUNCTION CHAPTER 27 RESET

Deletion of Note from Figure 27-3. Timing of Reset Due to Watchdog Timer Overflow, FUNCTION
Execution of Illegal Instruction, Detection of RAM Parity Error, or Detection of Illegal
Memory
Modification of Table 27-1. Operation Statuses During Reset Period and Remark in it
Modification of 27.3.3 RTC power-on-reset status register (RTCPORSR)
Modification of Figure 27-7. Format of RTC power-on-reset status register (RTCPORSR)
Modification of Note of Figure 28-2. Timing of Generation of Internal Reset Signal by CHAPTER 28 POWER-
Power-on-reset Circuit and Voltage Detector ON-RESET CIRCUIT
Modification of 29.1 Functions of Voltage Detector CHAPTER 29
Modification of Figure 29-2. Block Diagram of VDD Pin Voltage Detector VOLTAGE DETECTOR
Modification of Figure 29-3. Block Diagram of VBAT Pin Voltage Detector
Modification of Figure 29-4. Block Diagram of VRTC Pin Voltage Detector
Modification of Figure 29-5. Block Diagram of EXLVD Pin Voltage Detector
Modification of Notes of Figure 29-11. Format of Voltage detection control register for
VBAT pin (LVDVBAT)
Modification of Figure 29 - 15 Format of Voltage Detection Control for EXLVD Pin
Register (LVDEXLVD)
Modification of 29.4.2 When used as interrupt mode
Addition of (5) When supply voltage from the pins is shut off to 29.6 Cautions for Voltage
Detector
Addition of (6) When supply voltage output to the VDDOUT pin is shut off to 29.6 Cautions
for Voltage Detector
Modification and deletion of Table 30-1. Peripheral Circuit Operation State during Battery CHAPTER 30
Backup and addition of Notes BATTERY BACKUP
Modification of Figure 30-1. Block Diagram of Battery Backup Function FUNCTION
Modification of 30.2.1 Battery backup power switching control register 0 (BUPCTL0)

Modification of Figure 30-2. Format of Battery Backup Power Switching Control Register
0 (BUPCTL0), addition of Notes, and modification of Cautions and Remark
Modification of 30.3.1 Battery backup function
Modification of Figure 30-7. Procedure for Setting Battery Backup Function Operation
Modification of Figure 30-8. Procedure for Setting Battery Backup Function Stop
Addition of 30.3.2 Using the battery backup function
Addition of explanation to 30.4 Usage Notes
Modification of Figure 31-1. Block Diagram of Oscillation Stop Detector CHAPTER 31
Modification of 31.3.3 Subsystem clock supply option control register (OSMC) OSCILLATION STOP
DETECTOR
Modification of Notes of Figure 32-1. Format of Flash Memory CRC Control Register CHAPTER 32 SAFETY
(CRC0CTL) FUNCTIONS
Modification of Figure 32-10. Format of Invalid Memory Access Detection Control
Register (IAWCTL)
Modification of Figure 32-11. Invalid access detection area and Note in it
Addition of explanation to (3) 000C2H/010C2H in 35.1.1 User option byte (000C0H to CHAPTER 35 OPTION
000C2H/010C0H to 010C2H) BYTE
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Rev.1.00 Modification of CHAPTER 36 FLASH MEMORY CHAPTER 36 FLASH

Modification of Figure 36-4. Communication with External Device MEMORY
Modification of Table 36-5. Programming Modes and Voltages at Which Data Can Be
Written, Erased, or Verified
Modification of Table 36-8. Signature Data List
Modification of Cautions in 36.6 Self-Programming
Modification of Figure 36-11. Flash Shield Window Setting Example
Modification of Figure 37-1. Example of Connections with the E1 On-chip Debugging CHAPTER 37 ON-CHIP
Emulator (when the Battery Backup Function is in Use) and Notes in it DEBUG FUNCTION
Modification of Notes of Figure 37-3. Memory Spaces Where Debug Monitor Programs
Are Allocated
Deletion of “TARGET” from CHAPTER 41 ELECTRICAL SPECIFICATIONS CHAPTER 41
Modification of 41.1 Absolute Maximum Ratings ELECTRICAL
Modification of 41.2.2 On-chip oscillator characteristics SPECIFICATIONS
Modification of 41.3.2 Supply current characteristics and Note

Modification of 41.4 AC Characteristics
Addition of Key interrupt Input Timing to 41.4 AC Characteristics
Modification of 41.6.2 24-bit A/D converter characteristics
Modification of 41.7.1 Power supply switching characteristics
Modification of 41.7.2 VDD pin voltage detection characteristics and addition of figure
Modification of 41.7.3 VBAT pin voltage detection characteristics and addition of figure
Modification of 41.7.4 VRTC pin voltage detection characteristics and addition of figure
Modification of 41.7.5 EXLVD pin voltage detection and addition of figure
Modification of 41.9 RAM Data Retention Characteristics
Modification of 42.3 100-pin Products CHAPTER 42
PACKAGE DRAWINGS
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RL78/I1C User’s Manual: Hardware
Publication Date: Rev. 0.50 Aug 31, 2015

Rev. 2.00 Aug 31, 2018
Published by: Renesas Electronics Corporation

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User’s Manual

16-Bit Single-Chip Microcontrollers

www.renesas.com Rev. 2.00 Aug 2018

(Rev.4.0-1 November 2017)

● 64-pin: R5F10NLG, R5F10NLE

RL78/I1C RL78 Microcontroller

● Pin functions ● CPU functions

Documents Related to Devices

RL78/I1C User’s Manual Hardware This manual

Documents Related to Flash Memory Programming

PG-FP5 Flash Memory Programmer User’s Manual –

RENESAS MICROCOMPUTER RL78 FAMILY R01CP0003E

1.1 Features ........................................................................................................................................... 1

CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 16

2.1 Port Function ................................................................................................................................ 16

CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 46

3.1 Memory Space .............................................................................................................................. 46

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 97

4.1 Port Functions .............................................................................................................................. 97

CHAPTER 5 OPERATION STATE CONTROL ................................................................................... 137

5.1 Configuration of Operation State Control ................................................................................ 137

CHAPTER 6 CLOCK GENERATOR .................................................................................................... 148

6.1 Functions of Clock Generator ................................................................................................... 148

CHAPTER 7 HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION

CHAPTER 8 TIMER ARRAY UNIT ...................................................................................................... 215

8.1 Functions of Timer Array Unit ................................................................................................... 216

CHAPTER 9 REALTIME CLOCK WITH INDEPENDENT POWER SUPPLY.................................. 321

9.1 Overview ...................................................................................................................................... 321

CHAPTER 10 FREQUENCY MEASURE CIRCUIT ............................................................................. 384

10.1 Frequency Measurement Circuit............................................................................................. 384

CHAPTER 11 12-BIT INTERVAL TIMER ............................................................................................ 393

11.1 Functions of 12-bit Interval Timer........................................................................................... 393

CHAPTER 12 8-BIT INTERVAL TIMER .............................................................................................. 400

12.1 Overview .................................................................................................................................... 400

CHAPTER 13 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................... 416

13.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 416

CHAPTER 14 WATCHDOG TIMER ..................................................................................................... 421

14.1 Functions of Watchdog Timer ................................................................................................. 421

CHAPTER 15 A/D CONVERTER ......................................................................................................... 430

15.1 Function of A/D Converter ....................................................................................................... 430

CHAPTER 16 TEMPERATURE SENSOR 2........................................................................................ 485

16.1 Functions of Temperature Sensor .......................................................................................... 485

CHAPTER 17 24-BIT ΔΣ A/D CONVERTER...................................................................................... 490

17.1 Functions of 24-bit ΔΣ A/D Converter .................................................................................... 490

CHAPTER 18 SERIAL ARRAY UNIT .................................................................................................. 523

18.1 Functions of Serial Array Unit................................................................................................. 524

CHAPTER 19 SERIAL INTERFACE IICA ........................................................................................... 686

19.1 Functions of Serial Interface IICA ........................................................................................... 686

CHAPTER 20 IrDA ................................................................................................................................. 775

20.1 Functions of IrDA ..................................................................................................................... 775

CHAPTER 21 LCD CONTROLLER/DRIVER ....................................................................................... 783

21.1 Functions of LCD Controller/Driver ........................................................................................ 784

CHAPTER 22 DATA TRANSFER CONTROLLER (DTC).................................................................. 849

22.1 Functions of DTC...................................................................................................................... 850

CHAPTER 23 EVENT LINK CONTROLLER (ELC) ........................................................................... 878

23.1 Functions of ELC ...................................................................................................................... 878

CHAPTER 24 INTERRUPT FUNCTIONS............................................................................................. 887

24.1 Interrupt Function Types ......................................................................................................... 887

CHAPTER 25 KEY INTERRUPT FUNCTION ..................................................................................... 914