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DDR SDRAM - An Walk Down The Memory Lane (1) : Gaonkar

Double data rate (DDR) memory is basically an SDRAM. For a given clock speed, data can be read / written at twice the rate. 2 words of data can be written / read in a single clock cycle.

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Arati Halbe
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77 views4 pages

DDR SDRAM - An Walk Down The Memory Lane (1) : Gaonkar

Double data rate (DDR) memory is basically an SDRAM. For a given clock speed, data can be read / written at twice the rate. 2 words of data can be written / read in a single clock cycle.

Uploaded by

Arati Halbe
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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DDR SDRAM - An walk down the memory lane (1)

Since PCs were not a household commodity when we were undergraduates, our first
introduction to "memory" in the context of a microprocessor based system happened
through a typical block diagram in Gaonkar. We just read it as a block essential in the
system, and that it does the job of storing data. As I started doing more projects and
advanced stuff, the understanding of speed, access times, latencies started coming.
Somewhere in that same flow, i learnt about double data rate SDRAMs.

First things first :

So a double data rate (DDR) memory is basically an SDRAM - It is a Synchronous


Dynamic Random Access Memory. It is synchronous, means that data reads and writes
happen in sync with a clock provided by the system. It is dynamic means the data is
stored as charge in capacitors inside integrated circuits. Since capacitors tend to lose
charge over a period of time, a periodic refresh is required. It is random access means that
one can place any address on the address lines, followed by any other address and the
data is accurately accessed and produced on the data lines provided the specified timing
relations are adhered to.

In the best case, normal SDRAMs are capable of delivering only one word of data every
clock cycle.
DDR is double data rate, which means that for a given clock speed, data can be
read/written at twice the rate. 2 words of data can be written/read in a single clock cycle.

For the write mechanism, the controller module provides a clock, (which is not free
running) called the DQS and the data is written on the positive as well as the negative
edge of DQS. The DQS is called as the strobe in same cases. The write signal needs to be
asserted.

For the read operation, the controller issues a read command and after a certain number
of clock cycles, (called CAS Latency), the memory puts the data on the data bus. This
time, the clock to which the data is synchronised is provided by the memory. The same
DQS lines as before are used, but this time, the memory drives those. The DDR memory
internally prefetches 2 data words so that it can output data on both edges of the clock.

DDR SDRAM - An walk down the memory lane (2)

Part 1 | Part 3

We now look at the various aspects of DDR SDRAM one by one.

Reading or writing data needs to follow a command sequence


The construction of SDRAM is in the form of rows and columns of memory elements.
Usually, SDRAMs are divided internally into 2 or 4 'banks' or chunks of memory
elements. Hence the way to access data from SDRAM is to specify a bank address, then a
row address and the column address.
A specific sequence needs to be carried out when reading from or writing to an SDRAM.
JEDEC specifies a set of registers and a set of commands for SDRAM. Separate sets of
registers and commands are specified for SDRAM, DDR, DDR2 and DDR3 memories.
Before a row can be accessed inside an SDRAM, an ACTIVE command needs to be
issued. This opens a row for data access. It is open for data access till access is closed by
a "PRECHARGE" command. Usually, an address line lets you select whether AUTO
PRECHARGE is enabled. In case of AUTO PRECHARGE, the access to the row is
closed automatically.

Data is read/written on both the edges of the strobe signal


The DDR memory system is a source synchronous interface. This means that the clock
signal is transported from the transmitter to the receiver along with the data. This clock is
not free running, but only driven during data transfer. The signal is called data strobe or
DQS for short. Data is transferred on both the edges of DQS. While defining the
specification for DDR, the JEDEC committee decided that the while writing to the
memory, the controller must align the DQS to the center of the data eye and while
reading from the memory, the memory transmits the DQS edge aligned to the data edge.
The design-reuse website has a very nice article on the three most critical decisions
regarding the DDR specification from JEDEC.

Reading data in bursts is more efficient


Since an entire row is open for access once activated, and data is prefetched, it is most
effeciently read in bursts. The access to SDRAM data always happens in bursts and if one
is interested in only 1 or 2 bytes/words, then the rest of the bytes/words are masked using
the signal DM or data mask.

Periodic Refresh is required to hold the data


The DDR SDRAM memory controller needs to take care of refreshing the memory every
specified time interval by issuing the auto refresh command.

Timing specifications between various commands


Data sheets for SDRAMs usually specify timing requirements for the various operations.
For example, minimum time interval between precharge of a row in the same bank to the
activation of another row, or amount of time after which ACTIVE command can be
issued after the AUTO-REFRESH command can be issued. Since these timings must be
strictly adhered to, to ensure accurate data.

DDR SDRAM - An walk down the memory lane (3)

Part 1 | prev | next


In this part let us discuss the DDR memory signals. A typical DDR memory has the
following pins

Address lines input to memory


The address pins are used to
1. Provide row address
2. Provide column address
3. One pin indicates whether PRECHARGE is applicable to one bank or all banks
4. To carry the opcode during the LOAD MODE REGISTER command.

Bank address input


These have follwing function
1. Select the bank during normal operation
2. To determine whether mode register or extended mode register is selected during
LOAD MODE REGISTER command

Clock pins
Clock inout (2 pins : CK and CK#)
The clock is a differential clock. All control signals are sampled on crossing of rising CK
edge and falling CK# edge

Clock enable
This input high activates the internal clocks, input buffers and output drivers.

Chip select
This signal is active low in most cases. It acts as an enable for the commands. All
commands are masked when this signal is sampled high. *

Control pins
RAS, CAS and WE are the control inputs. These three pins alongwith the CS pin define
the command being entered. The DDR data sheets usually specify the definitions of
various commands like ACTIVE, PRECHARGE, WRITE, READ etc. as a combination
of these signals

Data pins
DQ or data lines
This is usually an 8 bit bus, with either 4 or 8 pins active depending on the data bus
width. In 16 bit devices this can be 16 bit wide too. This is a bidirectional bus

DQS or data strobe


A single strobe for every 8 data pins. SO for a 16 bit data bus, 2 bit DQS signal exists.
DQS is bi-directional.
Data mask signal
DM is a signal input to memory, with one pin per 8 bits of data. For example, for 16 bit
data bus, this signal is 2 bits, one bit corresponding to lower 8 bit of data and the other bit
corresponding to higher 8 bit of data. This signal is used as a mask during write
operation. If this signal is sampled high, then the data byte is masked.

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