∗

Classical Floorplanning Harmful?

Andrew B. Kahng
UCLA Computer Science Department
3713 Boelter Hall
Los Angeles, CA 90095-1596 USA
[email protected]

ABSTRACT aspect ratio, usually corresponding to alternative block re-

Classical floorplanning formulations may lead researchers to alizations (e.g., allowed foldings of datapaths).1 Since the
solve the wrong problems. This paper points out several ex- mid-1990s, L- and T-shaped block shapes have been speci-
amples, including (i) the preoccupation with packing-driven, fiable and/or permissible; this is motivated by enforced co-
as opposed to connectivity-driven, problem formulations and location of a datapath block with related control, or the
benchmarking standards; (ii) the preoccupation with rect- shape of particular types of datapath blocks. The target lay-
angular (and L or T shaped) block shapes; and (iii) the out region is typically specified by upper and lower bounds
lack of attention to algorithm scalability, fixed-die layout on its aspect ratio, e.g., a square layout has upper bound =
requirements, and the overall RTL-down methodology con- lower bound = 1.
text. The right problem formulations must match the pur- The classical floorplanning problem seeks to shape and pack
pose and context of prevailing RTL-down design method- all blocks, such that no blocks overlap and the enclosing lay-
ologies, and must be neither overconstrained nor undercon- out region has minimum area while satisfying aspect ratio
strained. The right solution ingredients are those which are constraints. This corresponds to a minimum whitespace ob-
scalable while delivering good solution quality according to jective. Optionally, the packing can attempt to minimize an
relevant metrics. We also describe new problem formula- estimate of the wiring needed to realize the netlist connectiv-
tions and solution ingredients, notably a perfect rectilinear ity. This corresponds to a minimum wirelength objective.2
floorplanning formulation that seeks zero-whitespace, per- With respect to wiring, early works such as [13] focused
fectly packed rectilinear floorplans in a fixed-die regime. The on channeled block layouts and the associated global rout-
paper closes with a list of questions for future research. ing and pin assignment issues. Today, for various reasons –
fixed-die regime, presynthesis floorplanning, N-layer metal
Categories and Subject Descriptors with available over-the-block routing – channelless layouts
B.7.2 [Hardware]: Integrated Circuits— design aids; place- are the norm and the top-level routing is more or less viewed
ment and routing; F.2.2 [Theory of Computation]: Anal- (or more accurately, ignored) as “area-routed”.
ysis of Algorithms and Problem Complexity—geometrical This invited paper addresses the question, “Classical floor-
problems and computations; routing and layout planning harmful?” The “classical floorplanning” problem
has inspired an immense literature of valuable research re-
General Terms sults. Nevertheless, “classical floorplanning” has in several
VLSI floorplanning, coarse placement, block packing and ways led researchers and practitioners to focus on the wrong
layout, hierarchical design methodology. problem. Examples include (i) preoccupation with packing
driven, as opposed to connectivity driven, problem formu-
1. INTRODUCTION lations and benchmarking practices; (ii) preoccupation with
Classical floorplanning takes as input a set of blocks, a netlist, only rectangular (and L- or T-shaped) block shapes; (iii)
and a target layout region. The (rectangular) blocks may lack of attention to the fixed-die context; (iv) lack of at-
be hard, soft or semi-soft. Hard blocks have fixed aspect tention to the overall RTL-down methodology context, and
ratio and pin locations. Soft blocks have fixed area, with to whether there are any real differences between “floorplan-
(upper- and lower-bounded) continuously variable aspect ra- ning” and “hierarchical approaches to achieving placement”;
tio. Semi-soft blocks have fixed area with discrete allowed and (v) lack of attention to achieving a holistic, scalable
∗This research supported by Cadence Design Systems, Inc. approach. The main conclusion is that the problem must
be changed. The right problem formulations must match
and the MARCO Gigascale Silicon Research Center. the purpose of floorplanning (i.e., coarse placement enabling
route planning), and the context of today’s convergent RTL-
down design methodologies. Furthermore, the right formula-
Permission to make digital or hard copies of all or part of this work 1
for personal or classroom use is granted without fee provided that An alternative taxonomy lumps soft blocks together with
copies are not made or distributed for profit or commercial advantage semi-soft blocks: since the layout region is row-based, block
and that copies bear this notice and the full citation on the first page. heights are discrete and there is no such thing as a block
To copy otherwise, to republish, to post on servers or to redistribute with continuously variable aspect ratio.
2
to lists, requires prior specific permission and/or a fee. The minimum wirelength objective is not yet consistently
ISPD 2000, San Diego, CA. addressed in either the definition or the reporting of bench-
Copyright 2000 ACM 1-58113-191-7/00/0004 ..$5.00 marks in the literature.

207
tions must be neither overconstrained nor underconstrained. • Complex objectives such as path-timing or wirelength
The right solution ingredients are those which are scalable seem difficult to handle with, e.g., annealing of se-
while delivering good solution quality according to relevant quence pairs. Notice, for example, that the whites-
metrics. pace and wirelength objectives are not simultaneously
The remainder of this paper is organized as follows. Section optimized by floorplan compaction.
2 of this paper gives limitations of the classical floorplanning • To handle objectives such as wirelength and path tim-
formulation, along with desiderata for an improved formula- ing, one must focus on connectivity. Indeed, the cor-
tion. Section 3 sketches a “perfect rectilinear floorplanning rect approach must be connectivity-centric, rather than
problem” (PRFP) formulation, along with an example solu- packing-centric. Packing must be made into a sec-
tion flow and supporting algorithm technologies. The PRFP ondary issue – or ideally, a non-issue.
seeks zero-whitespace, perfectly packed rectilinear floorplans
in a fixed-die regime, and is presented as an example alter- 2.2 Design Methodology Context
native to classical floorplanning. Section 4 concludes with a Floorplanning coarsely maps portions of the IC design to
few open research questions. portions of the IC layout region. It delivers “coarse embed-
ding” or “coarse placement” to support global interconnect
2. LIMITATIONS OF CLASSICAL FLOOR- planning and performance optimizations. We observe:
PLANNING • (Hierarchical) floorplanning is the natural response to
A modern floorplanner must deal with (i) up to thousands of
three facts of life: (i) complexity, (ii) the need for for-
blocks, including hard IP blocks and presynthesis RTL soft
ward prediction in a convergent design process, and
blocks; (ii) timing and routability objectives, as well as tight
(iii) the fact that the only useful prediction technolo-
interactions with route planning and performance optimiza-
gies we know of are constructive predictors. When
tion tools; and (iii) a fixed-die layout resource with discrete-
upstream tools cannot predict downstream outcomes,
ness (cell row pitch) in the vertical dimension. (This is not
they must constructively (e.g., by floorplanning and
very different from what a placer deals with!) In this sec-
top-level route planning) predict, then constrain, the
tion, we compare these modern floorplanning requirements
downstream outcomes. Hierarchy arises because hu-
against the “classical floorplanning” formulation.
mans are limited in how many things they can think
of at once. Hence, the sequence of no-floorplanning,
2.1 Obsession With Packing physical-floorplanning, RTL-floorplanning, etc. is nat-
The classical floorplanning literature has had an obsession ural as design complexities increase.
with packing (an NP-hard problem) and the minimum-whitespace • To find the most useful floorplanning formulations, es-
objective.3 Floorplan representations have evolved from pecially in light of “hierarchical floorplanning is hierar-
dual graphs (the standard representation in literatures such chical coarse placement”, we should ask whether there
as facility layout and architecture since the early 1970s [17] are any fundamental differences between the purpose
[8]) to slicing trees, to sequence-pairs [37], bounded-slicing of floorplanning and the purpose of placement.5 Along
grids [38], O-trees [18], etc. This evolution has been driven a similar vein, we should ask whether the design pro-
by the quest for a complete and irredundant representa- cess is really different depending on whether hierarchy
tion that allows efficient heuristic search for good packings.4 management is automated (within a block-based hier-
Since the solution spaces are so large, appropriate neigh- archical floorplanning tool) or manual. If the answer
borhood operators for iterative optimization metaheuristics to either question is “no”, then floorplanners should
(e.g., simulated annealing, evolutionary optimization, or tabu probably look more like placers than packers.6
search) are also sought. We make the following observations. • In modern methodologies, RTL is partitioned, floor-
planned, route-planned and optimized for performance
• Recent “complete” representations (SP, BSG, O-tree) before logic synthesis and place-and-route. Hence, area
require heavy coercion to deal with natural instance at- and performance are at best crudely estimated (hope-
tributes (e.g., fixed blocks, alignment constraints, and fully within 15%, but sensitive to block aspect ratios,
pitch-matching constraints for datapaths). Further- actual critical path structure after top-level routing
more, they suffer from combinatorial explosion when and pin assignment, etc.). The amount of effort spent
the instance contains semi-soft blocks that have many in addressing the resulting floorplan instances – and in
alternative realizations. Scalability to instances of hun- particular, their “zero whitespace” packing objectives
dreds or thousands of blocks seems out of reach. – must be impedance-matched to this level of accu-
• Working with a floorplan representation, rather than racy.7
directly with a floorplan realization, has overheads in 5
terms of cost function evaluation and accuracy. For ex- For example, non-rectangular shapes and noisy area esti-
ample, sizing and compaction steps are required before mates occur in floorplanning, but not in placement. How-
ever, these aspects of floorplanning instances may be side
one can even estimate the wirelength corresponding to effects of current abstractions of RT-level (timing and chip
a given sequence-pair. planning) design needs.
3 6
Published benchmarking practices and floorplanning met- Advances in design and process technologies could help re-
rics all focus on whitespace. We note that a more pragmatic move distinctions between floorplanning and placement. For
reaction to an NP-hard problem is to avoid it as much as example, better understanding of delay sensitivity with re-
possible. spect to sizing, and repeater library design, can together
4 eliminate the need for buffer block methodologies. A second
Other, more greedy/constructive approaches such as shelf-
packing or cluster growth in combination with zone- active device layer can make repeater insertion and associ-
refinement [28] have been attempted. However, solution ated floorplanning issues trivial [47].
7
quality is poor (and scales even more poorly). In addition, the modern use model for floorplanning en-

208
2.3 Overconstrained Shaping cast as a fixed-die problem, and the packing must simultane-
Soft floorplan blocks are created by partitioning and reclus- ously achieve zero whitespace and zero overlap for the given
tering of RT-level HDL code. Each block contains hundreds choice of fixed die. Current formulations do not enforce this
or thousands of standard cells, and is hence very granular. constraint.
The granularity of the layout resource is even finer: cell row
pitch (a few routing tracks) in the vertical dimension, and 3. PERFECT RECTILINEAR FLOORPLAN-
site width (less than a single track) in the horizontal dimen- NING
sion. We make several observations. In this section, we describe a new perfect rectilinear floor-
planning problem (PRFP) formulation that addresses many
• Restricting pre-synthesis or pre-place-and-route soft of the above issues. The discussion draws largely on the
blocks to rectangular, L- or T- shapes is an overcon- presentation in [9]. The PRFP formulation entails (i) a
straint. Even if hard blocks and synthesized datapaths fixed-die, zero-whitespace layout region into which rectilin-
with regular structure are present in the netlist, most ear blocks must be perfectly packed; (ii) discreteness con-
blocks will be amenable to non-rectangular shaping.8 straints on vertical edges in block boundaries (corresponding
• Even though “round” blocks with low aspect ratio help to row pitch in standard-cell layouts); and (iii) rectilinear
wire estimation, this does not mean that block shapes blocks that may be continuously shaped while maintaining
can have only four, six or eight sides (rectangle, L, T fixed area.
respectively). Roundness of a polygonal shape, in fact, Our premise is that no matter how good the block packer is,
has very little to do with the number of sides. there will be whitespace and overlaps in its solution. PRFP
• No requirement for particular block shapes arises from welcomes such “global floorplanning solutions”, and turns
the downstream place-and-route tools. For example, them into zero-whitespace, zero-overlap “detailed floorplan-
irregular block outlines can be handled by balance con- ning solutions” with minimum perturbation.
straints in a partitioning-based approach (similar to
how PDEF3.0 region constraints are handled in top- 3.1 An Example PRFP-Based Flow
down placers today). Analytic placers can also impose An example flow built around the PRFP formulation might
region constraints at appropriate levels of granularity be as follows.
to reflect complex block shapes.
• Finally, it is not even necessary for the blocks to be 1. RTL partitioning to create blocks. Hierarchy-aware,
non-overlapping as long as there is sufficient cell area bus structure-aware aware, timing constraint-aware re-
assigned to all blocks. As noted in the previous foot- cursive 2- and k-way partitioning engines can be built
note, arguably blocks should overlap and intermingle from existing algorithm components in the literature.
their contents. One possible formulation is to allow An important open research issue addresses the inter-
any given hierarchy block to cover its footprint with action between the block definition process (i.e., the
varying “depths” (i.e., densities with respect to avail- partitioning objective and constraints) and the floor-
able sites). Then, a legal floorplan solution is one that plan quality that is achievable with the resulting set
has total depth = 1 everywhere.9 of blocks.
2. Global floorplanning to create a connectivity- and timing-
driven, near-legal floorplan. The result of global floor-
2.4 Underconstrained Layout Region planning can have whitespace and overlaps. We be-
The classical floorplanning literature treats the die area as lieve that the key technologies for global floorplanning
having constrained aspect ratio, but unbounded size. The will be based on recursive top-down partitioning, since
objective is to “find the packing with smallest containing this affords a spatially convergent creation of the em-
die”. In reality, the use of floorplanning during the chip bedding. At the top levels of the physical hierarchy,
synthesis process almost always comes after the die size and packing effects are negligible. At the bottom levels
package have been chosen. Thus, floorplanning should be (e.g., < 10 blocks), branch-and-bound end case shap-
tails partial and probabilistic information, as well as many ing/packing can be applied to packing representations
types of ECOs. Thus, an ideal framework should deliver such as O-trees.
incremental and anytime [6] solutions. 3. Detailed floorplanning to obtain a set of rectilinear
8 block shapes with zero-whitespace and zero-overlap.
Color plots of logic hierarchy vs. final placed location in
highly optimized, flat placements show that cells of hierar- The detailed floorplanning solution should be as close
chy blocks tend to intermingle at the block boundaries. Ac- as possible to the global floorplanning solution, and
cordingly, terms like “amoeba placement”, “flexible block”, the complexity of block outlines should be minimized
etc. abound in the commercial EDA world today. For logic (see the discussion of shape metrics, below). Top-level
that is not built into a given system-on-chip platform, hard-
IP reuse is likely to decrease because of rapid scaling and routing and pin assignment can be performed in iter-
divergent process recipes. Thus, there will be more “soft- ation with both global and detailed floorplanning.
ness” in the part of the design that is synthesized from RTL 4. Generic standard-cell placement to achieve a legal, timing-
to layout. and routability-driven gate-level placement that re-
9
For example, two blocks with equal amounts of cell area spects detailed floorplan block outlines (if not as region
could be placed into adjacent disjoint regions, with each constraints, then as “suggestions”).
block having depth = 1 in its respective region. An alterna-
tive would be to place each block with uniform depth = 1/2
into the union of the two regions. This idea was first pro- This PRFP-based flow doubtless resembles existing RTL-
posed in 1987 by Prof. T. C. Hu in the context of a “TACP” down methodologies. However, it is more direct in exploit-
(tentative assignment and competitive pricing) approach to ing the flexibility and high quality of standard-cell place-
placement. ment (which typically follows block placement and logic

209
synthesis). It is consistent with flows in which standard- vertically within a range of H − (ymax − ymin ) units (here,
cell block synthesis and place-and-route follow after (soft- xmin is the leftmost x-coordinate of the vertices of rectan-
block dominated) RTL floorplanning (i.e., PRFP serves ei- gles, xmax is the rightmost, etc.). By slightly moving the
ther as a cleanup step after traditional floorplanning, or as global W ∗ H-rectangle, we may improve the distribution of
the end-case optimizer for recursive partitioning-based floor- white spaces with respect to the distribution of the overlap-
planning). The logic synthesis and timing optimizations oc- ping areas. Finally, the area of a simple rectilinear polygon
cur in “coarse mode” at the beginning of Step (3), and in with k vertices can be computed in O(k) time (e.g., [10]).
“detailed mode” at the beginning of Step (4). There is it-
Given all this information, we can build a graph G = (V, E)
eration. PRFP also removes unnecessary and artificial con-
(see Figure 1(d)):
straints on the floorplan solution that stem from the tradi-
tional “block packing” perspective; it reduces the pressure
on block packing algorithms and allows more connection- • With each rectangle associate a blue node (so, p1 , ..., pn );
centric (rather than packing-centric) approaches to be used. • With each simple white subpolygon, a white node (so,
w1 , ..., wm );
3.2 Some Details of Detailed Floorplanning
We now sketch some thoughts on the PRFP-based detailed • Draw an edge between pi and wj iff these polygons
floorplanning part of the above flow. We are given n rectan- share a common boundary;
gles R1 , . . . , Rn (some of them are overlapping) in the layout
region, as illustrated in Figure 1(a).10 The layout region is • Draw an edge (pi , pj ) iff Ri and Rj share a common
a “global” rectangle with fixed width W and height H. We boundary but do not have a common inner point;
have that the sum of the areas of rectangles is equal to the
area of the layout region (W · H). • Between each Ri and Rj which share a common inner
point (i.e., intersect each other) draw an edge (pi , pj ).
Turning the global floorplan into a detailed floorplan essen- Furthermore, associate with this intersection an addi-
tially means that overlaps must be migrated toward whites- tional red vertex sij and draw two edges (sij , pi ) and
pace, and vice-versa, until both disappear. This area migra- (sij , pj ).
tion (legalization) entails the following subproblems.
Using this graph, we can find efficient ways to migrate area
P1. Find all intersecting pairs of rectangles (overlapping or from overlap-spaces to white-spaces. A resulting iterative
touching each other); and greedy heuristic for area migration (legalization) might be
as follows.11
P2. Find all white simple rectilinear polygons (white spaces
that exist in the layout region because of overlapping while there is a white subpolygon
rectangles) and their areas.
do choose a white subpolygon w of largest area
Subproblem P1 can be solved in O(n2 ) time directly, or op-
timally in O(nlogn+s) time (where s is the number of inter- using the graph G find the closest to w red vertex r
secting pairs) by using plane-sweep techniques supported by
interval trees (see pp. 359-363 in [1]). Subproblem P2 can migrate area of size x = min{area(w), area(r)}
be solved as follows (see pp. 13-15 and 340-347 in [1]). Using
a plane-sweep technique supported by segment trees, deter- from r to w along a shortest (r, w)-path
mine the contour of the union F of n rectangles R1 , . . . , Rn ,
i.e., a collection of disjoint cycles composed of (alternating) put area(r) = area(r) − x, area(w) = area(w) − x
vertical and horizontal edges. This is illustrated in Figure
1(b). if area(r) = 0 then delete r from G
By convention, any edge is directed in such a way that
we have the figure on the left while traversing the edge. if area(w) = 0 then delete w from G
This is equivalent to saying that a cycle is oriented clock-
wise if it is the boundary of a hole (i.e., an inner whites- update the graph G
pace), and counterclockwise if it is an external boundary
of a connected component. Since all rectangles are in the
layout region (global rectangle of size W ∗ H), external At each iteration of the algorithm, we obtain a migration
boundary cycles are located inside of the global W ∗ H- path and an amount of area to migrate from an overlap-
rectangle. So, the holes and the regions between the bound- space to a white-space. For example, for an edge (v, u) of
ary of the global W ∗H-rectangle and the external boundary the (r, w)-path connecting two blue vertices or a blue vertex
cycles comprise our simple rectilinear polygons of whites- with a white vertex, x gives us the area that must migrate
pace. (See Figure 1(c).) The time complexity of this ap- from polygon pv to polygon pu (polygon pv borrows an area
proach is O(nlogn + p log(n2 /p)), where p is the number of size x from polygon pu ). For details, see [9]. Note that mi-
of edges in the contour that we find. Note that here we grating area of size x from an overlap-space to a white-space
can have some flexibility to shift the global W ∗ H-rectangle can change the adjacency between vertices in the graph G
horizontally within a range of W − (xmax − xmin ) units and 11
Other approaches are discussed in [9]: flow and/or trans-
10
The input does not have to consist of rectangular block portation approaches can operate on a structure similar to
shapes. We use this for simplicity, and to emphasize that the dual graph of the floorplan; physical-analog systems can
detailed floorplanning can be applied to results of existing be simulated; and geometric matching techniques can also
block packers. be used to match up overlap with nearby whitespace.

210
 (a) (b)

w5 R4
R4 w5
R3 s34
w1 R3 s45
w1 w6
w6
s23 s56
R2 R5 R6 s58
w2 R2
R8 w2 s38 R8
R6
R5 s67
s12
w3
w3
R1 s18
R1 s78
R7
w4
w4
R7

(c) (d)

Figure 1: (a) A global floorplanning result (rectangles); (b) the contour (defining whitespace); (c) whitespace
and overlap within the layout region; and (d) the corresponding graph.

(e.g., pi and pj are no longer neighbors, or they become

neighbors). So, after each iteration our graph can change
and we must update G. P1

The above approach (and other intuitive heuristics) gener-

ally entail solving the following subproblems many times
over.

P3. For two given simple rectilinear polygons Pi , Pj , that

touch each other, find their common boundary Γij - a P2
collection of disjoint chains composed of (alternating)
vertical and horizontal edges belonging to boundaries
of both polygons;

P4. Find a way to simplify the shape of Γij while trans-

ferring an amount of area x from Pj to Pi (without
disconnecting either of these polygons). Figure 2: Two polygons with common boundary.

Subproblem P3 can be directly solved in O((|Pi |+|Pj |)log|Pi |)

time. Subproblem P4 is the key to delivering a reasonable that Γ12 is connected, i.e., it is a chain of (alternating) ver-
detailed floorplanning result via area migration: it enables tical and horizontal edges belonging to boundaries of both
chains of “area borrowing” between regions. Addressing P4 polygons (see Figure 2). If Γ12 is not connected, then we
first requires a formal objective that captures “simplicity” can work on each connected part separately.
of a shape. To this end, we know that for a fixed area, the We seek to redraw the common boundary Γ12 so as to define
perimeter of an object increases as it becomes more irregu- two new polygons P10 and P20 in such a way that the length
lar in shape. Hence, we can use the perimeter of a polygon of the new common boundary Γ012 is minimized, subject to
as a measure of its shape irregularity. (For example, the
perimeter of a rectilinear object is minimized if the object • both P10 and P20 are simple rectilinear polygons;
is square-shaped.) Subproblem P4 is thus formalized as [9]:
• P1 ∪ P2 and P10 ∪ P20 are equal;
Given two simple rectilinear polygons P1 and P2 that touch
each other, and their common boundary Γ12 . We assume • area(P1 ) = area(P10 ) + x, area(P2 ) = area(P20 ) − x,

211
 where x is a given value; and for our PRFP context. An ideal shape metric should
distinguish between changes of aspect ratio, penalize
area(P1 ∩P10 )
• area(P1 )
≥ c, where c is a given constant. complex shapes, encourage blocks to remain as close
to their original locations as possible, and be quickly
Although this problem is NP-hard [9], it appears to be amenable computable [9].
to effective heuristics within a PRFP-based flow. Notice • Partitioning objectives that yield friendly floorplanning
that the variant of the problem when x = 0 is also of in- instances. As noted above, no research has yet ad-
terest since we may want to improve the boundary between dressed the interaction between the block definition
two polygons without borrowing any area (simply to make process (i.e., the RTL partitioning objective and con-
the shapes of polygons more regular); see also [24]. straints) and the floorplan quality that is achievable
with the resulting set of blocks. However, this issue
4. CONCLUSIONS AND OPEN QUESTIONS must be understood for the best solutions to remain
In this paper, I have tried to marshal support for a some- attainable as far down into the design process as pos-
what extreme and provocative title, “Classical Floorplan- sible.
ning Harmful?”. Of course, classical floorplanning has pro-
vided great benefits to researchers and designers alike, and 5. ACKNOWLEDGMENTS
any attempt to box its rich literature into a “strawman”
This paper draws heavily on recent results obtained with
is bound to displease some. Nevertheless, there are indeed
Andy Caldwell and Dr. Feodor Dragan at UCLA, cited as
several ways in which “classical floorplanning formulations”
[9]. Discussions with Doug Carroll (on flexibility metrics)
have diverged from real-world physical chip implementation
and with Dr. Ravi Varadarajan (on RTL-down planning in
requirements. The PRFP-based flow shows that it is possi-
general) have also been invaluable.
ble to remain purely connectivity- and timing-driven until
very late in the “floorplanning” game, and that packing can
be made into a virtual non-issue. The question of whether
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