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EE141 s09 Hw3 Solution

This document appears to be homework instructions from a professor for EECS 141 at the University of California. It includes 3 problems related to digital circuit design. Problem 1 involves calculating logical effort for skewed inverters and designing clock distribution networks. Problem 2 involves sizing gates in an OR logic circuit to minimize propagation delay for different load capacitances. Problem 3 involves sizing inverters in a clock distribution network and calculating the energy drawn and dissipated during a transition. The homework is due on February 13th and should be submitted in box 240 Cory.

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295 views6 pages

EE141 s09 Hw3 Solution

This document appears to be homework instructions from a professor for EECS 141 at the University of California. It includes 3 problems related to digital circuit design. Problem 1 involves calculating logical effort for skewed inverters and designing clock distribution networks. Problem 2 involves sizing gates in an OR logic circuit to minimize propagation delay for different load capacitances. Problem 3 involves sizing inverters in a clock distribution network and calculating the energy drawn and dissipated during a transition. The homework is due on February 13th and should be submitted in box 240 Cory.

Uploaded by

anil rajput
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF CALIFORNIA

College of Engineering
Department of Electrical Engineering and Computer Sciences

Jan M. Rabaey Homework #3 EECS 141


Due Friday, February 13, 5pm, box in 240 Cory

1. We sometimes design the inverter to favor one transition. Fig 1 shows two examples with
unequal rising and falling delays.

(a) (b)
Figure 1 Skewed inverters.

Figure 2 Clock distribution network.

(1) Calculate the logical effort of the skewed inverters shown in Fig. 1 for both rising and
falling output transitions. Which inverter does favor rising output transition? Why? (10
pts)
(2) Suppose the skewed inverters shown in Fig. 1 are included in your digital cell library.
Choose and design the inverter m1, m2, and m3 to minimize the delay Td for the low-to-
high input transition, as shown in Fig. 2. Calculate the delay Td and the corresponding
delay for the high-to-low input transition. (15 pts)

Solution:
(1) For skewed inverter (a):
Logical effort for the rising output transition
Logical effort for the falling output transition
For skewed inverter (b):
Logical effort for the rising output transition
Logical effort for the falling output transition
Skewed inverter (b) has the smaller logical effort for the rising output transition and
therefore favors rising output transition.

(2) For the low-to-high input transition, the output of m1 is pulled high, the output of m2 is
pulled low, and the output of m3 is pulled high. As a result, we can choose inverter (b) as
the second stage, inverter (a) as the third stage, and inverter (b) as the final stage to
minimize Td.

, , ,

Sizing of gates accordingly:


(Note: I use the same definition in the lecture note. Size 2 gate has twice the input
capacitance of a unit inverter)

, , ,

For the high-to-low input transition:

2. Following schematic implements the logic equation of (A+B+C+D). The four inverters
connected to inputs are minimum sized.
Figure 3 4-Input OR logic.

(1) If Cload is 25xCgmin, where Cgmin is the gate capacitance of a minimum-size inverter. Size
the NAND, NOR and INV gates to minimize the propagation delay from input to output.
(10 pts)
(2) Repeat part (1) if Cload is 1xCgmin. Be reminded that the input inverters are already
minimum sized. Subsequent gates therefore cannot be smaller than unit size. (10 pts)
(3) Can you design another circuit that implements the same logic but has shorter
propagation delay for the case of Cload =1xCgmin? The four input inverters come from the
I/O interface design. They can neither be replaced nor be resized. (10 pts)

Solution:
(1)

, , ,

Sizing of gates accordingly:


, , ,

(Above sizing is based on unit-size NAND and NOR gates that have equal resistance as a
unit-size inverter. If unit-size NAND and NOR gates are sized with equal input
capacitance as a unit-size inverter, sizing should then be: , s2 = 2.7 , s3 = 5.5 and
s4 = 8.7 .)

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(2) Using the same approach as in (1):

, this is impractical because a gate cannot be smaller than

unit size  (You get full credits too if you argue that the NAND gate can be sized
down to 0.5x, because the minimum transistor width in a unit-size NAND gate is 2. This
apparently does not apply to an NOR gate.)

Now apply logical effort analysis to the 3-stage circuit starting with NAND since its size
has been fixed.

, ,

Therefore,
, . Again this is impractical 

Finally apply logical effort analysis to the 2-stage circuit starting with NOR.

Final sizing schematic:


(Again above sizing is based on unit-size NAND and NOR gates that have equal
resistance as a unit-size inverter.)

(3) Actual fan-out in above schematic:

, , ,

Total propagation delay is

By rearranging the circuit to the following, propagation delay can be reduced (there are
other options such as using 4-input NOR):

Total propagation delay is:

3. Following schematic exemplifies a clock distribution network. The first inverter is of


minimum size (1×). Input capacitance of a minimum-size inverter is C. Also assume .
Figure 4 A clock distribution network.

(1) Size the inverter m1 and m2 for the minimum delay. (5 pts)
(2) Assume all inverters share the same supply Vdd. What is the total energy drawn from the
supply when the input switches from 0 to Vdd? What is the total energy dissipated as
heat? (10 pts)

Solution:

(1) For the first two stages:

For the last two stages:

(2) The total energy drawn from the supply when the input switches from 0 to Vdd is:

The total energy dissipated as heat is:

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