HALF USING ALL THREE MODELS

VHDL Behavioral Description

entity half_add is

port (I1, I2 : in bit; O1, O2 : out bit);

end half_add;

architecture behave_ex of half_add is

--The architecture consists of a process construct

begin
process (I1, I2)
--The above statement is process statement
begin
O1 <= I1 xor I2 after 10 ns;
O2 <= I1 and I2 after 10 ns;
end process;
end behave_ex;

VHDL Structural Description

entity system is

port (a, b : in bit;

sum, cout : out bit);
end system;

architecture struct_exple of system is

component xor2
--The above statement is a component statement
port(I1, I2 : in bit;
O1 : out bit);
end component;
component and2
port(I1, I2 : in bit;
O1 : out bit);
end component;
begin
X1 : xor2 port map (a, b, sum);
A1 : and2 port map (a, b, cout);
end struct_exple;

entity halfadder is
port (
a: in bit;
 b: in bit;
s: out bit;
c: out bit);
end halfadder;
architecture HA_DtFl of halfadder is

--The architecture has no process, component, cmos,

--tranif0, tran,or tranif0

begin
s <= a xor b;
c <= a and b;
end HA_DtFl;

DATA FLOW
mutiplexer

VHDL 2x1 Multiplexer Description

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2x1 is
port (A, B, SEL, Gbar : in std_logic;
Y : out std_logic);
end mux2x1;

architecture MUX_DF of mux2x1 is

signal S1, S2, S3, S4, S5 : std_logic;
 Begin

-- Assume 7 nanoseconds propagation delay

-- for all and, or, and not.

st1: Y <= S4 or S5 after 7 ns;

st2: S4 <= A and S2 and S1 after 7 ns;
st3: S5 <= B and S3 and S1 after 7 ns;
st4: S2 <= not SEL after 7 ns;
st5: S3 <= not S2 after 7 ns;
st6: S1 <= not Gbar after 7 ns;
end MUX_DF;

multiplier

VHDL 2x2 Unsigned Combinational Array Multiplier Description

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult_arry is
port (a, b : in std_logic_vector(1 downto 0);
P : out std_logic_vector (3 downto 0));
end mult_arry;

architecture MULT_DF of mult_arry is

begin
-- For simplicity propagation delay times are not considered
-- in this example.
P(0) <= a(0) and b(0);
 P(1) <= (a(0) and b(1)) xor (a(1) and b(0));
P(2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and
b(0)));
P(3) <= (a(1) and b(1)) and ((a(0) and b(1)) and (a(1) and
b(0)));
end MULT_DF;
D-lacth

VHDL D-Latch Description

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_Latch is
port (D, E : in std_logic;
Q, Qbar : buffer std_logic);
-- Q and Qbar are declared as buffer because they act as
--both input and output, they appear on the right and left
--hand side of signal assignment statements. inout or
-- linkage could have been used instead of buffer.
end D_Latch;

architecture DL_DtFl of D_Latch is

constant Delay_EorD : Time := 9 ns;
constant Delay_inv : Time := 1 ns;
begin
--Assume 9-ns propagation delay time between
--E or D and Qbar; and 1 ns between Qbar and Q.

Qbar <= (D and E) nor (not E and Q) after Delay_EorD;

Q <= not Qbar after Delay_inv;
end DL_DtFl;
behave
MUX

VHDL 2x1 Multiplexer Using IF-ELSE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_if is
port (A, B, SEL, Gbar : in std_logic; Y : out std_logic);
end MUX_if;
architecture MUX_bh of MUX_if is
begin
process (SEL, A, B, Gbar)
-- SEL, A, B, and Gbar are the sensitivity list of the process.
variable temp : std_logic;

--It is common practice in behavioral description to use

--variable(s) rather than signal(s). This is done to avoid
--any timing errors that may arise due to the sequential
--execution of signal statements by the behavioral
--description. Execution of variable assignment statements
--is the same as in C language. After calculating the value
--of the variable, it is assigned to the output signal.
--In this example, temp is calculated as the output of the
 --multiplexer. After calculation, temp is assigned to
--the output signal Y.

begin
if Gbar = '0' then
if SEL = '1' then
temp := B;
else
temp := A;
end if;
Y <= temp;
else
Y <= 'Z';
end if;
end process;

end MUX_bh;
VHDL 2x1 Multiplexer Using ELSE-IF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUXBH is
port (A, B, SEL, Gbar : in std_logic;
Y : out std_logic);
end MUXBH;
architecture MUX_bh of MUXBH is
begin
process (SEL, A, B, Gbar)
variable temp : std_logic;
begin
if (Gbar = '0') and (SEL = '1') then
temp := B;
elsif (Gbar = '0') and (SEL = '0')then
temp := A;
else
temp := 'Z'; -- Z is high impedance.
end if;
Y <= temp;
end process;
end MUX_bh;
D-LATCH

entity Dltch_sig is
port (d, E : in bit; Q : buffer bit; Qb : out bit);
--Q is declared as a buffer because it is an input/output
--signal; it appears on both the left and right
-- hand sides of assignment
--statements.
end Dltch_sig;
architecture DL_sig of Dltch_sig is
begin
process (d, E)
begin
if E = '1' then
Q <= d; -- signal assignment
Qb <= not Q; -- signal assignment
end if;
end process;

end DL_sig;
JK FLIPFLOP
VHDL Positive Edge-Triggered JK Flip-Flop Using Case
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is
port(JK : in bit_vector (1 downto 0);
clk : in std_logic; q, qb : out bit);
end JK_FF;

architecture JK_BEH of JK_FF is

begin
P1 : process (clk)
variable temp1, temp2 : bit;
begin
if rising_edge (clk) then
case JK is
when "01" => temp1 := '0';
when "10" => temp1 := '1';
when "00" => temp1 := temp1;
when "11" => temp1 := not temp1;
end case;
q <= temp1;
temp2 := not temp1;
qb <= temp2;
end if;
end process P1;

end JK_BEH;
VHDL 3-Bit Binary Counter Case Statement Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CT_CASE is
port (clk, clr : in std_logic;
q : buffer std_logic_vector (2 downto 0));
end CT_CASE;
architecture ctr_case of CT_CASE is
begin
ctr : process(clk)
variable temp : std_logic_vector (2 downto 0) := "101";
--101 is the initial value, so the counter starts from 110
begin
if rising_edge (clk) then
if clr = '0' then
case temp is
when "000" => temp := "001";
 when "001" => temp := "010";
when "010" => temp := "011";
when "011" => temp := "100";
when "100" => temp := "101";
when "101" => temp := "110";
when "110" => temp := "111";
when "111" => temp := "000";
when others => temp := "000";
end case;
else
temp := "000";
end if;
end if;
q <= temp;
end process ctr;
end ctr_case;
struct
VHDL Half Adder Descri with its component
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor2 is
port(I1, I2 : in std_logic; O1 : out std_logic);
end xor2;
architecture Xor2_0 of xor2 is
begin
O1 <= I1 xor I2;
end Xor2_0;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and2 is
port (I1, I2 : in std_logic; O1 : out std_logic);
end and2;
architecture and2_0 of and2 is
begin
O1 <= I1 and I2;
end and2_0;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_add is
port (a, b : in std_logic; S, C : out std_logic);
end half_add;
architecture HA_str of half_add is
component xor2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
 component and2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
begin
X1 : xor2 port map (a, b, S);
A1 : and2 port map (a, b, C);
end HA_str;
VHDL Code for Several Gates

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bind1 is
port (I1 : in std_logic; O1 : out std_logic);
end bind1;
architecture inv_0 of bind1 is
begin
O1 <= not I1; --This is an inverter with zero delay
end inv_0;
architecture inv_7 of bind1 is
begin
O1 <= not I1 after 7 ns; --This is an inverter with a 7-ns delay
end inv_7;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bind2 is
port (I1, I2 : in std_logic; O1 : out std_logic);
end bind2;
architecture xor2_0 of bind2 is
begin
O1 <= I1 xor I2; --This is exclusive-or with zero delay.
end xor2_0;
architecture and2_0 of bind2 is
begin
O1 <= I1 and I2; --This is a two input and gate with zero delay.
end and2_0;
architecture and2_7 of bind2 is
begin
O1 <= I1 and I2 after 7 ns; -- This is a two input and gate with 7-ns delay.
end and2_7;
architecture or2_0 of bind2 is
begin
O1 <= I1 or I2; -- This is a two input or gate with zero delay.
end or2_0;
architecture or2_7 of bind2 is
begin
 O1 <= I1 or I2 after 7 ns; -- This is a two input or gate with 7-ns delay.
end or2_7;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bind3 is
port (I1, I2, I3 : in std_logic; O1 : out std_logic);
end bind3;
architecture and3_0 of bind3 is
begin
O1 <= I1 and I2 and I3; -- This is a three input and gate with zero delay.
end and3_0;
architecture and3_7 of bind3 is
begin
O1 <= I1 and I2 and I3 after 7 ns; --This is a three input and gate with 7-ns delay.
end and3_7;
architecture or3_0 of bind3 is
begin
O1 <= I1 or I2 or I3; --This is a three input or gate with zero delay.
end or3_0;
architecture or3_7 of bind3 is
begin
O1 <= I1 or I2 or I3 after 7 ns; --This is a three input or gate with 7-ns delay.
end or3_7;
MUX

VHDL 2x1 Multiplexer with Active Low Enable

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2x1 is
port (A, B, SEL, Gbar : in std_logic;
Y : out std_logic);
end mux2x1;
architecture mux_str of mux2x1 is
 --Start Components Declaration
component and3
port (I1, I2, I3 : in std_logic; O1 : out std_logic);
end component;

--Only different types of components need be declared.

--Since the multiplexer has two identical AND gates,
--only one is declared.

component or2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
component Inv
port (I1 : in std_logic; O1 : out std_logic);
end component;

signal S1, S2, S3, S4, S5 : std_logic;

for all : and3 use entity work.bind3 (and3_7);
for all : Inv use entity work.bind1 (inv_7);
for Or1 : or2 use entity work.bind2 (or2_7);
begin
--Start instantiation
A1 : and3 port map (A,S2, S1, S4);
A2 : and3 port map (B,S3, S1, S5);
IV1 : Inv port map (SEL, S2);
IV2 : Inv port map (Gbar, S1);
IV3 : Inv port map (S2, S3);
or1 : or2 port map (S4, S5, Y);
end mux_str;
decoder
VHDL 2x4 Decoder with Tri-State Output
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder2x4 is
port (I : in std_logic_vector(1 downto 0); Enable : in
std_logic; D : out std_logic_vector (3 downto 0));

end decoder2x4;

architecture decoder of decoder2x4 is

component bufif1
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
component inv
port (I1 : in std_logic; O1 : out std_logic);
end component;
component and2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
for all : bufif1 use entity work.bind2 (bufif1);
for all : inv use entity work.bind1 (inv_0);
for all : and2 use entity work.bind2 (and2_0);
signal s0, s1, s2, s3 : std_logic;
signal Ibar : std_logic_vector (1 downto 0);
-- The above signals have to be declared before they can be used
begin
B0 : bufif1 port map (s0, Enable, D(0));
B1 : bufif1 port map (s1, Enable, D(1));
B2 : bufif1 port map (s2, Enable, D(2));
B3 : bufif1 port map (s3, Enable, D(3));
iv0 : inv port map (I(0), Ibar(0));
iv1 : inv port map (I(1), Ibar(1));
a0 : and2 port map (Ibar(0), Ibar(1), s0);
a1 : and2 port map (I(0), Ibar(1), s1);
a2 : and2 port map (Ibar(0), I(1), s2);
a3 : and2 port map (I(0), I(1), s3);
end decoder;
FULLADDER BY HALF ADDER
VHDL Full Adder Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FULL_ADDER is
Port (x, y, cin : in std_logic; sum, carry : out std_logic);
end FULL_ADDER;
architecture full_add of FULL_ADDER is
component HA
Port (I1, I2 : in std_logic; O1, O2 : out std_logic);
end component;
component or2
Port (I1, I2 : in std_logic; O1 : out std_logic);
end component;

for all : HA use entity work.bind22 (HA);

for all : or2 use entity work.bind2 (or2_0);
signal s0, c0, c1 : std_logic;

begin
HA1 : HA port map (y, cin, s0, c0);
HA2 : HA port map (x, s0, sum, c1);
r1 : or2 port map (c0, c1, carry);
end full_add;
SR LATCH

VHDL SR Latch with NOR Gates

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SR_latch is
port (R, S : in std_logic;
Q, Qbar : buffer std_logic);

--Q, Qbar are declared buffer because

--they behave as input and output.

end SR_latch;
 architecture SR_strc of SR_latch is
--Some simulators would not allow mapping between
--buffer and out. In this
--case, change all out to buffer.
component nor2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
for all : nor2 use entity work.bind2 (nor2_0);
begin
n1 : nor2 port map (S, Q, Qbar);
n2 : nor2 port map (R, Qbar, Q);
end SR_strc;
ripple carry adder

VHDL 3-Bit Ripple Carry Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity three_bit_adder is
port(x, y : in std_logic_vector (2 downto 0);
cin : in std_logic; sum : out std_logic_vector (2 downto 0);
cout : out std_logic);
end three_bit_adder;

architecture three_bitadd of three_bit_adder is

component full_adder
port (I1, I2, I3 : in std_logic; O1, O2 : out std_logic);
end component;
for all : full_adder use entity work.bind32 (full_add);
signal carry : std_logic_vector (1 downto 0);
begin
M0 : full_adder port map (x(0), y(0), cin, sum(0), carry(0));
M1 : full_adder port map (x(1), y(1), carry(0), sum(1), carry(1));
M2 : full_adder port map (x(2), y(2), carry(1), sum(2), cout);
end three_bitadd;