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Sequential Logic, Latches and Flip - Flops

1. The document discusses S-R latches, which are basic building blocks of flip-flops used in sequential digital circuits. 2. S-R latches can be constructed using cross-coupled NAND or NOR gates, with outputs Q and not-Q. 3. The state of the latch is determined by the inputs - it remains unchanged if both inputs are 1 for NAND or 0 for NOR, is set if the S input is 1 for NAND or 0 for NOR, and is reset if the R input is 1 for NAND or 0 for NOR.

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66 views20 pages

Sequential Logic, Latches and Flip - Flops

1. The document discusses S-R latches, which are basic building blocks of flip-flops used in sequential digital circuits. 2. S-R latches can be constructed using cross-coupled NAND or NOR gates, with outputs Q and not-Q. 3. The state of the latch is determined by the inputs - it remains unchanged if both inputs are 1 for NAND or 0 for NOR, is set if the S input is 1 for NAND or 0 for NOR, and is reset if the R input is 1 for NAND or 0 for NOR.

Uploaded by

AanyaAlang
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 14

Sequential logic, Latches and


Flip-Flops
Lesson 1

S-R Latch (Set-Reset Latch) using


Cross Coupled NANDs or NORs

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2


Outline
• SR Latch
• Cross coupled NANDs and NORs
• Unstable State (Race Condition

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3


SR Latch
• An S-R latch (set-reset latch) —a basic
building block of a FF in the digital
sequential circuits.
• A simplest from of a storage register unit
(memory unit)
• Consists of cross coupled NAND or NOR
gates.

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4


Outline
• SR Latch
• Cross coupled NANDs and NORs
• Unstable State (Race Condition

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5


Cross coupled NANDs
• Output Q and Q

R Q R Q
SR Latch
S Q
S
Q

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6


Cross Coupled NANDs
• Table Qn means same state as before

Input Output State


R S Q Q
1 1 Q Q Qn
0 1 Q Q Set
1 0 Q Q Reset
1 1 Q Q *
* means unstable state
Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7
Cross coupled NORs
• Output Q and Q

R Q R Q
SR Latch
S Q
S
Q

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8


Cross Coupled NORs
• Table Qn means same state as before

Input Output State


R S Q Q
0 0 Q Q Qn
1 0 Q Q Set
0 1 Q Q Reset
0 0 Q Q *
* means unstable state
Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9
No Change State in SR Latch
• If R reset and S set inputs are in activated. It
means made ‘1’, the logic state does not
change in case of SR latch of cross coupled
NANDs
• If R reset and S set inputs are in activated. It
means made ‘0’, the logic state does not
change in case of SR latch of cross coupled
NORs

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10


Set State in SR Latch
• If S set input activated. It means made ‘1’,
the logic state Q = 1 (set) in case of SR
latch of cross coupled NANDs
• If S set input activated. It means made ‘0’,
the logic state Q = 0 (set) in case of SR
latch of cross coupled NANDs

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11


Reset State in SR Latch
• If R set input activated. It means made ‘1’,
the logic state Q = 0 (reset) in case of SR
latch of cross coupled NANDs
• If R set input activated. It means made ‘0’,
the logic state Q = 1 (reset) in case of SR
latch of cross coupled NANDs

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12


Outline
• SR Latch
• Cross coupled NANDs and NORs
• Unstable State (Race Condition

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13


Cross Coupled NAND SR Latch
• If both R reset and S set inputs are inactivated. It
means made ‘0’, both Q and Q tend to be ‘1’.
[NAND gate characteristic is that only when both
inputs are 1,the output is 0.] The logic of the
circuit (Q is complement of Q) not satisfied, and
the final state at an instant after inputs R and S
changed to ‘0’, is only a matter of chance.
• Logic state is said to be indeterminate state or
racing state.
• Each state, Q =‘1’ and Q =‘0’, and Q =‘0’,
Q=‘1’ trying to race through.

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14


Cross Coupled NOR SR Latch
• If both R reset and S set inputs are
inactivated. It means made ‘1’, both Q and
Q tend to be ‘0’. The logic of the circuit is
not satisfied, and the final state at an instant
after the inputs R and S changed to ‘0’, is
only a matter of chance.
• Logic state is said to be indeterminate state
or racing state.
• Each state, Q =‘0’ and Q =‘1’, and Q =‘1’,
Q=‘0’ trying to race through.
Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15
Timing Diagram

• Refer Text

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16


Summary
We learnt
• Internal Devices and Port Registers
and their Addresses
• Timer Devices- Registers
• System Control Registers
• On-Chip Memory Addresses
• Memory Map
Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18
End of Lesson 1
S-R Latch (Set-Reset Latch) using
Cross Coupled NANDs or NORs
THANK YOU

Ch14L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20

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