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Lecture 9 - Sequential and Programmable Logic

Sequential logic uses both present inputs and previous outputs to determine its current outputs. It includes latches and flip flops, which are memory elements that store state. Latches continuously check inputs and change outputs accordingly without a clock, while flip flops use a clock signal. Common latches include the SR latch with NOR or NAND gates and the D latch.

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12 views

Lecture 9 - Sequential and Programmable Logic

Sequential logic uses both present inputs and previous outputs to determine its current outputs. It includes latches and flip flops, which are memory elements that store state. Latches continuously check inputs and change outputs accordingly without a clock, while flip flops use a clock signal. Common latches include the SR latch with NOR or NAND gates and the D latch.

Uploaded by

ShujaAmjad
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture 9

Sequential and programmable Logic

Latches, Flip Flops, Memory Registers,


RAM, ROM

1
Sequential logic
• Whose outputs are determined from present inputs as well as
previous outputs
• They are slower than combinational circuits
• It consists of input variables, logic gates, memory unit and output
variables
• Example:
Flip Flops, counters

2
Latches
• Continuously check its inputs and changes its output accordingly
• It does not require clock signal
• It is based on the enable signal
• Power requirement of latch is less
• Different latches are
- SR latch with NOR gates
- SR latch with NAND gates
- SR latch with control input
- D latch

3
SR Latch with NOR Gates
R
• Gate level representation

S
• Truth table S R Output
0 0 No change
1 0 Q=1
0 1 Q=0
• Waveform 1 1 Invalid

4
SR Latch with NAND Gates
• Gate level representation

• Truth table S R Output


1 1 No change
0 1 Q=1
1 0 Q=0
• Waveform 0 0 Invalid

5
SR Latch with Enable Input
S'

• Gate level representation

R'

• Truth table

E S R Output
0 X X No change
1 0 0 No change
1 0 1 Q=0
1 1 0 Q=1
1 1 1 Invalid 6
D Latch
• Gate level representation

• Truth table E D Output


0 X No change
1 0 0
1 1 1
• Waveform

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