Logic Circuits Indiabix

LOGIC CIRCUITS INDIABIX
1. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?

A. 1
B. 2
C. 4
D. 8
Answer: Option C
Explanation:
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2. Which of the figures shown below represents the exclusive-NOR gate?
A. a
B. b
C. c
D. d
Answer: Option B
Explanation:
3. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

A. a
B. b
C. c
D. d
Answer: Option D
Explanation:
4. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input
be LOW. What is the status of the Y output?
A. LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A
Explanation:
5. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input
be HIGH. What is the status of the Y output?
A. LOW
B. HIGH
C. Don't Care
D. Cannot be determined
Answer: Option A
Explanation:
6. Convert BCD 0001 0010 0110 to binary.
A. 1111110
B. 1111101
C. 1111000
D. 1111111
Answer: Option A
Explanation:
7. A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What
would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
A.
B.
C.
D.
Answer: Option A
Explanation:
8. Convert BCD 0001 0111 to binary.

A. 10101
B. 10010
C. 10001
D. 11000
Answer: Option C
Explanation:
9. Which of the figures in figure (a to d) is equivalent to figure (e)?

A. a
B. b
C. c
D. d
Answer: Option B
Explanation:
10. How many data select lines are required for selecting eight inputs?
A. 1
B. 2
C. 3
D. 4
Answer: Option C
Explanation:
11. The simplest equation which implements the K-map shown below is:
A.
B.
C.
D.
Answer: Option A
Explanation:
12. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A. 5
B. 6
C. 7
D. 8
Answer: Option D
Explanation:
13. Which of the following logic expressions represents the logic diagram shown?
A.
B.
C.
D.
Answer: Option D
Explanation:
14. The implementation of simplified sum-of-products expressions may be easily implemented into
actual logic circuits using all universal ________ gates with little or no increase in circuit
complexity. (Select the response for the blank space that will BEST make the statement true.)
A. AND/OR
B. NAND
C. NOR
D. OR/AND
Answer: Option B
Explanation:
15. Which of the following statements accurately represents the two BEST methods of logic circuit
simplification?
A. Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis
C. Actual circuit trial and error evaluation and waveform analysis
D. Boolean algebra and actual circuit trial and error evaluation

Answer: Option A
Explanation:
16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and
the input is HIGH. What is the status of the outputs?
A. All are HIGH.
B. All are LOW.
C. All but are LOW.
D. All but are HIGH.

Answer: Option A
Explanation:
17. Which of the following combinations cannot be combined into K-map groups?
A. Corners in the same row
B. Corners in the same column
C. Diagonal corners
D. Overlapping combinations
Answer: Option C
Explanation:
18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You
have taken several readings at numerous IC chips, but the readings are inconclusive because of
their erratic nature. Of the possible faults listed, select the one that most probably is causing the
problem.
A. A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to Vcc

Answer: Option C
Explanation:
19. Which gate is best used as a basic comparator?

A. NOR
B. OR
C. Exclusive-OR
D. AND
Answer: Option C
Explanation:
20. The device shown here is most likely a ________.
A. comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option C
Explanation:
21. In VHDL, macrofunctions is/are:
A. digital circuits.
B. analog circuits.
C. a set of bit vectors.

D. preprogrammed TTL devices.
Answer: Option D
Explanation:
22. Which of the following expressions is in the product-of-sums form?

A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD
Answer: Option A
Explanation:
23. Which of the following is an important feature of the sum-of-products form of expressions?
A. All logic circuits are reduced to nothing more than simple AND and OR operations.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
The maximum number of gates that any signal must pass through is reduced by a factor
D.
of two.
Answer: Option A
Explanation:
24. For the device shown here, assume the D input is LOW, both S inputs are LOW, and
the input is LOW. What is the status of the outputs?
A. All are HIGH.

B. All are LOW.
C. All but are LOW.
D. All but are HIGH.

Answer: Option D
Explanation:
25. An output gate is connected to four input gates; the circuit does not function. Preliminary tests
with the DMM indicate that the power is applied; scope tests show that the primary input gate
has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on
different ICs. Which instrument will best help isolate the problem?
A. Current tracer
B. Logic probe
C. Oscilloscope
D. Logic analyzer
Answer: Option A
Explanation:
26. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are
the output levels?
A. A > B = 1, A B = 0, A B = 1, A B = 0, A < B = 1, A = B = 1
Answer: Option C
Explanation:
27. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used
on each of the input terminals, but the output indication does not change. What is wrong?
A. The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.

Answer: Option A
Explanation:
28. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input
is 1. What are the values for the sum and carry output?
A. 4 3 2 1 = 0111, Cout = 0
B. 4 3 2 1 = 1111, Cout = 1
C. 4 3 2 1 = 1011, Cout = 1
D. 4 3 2 1 = 1100, Cout = 1
Answer: Option C
Explanation:
29. Each "1" entry in a K-map square represents:

A. a HIGH for each input truth table condition that produces a HIGH output.
B. a HIGH output on the truth table for all LOW input combinations.
C. a LOW output for all possible HIGH input conditions.
D. a DON'T CARE condition for all possible input truth table combinations.
Answer: Option A
Explanation:
30. Looping on a K-map always results in the elimination of:

A. variables within the loop that appear only in their complemented form.
B. variables that remain unchanged within the loop.
C. variables within the loop that appear in both complemented and uncomplemented form.
D. variables within the loop that appear only in their uncomplemented form.
Answer: Option C
Explanation:
31. What will a design engineer do after he/she is satisfied that the design will work?
A. Put it in a flow chart
B. Program a chip and test it

C. Give the design to a technician to verify the design
D. Perform a vector test

Answer: Option B
Explanation:
32. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the
circuit?
The logic probe is unable to determine the state of the circuit at that point and is blinking
A.
to alert the technician to the problem.
B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.
C. The output appears to be LOW, but is being pulsed by the pulser.
D. Nothing appears to be wrong at that point.

Answer: Option D
Explanation:
33. What is the indication of a short on the input of a load gate?

A. Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.

There is a signal loss to all gates on the node, and the affected node will be stuck in the
D.
LOW state.
Answer: Option D
Explanation:
34. In HDL, LITERALS is/are:

A. digital systems.
B. scalars.
C. binary coded decimals.
D. a numbering system.
Answer: Option B
Explanation:
35. Which of the following expressions is in the sum-of-products form?

A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD
Answer: Option D
Explanation:
36. The carry propagation can be expressed as ________.
A. Cp = AB
B. Cp = A + B
C.
D.
Answer: Option B
Explanation:
37. Which of the K-maps given below represents the expression X = AC + BC + B?

A. a
B. b
C. c
D. d
Answer: Option C
Explanation:
38. A decoder can be used as a demultiplexer by ________.

A. tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input
Answer: Option D
Explanation:
39. How many 4-bit parallel adders would be required to add two binary numbers each representing
decimal numbers up through 30010?
A. 1
B. 2
C. 3
D. 4
Answer: Option C
Explanation:
40. Which statement below best describes a Karnaugh map?

A. A Karnaugh map can be used to replace Boolean rules.
B. The Karnaugh map eliminates the need for using NAND and NOR gates.
C. Variable complements can be eliminated by using Karnaugh maps.
D. Karnaugh maps provide a visual approach to simplifying Boolean expressions.

Answer: Option D
Explanation:
41. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform
is correct?
A. a
B. b
C. c
D. d
Answer: Option D
Explanation:
42. A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which
output goes LOW when the inputs are 1001?
A. 0
B. 3
C. 9
D. None. All outputs are HIGH.

Answer: Option C
Explanation:
43. Solve the network in the figure given below for X.
A. A + BC + D
B. ((A + B)C) + D
C. D(A + B + C)
D. (AC + BC)D
Answer: Option B
Explanation:
44. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?
A. = 0, Cout = 0
B. = 0, Cout = 1
C. = 1, Cout = 0
D. = 1, Cout = 1
Answer: Option B
Explanation:
45. What type of logic circuit is represented by the figure shown below?
A. XOR
B. XNOR
C. XAND
D. XNAND
Answer: Option B
Explanation:
46. The device shown here is most likely a ________.
A. comparator
B. multiplexer
C. demultiplexer
D. parity generator
Answer: Option B
Explanation:
47. The design concept of using building blocks of circuits in a PLD program is called a(n):
A. hierarchical design.
B. architectural design.
C. digital design.
D. verilog.
Answer: Option A
Explanation:
48. When adding an even parity bit to the code 110010, the result is ________.
A. 1110010
B. 1111001
C. 110010
D. 001101
Answer: Option A
Explanation:
49. Which of the following combinations of logic gates can decode binary 1101?
A. One 4-input AND gate
B. One 4-input AND gate, one OR gate
C. One 4-input NAND gate, one inverter
D. One 4-input AND gate, one inverter

Answer: Option D
Explanation:
50. What is the indication of a short to ground in the output of a driving gate?
A. Only the output of the defective gate is affected.
B. There is a signal loss to all load gates.
C. The node may be stuck in either the HIGH or the LOW state.
D. The affected node will be stuck in the HIGH state.

Answer: Option B
Explanation:
How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder,
have?
A. 3
B. 4
C. 5
D. 6
Answer: Option B
Explanation:
1. How many inputs are required for a 1-of-10 BCD decoder?
A. 4
B. 8
C. 10
D. 1
Answer: Option A
Explanation:
2. Most demultiplexers facilitate which of the following?

A. decimal to hexadecimal
B. single input, multiple outputs
C. ac to dc
D. odd parity to even parity

Answer: Option B
Explanation:
3. One application of a digital multiplexer is to facilitate:

A. code conversion
B. parity checking
C. parallel-to-serial data conversion
D. data generation
Answer: Option C
Explanation:
4. Select one of the following statements that best describes the parity method of error detection:
A. Parity checking is best suited for detecting single-bit errors in transmitted codes.
Parity checking is best suited for detecting double-bit errors that occur during the
B.
transmission of codes from one location to another.
C. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
D. Parity checking is capable of detecting and correcting errors in transmitted codes.

Answer: Option A
Explanation:
5. A multiplexed display:
A. accepts data inputs from one line and passes this data to multiple output lines
B. uses one display to present two or more pieces of information
C. accepts data inputs from multiple lines and passes this data to multiple output lines
D. accepts data inputs from several lines and multiplexes this input data to four BCD lines
Answer: Option B
Explanation:
7. Which type of decoder will select one of sixteen outputs, depending on the 4-bit binary input
value?
A. hexadecimal
B. dual octal outputs
C. binary-to-hexadecimal
D. hexadecimal-to-binary
Answer: Option A
Explanation:
8. A magnitude comparator determines:

A. A B and if A B or A >> B
B. A B and if A > B or A B or A B
Answer: Option C
Explanation:
9. A circuit that responds to a specific set of signals to produce a related digital signal output is
called a(n):
A. BCD matrix
B. display driver
C. encoder
D. decoder
Answer: Option C
Explanation:
10. Which digital system translates coded characters into a more intelligible form?
A. encoder
B. display
C. counter
D. decoder
Answer: Option D
Explanation:
11. A basic multiplexer principle can be demonstrated through the use of a:
A. single-pole relay
B. DPDT switch
C. rotary switch
D. linear stepper
Answer: Option C
Explanation:
12. In a BCD-to-seven-segment converter, why must a code converter be utilized?

A. No conversion is necessary.
B. to convert the 4-bit BCD into gray code
C. to convert the 4-bit BCD into 10-bit code
D. to convert the 4-bit BCD into 7-bit code

Answer: Option D
Explanation:
1. The format used to present the logic output for the various combinations of logic inputs to a gate
is called a(n):
A. truth table.
B. input logic function.
C. Boolean constant.
D. Boolean variable.
Answer: Option A
Explanation:
2. What is the basic difference between AHDL and VHDL?

A. ADHL is used in all PLD's.
B. VHDL is used in all PLD's.
C. ADHL is proprietary.
D. VHDL is proprietary.
Answer: Option C
Explanation:
3. A small circle on the output of a logic gate is used to represent the:

A. Comparator operation.
B. OR operation.
C. NOT operation.
D. AND operation.
Answer: Option C
Explanation:
4. For a three-input OR gate, with the input waveforms as shown below, which output waveform is
correct?
A. a
B. b
C. c
D. d
Answer: Option B
Explanation:
5. Which of the figures given below represents a NOR gate?
A. a
B. b
C. c
D. d
Answer: Option D
Explanation:
6. Which of the figures (a to d) is the DeMorgan equivalent of Figure (e)?
A. a
B. b
C. c
D. d
Answer: Option A
Explanation:
7. Which of the figures in figure (a to d) is equivalent to figure (e)?
A. a
B. b
C. c
D. d
Answer: Option C
Explanation:
8. In VHDL, the mode of a port does not define:
A. an input.
B. an output.
C. both an input and an output.
D. the TYPE of the bit.

Answer: Option D
Explanation:
9. Which of the following equations would accurately describe a 4-input OR gate when A = 1, B =
1, C = 0, and D = 0?
A. 1+1+0+0=1
B. 1 + 1 + 0 + 0 = 01
C. 1 + 1 + 0 + 0 = 0
D. 1 + 1 + 0 + 0 = 00
Answer: Option A
Explanation:
10. Which of the examples below expresses the distributive law?

A. (A + B) + C = A + (B + C)
B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
D. A(BC) = (AB) + C
Answer: Option B
Explanation:
11. Which of the examples below expresses the associative law of addition:
A. A + (B + C) = (A + B) + C
B. A + (B + C) = A + (BC)
C. A(BC) = (AB) + C
D. ABC = A + B + C
Answer: Option A
Explanation:
12. How are the statements between BEGIN and END not evaluated in VHDL?
A. Constantly
B. Simultaneously
C. Concurrently
D. Sequentially
Answer: Option D
Explanation:
13. Which logic gate does this truth table describe?
A. AND
B. OR
C. NAND
D. NOR
Answer: Option D
Explanation:
14. For a 3-input NAND gate, with the input waveforms as shown below, which output waveform is
correct?
A. a
B. b
C. c
D. d
Answer: Option C
Explanation:
15. Which of the figures given below represents a NAND gate?
A. a
B. b
C. c
D. d
Answer: Option A
Explanation:
16. Which timing diagram shown below is correct for an inverter?
A. a
B. b
C. c
D. d
Answer: Option B
Explanation:
17. A NOR gate with one HIGH input and one LOW input:
A. will output a HIGH
B. functions as an AND
C. will not function
D. will output a LOW

Answer: Option D
Explanation:
18. A NAND gate has:

A. active-LOW inputs and an active-HIGH output.
B. active-LOW inputs and an active-LOW output.
C. active-HIGH inputs and an active-HIGH output.
D. active-HIGH inputs and an active-LOW output.

Answer: Option D
Explanation:
19. Which of the figures given below represents an OR gate?
A. a
B. b
C. c
D. d
Answer: Option A
Explanation:
20. Which of the following is a form of DeMorgan's theorem?

A.
B.
C.
D.
Answer: Option C
Explanation:
21. The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):
A. NOR gate
B. OR gate
C. AND gate
D. NOT operation
Answer: Option B
Explanation:
22. Which of the symbols shown below represents an AND gate?

A. a
B. b
C. c
D. d
Answer: Option D
Explanation:
23. For a three-input AND gate, with the input waveforms as shown below, which output waveform is
correct?
A. a
B. b
C. c
D. d
Answer: Option C
Explanation:
24. An OR gate with inverted inputs functions as:

A. an AND gate.
B. a NAND gate.
C. a NOR gate.
D. an inverter.
Answer: Option B
Explanation:
25. The special software application that translates from HDL into a grid of 1's and 0's, which can be
loaded into a PLD, is called a:
A. formatter.
B. compiler.
C. programmable wiring.
D. CPU.
Answer: Option B
Explanation:
26. The Boolean equation for a NOR function is:
A.
B.
C.
D.
Answer: Option B
Explanation:
27. Which step in this reduction process is using DeMorgan's theorem?

A. STEP 1
B. STEP 2
C. STEP 3
D. STEP 4
Answer: Option A
Explanation:
28.
Simplify the expression using DeMorgan's theorems.
A.
B.
C.
D.
Answer: Option B
Explanation:
29. For a three-input NOR gate, with the input waveforms as shown below, which output waveform
is correct?
A. a
B. b
C. c
D. d
Answer: Option A
Explanation:
1. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.
A. A = 1, B = 1, C = 0
B. A = 0, B = 0, C = 0
C. A = 1, B = 1, C = 1
D. A = 1, B = 0, C = 1
Answer: Option C
Explanation:
2. If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a
HIGH output?
A. 1
B. 2
C. 7
D. 8
Answer: Option A
Explanation:
3. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the
output is HIGH, the gate is a(n):
A. AND
B. NAND
C. NOR
D. OR
4. A device used to display one or more digital signals so that they can be compared to expected
timing diagrams for the signals is a:
A. DMM
B. spectrum analyzer
C. logic analyzer
D. frequency counter
Answer: Option C
Explanation:
5. When used with an IC, what does the term "QUAD" indicate?
A. 2 circuits
B. 4 circuits
C. 6 circuits
D. 8 circuits
Answer: Option B
Explanation:
6. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.
A. A = 0, B = 0, C = 0
B. A = 0, B = 0, C = 1
C. A = 0, B = 1, C = 1
D. all of the above
Answer: Option A
Explanation:
7. Which of the following logical operations is represented by the + sign in Boolean algebra?
A. inversion
B. AND
C. OR
D. complementation
Answer: Option C
Explanation:
8. Output will be a LOW for any case when one or more inputs are zero for a(n):
A. OR gate
B. NOT gate
C. AND gate
D. NOR gate
Answer: Option C
Explanation:
9. How many pins does the 4049 IC have?

A. 14
B. 16
C. 18
D. 20
Answer: Option B
Explanation:
10. Which of the following choices meets the minimum requirement needed to create specialized
waveforms that are used in digital control and sequencing circuits?
A. basic gates, a clock oscillator, and a repetitive waveform generator
B. basic gates, a clock oscillator, and a Johnson shift counter
C. basic gates, a clock oscillator, and a DeMorgan pulse generator
basic gates, a clock oscillator, a repetitive waveform generator, and a Johnson shift
D.
counter
Answer: Option A
Explanation:
11. TTL operates from a ________.
A. 9-volt supply
B. 3-volt supply
C. 12-volt supply
D. 5-volt supply
Answer: Option D
Explanation:
12. The output of a NOR gate is HIGH if ________.

A. all inputs are HIGH
B. any input is HIGH
C. any input is LOW
D. all inputs are LOW

Answer: Option D
Explanation:
13. The switching speed of CMOS is now ________.

A. competitive with TTL
B. three times that of TTL
C. slower than TTL
D. twice that of TTL

Answer: Option A
Explanation:
14. The format used to present the logic output for the various combinations of logic inputs to a gate
is called a(n):
A. Boolean constant
B. Boolean variable
C. truth table
D. input logic function

Answer: Option C
Explanation:
15. The power dissipation, PD, of a logic gate is the product of the ________.
A. dc supply voltage and the peak current
B. dc supply voltage and the average supply current
C. ac supply voltage and the peak current
D. ac supply voltage and the average supply current

Answer: Option B
Explanation:
16. A logic probe is again applied to the pins of a 7421 IC with the following results. Is there a
problem with the circuit and if so, what is the problem?
A. Pin 6 should be ON.
B. Pin 8 should be ON.
C. Pin 8 should be pulsing.

D. no problem
Answer: Option D
Explanation:
17. If a 3-input AND gate has eight input possibilities, how many of those possibilities will result in a
HIGH output?
A. 1
B. 2
C. 7
D. 8
Answer: Option A
Explanation:
18. The Boolean expression for a 3-input AND gate is ________.

A. X = AB
B. X = ABC
C. X = A + B + C
D. X = AB + C
Answer: Option B
Explanation:
19. A CMOS IC operating from a 3-volt supply will consume ________.

A. less power than a TTL IC
B. more power than a TTL IC
C. the same power as a TTL IC
D. no power at all
Answer: Option A
Explanation:
20. What does the small bubble on the output of the NAND gate logic symbol mean?
A. open collector output
B. tristate
C. The output is inverted.
D. none of the above

Answer: Option C
Explanation:
21. What are the pin numbers of the outputs of the gates in a 7432 IC?
A. 3, 6, 10, and 13
B. 1, 4, 10, and 13
C. 3, 6, 8, and 11
D. 1, 4, 8, and 11
Answer: Option C
Explanation:
22. The output of a NOT gate is HIGH when ________.

A. the input is LOW
B. the input is HIGH
C. power is applied to the gate's IC
D. power is removed from the gate's IC

Answer: Option A
Explanation:
23. If the input to a NOT gate is A and the output is X, then ________.
A. X=A
B.
C. X = 0

Answer: Option B
Explanation:
24. A logic probe is used to test the pins of a 7411 IC with the following results. Is there a problem
with the chip and if so, what is the problem?
A. Pin 6 should be ON.
B. Pin 6 should be pulsing.
C. Pin 8 should be ON.
D. no problem
Answer: Option B
Explanation:
25. How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate
to go HIGH?
A. any one of the inputs
B. any two of the inputs
C. any three of the inputs
D. all four inputs

Answer: Option D
Explanation:
26. If the output of a three-input AND gate must be a logic LOW, what must the condition of the
inputs be?
A. All inputs must be LOW.
B. All inputs must be HIGH.
C. At least one input must be LOW.
D. At least one input must be HIGH.

Answer: Option C
Explanation:
27. Logically, the output of a NOR gate would have the same Boolean expression as a(n):
A. NAND gate immediately followed by an inverter
B. OR gate immediately followed by an inverter
C. AND gate immediately followed by an inverter
D. NOR gate immediately followed by an inverter

Answer: Option B
Explanation:
28. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used
on each of the input terminals, but the output indication does not change. What is wrong?
A. The dim indication on the logic probe indicates that the supply voltage is probably low.
B. The output of the gate appears to be open.
C. The dim indication is the result of a bad ground connection on the logic probe.
D. The gate is a tristate device.

Answer: Option B
Explanation:
29. What is the Boolean expression for a three-input AND gate?

A. X=A+B+C
B. X = A BC
C. A – B – C
D. A $ B $ C
Answer: Option B
Explanation:
30. Which of the following gates has the exact inverse output of the OR gate for all possible input
combinations?
A. NOR
B. NOT
C. NAND
D. AND
Answer: Option A
Explanation:
31. What is the difference between a 7400 and a 7411 IC?
A. 7400 has two four-input NAND gates; 7411 has three three-input AND gates
B. 7400 has four two-input NAND gates; 7411 has three three-input AND gates
C. 7400 has two four-input AND gates; 7411 has three three-input NAND gates
D. 7400 has four two-input AND gates; 7411 has three three-input NAND gates
Answer: Option B
Explanation:
32. Write the Boolean expression for an inverter logic gate with input C and output Y.
A. Y=C
B. Y =
Answer: Option B
Explanation:
33. The output of an exclusive-OR gate is HIGH if ________.

A. all inputs are LOW
B. all inputs are HIGH
C. the inputs are unequal

Answer: Option C
Explanation:
34. A clock signal with a period of 1 s is applied to the input of an enable gate. The output must
contain six pulses. How long must the enable pulse be active?
A. Enable must be active for 0 s.
B. Enable must be active for 3 s.
C. Enable must be active for 6 s.
D. Enable must be active for 12 s.

Answer: Option C
Explanation:
35. The AND function can be used to ________ and the OR function can be used to ________ .
A. enable, disable
B. disable, enable
C. enable or disable, enable or disable
D. detect, invert
Answer: Option C
Explanation:
36. One advantage TTL has over CMOS is that TTL is ________.
A. less expensive
B. not sensitive to electrostatic discharge
C. faster
D. more widely available

Answer: Option B
Explanation:
37. A 2-input NOR gate is equivalent to a ________.

A. negative-OR gate
B. negative-AND gate
C. negative-NAND gate

Answer: Option B
Explanation:
38. If a 3-input OR gate has eight input possibilities, how many of those possibilities will result in a
HIGH output?
A. 1
B. 2
C. 7
D. 8
Answer: Option C
Explanation:
39. Fan-out is specified in terms of ________.

A. voltage
B. current
C. wattage
D. unit loads
Answer: Option D
Explanation:
40. How many input combinations would a truth table have for a six-input AND gate?
A. 32
B. 48
C. 64
D. 128
Answer: Option C
Explanation:
41. What is the circuit number of the IC that contains four two-input AND gates in standard TTL?
A. 7402
B. 7404
C. 7408
D. 7432
Answer: Option C
Explanation:
42. The terms "low speed" and "high speed," applied to logic circuits, refer to the ________.
A. rise time
B. fall time
C. propagation delay time
D. clock speed
Answer: Option C
Explanation:
43. The NOR logic gate is the same as the operation of the ________ gate with an inverter
connected to the output.
A. OR
B. AND
C. NAND

Answer: Option A
Explanation:
44. The logic expression for a NOR gate is ________.

A.
B.
C.
D.
Answer: Option D
Explanation:
45. With regard to an AND gate, which statement is true?
A. An AND gate has two inputs and one output.
B. An AND gate has two or more inputs and two outputs.
C. If one input to a 2-input AND gate is HIGH, the output reflects the other input.
D. A 2-input AND gate has eight input possibilities.

Answer: Option C
Explanation:
46. The term "hex inverter" refers to:
A. an inverter that has six inputs
B. six inverters in a single package
C. a six-input symbolic logic device
D. an inverter that has a history of failure

Answer: Option B
Explanation:
47. How many inputs are on the logic gates of a 74HC21 IC?
A. 1
B. 2
C. 3
D. 4
Answer: Option D
Explanation:
48. The basic logic gate whose output is the complement of the input is the:
A. OR gate
B. AND gate
C. inverter
D. comparator
Answer: Option C
Explanation:
49. When reading a Boolean expression, what does the word "NOT" indicate?
A. the same as
B. inversion
C. high
D. low
Answer: Option B
Explanation:
50. The output of an exclusive-NOR gate is HIGH if ________.

A. the inputs are equal
B. one input is HIGH, and the other input is LOW
C. the inputs are unequal

Answer: Option A
Explanation:
51. How many AND gates are found in a 7411 IC?
A. 1
B. 2
C. 3
D. 4
Answer: Option C
Explanation:
52. Which of the following equations would accurately describe a four-input OR gate when A =
1, B = 1, C = 0, and D = 0?
A. 1 + 1 + 0 + 0 = 01
B. 1 + 1 + 0 + 0 = 1
C. 1 + 1 + 0 + 0 = 0
D. 1 + 1 + 0 + 0 = 00
Answer: Option B
Explanation:
53. What is the name of a digital circuit that produces several repetitive digital waveforms?
A. an inverter
B. an OR gate
C. a Johnson shift counter
D. an AND gate
Answer: Option C
Explanation:
54. The basic types of programmable arrays are made up of ________.

A. AND gates
B. OR gates
C. NAND and NOR gates
D. AND gates and OR gates

Answer: Option D
Explanation:
55. The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is
HIGH is a(n):
A. OR gate
B. AND gate
C. NOR gate
D. NOT operation
Answer: Option A
Explanation:
56. CMOS IC packages are available in ________.
A. DIP configuration
B. SOIC configuration
C. DIP and SOIC configurations
D. neither DIP nor SOIC configurations

Answer: Option C
Explanation:
57. Which of the following is not a basic Boolean operation?

A. OR
B. NOT
C. AND
D. FOR
Answer: Option D
Explanation:
58. Which of the following gates is described by the expression ?

A. OR
B. AND
C. NOR
D. NAND
Answer: Option D
Explanation:
59. What is the Boolean expression for a four-input OR gate?

A. Y=A+B+C+D
B. Y = A B  C  D
C. Y = A – B – C – D
D. Y = A $ B $ C $ D
Answer: Option A
Explanation:
60. How many truth table entries are necessary for a four-input circuit?
A. 4
B. 8
C. 12
D. 16
Answer: Option D
Explanation:
61. How many entries would a truth table for a four-input NAND gate have?
A. 2
B. 8
C. 16
D. 32
62. The Boolean expression for a 3-input OR gate is ________.

A. X=A+B
B. X = A + B + C
C. X = ABC
D. X = A + BC
Answer: Option B
Explanation:
63. From the truth table for a three-input NOR gate, what is the only condition of inputs A, B,
and C that will make the output X high?
A. A = 1, B = 1, C = 1
B. A = 1, B = 0, C = 0
C. A = 0, B = 0, C = 1
D. A = 0, B = 0, C = 0
Answer: Option D
Explanation:
64. The logic gate that will have a LOW output when any one of its inputs is HIGH is the:
A. NAND gate
B. AND gate
C. NOR gate
D. OR gate
Answer: Option C
Explanation:
65. The output of a NAND gate is LOW if ________.

A. all inputs are LOW
B. all inputs are HIGH
C. any input is LOW
D. any input is HIGH

Answer: Option B
Explanation:
1. Which statement below best describes the function of a decoder?
A. A decoder will convert a decimal number into the proper binary equivalent.
A decoder will convert a binary number into a specific output representing a particular
B.
character or digit.
C. Decoders are used to prevent improper operation of digital systems.
Decoders are special ICs that are used to make it possible for one brand of computer to
D.
talk to another.
Answer: Option B
Explanation:
2. One can safely state that the output lines for a demultiplexer are under the direct control of the:
A. input data select lines.
B. the internal AND gates.

C. the internal OR gate.
D. Input data line.

Answer: Option A
Explanation:
3. Refer to the figure given below. The logic function generator being implemented with the
multiplexer in this circuit produces a constant LOW on the output. The ABC inputs are checked
and appear to be pulsing; also, the 0–7 and EN inputs are checked with the scope and all
appear to be at 0 V. A check with the DMM confirms that power is on. What is the problem, and
what should be done to correct it?
A. The output is shorted to Vcc; replace the IC.
The scope's vertical input is in the AC mode and the common connection for the 0,2,3
B. and 5 inputs is bad. Set the scope's vertical input mode to DC, and repair the bad solder
connection.
C. Power has not been applied to the circuit; apply power.
D. The output is shorted to ground; replace the IC.

Answer: Option B
Explanation:
4. Refer to the keyboard encoder in figure (a). Sometimes when the 5 key is pressed, the system
attached to the keypad does not respond. The 5 input on the 74147 is monitored with a digital
storage scope while repeatedly pressing the 5 key, and the waveform in figure (b) is obtained;
the P above the trace indicates the points at which the technician pressed the key. What is most
likely wrong with the circuit?
The switches on the 5 key are intermittent; the contacts need to be cleaned or the switch
A.
replaced.
B. The pull-up resistor connected to the 5 key is bad and should be replaced.
The common ground connection at the bottom of the 0 key has a bad solder connection;
C.
repair the connection.
D. The 74147 is intermittent, possibly due to high temperature, and should be replaced.
Answer: Option A
Explanation:
5. The BCD/DEC decoder shown in figure (a) is examined with a logic analyzer and the results are
shown in the waveforms in figure (b). What, if anything, is wrong with the circuit?
A. The "2" output is shorted to Vcc.
B. The A1 input is internally open.

C. The A1 input node is internally stuck LOW.
D. Nothing is wrong with the circuit.

Answer: Option C
Explanation:
1. Which statement below best describes a Karnaugh map?
A. It is simply a rearranged truth table.
B. The Karnaugh map eliminates the need for using NAND and NOR gates.
C. Variable complements can be eliminated by using Karnaugh maps.
D. A Karnaugh map can be used to replace Boolean rules.

Answer: Option A
Explanation:
2. Which of the examples below expresses the commutative law of multiplication?

A. A+B=B+A
B. A • B = B + A
C. A • (B • C) = (A • B) • C
D. A • B = B • A
Answer: Option D
Explanation:
3.
The Boolean expression is logically equivalent to what single gate?
A. NAND
B. NOR
C. AND
D. OR
Answer: Option A
Explanation:
4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND
gate is referred to as:
A. a Karnaugh map
B. DeMorgan's second theorem
C. the commutative law of addition
D. the associative law of multiplication

Answer: Option B
Explanation:
5. The systematic reduction of logic circuits is accomplished by:

A. symbolic reduction
B. TTL logic
C. using Boolean algebra
D. using a truth table

Answer: Option C
Explanation:
6. Logically, the output of a NOR gate would have the same Boolean expression as a(n):
A. NAND gate immediately followed by an INVERTER
B. OR gate immediately followed by an INVERTER
C. AND gate immediately followed by an INVERTER
D. NOR gate immediately followed by an INVERTER

Answer: Option B
Explanation:
7. Which of the examples below expresses the distributive law of Boolean algebra?
A. A • (B • C) = (A • B) + C
B. A + (B + C) = (A • B) + (A • C)
C. A • (B + C) = (A • B) + (A • C)
D. (A + B) + C = A + (B + C)
Answer: Option C
Explanation:
8. Which output expression might indicate a product-of-sums circuit construction?
A.
B.
C.
D.
Answer: Option D
Explanation:
9. One of DeMorgan's theorems states that . Simply stated, this means that logically
there is no difference between:
A. a NAND gate and an AND gate with a bubbled output
B. a NOR gate and an AND gate with a bubbled output
C. a NOR gate and a NAND gate with a bubbled output
D. a NAND gate and an OR gate with a bubbled output

Answer: Option B
Explanation:
10. The commutative law of addition and multiplication indicates that:

A. the way we OR or AND two variables is unimportant because the result is the same
B. we can group variables in an AND or in an OR any way we want
an expression can be expanded by multiplying term by term just the same as in ordinary
C.
algebra
the factoring of Boolean expressions requires the multiplication of product terms that
D.
contain like variables
Answer: Option A
Explanation:
Which of the following expressions is in the sum-of-products (SOP) form?
A. Y = (A + B)(C + D)
B. Y = AB(CD)
C.
D.
Answer: Option C
Explanation:

Logic Circuits Indiabix

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LOGIC CIRCUITS INDIABIX

1. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?

2. Which of the figures shown below represents the exclusive-NOR gate?

3. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

8. Convert BCD 0001 0111 to binary.

9. Which of the figures in figure (a to d) is equivalent to figure (e)?

B. Karnaugh mapping and circuit waveform analysis

C. Actual circuit trial and error evaluation and waveform analysis

D. Boolean algebra and actual circuit trial and error evaluation

A. All are HIGH.

B. All are LOW.

C. All but are LOW.

D. All but are HIGH.

B. Corners in the same column

D. A defective output IC chip that has an internal open to Vcc

19. Which gate is best used as a basic comparator?

20. The device shown here is most likely a ________.

C. a set of bit vectors.

22. Which of the following expressions is in the product-of-sums form?

B. The delay times are greatly reduced over other forms.

A. All are HIGH.

C. All but are LOW.

D. All but are HIGH.

D. The gate may be a tristate device.

29. Each "1" entry in a K-map square represents:

C. a LOW output for all possible HIGH input conditions.

30. Looping on a K-map always results in the elimination of:

B. variables that remain unchanged within the loop.

B. Program a chip and test it

D. Perform a vector test

C. The output appears to be LOW, but is being pulsed by the pulser.

D. Nothing appears to be wrong at that point.

33. What is the indication of a short on the input of a load gate?

B. There is a signal loss to all gates on the node.

C. The affected node will be stuck in the LOW state.

34. In HDL, LITERALS is/are:

C. binary coded decimals.

35. Which of the following expressions is in the sum-of-products form?

37. Which of the K-maps given below represents the expression X = AC + BC + B?

38. A decoder can be used as a demultiplexer by ________.

B. tying all data-select lines LOW

C. tying all data-select lines HIGH

40. Which statement below best describes a Karnaugh map?

C. Variable complements can be eliminated by using Karnaugh maps.

D. Karnaugh maps provide a visual approach to simplifying Boolean expressions.

D. None. All outputs are HIGH.

43. Solve the network in the figure given below for X.

B. One 4-input AND gate, one OR gate

C. One 4-input NAND gate, one inverter

D. One 4-input AND gate, one inverter

B. There is a signal loss to all load gates.

D. The affected node will be stuck in the HIGH state.

2. Most demultiplexers facilitate which of the following?

B. single input, multiple outputs

D. odd parity to even parity

3. One application of a digital multiplexer is to facilitate:

C. parallel-to-serial data conversion

D. Parity checking is capable of detecting and correcting errors in transmitted codes.

B. uses one display to present two or more pieces of information