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Module 3 - Organisation of Processor

This document discusses the organization of processors and their internal structure. It covers topics like register organization, the instruction cycle, and instruction pipelining. The key points are: - Processors contain different types of registers like general purpose and special purpose registers that temporarily hold data and instructions. - The instruction cycle involves fetching an instruction from memory, decoding it, and executing it. It is broken down into fetch, indirect, interrupt, and execute subcycles. - The control unit sequences the CPU through a series of micro-operations during each subcycle to properly execute instructions step-by-step. It uses control signals to manage the data paths between hardware units.

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Naveen Suddala
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43 views

Module 3 - Organisation of Processor

This document discusses the organization of processors and their internal structure. It covers topics like register organization, the instruction cycle, and instruction pipelining. The key points are: - Processors contain different types of registers like general purpose and special purpose registers that temporarily hold data and instructions. - The instruction cycle involves fetching an instruction from memory, decoding it, and executing it. It is broken down into fetch, indirect, interrupt, and execute subcycles. - The control unit sequences the CPU through a series of micro-operations during each subcycle to properly execute instructions step-by-step. It uses control signals to manage the data paths between hardware units.

Uploaded by

Naveen Suddala
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Organization and

Architecture

Module 3 - Organization of
Processors
Organization of Processor

• Processor Organization
• Register Organization
• Instruction Cycle
• Instruction Pipelining/ Dealing with Branches
Von Neumann Architecture
CPU Internal Structure
Registers
• It holds data temporarily during the execution
of instruction.
• They are a part of CPU.
• Length of register = No. of bits it can store.

Two types -
• Special Purpose Registers
• General Purpose Registers
List of Special Purpose Registers

• Decoder
• Program Control Register (Program Counter)
• Memory Address Register
• Memory Buffer Register
• Instruction Register
• I/O Register
• Accumulator
List of Special Purpose Registers
De c o d e r
• It interprets the instruction to be executed.
Program Control Register
• It holds the address of next instruction to be
executed. In case of branch instruction, system
passes the address part of branch instruction to PC.
Memory Address Register
• It holds the address of the active memory location.
List of Special Purpose Registers
Memory Buffer Register
• It holds the content of accessed memory
word. It holds the data word when it is transferred
to and from the main memory.
Instruction Register
• It holds the instruction being executed. Instruction
is divided into two parts :
• Operation Part - Given to MAR
• Address part - Given to Decoder
List of Special Purpose Registers
I/O Register
• It is used for communication with the I/O devices.
• An input unit transfers all the contents to this
register & then system picks up the data & vice-
versa.
Accumulator
• It holds the data under execution, intermediate
results & result of operations.
Result Accumulator MBR Main Memory
Example Register Org.
Micro-Operations
• A computer executes a program
• Fetch/execute cycle
• Each cycle has a number of steps
—see pipelining
• Called micro-operations
• Each step does very little
• Atomic operation of CPU
Constituent Elements of
Program Execution
Instruction Cycle

• It is the time in which a single


instruction is fetched from memory,
decoded, and executed

• An Instruction Cycle requires the


following subcycle:
Instruction Cycle
 Fetch
Read next instruction from memory into the
processor
 Indirect Cycle (Decode Cycle)
May require memory access to fetch operands,
therefore more memory accesses.
 Interrupt
Save current instruction and service the interrupt
 Execute
Interpret the opcode and perform the indicated
operation
Instruction Cycle

Fetch

Interrupt Indirect
Indirect

Execute
Instruction Cycle
• Each phase decomposed into sequence of
elementary micro-operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
—One sequence of micro-operations for each opcode
• Need to tie sequences together
• Assume new 2-bit register
—Instruction cycle code (ICC) designates which part of
cycle processor is in
– 00: Fetch
– 01: Indirect
– 10: Execute
– 11: Interrupt
Fetch Sequence
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with data fetch
from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
Fetch Sequence (symbolic)
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• PC <- (PC) +1
• t3: IR <- (MBR)
• (tx = time unit/clock cycle)
or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
• IR <- (MBR)
Rules for Clock Cycle Grouping
• Proper sequence must be followed
—MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
—Must not read & write same register at same time
—MBR <- (memory) & IR <- (MBR) must not be in
same cycle
• Also: PC <- (PC) +1 involves addition
—Use ALU
—May need additional micro-operations
Indirect Cycle
• MAR <- (IRaddress) - address field of IR
• MBR <- (memory)
• IRaddress <- (MBRaddress)

• MBR contains an address


• IR is now in same state as if direct addressing
had been used
• (What does this say about IR size?)
Interrupt Cycle
• t1: MBR <-(PC)
• t2: MAR <- save-address
• PC <- routine-address
• t3: memory <- (MBR)
• This is a minimum
—May be additional micro-ops to get addresses
—N.B. saving context is done by interrupt handler
routine, not micro-ops
Execute Cycle (ADD)
• Different for each instruction

e.g. ADD R1,X - add the contents of location X to


Register 1 , result in R1
• t1: MAR <- (IRaddress)
• t2: MBR <- (memory)
• t3: R1 <- R1 + (MBR)
• Note no overlap of micro-operations
Execute Cycle (BSA)
• BSA X - Branch and save address
—Address of instruction following BSA is saved in X
—Execution continues from X+1
—t1: MAR <- (IRaddress)
— MBR <- (PC)
—t2: PC <- (IRaddress)
— memory <- (MBR)
—t3: PC <- (PC) + 1
Types of Micro-operation
• Transfer data between registers
• Transfer data from register to external
• Transfer data from external to register
• Perform arithmetic or logical ops
Functions of Control Unit
• Sequencing
—Causing the CPU to step through a series of micro-
operations
• Execution
—Causing the performance of each micro-op
• This is done using Control Signals
Data Paths and Control Signals
Data Paths and Control Signals

• Hardware units like ALU's, registers, memory, etc., are


linked together into a data-path.

• The flow of bits around the data-path is controlled by


the "gates" which allow the bits to flow (on) or not
flow (off) through the data-path.

• The binary instructions (1 = on; 0 = off) that control


the flow are called micro-instructions.
Simplified Data Paths
Internal Organization
• Usually a single internal bus
• Gates control movement of data onto and off
the bus
• Control signals control data transfer to and from
external systems bus
• Temporary registers needed for proper
operation of ALU
CPU with
Internal
Bus

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