LIST OF EXPERIMENTS

Cycle 1

1.STUDY OF DIGITAL IC’S AND IC TRAINER KIT

2 REALISATION OF HALF ADDER AND FULL ADDER CIRCUITS
3.STUDY OF FLIP FLOP ICS
4.ASYNCHRONOUS COUNTERS
5.RING COUNTER AND JOHNSON COUNTER
6.TTL CHARACTERISTICS
7.ASTABLE MULTIVIBRATOR USING OP-AMP
8.ENCODER AND DECODER
9.ASTABLE MULTIVIBRATOR USING 555
Cycle 2
1 MONOSTABLE MULTIVIBRATOR
2 SEVEN SEGMENT DISPLAY
3.DIGITAL TO ANALOG CONVERTER
4. ANALOGE TO DIGITAL CONVERTER
5. ARITHMETIC CIRCUITS USING OP AMPS
6. SYNCHRONOUS COUNTERS
7. SHIFT REGISTERS
8. DIFFERENTIATOR AND INTEGRATOR
 STUDY OF DIGITAL IC’S AND IC TRAINER KIT

Aim: To familiarize with logic gate IC packages and to verify the truth tables of the logic
gate. Also to familiarize with the digital IC trainer kit.

Theory :
IC trainer kit: It is an equipment mainly used to test and set up digital circuits while
doing experiments. Integrated circuits can be fitted in sockets or breadboard provided in
it. The associated circuits can be setup on the breadboard. There are building voltage
source and clock signals in it. The frequency of the clock can be selected by turning the
knob in to different positions. In order to feed monopulses manually a debouncer switch
is also provided. Select switches are provided to obtain 0 or 1 state voltages for digital
inputs. Green and red LED’s are provided to represent logic low and high states visually.
Logic Gates
In digital electronics a gate is a logic circuit with one output and one or more inputs
.Logic gates are available as integrated circuits (ICs).

AND gate:
It is a logic gate whose output becomes high when all the inputs are high.7408 is a
digital IC in the TTL family and contains 4 AND gates. AND gate performs logical
multiplication.
OR gate:
It is a logic gate whose output becomes high if any of the inputs are high.7432 is a
quad 2 input OR gate. It performs logical addition.
NOT gate:
It is also called an inverter whose purpose is to change one logic level to opposite
level.IC 7404 is a hex inverter.
NAND gate:
A NOT gate following an AND gate is called a NAND gate .Its output will be low
if all the inputs are in high state.7400 IC is a quad 2 input NAND gate.
NOR gate:
A NOT gate following an OR gate is called a NOR gate. Its output will be in low
state if any of its inputs is in high state.7402 is a quad 2 input NOR gate .
EXCLUSIVE-OR (EX-OR)gate:
Its output will be high if and only if one input is in high state.7486 is a quad
2input EX-OR gate.
 INTRODUCTION TO LOGIC GATES

In digital electronics a gate is a logic circuit with one output and one
or more inputs .Logic gates are available as integrated circuits (ICs).

AND gate:
It is a logic gate whose output becomes high when all the inputs are high.7408 is a
digital IC in the TTL family and contains 4 AND gates. AND gate performs logical
multiplication.
OR gate:
It is a logic gate whose output becomes high if any of the inputs are high.7432 is a
quad 2 input OR gate. It performs logical addition.
NOT gate:
It is also called an inverter whose purpose is to change one logic level to opposite
level.IC 7404 is a hex inverter.
NAND gate:
A NOT gate following an AND gate is called a NAND gate .Its output will be low
if all the inputs are in high state.7400 IC is a quad 2 input NAND gate.
NOR gate:
A NOT gate following an OR gate is called a NOR gate. Its output will be in low
state if any of its inputs is in high state.7402 is a quad 2 input NOR gate .
EXCLUSIVE-OR (EX-OR)gate:
Its output will be high if and only if one input is in high state.7486 is a quad
2input EX-OR gate.

Quad two input AND gate. Quad two input NAND gate.
Quad two input OR gate Quad two input NOR gate

HEX inverter gates Quad two input EXOR gates

 Experiment No: 1

REALISATION OF HALF ADDER AND FULL ADDER CIRCUITS

Aim:
1. To design and setup a Half Adder using (a) EXOR gates and NAND gates (b) NAND
gates only.
2. To design and setup a Full Adder using (a)EXOR gates and NAND gates (b) NAND
gates only

Components and equipments required:

ICs 7400, IC Trainer Kit.
Theory:
Half Adder: A logic circuit used for the addition of two 1-bit signals is known as a half
adder. Its logic diagram and truth table are given in figure. Here A and B are the two
inputs. S is the Sum output and C is the Carry Output.
Full Adder: A Half adder has only two input terminals and there is no provision to add a
carry coming from the lower order bits when binary numbers are added. For this purpose
a third input terminal is added and this circuit is used to add An, Bn and Cn-1 where An and
Bn are the nth order bits of the numbers A and B respectively and Cn-1 is the carry
generated from the addition of the (n-1)th order bits. The block diagram of a Full adder
and its truth table are given in figure.

Procedure:
1. Test all components and IC packages using IC tester.
2. Set up the circuit and feed the input bit combinations.
3. Observe the output corresponding to input combinations and enter it in truth tables.

Result
Half adder and full adder circuits are set up and the truth tables are verified.
Circuit Diagram
Realization of sum and carry using K-Map
IMPLEMENTATION USING LOGIC GATES
 Experiment No: 2
STUDY OF FLIP FLOP ICS

Aim : 1.To test the following flip flops

(a)Clocked SR Flip Flop
(b) JK Flip Flop
(d) D Flip Flop
(e) T Flip Flop

Components and equipments required:

ICs7476, 7473 & IC Trainer Kit
Theory :
The Flip Flop a basic memory element .Since its output will remain in its state
until it is forced to change it by some means. If Flip Flops are also used in addition to the
gates the circuits are known as sequential circuits. A Flip Flop is basically a bistable
multivibrator having 2 stable states. One of the stable states is known as SET or
1,whereas the other stable state is called RESET, CLEAR or 0.Normally there are 2 input
terminals known as data inputs and 2 output terminals Q and Q , the outputs Q and Q are
complementary. In addition to the 2 data input terminals ,the Flip Flop has a clock
terminal .A train of pulses is applied at this terminal .The state of the output at any instant
of time depends upon the past outputs and the data inputs present at that instant of time.
The state can change only when the clock pulse is applied.

Clocked SR Flip Flop: The SET RESET Flip Flop is the basic Flip Flop. The output Q is
1 if S=1 and R=0. If S is removed, the output Q still remains 1. This means it memorizes
the 1.similarly it memorizes the 0. But S=R=1 is forbidden since the output will be
indeterminate.

JK Flip Flop: The indeterminate o/p state of SR Flip Flop when S=R=1 is avoided by
converting it to a JK Flip Flop.

MS JK Flip Flop: The JK Flip Flop has the problem of race around .ie, for some i/psthe
o/p at the end of the clock pulse is uncertain. Racing is the toggling of the o/p more than
once during a positive clock edge. This problem can be eliminated by using MS JK Flip
Flop created by cascading 2 JK Flip Flops. The clock fed to the first stage(MASTER) is
inverted and fed to the second stage(SLAVE).This ensures that the slave follows the
master and eliminates the chance of racing .

D Flip Flop: It has only 1 i/p referred to as the ‘D’ input or DATA i/p. The i/p data is
transferred to the o/p after clock pulse is applied. D Flip Flop can be derived from the JK
Flip Flop by using J i/p as the D i/p and J is inverted and fed to K i/p.

T Flip Flop: T stands for TOGGLE. The o/p toggles when a clock pulse is applied .i.e,
the o/p of the Flip Flop changes state for an input pulse. T Flip Flop can be derived from
JK Flip Flop by shorting J and K i/ps.
Flip Flop ICS

7476 is a dual negative edge triggered MSJK FF with preset and clear facility. It is a 16
pin DIP chip.7473 is a dual negative edge triggered MSJK FF with clear facility in 14 pin
DIP. It does not have preset input.7474 is positive edge triggered dual DFF with 14 pin
DIP.

Procedure
1. Test all components and IC packages using IC tester.
2. Setup the circuit and verify the truth tables. When an initial state is to be assigned, two
separate inputs called preset and clear are used. They are active low inputs.

Result
The various flip flop ICs are studied and the truth tables are verified.
T FLIP FLOP
 Experiment No.3
ASYNCHRONOUS COUNTERS

Aim:
To design and set up the asynchronous counters and see how they function
(a) 4 bit binary up counter (mod16)
(b) 4 bit binary down counter
(c) Decade up counter

Components required:
ICs 7476,7473,7400,7408,7432 ,counter ICs -7493,7490
Theory:
Counters
Digital counters are composed of flip flops, those function is to count any number
of events in the form of electrical pulses. A count-by-N (modulo N or divide-by-
N)counter circuit which is capable of counting up to a specified number N, requires at
least n flip flops, where 2n ≥N. Counting can be UP counting (low valued decimal
number to high valued decimal number)or DOWN counting(high valued decimal number
to low valued decimal number). .

Asynchronous counters:

(a) 4-bit binary up counter: Here all the flip flops are clocked by the Q output of the
preceding flip flop. A ripple counter comprising of N flip flops can be used to count up to
2n pulses. A circuit with 4 flip flops can be used to count up to maximum of 24 =16.ie,
natural binary count from 0-15 and resets to initial condition on 16 th input pulse.

(b) 4 -bit binary down counter: Here all the flip flops are clocked by the output of
the preceding flip flops. The outputs are taken from the Q outputs .Initially all the outputs
are set. At the arrival of the 16th clock pulse all Q outputs become reset and cycle
continues.

(c)Decade up Counter: It is a ripple counter counting from 0000 to 1001.As soon as the
count 1010 takes place, a NAND gate clears the flip flops and the counting restarts from
0.
.
If clock is applied at input A and QA is connected to input b it functions as a mode-16
,four bit binary ripple counter as internally there is one mode-2 and a mode-8 counter that
can be connected in cascade. The outputs are QA,QB,QC, and QD. If clock is applied at
input B. the output will appear at QB,QC and QD and it will behave as a mode- 8
counter, here flip flop QA is not used

IC 7490 is a TTL decade counter having a mode-2 and a mode-5 counter in it. Flip flop
A is the mode-2 counter and flip flops B,C and D form a mode- 5 counter. Decade
counter can be obtained by applying clock at the input A and QA connected to the input
B.

Procedure
.
Asynchronous Counter

1. Test all ICs using digital IC tester

2. Set up the circuit for 4 bit ripple counter .Connect all the PRESET pins to +5V to
disable it
.
3. Clear all the flip flop outputs initially connecting common CLEAR terminal to logic
0.After the usage of CLEAR pins connect them to logic 1 or keep them open. Apply
monopulses. Counter starts counting up.

4. Move clock inputs of every flip flops except FF0 from Q outputs to the Q outputs.
Preset all flip flops by connecting common PRESET terminal to logic 0. Apply
monopulses. Counter will start counting downwards.

Set up the decade counter circuit and repeat steps for counting up.

Result

The 4 bit binary up counter, binary down counter and decade counter are designed and
the truth tables are verified.
4 BIT BINARY UP COUNTER

TRUTH TABLE

4 BIT BINARY DOWN COUNTER

TRUTH TABLE
DECADE COUNTER
DECADE COUNTER USING IC7490

Clk A QA QD QB QC

14 13 12 11 10 9

7490

1 2 3 4 5 6
Clk B NC

Experiment No.4
SHIFT REGISTER COUNTERS

AIM

ICs 7476 and IC trainer kit

Theory
Ring counter and Johnson counter are basically shift registers.
Ring counter
It is connected by JKFFs by connecting Q and Q outputs from one FF to the J and K
inputs of the next FF. To start the counters first FF is set using the Preset facility and the
remaining FFs are reset using reset input.When the clock signal arrives this set condition
continues to shift around the ring.
Johnson counter
The Q and Q outputs of the last FF are connected to the J and K inputs of the first flip
flop respectively. This is a Johnson counter.

Procedure
1. Test all components and IC packages using IC tester.
2. Set up the ring counter and set up any Q output using PRESET and apply monopulses
using debounce switch in the trainer kit to the clock input. 3 .Note down the states of ring
counter outputs on the truth table for successive clocks.
4. Repeat the above steps for Johnson counter

Result

Designed and set up four bit Johnson and Ring counter using JKFF and the truth tables
are verified.
Circuit Diagram
Ring Counter using JK Flip Flop

Johnson Counter using JK flip flop

 Experiment No.5
TTL CHARACTERISTICS

Aim: To plot the transfer characteristics of a TTL NAND gate and to measure the
sourcing and sinking current.

Components and equipments required: IC 7400, ammeters, voltmeters, CRO and

trainer kit.

Theory
Transfer characteristics

For the NAND gate,if any of the input is low,Q2 and Q3 will be turned off and Q4 will
be turned on to give a logical output.Then V0 will have a value Vcc-(VBE+ VD) where
VBE is base emitter potential of transistor and VD is diode voltage drop.Collector
potential of Q2 is Vcc.Current flows through R1 and base emitter of Q1.If input voltage
Vi rises current gets diverted from the emitter of Q1 to its collector causing Q2 to
conduct,which operates then in the linear region .Since Q4 remains on and acts as an
emitter follower, the output decreases.When the input is high enough to turn on
Q3,emitter impedance of q2 falls thereby output falling at a steep slope.

SOURCING CURRENT
When the output of the NAND gate is in logic 1 state, the transistor Q4 acts as a source
because the current flow is out of its emitter into load, which is the sourcing current
with a max. value of 400uA.

SINKING CURRENT
When the output is in logic 0 state, transistor Q3 acts as a current sink because the current
flows from the load through the transistor to the ground which is called the sinking
current of a max. value 16mA.

Procedure

1. Set up the circuit as given in the figure to plot the input and transfer
characteristics.Vary the input voltage from 0-5V and take the voltmeter readings.
2. Draw the characteristics with Vi on the X axis and Vo on the Y axis.
3. Set up circuit to plot the sourcing and sinking characteristics and take readings
from the ammeter.Ensure a gate output logic 1 for sourcing and a logic 0 for a
sinking circuit.

Logic swing VOH –VOL

Transition width VIH- VIL
High level DC noise margin VOH- VIH
Low level DC noise margin VIL- VOL
RESULT:
Plotted the input,sourcing,sinking and transfer characteristics of TTL gates
TTL INPUT CHARACTERISTICS

+5V
-1
0 mA 1
A 3
10KΩ 2

V 0-5 V

V(v) I(m A) I

SINKING CHARACTERISTICS

1 0 -1 m A 220Ω
3 A 10KΩ
2

V 0 -5 V

V(v) I (m A) I
 V

SOURCING CHARACTERISTICS

1 220Ω
3 A 0-1 m A
2 10KΩ

V -5
0 V

I
V(v) I(m A)

TRANSFER CHARACTERISTICS

+5V
1
10KΩ 3
2

V 0-5 V 0-5V V
 Experiment No.6
ASTABLE MULTIVIBRATOR USING OP-AMP

AIM
To design and set up an astable multivibrator using op amo for a frequency of oscillations
of 1kHz
COMPONENTS REQUIRED

Power supplies,op amp,resistors and capacitors.

THEORY
The output of the op-amp is forced to swing between + Vsat and –Vsat resulting in a square
wave output.Condider the instant at which VO is at + Vsat .Now the capacitor charges
exponentially towards + Vsat through R.Automatically Vd increases and crosses zero.This
occurs when Vc =β Vsat .The moment Vd becomes positive due to further charging of
capacitor,output changes to –Vsat .Now capacitor starts to discharge to zero and recharges
to–Vsat . Now Vd decreases and ceosses zero.This occurs when Vc = -β Vsat .The moment
Vd become negative,output changes to + Vsat.This completes the cycle.

PROCEDURE
Set up the circuit of astable multivibrator using op-amp and plot the waveforms.

RESULT

Designed and set up the astable multivibrator using op amp and plotted waveform
 4.7K Ω V

8
3 V+
+
1
741COUT 10kΩ
2 V-
-

4
NC Vcc O/P
0.1μf
Offset null
10KΩ

8 7 6 5
741C

1 2 3 4

+Vin +Vin VEE

Offset null
-

DESIGN

T=2RC ln(1+β)/(1-β)
β= feedback factor=R2 /(R1 + R2 )
Let β=0.5, R2 =10KΩ,R1 =10KΩ
When C=0.1μ F,T=2.2RC
Required T=1 ms =10-3 =2 RX10-6 ln (1+0.5)/(1-0.5). R=4.7KΩ
 Experiment No.7

ENCODER AND DECODER

AIM
To design and set up decoder and encoder circuits using gates and Ics.
COMPONENTS USED
IC 74154,7411,7432,7404
THEORY

74154 is a 4 to 16 decoder. The data sheet inputs A,B,C,D decodes the input pin at which
the data should be available .Decoder converts the codes to signals. ie,it is a circuit which
is designed to detect the presence of a specified combination of bits on its inputs and to
indicate the presence by a specified input level.
Encoder converts signals on the segments to a code format.There are 2n input lines and n
output lines.An encoder accepts active level on one of its inputs representinga digit such
as octal,decimal ,etc and converts it to coded format such as BCD.
PROCEDURE

Set up the circuits for decoder and encoder.

Verify the working using truth tables
RESULT

Designed and set up decoder and encoder circuits using gates and ICs.
DECIMAL TO BINARY ENCODER

D0
D1

D2

D3
D4

D5

D6

D7

D8

D9 2 1 2 1
2 1 2 1

3 3
3 3

A0 A1 A2 A3

INPUT OUTPUT
A3 A2 A1 A0
D0 0 0 0 0
D1 0 0 0 1
D2 0 0 1 0
D3 0 0 1 1
 D4 0 1 0 0
D5 0 1 0 1
D6 0 1 1 0
D7 0 1 1 1
D8 1 0 0 0
D9 1 0 0 1
DECIMAL TO BINARY DECODER
X Y Z 1 2
1 2 1 2

1
2 D0
13

1
2 D1
13

1
2 D2
13

1
2 D3
13

1
2 D4
13

1
2 D5
13

1
2 D6
13

1
2 D7
13

INPUT OUTPUT
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
20 21 22 23

D 0.

18 Data
19 Strobe

7 4154

24 Vcc

GND D 15
17
 Experiment No.8
ASTABLE MULTIVIBRATOR

AIM

To design and set up astable multivibrator using 555 IC and plot the output waveform.

COMPONENTS USED

SI NO COMPONENTS SPECIFICATION QUANTITY

1 Timer 555 1
2 Resistor 7.2kΩ 2
3 Capacitor 0.1μf,0.01 μf 1 each

THEORY
It is a circuit which switches continuously between ON state and OFF state.In ON
state,VO is high and in other low.Consider the case when VO is high.Then C starts
charging through R.1 C1 acts like a differentiator..When voltage is at Vi which becomes
lower than threshold voltage of the gate,VO is high at the same moment.C2 charges R2 and
V12 becomes high and cycle repeats.

Procedure
Test the components and IC packages. Set up the circuit and observe the output on CRO.

RESULT
Designed and set up astable multivibrator and plotted the output waveforms.
 +5V
7.2K Ω
8 4
7 3

555
7.2K Ω

2 5
6 1

0.1μf
0.01μf

DESIGN

TON =0.693(RA+RB)C and TOFF =0.693 RB C

TON =1msec and TOFF =0.5msec &C=0.1Μf
1x10-3 =0.693(RA+RB)0.1X10-6 & 0.5X10-3 =0693RB X 0.1X10-6
Solving these equations, RB =7.2KΩ and RA =7.2KΩ
f= 1.44/{( RA+2RB)C} =0.66 kHz.
Duty cycle= 0.66
=RA+RB/(RA+2RB )
 Experiment No.9
MONOSTABLE MULTIVIBRATOR

AIM

To design and set up monostable multivibrator using 555 IC and plot the output
waveform.
COMPONENTS USED

SI NO COMPONENTS SPECIFICATION QUANTITY

1 Timer 555 1
2 Resistor 10kΩ,4.7kΩ 2
3 Capacitor 0.1μf 1
0.01 μf 2
4 Diode IN4001 1

THEORY

It has only one stable state.When a trigger is applied,it goes to quasi stable stateand come
back and set in stable state.Now the output is in logic zero and the capacitor is
discharged.
DESIGN
T=1.1RC=1msec
C=0.1μ f
R=10-3 /(1.1X10-6 X0.1) =10KΩ
Triggering Circuit
T=3msec
RC=0.0016T
Put C=0.01μ F
Then R=4.8KΩ
Procedure
Test the components and IC packages. Set up the circuit and observe the output on CRO.

RESULT
Designed and set up monostable multivibrator and plotted the output waveforms.
 7.2KΩ
8 4

6 3 DESIGN
T=1.1RC=1msec
7 555
VIN
0.01μf IiN4001 5 C=0.1μ f
2 1 R=10-3 /(1.1X10-6
X0.1) =10KΩ
4.7KΩ Triggering Circuit
0.1μf T=3msec
0.01μf RC=0.0016T
Put C=0.01μ F
t
Then R=4.8KΩ
 Experiment No.10
SEVEN SEGMENT DISPLAY

Aim:To design and set up BCD to 7 segment decoder

Components and equipments required:ICs 7446,7490,FND507
Theory
7 Segment indicator
It consists of 7 leds labeled a through g.By forward biasing,different leds we can
display the digits 0 through 9.The 7 segment led display is the most popular device used
in digital system. To use this display device, the data which is in the BCD format has to
be changed suitably. For this purpose a BCD to 7 segment decoder is used.7 segment
indicators are of two types.common anode type and common cathode type.In common
anode type anodes of all 7 leds are tied together.While in common cathode all cathodes
are tied together.When common anode is used current limiting resistors must be
connected between every led segments and ground.When a common cathode type is used
a resistor must be connected between every led segments and Vcc
7446 decoder
It has 4 input lines for receiving the BCD data and 7 output lines to drive a 7
segment display.The functions of LT,RBI,RBO and BIS is given below.
LT-This is called lamp test terminal and is used for segment testing.If it is connected to
logic 0 level all the segments of the display connected to the decoder will be on.For
nrmal decoding operation,this terminal is connected to logic 1.
RBI-For normal decoding operation,this is connected to logic 1.If it is connected to logic
0,the segment outputs will generate data for normal 7 segment decoding,for all bcd inputs
except 0.Whenever the bcd inputs correspond to 0,the 7 segment display switches
off.This is used for zero blanking in multi digit display.
RBO-This is used for cascading purposes and is connected to RBI terminal of succeeding
stage.
BI-This is blanking input.If it is connected to logic 0 level,the display will be switched
off irrespective of BCD inputs
Procedure
1.Test all the components and IC packages
2.Set up the circuit and feed the clock to the 7490 clock input and observe the decimal
display.
RESULT

Designed and tested a seven segment display system to display numbers from 0 to 9.
 V CC

8 3
10
7

180Ω
6 9

180Ω

4 2 1
180Ω
180Ω 180Ω
180Ω 180Ω
a b c d e f g

1 6 13 12 11 10 9 15 14

+5V
16
3 8
7447
4
5
6 2 1 7

D C B A

11 8 9 12
CLK 14
1
7490

5 2 3 6 7 10

V CC

C/K Output of 7490 Output of decoder Display

A B C D a b c d e f g
 10 9 8 7 6
a
f g b

e c
FND 507
1.segment e d
2. segment d 1 2 3 4 5
3. common
4. segment e

5.decimal point
6.segment b
7.segment a
8. common anode
9. segment f
10.segmentg

B Vcc

C R
LT ggg g
B1/RBO e
7447/7446
RBI d
c
D
b
A
a
 Experiment No.11
DIGITAL TO ANALOG CONVERTER

AIM
To design and set up a binary weighted code resistor DAC and R -2R ladder type DAC.

COMPONENTS USED

SI NO. COMPONENTS QUANTITY

1 IC 741C 1
2 Resistors 1 each
1 kΩ 10kΩ 4Ω.4kΩ,
2Ω.2kΩ,20kΩ
3. Pot 10kΩ,5kΩ 1 each

THEORY

In weighted resistor type DAC, op-amp is used to produce a weighted sum of digital
inputs where weights are produced to weights of bit positions of inputs. Each input is
amplified by a factor equal to ratio of feed back resistance to input resistance to which it
is connected.
VOUT = -RF/ /R (D3 +1/2 D2+ ¼ D1+1/8D0)
The R-2R ladder type DAC uses resistor of only two values R and2R.The inputs to
resistor network may be applied through digitally connected switches or from output pins
of a counter.The analoge output will be maximum ,when all inputs are of logic high.

V=-Rf/R (1/2 B3+1/4B2+1/8B1+1/16B0)

Procedure
Test 741 C IC using digital IC tester .Switch on the supply. Apply the binary inputs 0000
through 1111 and observe the analog the output using CRO.

RESULT

Designed and set up binary weighted DAC and R and 2R ladder type DAC
 R7

R f= 5kΩ po t

10k 8
ΩΩ 3 V+
B0 Ω +
1
4.7k OUT
ΩΩ 2
B1 - V-
2.2k
4
B2
1k

B3

22K

10K 10K 10K 8

3 V+
+
1
22K 22K 22K 22K 22K OUT
2 V-
-

B3 B2 B1 B0 Output

B3 B2 B1 B0 Output
 Experiment No.12
ANALOGE TO DIGITAL CONVERTER

AIM
To design and set up a 3 bit ADC.

COMPONENTS USE

SI NO. COMPONENTS QUANTITY

1 IC LM 324 1
2 IC 7408 1
3 IC 7432 1
4 IC 7404 1
5 Resistor 1kΩ 5
6 Pot 5kΩ 1

THEORY

A 3 input ADC is shown in fig:

If the analog signal exceeds the reference signal, comparator turns on.
If all comparators are off, analog input will be between 0 and V/4.If C1 is high and C2 is
low input will be between V/4 andV/2.If C1 andC2 are high and C3 is low input will be
between 3V/4 and V.

PROCEDURE

Set up the circuit and vary the input from 0 to 5V .Observe the output bits.

RESULT
Designed and observed the output of ADC
 8
3 U 5A
+

V+
1
OUT
2
- O P A 1 0 1 3 /B B

V-

1
74A C 04

4
R2

2
10K

8
3 U 9A 1
+ 3
V+

1 2
OUT
2 74A C 08
- O P A 1 0 1 3 /B B
V-

R3
4

10K
8

3 U 10A 1
+ 3
V+

1 2
OUT
2 74A C 08
- O P A 1 0 1 3 /B B
V-
4

R4
R E S IS T O R
1

74A C 04
1
3
8

3 1 2
+ 3
V+

1 2 74A C 32
OUT
2 74A C 08
R5 -
V-

10K
4

input Comparator output Binary output

voltage Q4 Q3 Q2 Q1 A B C

0-1 0 0 0 0 0 0 0
1-2 0 0 0 0 0 0 1
2-3 0 0 1 1 0 1 0
3-4 0 1 1 1 0 1 1
4-5 1 1 1 1 1 0 0
 00 01 11 10
00 01 11 10
00 0 1 0 x
01 X X 1 X 00 0 0 1 x
2222222 x x 1 x
X X 0 X 01 x x 1 x
11
10 X X X X 11 x x x x
10

—
C= Q4 Q2+Q2Q1 B=Q4 Q2

00 01 11 10
0 0 0 X
00
X X 0 X
01 A=Q4
X x 1 x
11
X x x x
10

Analog Digital o/p

Input voltage A B C

Experiment No.13
ARITHMETIC CIRCUITS USING OP AMPS
AIM
To design and set up the following operational circuits
(a) Zero crossing detector (b)Adder (c)Subtractor
(b)
COMPONENTS
IC 741 C,Capacitors, resistors and power supply

THEORY
The basic comparator can be used as a zero crossing detector by setting Vref to
zero.When it is used as inverting comparator the input voltage Vin passes through 0
in negative direction when output switches and saturates positively.
Subtractor
Vo = -R/R (Va –Vb) =(Vb –Va )
Adder
Vo is the sum of the input voltage applied to non inverting terminal and negative
sum of voltage at the inverting terminal.

PROCEDURE
Test all the components and IC packages. Set up the circuit and observe the wave
forms

RESULT
Designed and set up the circuits and plotted the waveforms
 10k

8
3

8
+ 3

V+
1 +

V+
OU T 1
2 OU T
- 2

V-
10k -

V-
1

4
V in 1 0 m V p p 1 0k 10k

1
2

V in 2 V p p
V re f

2
1 0k
8

3
+
V+

1
10 k 1 0k OU T
2
-
V-
1

V re f
4
1

V in 2 V p p
2
2

Vi

t t

Vo

t
 Experiment No: 15
SYNCHRONOUS COUNTERS
Aim:
To design and set up 3 bit up/down synchronous counter and see how they function

Components and equipments required:

ICs 7476, 7400,7410
Theory
Synchronous counters:

Synchronous and asynchronous counters provide the same outputs. The difference
is that in the synchronous counters all flip flops work in synchronism with the input clock
pulse. Therefore the propagation delay occurring in the asynchronous counter is
eliminated in the synchronous counters. Synchronous counters for any given sequence
can be designed and set up by the following procedure.
1. Find the number of flip flops using the relation M=2N where M is the modulus of
the counter and N is minimum number of flip flops required. N = log2 M.
2. Write down the count sequence (flip flop outputs) in a tabular form.
3. Determine the flip flop inputs which must be present for the desired next state
using excitation table of the flip flops.
4. Prepare K-maps for each flip flop input in terms of flip flop outputs as the input
variables. Obtain the minimized expressions from the K-maps.
5. Set up the circuit using FFs and other gates.

UP/DOWN counters: They are capable of progressing the counting in either direction .A
mode control pin is used to decide whether the counter should go up or down.

Self Starting Counters: While the counting progresses there is a chance of the counter
falling to an unused or undesired state. If this happens, the next state will be unknown to
the counter and it will not progress as desired. To avoid this lock out, a logic circuit is
designed to make the counter start from the initial state if the counter falls into undesired
state.
Design
Excitation table of JKFF

Qn Q(n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Procedure
Synchronous counters
1. Test all ICs using digital IC tester
2. Set up the circuit for and verify the counter states.

5V

S S S
J Q J Q J Q
CP _ CP _ CP _
K Q K Q K Q
R R R

COUNTER STATES
Present state next state JK FF Inputs
M Q2 Q1 Q0 Q2 Q1 Q0 J0 KO J1 K1 J2 K2
0 0 0 0 0 0 1 1 X 0 X 0 X
0 0 0 1 0 1 0 X 1 1 X 0 X
0 0 1 0 0 1 1 1 X X 0 0 X
0 0 1 1 1 0 0 X 1 X 1 1 X
0 1 0 0 1 0 1 1 X 0 X X 0
0 1 0 1 1 1 0 X 1 1 X X 0
0 1 1 0 1 1 1 1 X X 0 X 0
0 1 1 1 0 0 0 X 1 X 1 X 1
1 1 1 1 1 1 0 X 1 X 0 X 0
1 1 1 0 1 0 1 1 X X 1 X 0
1 1 0 1 1 0 0 X 1 0 X X 0
1 1 0 0 0 1 1 1 X 1 X X 1
1 0 1 1 0 1 0 X 1 X 0 0 X
1 0 1 0 0 0 1 1 X X 1 0 X
1 0 0 1 0 0 0 X 1 0 X 0 X
1 0 0 0 1 1 1 1 X 1 X 1 X
Realization using Karnaugh map.

0 0 1 1 X X X X
1 1 0 0 X X X X
X X X X 1 1 0 0
X X X X 0 0 1 1
J1 = MQ0+MQ0 K=MQ0+MQ0

0 X X 1 X 0 1 X
0 X X 0 X 0 0 X
1 X X 0 X 1 0 X
0 X X 0 X 0 0 X
J=MQ1Q0+MQ1Q0
K=MQ1Q0+MQ1Q0

Result The circuit is set up and the counter states are verified.
 QA QB QC QD
+5V PRE

1 1
3 3
2 2

JA JB JC JD

KA KB KC KD

CLK

CLR

Experiment No.15
 SHIFT REGISTERS
Aim:
To design and setup a serial in parallel out shift register using D FF

Components required:

ICs 7476,7474,7408,7432 and IC Trainer kit.

Theory

(1)Shift registers
A register is to store digital data. A shift register is a memory in which
information is shifted one position at a time when one clock pulse is applied. The data
can be shifted in either direction ie, right or left .A shift register can be used in for
configurations according to the way in which data is fed or taken out. They are

1) Serial Input Serial Output (SISO)

2) Parallel Input Serial Output (PISO)
3) Serial Input Parallel Output (SIPO)
4) Parallel Input Parallel Output (PIPO)

Serial input shift register: A serial input shift register allows the data to enter serially.
The output data can be available in parallel or serial. Serial input right shift register is
shown in the figure.
Serial input right shift (SIRS) register: As the name suggests SIRS register allows the
data to enter from left. The output data can be available in parallel or serial.
Procedure:

1. Test all the components and IC packages using digital IC tester.

2. Setup the serial input shift register using D flip flop . Clear all the flip flops using
CLEAR pins. Feed 1011 to the serial input starting from LSB using PRESET and
CLEAR pins. A low input to CLEAR and PRESET will make Q output 0 and 1
respectively
3. Apply 1 Hz clock and observe the bits are shifting right.

Circuit Diagram
Serial in serial out shift register
 SISO

SOPO

Q0 Q1 Q2 Q3

SIPO

Parallel in Parallel Out (PIPO)

 S S S S
D Q D Q D Q D Q
_ _ _ _
CP Q CP Q CP Q CP Q
R R R R

Parallel In Serial Out(PISO)

S S S
S D Q D Q D Q
D Q _ _ _
_ CP Q CP Q CP Q
CP Q R R R
R
 Experiment No.16
DIFFERENTIATOR AND INTEGRATOR

AIM

To design and set up an integrator and differentiator and to plot the frequency resoponse.

COMPONENTS USED

SI NO COMPONENTS QUANTITY

1 Resistor 1.6k 1
2 Resistor 82 1
3 Resistor941 1
4 Resistor 78 1
5 Resistor 1k 1
6 capacitor 0.1μF,0.01μF 1 each
7. op amp 741C

THEORY
In a differentiator,the output waveform is the derivative of input waveform.
VO =-Rf C1 d Vin/dt.

PROCEDURE
Connections are made as per the diagram.Apply the input square waveform. Observe the
ouput waveform on the CRO. Vary the frequency from 50Hz to 50KHz. And note the
output voltage.Calculate gain using 20 log (VO /VIN ).Plot the frequency response with
gain ony axis and log f on x axis.

RESULT
Designed and set up an integrator and differentiator and plotted the frequency response.
 0.01μ

1.6k
Ω
8
0.1μ 82 3 V+
μ Ω +
1
OUT
2 V-
-
1
4
1Vpp 50Hz-50kHz
78
Ω

DESIGN
Integrator:
Rf/R1 =gain=10. So Rf=10KΩ R1=1k Ωand fa=1kHz
Ra =1/2πRf Cf
103 = 1/2πx10x103Cf
Cf =0.015x10-6 F Select 0.01Μf
ROM =R1 Rf /( R1 + Rf ) =103 x10x103 / (103 +1) =909Ω =1kΩ
Differentiator:
0 .0 1
μμ

1 .6 k

8
1k 3 V+
+
1
OUT
2 V-
-
1
4
1 V p p 50 H-50
z kH z
9 41

In integrator circuit VO=--1/R1 CF ƒ Vin dt+C

fa= 1/2πRf C1 C1 =0.1Μf,fa =1kHz
103 =1/(2πRf x0.1x10-6) Rf =1.6kΩ
fb =20fa.
20/(2xπRf C1 ) =1/( 2xπRf Cf)
Cf =0.1Μf.
Rf Cf =R1C1
R1 =82 Ω
ROM =R1 RF/(R1+RF) =82X1.6X103 /(82+1.6X103 ) = 78Ω.
Select 82Ω

VOLTAGE REGULATOR USING 723 IC

AIM
To design and set up a low voltage regulator for an output voltage of 6V.
Components used
IC 723,Resistors,Capacitors
Theory
In order to understand the working, consider the functional block diagram of a low
voltage regulator.Vref is connected through a resistor to non-inverting terminal and
output is fed back to inverting terminal of the error amplifier.This makes output of error
amplifier more positive,there by driving transistor Q 1 more into conduction. This
reduces the voltage across Q 1 and draws more current into load causing the voltage
across the load to increase.Thus initial decrease in load voltage os compensated.
The voltage at non inverting terminal is 7.15 R2/(R +R2).

Procedure
Set up the circuit and give the power supply and input voltage source.
Vary the input voltage from 6V to 15V and observe the output voltage. Note down the
readings.
Vary the rheostat and note change in output current
Draw the regulation characteristics with input along x axis and output along y axis.

Design
Vo=R1. /(R1+R2)=6V
Let the devider current through ID through resistor deviders is 1 A. Since error amplifier
draws very little current, we can neglect its input bias current.
Hence,R1=(Vref – Vo)/ I D =7.15-6/1mA. =1.1k use 1K Std.
R=Vo/Io=6/1mA =6kΏ Use 5.6KΏ