Assignment 1

EEE 4307
Course Teacher: Dr. Rakibul Hasan Sagor, Assistant Professor, EEE, IUT

Due: After the mid-sem exam (12 March 2018)

Problem (1-7): Digital Fundamentals, Floyd- Ninth Edition.

Problems:

1. Section 2-2: 8, 9 (Page 104)

2. Section 2-3: 13(d), (e),(g), (h), 14 (b), (c) (Page 105)
3. Section 2-5: 19 (e),(f) 20 (f), (g), (h) (Page 105)
4. Section 2-7: 32. (Page 106)
5. Section 2-8: 37 (d), (e), (f). 38 (d), (e), (f) (Page 106)
6. Section 2-9: 41 (f), (g), (h). 42 (f), (g), (h) (Page 106)
7. Section 2-10: 45(j),(k),48(e),(h),(i),52(f),(h) (Page 106)
8. Convert the following hexadecimal to binary:
(a) 7516 (b) B80F16
9. Convert binary 110101 to gray code.
10. Convert the following binary number to octal:
(a) 10111110 (b) 100010101 (c) 10111111001

11. (a) Find the 10’s complement of the following 6-digit decimal numbers: 123900;
090657; 100000; and 000000.

(b) Find the 1’s and 2’s complements of the following 8-digit binary numbers: 10101110;
10000001; 10000000; 00000001; and 00000000.

12. Convert the following decimal numbers to the indicated bases:

(a) 4575.62 to octal.

(b) 2857.238 to hexadecimal.

(c) 751.751 to binary.

13. Determine the value of base x if (211)x = (152)8

14. Find r’s complement of the following numbers

(a) (4953)10 (b) (1011)2 (c) (6734)8 (d) (14FD6)16

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15. Perform subtraction with the following unsigned decimal numbers by taking the 10’s
complement of the subtrahend.

(a) 9842 – 1883

(b) 2783 – 9450

16. The (r-1)’s complement of base-7 numbers is called the 6’s complement.

(a) Determine a procedure for obtaining 6’s complement of base-7 numbers.

(b) Obtain 6’s complement of (6543210)6

17. Add the following BCD numbers:

(a) 1000 + 0110

(b) 1001 + 1000

(c) 00100101 + 00100111

(d) 01010001 + 01011000

(e) 10011000 + 10010111

(f) 010101100001 + 011100001000

18. Express the switching circuit shown in the figure in binary logic notation. (L is the
output)

B
A L

C
Voltage Source

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19. Draw the timing diagram of f and g for the following circuits

20. Demonstrate by means of truth tables the validity of the following identities:

(a) DeMorgan’s theorem for three variables: (xyz)’ = x’ + y’ + z’.

(b) The second distributive law: x + yz = (x + y)(x + z).

21. Simplify the following Boolean expressions to a minimum number of literals:

(a) x’y’ + xy + x’y

(b) (x+y)(x+y’)

(c) x’y + xy’ + xy + x’y’

22. Reduce the following Boolean expressions to the indicated number of literals:

(a) A’C’ + ABC + AC’ to three literals

(b) (A’C’ + B)’ +B + AC + DB to three literals

(c) A’B(D’ + C’D) + B(A + A’CD) to one literal

(d) (A’+ C)( A’+ C’)(A+B+C’D) to four literals

23. Simplify the following Boolean expressions to a minimum number of literals:

(a) ABC + A’B + ABC’

(b) x’yz + xz

(c) (x + y)’(x’ + y’)

(d) xy +x(wz + wz’)

(e) xy + x(wz + wz’)

24. Find the complement of F= x + yz; then show that F.F’=0 and F + F’=1

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25. Given the following Boolean function:

F = xy’z + x’y’z + w’xy + wx’y + wxy

(a) Obtain the truth table of the function.

(b) Draw the logic diagram using the original Boolean expression.
(c) Simplify the function to a minimum number of literals using Boolean algebra.
(d) Obtain the truth table of the function from the simplified expression and show that it
is the same as the one in part (a).
(e) Draw the logic diagram from the simplified expression and compare the total number
of gates with the diagram of part (b).

26. Obtain the truth table of the following functions and express each function in sum of
minterms and product of maxterms:

(a) (xy + z)(y + xz)

(b) (A’ + B)(B’ + C)

(c) y’z + wxy’ + wxz’ + w’x’z

27. Convert the following expressions into sum of products and product of sums:

(a) (AB + C)(B + C’D)

(b) x’ + x(x + y’)(y + z’)

28. Show that the dual of the exclusive-OR is equal to its complement.
29. Simplify the following expressions and implement them with two-level NAND gate
circuits:

(a) AB’ + ABD + ABD’ + A’C’D’ + A’BC’

(b) BD + BCD’ + AB’C’D’

30. Simplify the following functions and implement them with two-level NOR gate circuits:

(a) F = wx’ + y’z’ + w’yz’

(b) F(w,x,y,z) = ∑(5, 6, 9, 10)

31. Simplify the following Boolean functions / expressions using Karnaugh Maps:
(a) F(x, y, z) = ∑(0, 2, 3, 4, 5)
(b) F(x, y, z) = ∑(3, 5, 6, 7)
(c) AB + A’B’C’ + A’BC’

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 (d) F(w, x, y, z) = ∑(0,1, 2, 4, 5, 7, 11, 15)

32. Simplify the following Boolean functions in (i) POS (ii) SOP form
(a) F(w, x, y, z) = ∑(0,2, 5,6, 7, 8, 10)
(b) F(w, x, y, z) = П(0,1, 2, 4, 5, 7, 11, 15)
(c) AC’ + B’D + A’CD + ABCD
(d) (A’ + B’ + D’)(A + B’ + C’)(A’ + B + D’)(B + C’ + D’)

33. Simplify the following expressions / functions and implement them with two-level (i)
NAND gate circuits (ii) NOR gate circuits:
(a) AB’ + ABD + ABD’ + A’C’D’ + A’BC’
(e) F(w, x, y, z) = ∑(5,6, 9, 10)

34. Simplify the Boolean function F together with the don’t care conditions d in (i) SOP and
(ii) POS form.
F(w, x, y, z) = ∑(3,4, 13, 15)
d(w, x, y, z) = ∑(5, 6, 11, 15)

35. A logic circuit implements the following Boolean expression:

F = A’C + AC’B’
It is found that the circuit input combination A = C = 1 can never occur. Find a simpler
expression for F using the proper don’t care conditions.

36. Simplify the following Boolean function by means of Tabulation method:

F(w, x, y, z) = ∑(0,1, 2, 4, 5, 7, 11, 15)

37. Design a full-adder. Show the truth table and construct Boolean expression for all
possible inputs. Draw the logic diagram.

38. Implement the full adder mentioned in question 7

(i) In sum of product form
(ii) Using two half adders and an OR gate
(iii) Using 3×8 decoder.

39. Construct an eight-bit parallel adder using eight “full-adder” circuits. What is the draw-
back of using this parallel adder? Design the 8-bit parallel adder using look-ahead carry
generator. Show all the necessary Boolean expressions and logic diagrams.

40. NAND and NOR gates can be defined as Universal gate. How?

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41. Design a combinational circuit with three inputs and one output. The output is equal to
logic-1 when the binary value of the input is less than 3. The output is logic-0 otherwise.

42. Design a combinational circuit with four inputs and four outputs. The output generates
the 2’s complement of the input binary number.

43. A majority function is generated in a combinational circuit when the output is equal to 1
the input variables have more 1’s than 0’s. The output is 0 otherwise. Design a 3-input
majority function.

44. Design a combinational circuit with three inputs, x, y and z, and three outputs, A, B, and
C. When the binary value of the input is 0, 1, 2, or 3, the binary output is one greater than
the input. When the binary value of the input is 4, 5, 6 or 7, the binary output is one less
than the input.

45. Design a combinational circuit with three inputs and six outputs. The output binary
number should be the square of the input binary number.

46. Design a combinational circuit with four inputs that represent a decimal digit in BCD and
four outputs that produce the 9’s complement of the input digit. The six unused
combinations can be treated as ‘don’t care’ conditions.

47. Prove that x’  y = x  y’ = (x  y)’ = xy + x’y’.

48. Design a combinational circuit that compares two 3-bit numbers A and B. The circuit has
three outputs x1, x2 and x3 so that

x1 = 1, x2 = 0 and x3 = 0 if A = B,

x1 = 0, x2 = 1 and x3 = 0 if A > B,

x1 = 0, x2 = 0 and x3 = 1 if A < B .

49. Design a BCD adder using two 4-bit binary adder.

50. A combinational circuit is defined by the following three Boolean functions. Design the
circuit with a decoder and external gates.
F1 = x’y’z’ + xz
F2 = xy’z’ + x’y
F3 = x’y’z + xy

51. Construct a 5 × 32 decoder with four 3 × 8 decoders with enable and one 2 × 4 decoder.

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52. Draw the logic diagram of a 2-to-4-line decoder with only NOR gates. Include an enable
input.

53. Design a 4-input priority encoder with inputs D0, D1, D2 and D3 where D0 having the
highest priority and input D3 the lowest priority.

54. An 8 × 1 multiplexer has inputs A, B and C connected to the selection inputs S2, S1 and S0
respectively. The data inputs, I0 through I7 are as follows:
I1 = I2 = I7 = 0;
I3 = I5 = 1,
I0 = I4 = D; and I6 = D’.
Determine the Boolean function that the multiplexer implements.

55. Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers. Use block
diagrams for the three multiplexers.

56. Implement the following Boolean function with an 8 × 1 multiplexer.

F(w, x, y, z) = ∑(0, 3, 5, 6, 8, 9, 14, 15)

57. Implement a full adder with two 4 × 1 multiplexers.

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