THD Analysis of Cascaded Multi Level Inverters Using Different PWM Techniques

International Journal of Trend in Scientific Research and Development (IJTSRD)
Volume: 3 | Issue: 4 | May-Jun 2019 Available Online: www.ijtsrd.com e-ISSN: 2456 - 6470
THD Analysis of Cascaded Multi-level

Inverters using different PWM Techniques
Shilpa Sambhi, Ankit Mittal, Aviral Srivastava, Ayan Mondal, Nitin Varshney
Electrical & Electronics Engineering Department, ABES Engineering College, Ghaziabad, Uttar Pradesh, India
How to cite this paper: Shilpa Sambhi | ABSTRACT

Ankit Mittal | Aviral Srivastava | Ayan Multi-level inverters (MLI) are used in places or industries that require very high
Mondal | Nitin Varshney "THD Analysis voltage and huge current. Multi-level inverter topologies have various
of Cascaded Multi-level Inverters using advantages over single level converters. These advantages are like: rise in output
different PWM Techniques" Published voltage, reduction in the total harmonic distortion (THD), reduction in electro-
in International Journal of Trend in magnetic interference (EMI) generation etc. Key attribute of a multi-level
Scientific Research and Development inverter is the reduction in the voltage stress on each power device. This
(ijtsrd), ISSN: 2456- reduction is due to the use of several levels available on the DC bus. The dawn of
6470, Volume-3 | multi-level inverter topologies have created requirement of various pulse width
Issue-4, June 2019, modulation techniques. In this paper authors have used PWM technique, by
pp.1082-1085, URL: which the total harmonic distortion of the multi-level inverter is decreased. In
https://www.ijtsrd. this we have also controlled the speed of the induction motor by supplying the
com/papers/ijtsrd2 power through a multi-level inverter.
3984.pdf IJTSRD23984
Copyright © 2019 by author(s) and I. INTRODUCTION

International Journal of Trend in Normally, the inverter is used to convert the dc supply into ac supply but during
Scientific Research and Development the conversion of this supply there are too many losses present in the converted
Journal. This is an Open Access article output and the waveform of the generated ac supply is not purely sinusoidal in its
distributed under entire time period. It is quite well known that, the distorted voltages and currents
the terms of the waveforms in the ac supply, produce harmonic distortions, high frequency noise
Creative Commons and power losses that can affect not only the power load but also the distribution
Attribution License (CC BY 4.0) system. All these undesirable things affect the machine and other equipment like
(http://creativecommons.org/licenses/ controllers and auxiliary systems. Thus, to overcome the losses and increase the
by/4.0) performance of the machine, multi-level inverters came into existence. They are
used to achieve the high-performance applications. have different topologies by arranging diodes and switches
Moreover, the benefits of using multi-level inverters are in different manner. In MLI, the arrangement of switches’
improved power quality, reduction in switching losses of the angles is of utmost importance. Basically, the multi-level
system and improved voltage capability. The MLIs generate inverter is used to achieve the perfect sinusoidal waveform
common mode voltage (CMV). CMV reduces the voltage of the output and thereby reducing losses and thus
stress of the motor without damaging it. MLIs can draw increasing output. There are three different topologies of
input current with very low distortion. MLIs can operate at multi-level inverters
very low or very high switching frequencies, compared to
the fundamental frequency. Lower switching frequency 1. Flying Capacitor
basically means lower switching losses and vice versa. This It is made up of a series connection of capacitor-clamped
ability of operation results in the higher efficiency of the switching-cells. These capacitors convert only a limited
operation. The combination of Selective Harmonic amount of voltage to provide to the electrical devices. This
Elimination Technique and the multi-level topologies topology also has the switching redundancy within phase, in
reduces the THD in the output. This reduces the requirement order to balance the flying capacitors. Flying Capacitor
of filter circuit. topology has the ability to control the active as well as the
reactive power flow, but due to high frequency switching,
II. MULTI-LEVEL INVERTER (MLI) switching losses take place.
An n-level inverter will generate an output voltage with n
levels w.r.t. the negative terminal of the Capacitor. Basically, 2. Diode Clamp
the term multi-level begins with three levels, if we increase The key working notion of Diode Clamped inverter is to use
the number of levels in the inverter; the output voltage diodes in order to provide multiple voltage levels through
waveform will be like a staircase waveform having different different phases to the capacitor banks, which are further
intermediate levels, which results in reduction in THD. connected in series. The DC voltage that you need to apply at
the input level needs to be twice the maximum output
The requirement of an MLI is to generate a high-power voltage that you desire. The problem is resolved by
output from medium voltage sources like batteries, super- increasing the number of switches, diodes and capacitors
capacitors, solar panels, low power wind turbines etc. MLIs used. There exists a capacitor balancing issue, due to which
@ IJTSRD | Unique Paper ID - IJTSRD23984 | Volume – 3 | Issue – 4 | May-Jun 2019 Page: 1082
International Journal of Trend in Scientific Research and Development (IJTSRD) @ www.ijtsrd.com eISSN: 2456-6470
these are limited only to three level multi-level inverters. where, Ns = the total number of switches used m= the
Diode Clamp MLI provides improved performance and voltage level.
efficiency due to the use of fundamental frequency for all the
switching devices. Moreover, it is a simple method for back
to back power transfer systems.
3. Cascaded H-Bridge(CHB)
The Cascaded H-bridge MLI uses capacitors and switches.
The power can be easily scaled, since it is composed of a
series of power conversion cells and thus the power can be
easily scaled. This combination of capacitors and switches’
pair is called an H-bridge and gives a separate input DC
voltage for each H-bridge. This model has H-bridge cells, and
each cell can provide the load with three different voltages,
like zero, +ve DC and -ve DC voltages.
As the levels increase, the control complexity increases and

voltage imbalance problems are observed. There are several
modulations and controlling techniques that have been Fig 1: 1-phase 5-level CHB Inverter
developed for MLIs, out of which some of them are Multi-
level Sinusoidal Pulse Width Modulation (SPWM) Multi-level In this diagram, total 8 MOSFETS are used and, it gives us the
Selective Harmonic Elimination, and Space-Vector output of 5-level voltage. The output is then provided to a
Modulation (SVM). resistive load. Comparison of the triangular wave and the
sinusoidal wave generates the pulses. For 5-level output, (n-
The main features due to which we used this type of 1) triangular waves are taken. This means that 4 triangular
multi-level inverter in our project are: waveforms are required, which are compared to the
1. The output voltage of multi-level inverters is of low sinusoidal waveform and thus each MOSFET is given a pulse
distortion with reduced dv/dt. with necessary time gap.
2. The input current that is drawn has reduced distortion.
3. the CMV generated is small. This helps in the reduction of
the stress in the motor bearings. In addition to all this,
using sophisticated modulation methods we can
eliminate CMV.
4. Cascaded H-Bridge MLI can operate with reduced
switching frequency.
But apart from having large number of advantages

multi-level inverter have some disadvantages and that
are: -
The number of components used is high. The Cascaded H-
Bridge inverter uses a large number of MOSFET modules.
The 5-level CHB MLI needs about 24 MOSFETS, with all the
gate drivers having the same number. The CHB MLI requires
a large number of isolated dc supplies to run. A stiff DC
supply, using an expensive phase shifting transformer, is
usually used to provide the various DC supplies for the CHB
inverter.
III. SINGLE-PHASE 5-LEVEL CHB MULTI-LEVEL

Fig 2: 1-phase 5-level CHB Inverter
INVERTER
The cascaded inverter shown in the figure has five voltage IV. SINGLE-PHASE 7-LEVEL CHB MULTI-
levels. The output voltage that will be obtained can be 0, ±E, LEVEL INVERTER
±2E. It is observed that different voltage levels can obtain The per-phase diagram of seven-level inverter is depicted in
when two or more switches are in switching state. This MLI Figure 2, where seven-level inverter has three H-bridge cells
provides huge pliability for switching pattern design, mainly in cascade as shown in the figure. The 7-level CHB Multi
for SVM schemes. Generally, if N is the number of single- Level Inverter has improved efficiency and better THD
phase H-bridges per phase, the total number of levels of the handling. It has reduced Harmonic Distortion than five-level
inverter is: MLI. This model is by far the best model which we made. It
m= (2N+1) gave the best simulation results and least THD in the output.
where, N is the number of H-bridge cells per phase leg and
for CHB inverter the value of m should be odd. The Cascade V. LEVEL SHIFTED MODULATION SCHEME:
H-Bridge MLI showed above, can be extended to any number Multiple carrier pulse modulation
of voltage levels. Let Ns be the total number of active
switches (IGBTs, MOSFETs) used in the CHB inverters can be A number of carriers are used in multi-level SPWM.
determined by, For ‘n’ level inverter ‘n-1’ carriers are used. These are
Ns = 6(m – 1) following three types
1. IN- PHASE DIPOSITION (IPD)
In this all the carries are in phase with respect to each other.
Fig 3: PD-PWM
2. PHASE OPPOSITIONDISPOSITION (POD) Fig 7: Image of the output waveform of a 7-level multi-
In POD technique, the carrier waveforms that are above the level inverter with APOD
zero are all out of phase with those below the zero by 180º.
Fig 4: POD-PWM
3. ALTERNATE PHASE OPPOSITION Fig 8: The First Fourier Transform Analysis of 5-level
DISPOSITION(APOD) multi-level inverter with Alternate Phase Opposition
APOD technique needs every (x – 1) carrier waveform, for an Disposition
x-level phase waveform, to be displaced by phase from each
other by 180º alternately
Fig 5: APOD-PWM
From all the above technique, APOD TECHNIQUE has the
least THD. So, the above simulations are done by using APOD
technique.
Fig 9: Image of the output waveform of a 5-level multi-
VI. SIMULATION RESULTS level inverter with Alternate Phase Opposition Disposition
In this section we will be showing the simulation result of
both the simulations. The output we get at the load side and V. CONCLUSION
the FFT analysis of both the simulation when we used APOD The Simulation results shows the performance and
technique. effectiveness of 1-Ф 5-level cascaded H-bridge multi-level
inverter and 7-level cascaded H-bridge multi-level inverter
of the proposed circuit for R-load, the result obtained is
having 5-level and 7-level of voltage and current .form by
using all the three PWM techniques like as:-IPD,POD,APOD.
After the comparison of the THD values obtained from all the
techniques we have concluded that APOD is much better
than other two techniques for the practical approach.
REFERENCE
[1] J. Rodriguez, J. S. Lai, F. Zheng. “Multi-level Inverters: A
survey of Topologies, controls, and applications” IEEE
Transactions on Industrial electronic, Vol 49. No 4.
August 2002. pp 724-738.
[2] P. Palanivel S. S. Dash, "Analysis of THD and output
voltage performance for cascaded multi-level inverter
Fig 6: The First Fourier Transform Analysis of 7-level using carrier pulse width modulation technique," iET
multi-level inverter with APOD Power Electron., vol. 4, Iss. 8, pp. 951-958, 201 l.
[3] B. P. McGrath, D. G. Holmes, "MulticalTier PWM Power Electronics, Vol. 17 N°1, January 2002, pp.125-
strategies for multi-level invelters," IEEE Trans. Ind. 131
Electronics., vol. 49, no. 4, pp.858-867, August 2002.
[7] Tolber, L.M., Habetler, T. G.: ‘Novel multi-level inverter
[4] E. Babaei, S. Alilu , S. L. A Karnik, "A New General carrier based PWM method’, IEEE Ind. Appl., 1999, 35,
Topology for Cascaded Multi-level Invelters With pp. 1098–11079.
Reduced Number of Components Based on Developed
[8] Naderi, R., Rahmati, A.: ‘Phase-shifted carrier PWM
H-Bridge," iEEE Trans. on industrial Electronics, vol.61 ,
technique forgeneral cascaded inverters’, IEEE Trans.
no. 8, pp. 3932-3939, October, 2013
Power Electron., 2008, 23, pp. 1257–1269 Fig. 10
[5] E. Babaei, "A cascade multi-level converter topology Phase-shifted pulse-width modulation output voltage a
with reduced number of switches," iEEE Trans. Power SH PWM b SFO PWM 958.
Electron, vol. 23, no. 6, pp. 2657-2664, November 2008
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Multi-level H-Bridge Drive”, IEEE Transactions on Volume 1 Issue 12 (December 2014)

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International Journal of Trend in Scientific Research and Development (IJTSRD)

THD Analysis of Cascaded Multi-level

How to cite this paper: Shilpa Sambhi | ABSTRACT

Copyright © 2019 by author(s) and I. INTRODUCTION

As the levels increase, the control complexity increases and

But apart from having large number of advantages

III. SINGLE-PHASE 5-LEVEL CHB MULTI-LEVEL

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