SCALE-iDriver Family

SID11x2KQ
Up to 8 A Single Channel IGBT/MOSFET Gate Driver for
Automotive Applications Providing Reinforced Galvanic Isolation

Product Highlights Description

Highly Integrated, Compact Footprint The SID11x2KQ is a single channel IGBT and MOSFET driver in an
• Split outputs providing up to 8 A peak drive current eSOP package. Reinforced galvanic isolation is provided by Power
• Integrated FluxLink™ technology providing safe isolation between Integrations’ innovative solid insulator FluxLink technology. 8 A peak
primary-side and secondary-side output drive current enables the product to drive IGBTs and MOSFETs
• Rail-to-rail stabilized output voltage up to 600 A (typical) without any additional active components. For
• Unipolar supply voltage for secondary-side gate drive requirements that exceed the stand-alone capability of the
• Suitable for 600 V / 650 V / 1200 V IGBT and MOSFET switches SID11x2KQ’s, an external amplifier (booster) may be added. Stable
• Up to 75 kHz switching frequency positive and negative voltages for gate control are provided by one
• Low propagation delay time 260 ns unipolar isolated voltage source.
• Propagation delay jitter ±5 ns
Additional features such as short-circuit protection (DESAT) with
• -40 °C to 125 °C operating ambient temperature
Advanced Soft Shut Down (ASSD), undervoltage lock-out (UVLO) for
• High common-mode transient immunity
primary-side and secondary-side and rail-to-rail output with tempera-
• eSOP package with 9.5 mm creepage and clearance
ture and process compensated output impedance guarantee safe
Advanced Protection / Safety Features operation even in harsh conditions.
• Undervoltage lock-out (UVLO) protection for primary and
Controller (PWM and fault) signals are compatible with 5 V CMOS logic,
secondary-side and fault feedback
which may also be adjusted to 15 V levels by using external resistor divider.
• Short-circuit protection using VCESAT monitoring and fault feedback
• Advanced Soft Shut Down (ASSD)
Product Portfolio
Full Safety and Regulatory Compliance
• 100% production partial discharge test Product1 Peak Output Drive Current
• 100% production HIPOT compliance testing at 6 kV RMS 1 s SID1132KQ 2.5 A
• Reinforced insulation meets VDE 0884-10 (pending)
• AEC Q-100 qualified reaching automotive grade level 1 SID1182KQ 8.0 A
Table 1. SCALE-iDriver Portfolio.
Green Package Notes:
• Halogen free and RoHS compliant 1. Package: eSOP-R16B.

Applications
• Electric vehicle power train
• Electric vehicle on-board chargers and charger stations
• High reliability drivers and inverters

Figure 2. eSOP-R16B Package.

SCALE-iDriver

VCE
Primary-Side Secondary-Side
Logic Logic

VGXX

IN

Fault VISO
Output SO VTOT
+
VIN GH -
VCC
FluxLink
VVCC + GL
-
GND

VEE

COM

PI-7949-072616
Figure 1. Typical Application Schematic.

www.power.com March 2018

This Product is Covered by Patents and/or Pending Patent Applications.
 SID11x2KQ

VCE
+
VDES

VGXX

COM
SHORT-CIRCUIT BOOTSTRAP
DETECTION CHARGE PUMP VISO

VCC
LEVEL
ASSD
SHIFTER
GH

FluxLink
SO
TRANSCEIVER TRANSCEIVER
(BIDIRECTIONAL) (BIDIRECTIONAL)
VISO
GL
GND
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
CORE LOGIC POWER SUPPLIES COM
IN SUPPLY
MONITORING
AUXILIARY VISO
POWER SUPPLIES
VEE CONTROL VEE

PI-7654-092216

Figure 3. Functional Block Diagram.

Pin Functional Description VISO Pin (Pin 14):

This pin is the input for the secondary-side positive supply voltage.
VCC Pin (Pin 1):
This pin is the primary-side supply voltage connection. COM Pin (Pin 15):
This pin provides the secondary-side reference potential.
GND Pin (Pin 3-6):
This pin is the connection for the primary-side ground potential. GL Pin (Pin 16):
All primary-side voltages refer to the pin. This pin is the driver output – sinking current (turn-off).

IN Pin (Pin 7):

This pin is the input for the logic command signal.

SO Pin (Pin 8):

This pin is the output for the logic fault signal (open drain).

NC Pin (Pin 9):

This pin must be un-connected. Minimum PCB pad size for soldering VCC 1 16 GL
is required. 15 COM
14 VISO
VEE Pin (Pin 10):
GND 3-6 13 GH
Common (IGBT emitter/MOSFET source) output supply voltage.
12 VGXX
VCE Pin (Pin 11): 11 VCE
This pin is the desaturation monitoring voltage input connection. IN 7 10 VEE
VGXX Pin (Pin 12): SO 8 9 NC
This pin is the bootstrap and charge pump supply voltage source.

GH Pin (Pin 13):

This pin is the driver output – sourcing current (turn-on) connection.
PI-7648-041415

Figure 4. Pin Configuration.

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 SID11x2KQ

SCALE-iDriver Functional Description

SCALE-iDriver
The single channel SCALE-iDriver™ family is designed to drive IGBTs
and MOSFETs or other semiconductor power switches with a blocking
voltage of up to 1200 V and provide reinforced isolation between R1
IN
micro-controller and the power semiconductor switch. The logic
input (PWM) command signals applied via the IN pin and the primary R2
supply voltage supplied via the VCC pin are both referenced to the SO
GND pin. The working status of the power semiconductor switch and
RSO
SCALE-iDriver is monitored via the SO pin.
VCC
PMW command signals are transferred from the primary (IN) to
C1
secondary-side via FluxLink isolation technology. The GH pin supplies
GND
a positive gate voltage and charges the semiconductor gate during
the turn-on process. The GL pin supplies the negative voltage and
discharges the gate during the turn-off process.

Short-circuit protection is implemented using a desaturation detection PI-7950-050916

technique monitored via the VCE pin. When the SCALE-iDriver detects
a short-circuit, the semiconductor turn-off process is activated Figure 5. Increased Threshold Voltages VIN+LT and V IN+HT. For R1 = 3.3 kW and
using an Advanced Soft Shut Down (ASSD) technique. R 2 = 1 kW the IN Logic Level is 15 V.

Power Supplies connected to the GH pin and turn-off gate resistor RGOFF to the GL pin.
The SID11x2KQ requires two power supplies. One is the primary-side If both gate resistors have the same value, the GL and GH pins can be
(V VCC) which powers the primary-side logic and communication with connected together. Note: The SCALE-iDriver data sheet defines the
the secondary (insulated) side. Another supply voltage is required for RGH and RGL values as total resistances connected to the respective
the secondary-side, V TOT is applied between the VISO pin and the pins GH and GL. Note that most power semiconductor data sheets
COM pin. V TOT needs to be insulated from the primary-side and must specify an internal gate resistor RGINT which is already integrated into
provide at least the same insulation capabilities as the SCALE-iDriver. the power semiconductor switch. In Addition to RGINT, external
V TOT must have a low capacitive coupling to the primary or any other resistor devices RGON and RGOFF are specified to setup the gate current
secondary-side. The positive gate-emitter voltage V VISO is provided by levels to the application requirements. Consequently, RGH is the sum
VISO which is internally generated and stabilized to 15 V (typically) of RGON and RGINT, as shown in Figures 9 and 10. Careful consideration
with respect to VEE. The negative gate-emitter voltage V VEE is should be given to the power dissipation and peak current associated
provided by VEE with respect to COM. Due to the limited current with the external gate resistors.
sourcing capabilities of the VEE pin, any additional load needs to be
applied between the VISO and COM pins. No additional load between The GH pin output current source (IGH) of SID1182KQ is capable of
VISO and VEE pins or between VEE and COM pins is allowed. handling up to 7.3 A during turn-on, and the GL pin output current
source (IGL) is able to sink up to 8.0 A during turn-off. The SCALE-
Input and Fault Logic (Primary-Side) iDriver’s internal resistances are described as RGHI and RGLI respec-
The input (IN) and output (SO) logic is designed to work directly with tively. If the gate resistors for SCALE-iDriver family attempt to draw
micro-controllers using 5 V CMOS logic. If the physical distance a higher peak current, the peak current will be internally limited to a
between the controller and the SCALE-iDriver is large or if a different safe value, see Figures 6 and 7. Figure 8 shows the peak current
logic level is required the resistive divider in Figure 5, or Schmitt-trigger
ICs (Figures 13 and 14) can be used. Both solutions adjust the logic level 9

PI-7910-121516
as necessary and will also improve the driver’s noise immunity.
Turn-On Peak Gate Current IGH (A)

Gate driver commands are transferred from the IN pin to the GH and 8
GL pins with a propagation delay tP(LH) and tP(HL).
7
During normal operation, when there is no fault detected, the SO pin
stays at high impedance (open). Any fault is reported by connecting 6
the SO pin to GND. The SO pin stays low as long as the V VCC voltage
(primary-side) stays below UVLOVCC, where the propagation delay is 5
negligible. If desaturation is detected (there is a short-circuit), or the
supply voltages V VISO, V VEE, (secondary-side) drop below UVLOVISO, 4
UVLOVEE, the SO status changes with a delay time tFAULT and keeps
status low for a time defined as tSO. In case of a fault condition the 3
driver applies the off-state (the GL pin is connected to COM). During RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 47 nF
the tSO period, command signal transitions from the IN pin are 2 RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 100 nF
ignored. A new turn-on command transition is required before the RGH = RGL = 0 Ω, CLOAD = 47 nF
driver will enter the on-state. 1
The SO pin current is defined as ISO; voltage during low status is
0
defined as VSO(FAULT).
-60 -40 -20 0 20 40 60 80 100 120 140
Output (Secondary-Side)
The gate of the power semiconductor switch to be driven can be Ambient Temperature (°C)
connected to the SCALE-iDriver output via pins GH and GL, using two Figure 6. Turn-On Peak Output Current (Source) vs. Ambient Temperature.
different resistor values. Turn-on gate resistor RGON needs to be Conditions: VCC = 5 V, V TOT = 25 V, fS = 20 kHz, Duty Cycle = 50%.

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 SID11x2KQ

0 7

PI-7912-042816
PI-7911-042816
Turn-Off Peak Gate Current IGL (A)

-1
RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 47 nF 6
-2 RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 100 nF

Gate Peak Current (A)

RGH = RGL = 0 Ω, CLOAD = 47 nF
-3 5

-4
4
-5
3
-6

-7 2
IGH, Turn-On Peak Gate Current
-8 IGL, Turn-Off Peak Gate Current
1
-9

-10 0
-60 -40 -20 0 20 40 60 80 100 120 140 20 21 22 23 24 25 26 27 28 29 30

Ambient Temperature (°C) Secondary-Side Total Supply Voltage – VTOT (V)

Figure 7. Turn-Off Peak Output Current (Sink) vs. Ambient Temperature. Figure 8. Turn-On and Turn-Off Peak Output Current vs. Secondary-Side Total
Conditions: VVCC = 5 V, V TOT = 25 V, fS = 20 kHz, Duty Cycle = 50% Supply Voltage (V TOT). Conditions: VVCC = 5 V, TJ = 25 °C, RGH = 4 W,
RGL = 3.4 W, CLOAD = 100 nF, fS = 1 kHz, Duty Cycle = 50%.

that can be achieved for a given supply voltage for same gate resistor
values, load capacitance and layout design.

Short-Circuit Protection
SCALE-iDriver
The SCALE-iDriver uses the semiconductor desaturation effect to
detect short-circuits and protects the device against damage by RVCE RVCEX
employing an Advanced Soft Shut Down (ASSD) technique. Desatu- VCE

ration can be detected using two different circuits, either with diode
sense circuitry DVCE (Figure 10) or with resistors RVCEX (Figure 9). With VGXX CRES DCL
the help of a well stabilized V VISO and a Schottky diode (DSTO) connected CGXX
between semiconductor gate and VISO pin the short-circuit current
VISO
value can be limited to a safe value.
DSTO
During the off-state, the VCE pin is internally connected to the COM RGON
GH Collector
pin and CRES is discharged (red curve in Figure 11 represents the
Gate RGINT
potential of the VCE pin). When the power semiconductor switch RGOFF
GL
receives a turn-on command, the collector-emitter voltage (VCE)
decreases from the off-state level same as the DC-link voltage to a Emitter
normally much lower on-state level (see blue curve in Figure 11) and VEE

CRES begins to be charged up to the VCE saturation level (VCE SAT). CRES
charging time depends on the resistance of RVCEX (Figure 9), DC-link COM
voltage and CRES and RVCE value. The VCE voltage during on-state is
continuously observed and compared with a reference voltage, VDES.
The VDES level is optimized for IGBT applications. As soon as VCE>VDES
PI-7952-080416
(red circle in Figure 11), the driver turns off the power semiconductor
switch with a controlled collector current slope, limiting the VCE
overvoltage excursions to below the maximum collector-emitter Figure 9. Short-Circuit Protection using a Resistor Chain RVCEX.
voltage (VCES). Turn-on commands during this time and during tSO are
ignored, and the SO pin is connected to GND.
and power-down. Any supply voltage related to VCC, VISO, VEE and
The response time tRES is the CRES charging time and describes the VGXX pins should be stabilized using ceramic capacitors C1, CS1X, CS2X,
delay between VCE asserting and the voltage on the VCE pin rising CGXX respectively as shown in Figures 13 and 14. After supply
(see Figure 11). Response time should be long enough to avoid false voltages reach their nominal values, the driver will begin to function
tripping during semiconductor turn-on and is adjustable via RRES and after a time delay tSTART.
CRES (Figure 10) or RVCE and CRES (Figure 9) values. It should not be
Short-Pulse Operation
longer than the period allowed by the semiconductor manufacturer.
If command signals applied to the IN pin are shorter than the minimum
Safe Power-Up and Power-Down specified by tGE(MIN), the SCALE-iDriver output signals, GH and GL pins,
During driver power-up and power-down, several unintended input / will be extended to value tGE(MIN). The duration of pulses longer than
output states may occur. In order to avoid these effects, it is tGE(MIN) will not be changed.
recommended that the IN pin is kept at logic low during power-up

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 SID11x2KQ

SCALE-iDriver
V
RVCE DVCE
VCE

VGXX VCE (IGBT) Signal

CRES RRES
CGXX Fault
VISO VDES

DSTO
RGON
GH Collector VCE SAT

Gate RGINT tRES t

RGOFF
GL

Emitter
VEE VCE Pin Signal

COM

COM

PI-7951-080416 PI-7671-093016

Figure 10. Short-Circuit Protection Using Rectifier Diode DVCE. Figure 11. Short-Circuit Protection Using Resistors Chain RVCEX.

Advanced Soft Shut Down (ASSD) to a safe value. At the end of period P1, VGE is reduced during tFSSD1.
This function is activated when a short-circuit is detected. It protects Due to collector current decrease a small VCE overvoltage is seen.
the power semiconductor switch against destruction by ending the During tFSSD1 VGE is further reduced and the gate of the power
turn-on state and limiting the current slope in order to keep momen- semiconductor switch is further discharged. During tFSSD2 additional
tary VCE overvoltages below VCES. This function is particularly suited to small VCE overvoltage events may occur. Once VGE drops below the
IGBT applications. Figure 12 shows how the ASSD function operates. gate threshold of the IGBT, the collector current has decayed almost to
The VCE desaturation is visible during time period P1 (yellow line). zero and the remaining gate charge is removed ‒ ending the short-
During this time, the gate-emitter voltage (green line) is kept very circuit event. The whole short-circuit current detection and safe
stable. Collector current (pink line) is also well stabilized and limited switch-off is lower than 10 µs (8 µs in this example).

VGE
tFSSD1

IGE VCE

ICE

tFSSD2
P1

Figure 12. Advanced Soft Shut Down Function.

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 SID11x2KQ

Application Examples and Components Selection CS11 and CS12. The gate charge will vary according to the type of
power semiconductor switch that is being driven. Typically, CS11 + CS12
Figures 13 and 14 show the schematic and typical components used should be at least 3 mF multiplied by the total gate charge of the
for a SCALE-iDriver design. In both cases the primary-side supply power semiconductor switch (QGATE) divided by 1 mC. A 10 nF capacitor
voltage (V VCC) is connected between VCC and GND pins and supported CGXX is connected between the GH and VGXX pins.
through a supply bypass ceramic capacitor C1 (4.7 mF typically). If the
command signal voltage level is higher than the rated IN pin voltage The gate of the power semiconductor switch is connected through
(in this case 15 V) a resistive voltage divider should be used. Additional resistor RGON to the GH pin and by RGOFF to the GL pin. If the value of
capacitor CF and Schmitt trigger IC1 can be used to provide input RGON is the same as RGOFF the GH pin can be connected to the GL pin
signal filtering. The SO output has 5 V logic and the RSO is selected and a common gate resistor can be connected to the gate. In any
so that it does not exceed absolute maximum rated ISO current. case, proper consideration needs to be given to the power dissipation
and temperature performance of the gate resistors.
The secondary-side isolated power supply (V TOT) is connected between
VISO and COM. The positive voltage rail (V VISO) is supported through To ensure gate voltage stabilization and collector current limitation
4.7 µF ceramic capacitors CS21 and CS22 connected in parallel. The during a short-circuit, the gate is connected to the VISO pin through
negative voltage rail (V VEE) is similarly supported through capacitors a Schottky diode DSTO (for example PMEG4010).

SCALE-iDriver
RVCE RVCE2-11
120 kΩ 100 kΩ × 10
VCE
Primary-Side Secondary-Side
Logic Logic

Command R1 IC1 VGXX CRES DCL

Signal 3.3 kΩ 74LVC 33 pF BAS416
IN CGXX
10 nF DSTO
RSO VISO
SO 4.7 kΩ SO CS21 CS22
RGON Collector
GH 4.7 µF 4.7 µF
C1 C2
VCC 4.7 µF 470 nF VCC Gate
+ V
FluxLink - TOT RGOFF
CF R2 GL
GND 1 kΩ
GND RSO Emitter
22 kΩ
VEE

CS11 CS12
4.7 µF 4.7 µF
COM

PI-8639-031218

Figure 13. SCALE-iDriver Application Example Using a Resistor Network for Desaturation Detection.

SCALE-iDriver
RVCE
330 Ω DVCE2 DVCE1
VCE
Primary-Side Secondary-Side
Logic Logic

Command R1 IC1 VGXX RRES CRES

Signal 3.3 kΩ 74LVC 24-62 kΩ 33-330 pF
IN CGXX
10 nF DSTO
RSO VISO
SO 4.7 kΩ SO CS21 CS22
RGON Collector
GH 4.7 µF 4.7 µF
C1 C2
VCC 4.7 µF 470 nF VCC Gate
+ V
FluxLink - TOT RGOFF
CF R2 GL
GND 1 kΩ
GND RDIS Emitter
22 kΩ
VEE

CS11 CS12
4.7 µF 4.7 µF
COM

PI-8638-031218

Figure 14. SCALE-iDriver Application Example Using Diodes for Desaturation Detection.

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 SID11x2KQ

To avoid parasitic power-switch-conduction during system power-on, PP = VVCC # I VCC (2)

the gate is connected to COM through 22 kΩ resistor. PSNL = VTOT # I VISO (3)
Figure 13 shows how switch desaturation can be measured using During IC operation, the PDRV power is shared between turn-on (RGH),
resistors RVCE2 – RVCE11. In this example all the resistors have a value turn-off (RGL) external gate resistors and internal driver resistances
of 100 kW using 1206 package. The total resistance is 1 MW. The RGHI and RGLI. For junction temperature estimation purposes, the
resistors should be chosen to limit current to between 0.6 mA to 0.8 dissipated power under load (POL) inside the IC can be calculated
mA at maximum DC-link voltage. The sum of RVCE2 – RVCE11 should be accordingly to equation 4:
approximately 1 MW for 1200 V semiconductors and 500 kW for 600 V
R GHI R GHL l
semiconductors. In each case the resistor string must provide POL = 0.5 # Q GATE # fS # VTOT # b R + R GH + R GHL + R GL
GHI
sufficient creepage and clearance distances between collector of the
semiconductor and SCALE-iDriver. The low leakage diode DCL keeps (4)
the short-circuit duration constant over a wide DC-link voltage range.
RGH and RGL represent sum of external (RGON, RGOFF) and power
Response time is set up through RVCE and CRES (typically 120 kW and semiconductor internal gate resistance (RGINT):
33 pF respectively for 1200 V semiconductors). If short-circuit
detection proves to be too sensitive, the CRES value can be increased. R GH = R GON + R GINT
The maximum short-circuit duration must be limited to the maximum
value given in the semiconductor data sheet. R GL = R GOFF + R GINT
Figure 14 illustrates how diodes DVCE1 and DVCE2 may be used to Total IC power dissipation (PDIS) is estimated as sum of equations 2, 3
measure switch desaturation. For insulation, two diodes in SMD and 4:
packages are used (STTH212U for example). RRES connected to VISO PDIS = PP + PSNL + POL
(5)
guarantees current flow through the diodes when the semiconductor
is in the on-state. When the switch desaturates, CRES starts to be The operating junction temperature (TJ) for given ambient tempera-
charged through RRES. In this configuration the response time is ture (TA) can be estimated according to equation 6:
controlled by RRES and CRES. In this application example CRES = 33 pF
and RRES = 62 kW; if desaturation is too sensitive or the short-circuit TJ = i JA # PDIS + T A (6)
duration too long, both CRES and RRES can be adjusted. Example
It is important to ensure that PCB traces do not cover the area below An example is given below,
the desaturation resistors or diodes DVCE1 and DVCE2. This is a critical
design requirement to avoid coupling capacitance with the SCALE- ƒS = 20 kHz, TA = 85 °C, V TOT = 25 V, V VCC = 5 V.
iDriver’s VCE pin and isolation issues within the PCB. QGATE = 2.5 mC (the gate charge value here should correspond to
selected V TOT), RGINT = 2.5 W, RGON = RGOFF = 1.8 W.
Gate resistors are located physically close to the power semiconductor
switch. As these components can get hot, it is recommended that PDRV = 2.5 mC × 20 kHz × 25 V = 1.25 W, according to equation 1.
they are placed away from the SCALE-iDriver. PP = 5 V × 13.5 mA = 67 mW, according to equation 2 (see Figure 16).
PSNL = 25 V × 7.5 mA = 185 mW, according to equation 3 (see Figure 17).
Power Dissipation and IC Junction
Temperature Estimation The dissipated power under load is:

First calculation in designing the power semiconductor switch gate

POL = 0.5 # 2.5 nC # 20 kHz # 25 V #
driver stage is to calculate the required gate power - PDRV. The power
is calculated based on equation 1: b 1.45 X 1.2 X l ≅ 0.3 W,
+
1.45 X + 4.3 X 1.2 X + 4.3 X
PDRV = Q GATE # fS # VTOT (1) according to equation 4.
where,
RGHI = 1.45 W as maximum data sheet value.
QGATE – Controlled power semiconductor switch gate charge (derived RGHL = 1.2 W as maximum data sheet value.
for the particular gate potential range defined by V TOT). See semicon- RGH = RGL = 1.8 W + 2.5 W = 4.3 W.
ductor manufacturer data sheet.
PDIS = 67 mW + 185 mW + 300 mW = 552 mW according to equation 5.
ƒS – Switching frequency which is same as applied to the IN pin of TJ = 67 °C/W × 552 mW + 85 °C = 122 °C according to equation 6.
SCALE-iDriver.
Estimated junction temperature for this design would be approximately
V TOT – SCALE-iDriver secondary-side supply voltage. 122 °C and is lower than the recommended maximum value. As the
In addition to PDRV, PP (primary-side IC power dissipation) and PSNL gate charge is not adjusted to selected V TOT and internal IC resistor
(secondary-side IC power dissipation without capacitive load) must be values are maximum values, it is understood that the example
considered. Both are ambient temperature and switching frequency represents worst-case conditions.
dependent (see typical performance characteristics).

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 SID11x2KQ

Table 2 describes the recommended capacitor and resistor

characteristics and layout requirements to achieve optimum
performances of SCALE-iDriver.

VCE Resistor Chain

Recommended
Pin Return Pin Symbol Remark
Value

Needed if command signals >5 V are used. For 15 V

Command Signal IC1 Application specific R1 input logic a value of 3.3 kΩ is recommended. The use
of 1% / 0.1 W / 50 V in 0603 package is recommended.
Needed if command signals >5 V are used. For 15 V
R1 GND Application specific R2 input logic a value of 1.2 kΩ is recommended. The use
of 1% / 0.1 W / 50 V in 0603 package is recommended.
Pull-up resistor, the use of 1% / 0.1 W / 50 V in 0603
SO VCC 4.7 kΩ RSO
package is recommended.
VCC blocking capacitors C1 must be placed close to the
IC. Enlarged loop could result in inadequate VCC supply
VCC GND 4.7 µF C1
voltage during operation. For C1 X7R / 25 V / 10% in a
1206 package is recommended.
VCC blocking capacitors C2 must be placed close to the
IC. Enlarged loop could result in inadequate VCC supply
VCC GND 470 nF C2
voltage during operation. For C2 X7R / 25 V / 10% in a
0608 package is recommended.
If used, the tau determines to τ = ( R1 × R2 × CF ) /
R1 GND Application specific CF (R1 + R2) The use of NP0, C0G / 50 V / 5% in 0603
package is recommended.
In case bad signal quality at the command signal input
is expected, a schmitt trigger could be used to improve
R1 IN Application specific IC1
the signal quality at the IN pin. As a reference Nexperia
74LVC1G17-Q100 could be used.
CS1x should be at least 3 μF multiplied by the total gate
charge of the power semiconductor switch (QGATE)
VEE COM Application specific CS1x divided by 1 μC. The use of X7R / 25 V / 10% in 1206
package is recommended. This capacitor needs to be
placed close to the IC pins.
CS2x should be at least 3 μF multiplied by the total gate
charge of the power semiconductor switch (QGATE)
VISO VEE Application specific CS2x divided by 1 μC. The use of X7R / 25 V / 10% in 1206
package is recommended. This capacitor needs to be
placed close to the IC pins.
Short-circuit response time capacitor. 33 pF is a typical
application value, higher values will increase the
response time while smaller values will decrease it. To
determine the correct value short-circuit testing in
VCE COM Application specific CRES double pulse configuration is recommended. Further-
more the use of NP0, C0G / 50 V / 5% in 0603 package
is recommended. Any net and any other layer should
provide sufficient distance to in order to CRES avoid
parasitic effects.
To avoid misoperation, this pin should not be connected
to anything else. This capacitor needs to be as close to
VGXX GH 10 nF CGXX
IC pins as possible. The use of X7R / 25 V / 10% in
0603 package is recommended.
Short-circuit response time resistor. The use of 1% /
0.1 W / 50 V in 0603 package is recommended. Any net
DCL VCE 120 kΩ RVCE1
and any other layer should provide sufficient distance to
RVCE1 in order to avoid parasitic effects.

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 SID11x2KQ

For a DC-link voltage of 800 V, the short-circuit resistor

chain have a overall value of 1.2 MΩ giving a current of
0.67 mA. Other values are also possible but it has to be
Power
considered that the current through the chain shall be
Semiconductor RVCE1 10 x 120 kΩ RVCE2 − RVCE10
0.6 to 0.8 mA. The use of 1% / 0.25 W / 200 V in 1206
Collector
package is recommended. Any net and any other layer
should provide sufficient distance to RVCE2 − RVCE10 in
order to avoid parasitic effects.
"To avoid parasitic power-switch-conduction during
Power
system power-on, the gate is connected to COM
Semiconductor COM 22 kΩ RDIS
through 22 kΩ. The use of 1% / 0.1 W / 50 V in 0603
Gate
package is recommended."
"To ensure gate voltage stabilization and collector
current limitation during a short-circuit, the gate is
Power connected to the VISO pin through the Schottky diode
VISO Semiconductor Schottky Diode DSTO DSTO. DSTO should be connected close to capacitor CS1 as
Gate well as the power semiconductor gate. Enlarged loop
could result in increased short-circuit current. The use
of Nexperia PMEG4010CEJ is recommended."
Clamping diode to the secondary-side power supply
voltage. The use of Nexperia BAS416 is recommended.
RVCE1 VISO Diode DCL
Any net and any other layer should provide sufficient
distance to DCL in order to avoid parasitic effects.
Power
As the turn-on gate resistor can get hot, the component
Semiconductor GH Application specific RGON
shall be placed away from the gate driver IC.
Gate

Power
As the turn-off gate resistor can get hot, the component
Semiconductor GL Application specific RGOFF
shall be placed away from the gate driver IC.
Gate

Table 2. PCB Layout and Component Guidelines Referring to Figure 13.

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VCE Diode Chain

Recommended
Pin Return Pin Symbol Remark
Value

Needed if command signals >5 V are used. For 15 V

Command Signal IC1 Application specific R1 input logic a value of 3.3 kΩ is recommended. The use
of 1% / 0.1 W / 50 V in 0603 package is recommended.

Needed if command signals >5 V are used. For 15 V

R1 GND Application specific R2 input logic a value of 1.2 kΩ is recommended. The use
of 1% / 0.1 W / 50 V in 0603 package is recommended.

Pull up resistor, the use of 1% / 0.1 W / 50 V in 0603

SO VCC 4.7 kΩ RSO
package is recommended.

VCC blocking capacitors C1 must be placed close to the

IC. Enlarged loop could result in inadequate VCC supply
VCC GND 4.7 µF C1
voltage during operation. For C1 X7R / 25 V / 10% in a
1206 package is recommended.
VCC blocking capacitors C2 must be placed close to the
IC. Enlarged loop could result in inadequate VCC supply
VCC GND 470 nF C2
voltage during operation. For C2 X7R / 25 V / 10% in a
0608 package is recommended.
If used, the tau determines to τ = ( R1 × R2 × CF ) /
R1 GND Application specific CF (R1 + R2) The use of NP0, C0G / 50 V / 5% in 0603
package is recommended.
In case bad signal quality at the command signal input
is expected, a schmitt trigger could be used to improve
R1 IN Application specific IC1
the signal quality at the IN pin. As a reference Nexperia
74LVC1G17-Q100 could be used.

CS1x should be at least 3 μF multiplied by the total gate

charge of the power semiconductor switch (QGATE)
VEE COM Application specific CS1x divided by 1 µC. The use of X7R / 25 V / 10% in 1206
package is recommended. This capacitor needs to be
placed close to the IC pins.

CS2x should be at least 3 μF multiplied by the total gate

charge of the power semiconductor switch (QGATE)
VISO VEE Application specific CS2x divided by 1 µC. The use of X7R / 25 V / 10% in 1206
package is recommended. This capacitor needs to be
placed close to the IC pins.

Short-circuit response time capacitor. 33 pF is a typical

application value, higher values will increase the
response time while smaller values will decrease it.
It can be adjusted in the range 33 pF to 330 pF. To
determine the correct value short-circuit testing in
VCE COM Application specific CRES
double pulse configuration is recommended. Further-
more the use of NP0, C0G / 50 V / 5% in 0603 package
is recommended. Any net and any other layer should
provide sufficient distance to in order to CRES avoid
parasitic effects.

To avoid misoperation, this pin should not be connected

to anything else. This capacitor needs to be as close to
VGXX GH 10 nF CGXX
IC pins as possible. The use of X7R / 25 V / 10% in
0603 package is recommended.
The use of 1% / 0.1 W / 50 V in 0603 package is
recommended. Any net and any other layer should
DVCE2 VCE 330 Ω RVCE
provide sufficient distance to RVCE in order to avoid
parasitic effects.

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This resistor in combination with CRES sets the

short-circuit response time. It can be adjusted in the
range from 24 kΩ to 62 kΩ. The use of 1% / 0.1 W/
VCE VISO Application specific RRES
50 V in 0603 package is recommended. Any net and any
other layer should provide sufficient distance to RRES in
order to avoid parasitic effects.

"To avoid parasitic power-switch-conduction during

Power
system power-on, the gate is connected to COM
Semiconductor COM 22 kΩ RDIS
through 22 kΩ. The use of 1% / 0.1 W / 50 V in 0603
Gate
package is recommended."
High-voltage diodes for the short-circuit detection.
Power Creepage and clearance distances need to be consid-
Semiconductor RRES Application specific DVCE1/DVCE2 ered. STTH212U or comparable could be used. Any net
Collector and any other layer should provide sufficient distance to
DVCE1 and DVCE2 in order to avoid parasitic effects.
"To ensure gate voltage stabilization and collector
current limitation during a short-circuit, the gate is
Power connected to the VISO pin through the Schottky diode
VISO Semiconductor Schottky Diode DSTO DSTO. DSTO should be connected close to capacitor CS1 as
Gate well as the power semiconductor gate. Enlarged loop
could result in increased short-circuit current. The use
of Nexperia PMEG4010CEJ is recommended."
Clamping diode to the secondary-side power supply
voltage. The use of Nexperia BAS416 is recommended.
RVCE1 VISO Diode DCL
Any net and any other layer should provide sufficient
distance to DCL in order to avoid parasitic effects.
Power
As the turn on gate resistor can get hot, the component
Semiconductor GH Application specific RGON
shall be placed away from the gate driver IC.
Gate

Power
As the turn off gate resistor can get hot, the component
Semiconductor GL Application specific RGOFF
shall be placed away from the gate driver IC.
Gate

Table 3. PCB Layout and Component Guidelines Referring to Figure 14.

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Parameter Symbol Conditions Min Max Units

Absolute Maximum Ratings1

Primary-Side Supply Voltage2 V VCC VCC to GND -0.5 6.5 V
Secondary-Side Total Supply Voltage V TOT VISO to COM -0.5 30 V
Secondary-Side Positive Supply Voltage V VISO VISO to VEE -0.5 17.5 V
Secondary-Side Negative Supply Voltage V VEE VEE to COM -0.5 15 V
Logic Input Voltage (command signal) VIN IN to GND -0.5 V VCC + 0.5 V
Logic Output Voltage (fault signal) VSO SO to GND -0.5 V VCC + 0.5 V
Logic Output Current (fault signal) ISO Positive Current Flowing into the Pin 10 mA
VCE Pin Voltage V VCE VCE ‒ COM -0.5 V TOT + 0.5 V
Switching Frequency fS 75 kHz
Storage Temperature TS -65 150 °C
Operating Junction Temperature TJ -40 1503 °C
Operating Ambient Temperature TA -40 125 °C
Operating Case Temperature TC -40 125 °C
Input Power Dissipation 4
PP V VCC = 5 V, V TOT = 28 V, 115
mW
Output Power Dissipation4 PS TA = 25 °C 1675
Total IC Power Dissipation4 PDJS fS = 75 kHz 1790 mW
NOTES:
1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
2. Defined as peak voltage measured directly on VCC pin.
3. Transmission of command signals could be affected by PCB layout parasitic inductances at junction temperatures higher than recommended.
4. Input Power Dissipation refers to equation 2. Output Power Dissipation is secondary-side IC power dissipation without capacitive load
(PSNL, equation 3) and dissipated power under load (POL, equation 4). Total IC power dissipation is sum of PP and PS.

Thermal Resistance
Thermal Resistance: eSOP-R16B Package: Notes:
(qJA) ................................................... 67 °C/W1 1. 2 oz. (610 g/m2) copper clad.
(qJC) ...................................................34 °C/W2 2. The case temperature is measured at the plastic surface at the top
of the package.

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Conditions
Parameter Symbol TJ = -40 °C to +125 °C Min Typ Max Units
See Note 1 (Unless Otherwise Specified)

Recommended Operation Conditions

Primary-Side
V VCC VCC ‒ GND 4.75 5.25 V
Supply Voltage
Secondary-Side
V TOT VISO ‒ COM 22 28 V
Total Supply Voltage

Logic Low Input Voltage VIL 0.5 V

Logic High
VIH 3.3 V
Input Voltage

Switching Frequency fS 0 75 kHz

Operating IC Junction
TJ -40 125 °C
Temperature
Electrical Characteristics
Logic Low Input
VIN+LT fS = 0 Hz 0.6 1.25 1.8 V
Threshold Voltage
Logic High Input
VIN+HT fS = 0 Hz 1.7 2.2 3.05 V
Threshold Voltage
Logic Input
VIN+HS fS = 0 Hz 0.1 V
Voltage Hysteresis

VIN = 5 V 56 113 165

Input Bias Current IIN VIN > 3 V mA
106
See Note 12

VIN = 0 V 4 11 17

Supply Current VIN = 5 V 16 23

IVCC mA
(Primary-Side) fS = 20 kHz 14.5 20

fS = 75 kHz 16.3 23

VIN = 0 V 6 8

Supply Current VIN = 5 V 7 9

IVISO mA
(Secondary-Side)
fS = 20 kHz 7.4 10

fS = 75 kHz 10.3 14

Clear Fault 4.28 4.65

Power Supply
Monitoring Threshold UVLOVCC Set Fault 3.85 4.12 V
(Primary-Side)
Hysteresis, See Notes 3, 4 0.02

Power Supply Clear Fault 12.85 13.5

Monitoring Threshold
UVLOVISO Set Fault, Note 3 11.7 12.35 V
(Secondary-Side,
Positive Rail V VISO) Hysteresis 0.3

Power Supply Monitor- Voltage Drop 13.5 V to 11.5 V

UVLOVISO(BL) 0.5 ms
ing Blanking Time, V VISO See Note 12

Power Supply Clear Fault, V TOT = 20 V 5.15 5.5

Monitoring Threshold
UVLOVEE Set Fault, V TOT = 20 V 4.67 4.93 V
(Secondary-Side,
Negative Rail V VEE) Hysteresis 0.1

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Conditions
Parameter Symbol TJ = -40 °C to +125 °C Min Typ Max Units
See Note 1 (Unless Otherwise Specified)

Electrical Characteristics (cont.)

Power Supply Monitor- Voltage Drop 5.5 V to 4.5 V
UVLOVEE(BL) 0.5 ms
ing Blanking Time, V VEE See Note 12

Secondary-Side
21 V ≤ V TOT ≤ 30 V,
Positive Supply Voltage V VISO(HS) 14.4 15.07 15.75 V
|i(VEE)| ≤ 1.5 mA
Regulation

V TOT = 15 V, V VEE set to 0 V 0.1

VEE Source Capability IVEE(SO) V TOT = 25 V, V VEE set to 7.5 V mA
1.85 3.3 4.5
See Note 13

V TOT = 25 V, V VEE set to 12.5 V

VEE Sink Capability IVEE(SI) 1.74 3.1 4.5 mA
See Note 13

DESAT Detection Level VDES VCE-VEE, VIN = 5 V 7.2 7.8 8.3 V

DESAT Sink Current IDES V VCE = 10 V, VIN = 0 V 15 28 50 mA

DESAT Bias Current IDES(BS) V VCE - V VEE = 4.5 V, VIN = 5 V -0.5 3 mA

VCE Pin Capacitance C VCE Between VCE and COM pins, See Note 12 12.5 pF

TJ = 25 °C, See Note 5 180 253 340

Turn-On
tP(LH) ns
Propagation Delay TJ = 125 °C, See Note 5 210 278 364

TJ = 25 °C, See Note 6 200 262 330

Turn-Off
tP(HL) ns
Propagation Delay TJ = 125 °C, See Note 6 211 287 359

Minimum Turn-On and

tGE(MIN) See Note 12 650 ns
Off Pulses

No CG, See Note 7 22 45

SID1132KQ
CG = 10 nF, 450
See Note 12
See Note 7
Output Rise Time tR SID1182KQ 55 90 150 ns

SID1132KQ
1950
CG = 47 nF, See Note 12
See Note 7
SID1182KQ 300 465 650

No CG, See Note 8 18 45

SID1132KQ
CG = 10 nF 450
See Note 12
See Note 8
Output Fall Time tF SID1182KQ 40 81 150 ns

SID1132KQ
1950
CG = 47 nF See Note 12
See Note 8
SID1182KQ 300 460 650

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Conditions
Parameter Symbol TJ = -40 °C to +125 °C Min Typ Max Units
See Note 1 (Unless Otherwise Specified)

Electrical Characteristics (cont.)

tFSSD1 VGE change from 14.5 V to 14 V, See Note 12 60
ASSD Rate of Change ns
tFSSD2 VGE change from 14.5 V to 2.5 V, See Note 12 950 1828 2800

Propagation Delay Jitter See Note 12 ±5 ns

Fault Signalization
tFAULT See Note 10 190 750 ns
Delay Time
SO Fault
tSO 6.8 10 13.4 µs
Signalization time
Power-On
tSTART See Note 11 10 ms
Start-Up Time

VGH ≥ VTOT - 8.8 V SID1132KQ

1.2
See Note 12
CG = 470 nF
Gate Sourcing See Note 13 SID1182KQ 3.6 4.6 5.5
IGH A
Peak Current GH Pin
SID1132KQ 2.4
RG = 0, CG = 47 nF
See Notes 2, 12, 13
SID1182KQ 7.3

VGL ≤ 7.5 V SID1132KQ

1.3
CG = 470 nF See Note 12
VGL is Referenced
Gate Sinking Peak to COM SID1182KQ 4 4.8 5.5
IGL A
Current GL Pin
RG = 0, CG = 47 nF SID1132KQ 2.6
See Notes 2, 12 SID1182KQ 7.8

SID1132KQ
4.8
Turn-On Internal I(GH) = -250 mA See Note 12
RGHI Ω
Gate Resistance VIN= 5 V
SID1182KQ 0.76 1.2

SID1132KQ
4
Turn-Off Internal I(GL) = 250 mA See Note 12
RGLI Ω
Gate Resistance VIN = 0 V
SID1182KQ 0.68 1.1

I(GH) = 6.6 mA SID1132KQ

Turn-On Gate VIN = 5 V, See Note 13 See Note 12
VGH(ON) V TOT-0.04 V
Output Voltage I(GH) = 20 mA
SID1182KQ
VIN = 5 V, See Note 13

I(GL) = -6.6 mA SID1132KQ

Turn-Off Gate VIN = 0 V See Note 12
Output Voltage VGL(OFF) 0.04 V
(Referred to COM Pin) I(GL) = -20 mA
SID1182KQ
VIN = 0 V

SO Output Voltage VSO(FAULT) Fault Condition, ISO = 3.4 mA, V VCC ≥ 3.9 V 210 450 mV

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Conditions
Parameter Symbol TJ = -40 °C to +125 °C Min Typ Max Units
See Note 1 (Unless Otherwise Specified)

Package Characteristics (See Notes 12, 14)

Distance Through the
DTI Minimum Internal Gap (Internal Clearance) 0.4 mm
Insulation

Minimum Air Gap Shortest Terminal-to-Terminal Distance

L1 (IO1) 9.5 mm
(Clearance) Through Air

Minimum External Shortest Terminal-to-Terminal Distance

L2 (IO2) 9.5 mm
Tracking (Creepage) Across the Package Surface

Tracking Resistance
DIN EN 60112 (VDE 0303-11): 2010-05
(Comparative Tracking CTI 600
EN / IEC 60112:2003 + A1:2009
Index)

Isolation Resistance, VIO = 500 V, TJ = 25 °C 1012

Input to Output R IO W
See Note 16 VIO = 500 V, 100 °C ≤ TJ ≤ TC(MAX) 1011

Isolation Capacitance,
Input to Output CIO 1 pF
See Note 16
Package Insulation Characteristics
Maximum Working
VIOWM 1000 VRMS
Isolation Voltage

Maximum Repetitive
VIORM 1414 VPEAK
Peak Isolation Voltage

Method A, After Environmental Tests

Subgroup 1, VPR = 1.6 × VIORM, t = 10 s 2263
(qualification) Partial Discharge < 5 pC

Method A, After Input/Output Safety Test

Input to Output
VPD Subgroup 2/3, VPR = 1.2 x VIORM, t = 10 s, 1697 VPEAK
Test Voltage
(qualification) Partial Discharge < 5 pC

Method B1, 100% Production Test,

VPR = 1.875 × VIORM, t = 1 s 2652
Partial Discharge < 5 pC

Maximum Transient V TEST = VIOTM, t = 60 s (qualification),

VIOTM 8000 VPEAK
Isolation Voltage t = 1 s (100% production)

Test Method Per IEC 60065, 1.2/50 μs

Maximum Surge
VIOSM Waveform, V TEST = 1.6 x VIOSM = 12800 V 8000 VPEAK
Isolation Voltage
(qualification)

Insulation Resistance RS VIO = 500 V at TS >109 W

Maximum Case
TS 150 °C
Temperature

Safety Total
PS TA = 25 °C 1.79 W
Dissipated Power

Pollution Degree 2

Climatic Classification 40/125/21

V TEST = VISO, t = 60 s (qualification),

Withstanding
VISO V TEST = 1.2 × VISO = 6000 VRMS, t = 1 s 5000 VRMS
Isolation Voltage
(100% production)

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2.0

PI-8178a-112717
1.8

Safe Operating Power (W)

1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 20 40 60 80 100 120 140 160

TC (°C)
Figure 15. Thermal Derating Curve Showing Dependence of Limited Dissipated Power on Case Temperature
(DIN V VDE V 0884-10).

Continuous device operating is allowed until TJ and/or TC of 125 °C are reached. Thermal stress beyond those values but below thermal derating
curve may lead to permanent functional product damage. Operating beyond thermal SR derating curve may affect product reliability.

NOTES:
1. V VCC = 5 V, V TOT = 25 V; GH and GL pins are shorted together. RG = 4 W, No CG; VCC pin is connected to the SO pin through a 2 kW resistor.
The VGXX pin is connected to the GH pin through a 10 nF capacitor. Typical values are defined at TA = 25 °C; fS = 20 kHz, Duty Cycle = 50%.
Positive currents are assumed to be flowing into pins.
2. Pulse width ≤ 10 ms, duty cycle ≤ 1%. The maximum value is controlled by the ASIC to a safe level. There is no need to limit the current by
the application. The internal peak power is safely controlled for RG ≥ 0 and power semiconductor module input gate capacitance CIES ≤ 47 nF.
3. During very slow V VCC power-up and power-down related to V TOT, V VCC and V VEE respectively, several SO fault pulses may be generated.
4. SO pin connected to GND as long as V VCC stays below minimum value. No signal transferred from primary to secondary-side.
5. VIN potential changes from 0 V to 5 V within 10 ns. Delay is measured from 50% voltage increase on IN pin to 10% voltage increase
on GH pin.
6. VIN potential changes from 5 V to 0 V within 10 ns. Delay is measured from 50% voltage decrease on IN pin to 10% voltage decrease
on GL pin.
7. Measured from 10% to 90% of VGE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.
8. Measured from 90% to 10% of VGE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.
9. ASSD function limits G-E voltage of controlled semiconductor in specified time. Conditions: CG = 10 nF, V TOT = V VISO = 15 V,
V VEE = 0 V (VEE shorted to COM).
10. The amount of time needed to transfer fault event (UVLO or DESAT) from secondary-side to SO pin.
11. The amount of time after primary and secondary-side supply voltages (V VCC and V TOT) reach minimal required level for driver proper
operation. No signal is transferred from primary to secondary-side during that time, and no fault condition will be transferred from the
secondary-side to the primary-side.
12. Guaranteed by design.

13. Positive current is flowing out of the pin.

14. Safety distances are application dependent and the creepage and clearance requirements should follow specific equipment isolation stan-
dards of an application. Board design should ensure that the soldering pads of an IC maintain required safety relevant distances.
15. Measured accordingly to IEC 61000-4-8 (fS = 50 Hz, and 60 Hz) and IEC 61000-4-9.
16. All pins on each side of the barrier tied together creating a two-terminal device.

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Typical Performance Characteristics

20 11.0

PI-7915-110716
PI-7917-050416
IN = 0 V DC
19 10.5

Supply Current IVISO (mA)

IN = 5 V DC
Supply Current IVCC (mA)

18 fS = 20 kHz 10.0
fS = 75 kHz
17 9.5
IN = 0 V DC
16 9.0 IN = 5 V DC
fS = 20 kHz
15 8.5 fS = 75 kHz
14 8.0
13 7.5
12 7.0
11 6.5
10 6.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140

Ambient Temperature (°C) Ambient Temperature (°C)

Figure 16. Supply Current Primary-Side I VCC vs. Ambient Temperature. Figure 17. Supply Current Secondary-Side I VISO vs. Ambient Temperature.
Conditions: V VCC = 5 V, V TOT = 25 V, No-Load. Conditions: V VCC = 5 V, V TOT = 25 V, No-Load.

3.60 3.50
PI-7928-110716

PI-7948-050416
IVEE(SO) Source Capability (mA)

VTOT = 22 V and VVISO = 17.5 V VTOT = 22 V and VVISO = 12.5 V

IVEE(SI) Sink Capability (mA)

3.55 3.45
VTOT = 25 V and VVISO = 17.5 V VTOT = 25 V and VVISO = 12.5 V
3.50 VTOT = 28 V and VVISO = 17.5 V 3.40 VTOT = 28 V and VVISO = 12.5 V

3.45 3.35
3.40 3.30
3.35 3.25
3.30 3.20
3.25 3.15
3.20 3.10
3.15 3.05
3.10 3.00
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140

Ambient Temperature (°C) Ambient Temperature (°C)

Figure 18. VEE Source Capability I VEE(SO) vs. Ambient Temperature and V VISO. Figure 19. VEE Sink Capability I VEE(SI) vs. Ambient Temperature and V VISO.
Conditions: V VCC = 5 V, fS = 20 kHz, Duty Cycle = 50%. Conditions: V VCC = 5 V, fS = 20 kHz, Duty Cycle = 50%.

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 SID11x2KQ

eSOP-R16B

2X 0.004 [0.10] C A
3 4 0.057 [1.45] Ref.
0.023 [0.58] 13X
0.050 [1.27]
0.018 [0.46] 2
0.010 [0.25] M C A B A 0.400 [10.16]
H
8 Lead Tips
16 9 0.006 [0.15] C 9 10 11 12 13 14 15 16
2X 0.010 [0.25]
0.004 [0.10] C B
Gauge Plane

Seating Plane
0.059 [1.50] 0° - 8° C
2 Ref. Typ. 0.040 [1.02]
0.350 [8.89] 0.464 [11.79] 0.028 [0.71]
0.059 [1.50]
Ref. Typ.
DETAIL A

B 0.020 [0.51]
1 8 0.006 [0.15] C 8 7 6 5 4 3 1
Ref. 0.022 [0.56] Ref.
4 Lead Tips 0.010 [0.24]
3 4 0.019 [0.48]
Ref.
Pin #1 I.D. 0.158 [4.01] Ref.
(Laser Marked) 0.045 [1.14] Ref. 0.152 [3.86]
0.080 [2.03] Ref.
0.032 [0.81]
0.028 [0.71] 0.029 [0.74]
Ref.
TOP VIEW BOTTOM VIEW

0.010 [0.25] Ref.

0.356 [9.04]Ref. Detail A

0.306 [7.77] Ref.
7 0.049 [1.23] .028 [0.71] .050 [1.27]
0.105 [2.67] 0.046 [1.16]
0.093 [2.36] 3
0.016 [0.41]
0.011 [0.28]
12X
Seating
C
Plane .070 [1.78]
0.012 [0.30] 0.092 [2.34] .460 [11.68]
0.004 [0.10] 0.086 [2.18]
0.004 [0.10] C
Seating Plane to 12 Leads
Molded Bumps Reference
Standoff Solder Pad
Dimensions
SIDE VIEW END VIEW
.162 [4.11]
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994. .165 [4.19]
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs, and inter-lead flash, but including any mismatch between the top .300 [7.62]
and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. INCH [mm]
.350 [8.89]
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined in Datum H.
7. Exposed metal at the plastic package body outline/surface between leads 6 and 7, connected PI-6995-051716
internally to wide lead 3/4/5/6. POD-eSOP-R16B Rev B

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 SID11x2KQ

MSL Table
Part Number MSL Rating
SID11x2KQ 3

ESD and Latch-Up Table

Test Conditions Results
Latch-up at 125 °C AEC-Q100-002 > ±100 mA or > 1.5 × VMAX on all pins
Human Body Model ESD AEC-Q100-002 > ±2000 V on all pins
Charged Device Model ESD AEC-Q100-011 > ±500 V on all pins

IEC 60664-1 Rating Table

Parameter Conditions Specifications

Basic Isolation Group Material Group I
Rated mains voltage ≤ 150 VRMS I - IV
Rated mains voltage ≤ 300 VRMS I - IV
Installation Classification
Rated mains voltage ≤ 600 VRMS I - IV
Rated mains voltage ≤ 1000 VRMS I - III

Electrical Characteristics (EMI) Table

Parameter Symbol Conditions Min Typ Max Units
Common-Mode Typical values measured according to Figures
Transient Immunity, CMH 33, 34. Maximum values are design values -35 / 50 -100 / 100 kV/ms
Logic High assuming trapezoid waveforms

Common-Mode Typical values measured according to Figures

Transient Immunity, CML 33, 34. Maximum values are design values -35 / 50 -100 / 100 kV/ms
Logic Low assuming trapezoid waveforms

Variable Magnetic Field HHPEAK See Note 15 1000

A/m
Immunity HLPEAK See Note 15 1000

Figure 20. Applied Common Mode Pulses for Generating Negative dv/dt. Figure 21. Applied Common Mode Pulses for Generating Positive dv/dt.

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Regulatory Information Table

VDE UL CSA

Certification to DIN V VDE V 0884-10 UR recognized under UL1577 Component UR recognized to CSA Component Acceptance
(VDE V 0884-10): 2006-12 pending Recognition Program Notice 5A

Reinforced insulation for Max. Transient

Isolation voltage 8 kVPEAK, Max. Surge Single protection, 5000 VRMS dielectric voltage Single protection, 5000 VRMS dielectric voltage
Isolation voltage 8 kVPEAK, Max. Repetitive withstand withstand
Peak Isolation voltage 1414 VPEAK

File No. pending File E358471 File E358471

Part Ordering Information

• SCALE-iDriver Product Family
• Series Number
• Package Identifier
K eSOP-R16B
• Q Automotive / Blank Industry
• Tape & Reel and Other Options
Blank Tube of 48 pcs.
SID 11x2 K Q - TL TL Tape & Reel, 1000 pcs min/mult.

21
www.power.com Rev. A 03/18
 Revision Notes Date
A Code A initial release. 03/18

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE, SCALE-iDriver, SCALE-iFlex, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch,
InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI
FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2018, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters Germany (AC-DC/LED Sales) Italy Singapore

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Japan
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e-mail: [email protected] e-mail: [email protected]