8255 Microprocessor

8255
Salient Features
1) It is a programmable general-purpose I/O device.
2) It has 3 8-bit bi-directional I/O ports: Port A, Port B, and Port C.
3) It provides 3 modes of data transfer: Simple I/O, Handshake I/O and Bi-directional
Handshake.
4) Additionally it also provides a Bit Set Reset Modes to alter individual bits of Port C.
ARCHITECTURE OF 8255
The architecture of 8255 can be divided into the following parts:

1) Data Bus Buffer: This is a 8-bit bi-directional buffer used to interface the internal data bus
of 8255 with the external (system) data bus. The CPU transfers data to and from the 8255
through this buffer.
2) Read/Write Control Logic: It accepts address and control signals from the µP. The Control
signals determine whether it is a read or a write operation and also select or reset the 8255
chip.
The Address bits (A1, A0) are used to select the Ports or the Control Word Register as shown:
3) Group A Control:
This Control block controls Port A and Port CUpper i.e. PC7-PC4. It accepts Control signals
from the Control Word and forwards them to the respective Ports.
4) Group B Control:
This Control block controls Port B and Port CLower i.e. PC3-PC0. It accepts Control signals
from the Control Word and forwards them to the respective Ports.
5) Port A, Port B, Port C:
These are 8-bit Bi-directional Ports. They can be programmed to work in the various modes
as follows:
Control Word of 8255 - I/O Mode (I/O Command)
To do 8-bit data transfer using the Ports A, B or C, 8255 needs to be in the IO mode. The bit
pattern for the control word in the IO mode is as follows:
Control Word of 8255 - BSR Mode (BSR Command)

The BSR Mode is used ONLY for Port C.
In this Mode the individual bits of Port C can be set or reset.
This is very useful as it provides 8 individually controllable lines which can be used while
interfacing with devices like an A to D Converter or a 7-segment display etc.
The individual bit is selected and Set/reset through the control word. Since the D7 bit of the
Control Word is 0, the BSR operation will not affect the I/O operations of 8255.
DATA TRANSFER MODES OF 8255

Mode 0 (Simple Bi-directional I/O)
Port A and Port B used as 2 Simple 8-bit I/O Ports.
Port C is used as 2 simple 4-bit I/O Ports.
Each port can be programmed as input or output individually.
Ports do not have handshake or interrupting capability. Hence, slower devices cannot be
interfaced.
Mode 1 (Handshake I/O)
In Mode 1, handshake signals are exchanged between the devices before the data transfer
takes place. Port A and Port B used as 2 8-bit I/O Ports that can programmed in Input OR in
output mode.
Each Port uses 3 lines from Port C for handshake.
The remaining lines of Port C can be used for simple IO.
Interrupt driven data transfer and Status driven data transfer possible. Hence, slower
devices can be interfaced.
Timing Diagram for Mode 1 Input Transfer (Refer text book)

Handshaking takes place in the following manner:
1) The peripheral device places data on the Port bus and informs the Port by making STB
low.
2) The input Port accepts the data and informs the peripheral to wait by making IBF high.
This prevents the peripheral from sending more data to the 8255 and hence data loss is
prevented.
3) 8255 interrupts the µP through the INTR line provided the INTE flip-flop is set.
4) In response to the Interrupt, the µP issues the RD signal and reads the data. The data byte
is thus transferred to the µP.
5) Now, the IBF signal goes low and the peripheral can send more data in the above sequence.
Timing Diagram for Mode 1 Output Transfer (Refer text book)

Each port uses 3 lines of Port C for the following signals: OBF (Output Buffer Full), ACK
(Acknowledgement) 🡪Handshake signals INTR (interrupt) -🡪Interrupt signal.
Additionally the WR signal of 8255 is also used.
Handshaking takes place in the following manner:
1) When the output port is empty (indicated by a high on the INTR line), the µP writes data
on the output port by giving the WR(active low) signal.
2) As soon as the WR operation is complete, the 8255 makes the INTR low, indicating that
the µP should wait. This prevents the µP from sending more data to the 8255 and hence data
loss is prevented.
3) 8255 also makes the OBF(active low) low to indicate to the output peripheral that data is
available on the data bus.
4) The peripheral accepts the data and sends an acknowledgement by making the ACK(active
low signal) low. The data byte is thus transferred to the peripheral.
5) Now, the OBF and ACK lines go high.
6) The INTR line becomes high to inform the µP that another byte can be sent. i.e. the output
port is empty. This process is repeated for further bytes.
INTERFACING OF 8255 WITH 8086

1) 8255 is a programmable peripheral interface. It is used to interface microprocessor with
I/O devices via three ports: PA, PB, PC. All ports are 8-bit and bidirectional.
2) 8255 transfers data with the microprocessor through its 8-bit data bus.
3) The two address lines A1 and A0 are used to make internal selection in 8255. They can
have 4 options, selecting PA, PB, PC or the control word. The ports are selected to transfer
data. The Control word is selected to send commands.
4) Two commands can be sent to 8255, called the I/O command and the BSR command. I/O
command is used to initialize the mode and direction of the ports. BSR command is used to
set or reset a single line of Port C.
5) 8255 has three operational modes of data transfer.
6) Mode 0 is a simple data transfer mode. It does not perform handshaking but all three ports
are available for data transfer.
7) Mode 1 performs unidirectional handshaking. That makes transfers more reliable. Port C
lines are used by Port A and Port B to perform Handshaking.
8) Mode 2 performs bidirectional handshaking. Only Port A can operate in Mode 2. At that
time Port B can operate in Mode 1 or Mode 0. Port C lines are again used up for performing
Handshaking for Port A and Port B.

8255 Microprocessor

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8255

The architecture of 8255 can be divided into the following parts:

Control Word of 8255 - BSR Mode (BSR Command)

DATA TRANSFER MODES OF 8255

Timing Diagram for Mode 1 Input Transfer (Refer text book)

Timing Diagram for Mode 1 Output Transfer (Refer text book)

INTERFACING OF 8255 WITH 8086

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