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Sr. No. List of Experiment

This document provides a list of 10 experiments for the Digital System Design subject in the Electronics Engineering department at G.H. Raisoni College of Engineering, Nagpur, for the 2011-12 session. The experiments include designing logic gates, a 4:1 multiplexer, an arithmetic logic unit, a BCD to 7-segment decoder, half and full adders, a 4-to-16 decoder, flip-flops, a 3-bit up-down counter, a 4-bit barrel shifter, and a finite state machine to detect the sequence "1011" using a Mealy model.

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pankaj rangaree
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40 views1 page

Sr. No. List of Experiment

This document provides a list of 10 experiments for the Digital System Design subject in the Electronics Engineering department at G.H. Raisoni College of Engineering, Nagpur, for the 2011-12 session. The experiments include designing logic gates, a 4:1 multiplexer, an arithmetic logic unit, a BCD to 7-segment decoder, half and full adders, a 4-to-16 decoder, flip-flops, a 3-bit up-down counter, a 4-bit barrel shifter, and a finite state machine to detect the sequence "1011" using a Mealy model.

Uploaded by

pankaj rangaree
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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G.H.

RAISONI COLLEGE OF ENGINEERING, NAGPUR

(An Autonomous Institute under UGC Act 1956)

DEPARTMENT OF ELECTRONICS ENGINEERING

Session :-2011-12

Name of Laboratory :- VLSI LAB (E-28)


Class & Branch :-VIII Sem. ETRX- A/B
Subject :-Digital System Design
Branch :-Electronics
Sr. No. List of Experiment
1 Write a VHDL code for different logic gates.
2 Design 4:1 multiplexer and write a VHDL code for same using data flow
style of modeling.
3 Design Arithmatic and Logic Unit.
4 Design BCD to seven segment decoder.
5 Design half adder and full adder and write a VHDL code for same using
dataflow style of modeling.
6 Design 4-to-16 decoder by combining two 3-to-8 decoders and write a
VHDL code for same using structural style of modelling.
7 Design of Flip-Flop and write a VHDL code for same using behavioural
style of modelling.
8 Design three- bit up-down counter and write a VHDL code for the same
using structural style of modelling. Implementation on FPGA .
9 Design 4 bit Barrel shifter and write a VHDL code for the same.
10 Design of Finite state machine to detect a sequence “1011”using Mealy
model and write VHDL code for the same.

Prof. P. H. Rangaree

Prof. Bharati B. Sayankar

Prof. P. P. Rane Prof. A. D. Tete Dr. A. Y. Deshmukh

Prof. P.L. Hirulkar Laboratory In-charge Head, ETRX Department

Subject Teachers

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