9 ROM, EPROM, AND EEPROM TECHNOLOGY

OVERVIEW

Read only memory devices are a special case of memory where, in normal system operation, the
memory is read but not changed. Read only memories are non-volatile, that is, stored informa-
tion is retained when the power is removed. The main read only memory devices are listed below:

ROM (Mask Programmable ROM—also called “MROMs”)

EPROM (UV Erasable Programmable ROM)
OTP (One Time Programmable EPROM)
EEPROM (Electrically Erasable and Programmable ROM)
Flash Memory - This device is covered in Section 10.

HOW THE DEVICE WORKS

The read only memory cell usually Column

consists of a single transistor (ROM
and EPROM cells consist of one
transistor, EEPROM cells consist of
one, one-and-a-half, or two transis-
tors). The threshold voltage of the Row

transistor determines whether it is a

“1” or “0.” During the read cycle, a
Cell
voltage is placed on the gate of the Selected
cell. Depending on the programmed
threshold voltage, the transistor will
Sense Amplifier
or will not drive a current. The Current Detector
sense amplifier will transform this
To Output Buffer
current, or lack of current, into a “1”
or “0.” Figure 9-1 shows the basic Source: ICE, "Memory 1997" 19956

principle of how a Read Only

Figure 9-1. Read Only Memory Schematic
Memory works.

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MASK PROGRAMMABLE ROMs

Mask programmable read-only memories (ROMs) are the least expensive type of solid state
memory. They are primarily used for storing video game software and fixed data for electronic
equipment, such as fonts for laser printers, dictionary data in word processors, and sound data in
electronic musical instruments.

ROM programming is performed during IC fabrication. Several process methods can be used to
program a ROM. These include

• Metal contact to connect a transistor to the bit line.

• Channel implant to create either an enhancement-mode transistor or a depletion-mode
transistor.
• Thin or thick gate oxide, which creates either a standard transistor or a high threshold
transistor, respectively.

The choice of these is a trade-off between process complexity, chip size, and manufacturing cycle
time. A ROM programmed at the metal contact level will have the shortest manufacturing cycle
time, as metallization is one of the last process steps. However, the size of the cell will be larger.

Figure 9-2 shows a ROM array programmed by channel implant. The transistor cell will have
either a normal threshold (enhancement-mode device) or a very high threshold (higher than VCC
to assure the transistor will always be off). The cell array architecture is NOR. The different types
of ROM architectures (NOR, NAND, etc.) are detailed in the flash memory section (Section 10) as
they use the same principle.

Figure 9-3 shows an array of storage cells (NAND architecture). This array consists of single tran-
sistors noted as devices 1 through 8 and 11 through 18 that is programmed with either a normal
threshold (enhancement-mode device) or a negative threshold (depletion-mode device).

ROM Cell Size and Die Size

The cell size for the ROM is potentially the smallest of any type of memory device, as it is a single
transistor. A typical 8Mbit ROM would have a cell size of about 4.5µm2 for a 0.7µm feature size
process, and a chip area of about 76mm2. An announced 64Mbit ROM, manufactured with a
0.6µm feature size, has a 1.23µm2 cell on a 200mm2 die.

The ROM process is the simplest of all memory processes, usually requiring only one layer of
polysilicon and one layer of metal. There are no special film deposition or etch requirements, so
yields are the highest among all the equivalent-density memory chips.

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 ROM, EPROM, & EEPROM Technology

Ground Diffusion
Selective
Implant
To Raise
VT
ROW 1 (Polysilicon) ROW 1

T3 T4
Drain
Contacts: T4 T3
Shared By
2 Bits
Drain Diffusion
ROW 2
ROW 2 (Polysilicon)

T1 T2 T1 T2

Ground

Metal Columns
(Not Drawn)

Source: ICE, "Memory 1997" 20845

Figure 9-2. ROM Programmed by Channel Implant

1
WORD 1/11 11

2
WORD 2/12 12
3
WORD 3/13 13
4
WORD 4/14 14
5
WORD 5/15 15

6
WORD 6/16 16

7
WORD 7/17 17

8
WORD 8/18 18

9
CONTROL LINE 19

10
SELECT LINE 20
BIT LINE

Source: ICE, "Memory 1997" 19050

Figure 9-3. Memory Cell Schematic

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Multimedia Card

In 1996, Siemens announced the introduction of a new solid-state memory chip technology that
enables the creation of a multimedia card that is sized 37mm x 45mm x 1.4mm, or roughly 40 per-
cent the size of a credit card. It is offered with either 16Mbit or 64Mbit of ROM.

EPROM

EPROM (UV Erasable Programmable Read Only Memory) is a special type of ROM that is pro-
grammed electrically and yet is erasable under UV light.

The EPROM device is programmed by forcing an electrical charge on a small piece of polysilicon
material (called the floating gate) located in the memory cell. When this charge is present on this
gate, the cell is “programmed,” usually a logic “0,” and when this charge is not present, it is a logic
“1.” Figure 9-4 shows the cell used in a typical EPROM. The floating gate is where the electrical
charge is stored.

First-Level
Polysilicon +VG Second-Level
(Floating) Polysilicon

Gate Oxide

Field Oxide

– – –
N+

P- Substrate

Source: Intel/ICE, "Memory 1997" 18474

Figure 9-4. Double-Poly Structure (EPROM/Flash Memory Cell)

Prior to being programmed, an EPROM has to be erased. To erase the EPROM, it is exposed to an
ultraviolet light for approximately 20 minutes through a quartz window in its ceramic package.
After erasure, new information can be programmed to the EPROM. After writing the data to the
EPROM, an opaque label has to be placed over the quartz window to prevent accidental erasure.

Programming is accomplished through a phenomenon called hot electron injection. High voltages
are applied to the select gate and drain connections of the cell transistor. The select gate of the
transistor is pulsed “on” causing a large drain current to flow. The large bias voltage on the gate
connection attracts electrons that penetrate the thin gate oxide and are stored on the floating gate.

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 ROM, EPROM, & EEPROM Technology

EPROM Floating Gate Transistor Characteristic Theory

The following explanation of EPROM floating gate transistor characteristic theory also applies to
EEPROM and flash devices. Figures 9-5 (a) and (b) show the cross section of a conventional MOS
transistor and a floating gate transistor, respectively. The upper gate in Figure 9-5 (b) is the con-
trol gate and the lower gate, completely isolated within the gate oxide, is the floating gate.

Control
Gate G
Floating
Control
Gate
Gate
G

S D S D
CFG

CFS
N+ N+ N+ N+

(a) Conventional MOS (b) Floating-Gate MOS

Source: ICE, "Memory 1997" 20846

Figure 9-5. Cross Section of a Conventional MOS Transistor and a Floating-Gate MOS Transistor

CFG and CFS are the capacitances between the floating gate and the control gate and substrate,
respectively. VG and VF are the voltages of the control gate and the floating gate, respectively.
-QF is the charge in the floating gate. (As electrons have a negative charge, a negative sign was
added). In an equilibrium state, the sum of the charges equals zero.

(VG − VF ) CFG + (0 − VF ) CFS − Q F = 0

 C FG  QF
VF   VG −
 C FG + C FS  C FG + C FS

VTC is the threshold voltage of the conventional transistor, and VTCG is the threshold voltage of
the floating gate transistor.

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ROM, EPROM, & EEPROM Technology

 C FG  QF
VTCG =   VTC −
 C FG + C FS  C FG + C FS

QF
VTCG = VTO −
CG

 C FG 
Where VTO =   VTC and C G = C FG + C FS
 C FG + C FS 

The threshold voltage of the floating gate transistor (VTCG) will be VTO (around 1V) plus a term
depending on the charge trapped in the floating gate. If no electrons are in the floating gate, then
VTCG = VTO (around 1V). If electrons have been trapped in the floating gate, then VTCG = VTO
-QF/CG (around 8V for a 5V part). This voltage is process and design dependent. Figure 9-6
shows the threshold voltage shift of an EPROM cell before and after programming.

–QF
VT =
CG

Erased State Programmed State

(Logic "1") (Logic "0")
Drain Current

–QF Select Gate

VT0 VT0 Voltage
Sense CG
Threshold
Source: ICE, "Memory 1997" 17548A

Figure 9-6. Electrical Characteristics of an EPROM

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 ROM, EPROM, & EEPROM Technology

The programming (write cycle) of an EPROM takes several hundred milliseconds. Usually a
byte—eight bits—is addressed with each write cycle. The read time is comparable to that of fast
ROMs and DRAMs (i.e., several tens of nanoseconds). In those applications where programs are
stored in EPROMs, the CPU can run at normal speeds.

Field programmability is the EPROM’s main advantage over the ROM. It allows the user to buy
mass-produced devices and program each device for a specific need. This characteristic also
makes the EPROM ideal for small-volume applications, as the devices are usually programmed in
very small quantities. Also, the systems supplier can program any last minute upgrades to the
program just before shipment. EPROM cells may be configured in the NAND structure shown
previously, or, more commonly, in the NOR configuration shown in Figure 9-7.

WORD WORD WORD WORD

1 2 3 n

BIT 1

BIT 2

Select Gate

Floating Gate
Source: ICE, "Memory 1997" 19051

Figure 9-7. NOR EPROM Configuration

EPROMs were created in the 1970s and have long been the cornerstone of the non-volatile
memory market. But the development of flash memory devices (see Section 10) will lead to a loss
of EPROM marketshare. EPROM uses a mature technology and design and is on the decline part
of its lifecycle. For this reason there is not a lot of R&D expenditure made for EPROM devices.
Figure 9-8 shows a cross section of a 1Mbit EPROM cell from two different manufacturers. The
main difference between the processes is the polysilicon gate. One manufacturer uses a polycide
to improve the speed.

EPROM Cell Size and Die Size

The cell size of the EPROM is also relatively small. The EPROM requires one additional polysili-
con layer, and will usually have slightly lower yields due to the requirement for nearly perfect
(and thin) gate oxides.

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Source: ICE, “Memory 1997” 22462

Figure 9-8. Typical 1Mbit EPROM Cells

These factors, plus the fact that an EPROM is encased in a ceramic package with a quartz window,
make the EPROM average selling price three to five times the price of the mask ROM. Figure 9-9
shows the main feature sizes of 1Mbit EPROM analyzed by ICEÕs laboratory.

Cell Size Die Size Min. Gate

Manufacturer Density Date Code
(µm2) (mm2) Length (µm)

Atmel 1Mbit 9428 4.40 14.6 0.6

AMD 1Mbit 9634 5.52 15.9 0.7

ST 1Mbit 9514 3.60 11.5 0.5

ISSI 1Mbit 94/95 6.80 18.0 0.7

Source: ICE, "Memory 1997" 22453

Figure 9-9. EPROM Feature Sizes

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OTP (One Time Programmable) EPROM

In most applications, EPROMs are programmed one time and will never have to be erased. To
reduce the cost for these applications, EPROMs may be manufactured in opaque plastic packages
since the standard ceramic package of an EPROM is expensive. EPROMs that are programmed one
time for a specific use and cannot be erased are referred to as One Time Programmable (OTP) devices.

EEPROM

EEPROM (Electrically Erasable Programmable ROM) offer users excellent capabilities and per-
formance. Only one external power supply is required since the high voltage for
program/erase is internally generated. Write and erase operations are performed on a byte per
byte basis.

The EEPROM uses the same principle as the UV-EPROM. Electrons trapped in a floating gate will
modify the characteristics of the cell, and so a logic “0” or a logic “1” will be stored.

The EEPROM is the memory device that implements the fewest standards in cell design. The
more common cell is composed of two transistors. The storage transistor has a floating gate (sim-
ilar to the EPROM storage transistor) that will trap electrons. In addition, there is an access tran-
sistor, which is required for operations. Figure 9-10 shows the voltages applied on the memory
cell to program/erase a cell. Note that an EPROM cell is erased when electrons are removed from
the floating gate and that the EEPROM cell is erased when the electrons are trapped in the float-
ing cell. To have products electrically compatible, the logic path of both types of product will give
a “1” for erase state and a “0” for a programmed state. Figure 9-11 shows the electrical differences
between EPROM and EEPROM cells.

Parallel EEPROM

There are two distinct EEPROM families: serial and parallel access. The serial access represents
90 percent of the overall EEPROM market, and parallel EEPROMs about 10 percent. Parallel
devices are available in higher densities (≥256Kbit), are generally faster, offer high endurance and
reliability, and are found mostly in the military market. They are pin compatible with EPROMs
and flash memory devices. Figure 9-12 shows feature sizes of three 1Mbit parallel EEPROM from
different manufacturers, analyzed by ICE’s laboratory. Figures 9-13 to 9-15 show photographs
and schematics of the respective cells. It is interesting to see the wide differences in these cells.

Serial EEPROM

Serial EEPROMs are less dense (typically from 256 bit to 256Kbit) and are slower than parallel
devices. They are much cheaper and used in more “commodity” applications.

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CL 0V CL 0V

SG 20V

CG 0V

S S

Erase Program
CL

SG CL CG S

SG Erase VPP 0 VPP 0

PP PP

Program VPP VPP

PP 0 0

CG Read VCC 1 VCC 0

Unselected 0 X 0 0

S
Source: ICE, "Memory 1997" 17554A

Figure 9-10. EEPROM Cell Program/Erase

EPROM programming: Hot electron

• High VPP Current
• High ISUB
• VPP must be an external supply
• No VBB generator

EEPROM programming: Tunneling

• VPP is generated by an internal pump.
Source: ICE, "Memory 1997" 17556

Figure 9-11. VPP EPROM Versus VPP EEPROM

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Cell Size Die Size Min Gate

Manufacturer Density Date Code
(µm2) (mm2) Length (µm)

Winbond 1Mbit 9432 7.8 22.6 0.9

Xicor 1Mbit 9443 21.0 51.0 1.3

Hitachi 1Mbit 94/95 22.5 51.0 0.6

Source: ICE, "Memory 1997" 22463

Figure 9-12. 1Mbit Parallel EEPROM Feature Sizes

ALUMINUM
CAP

BARRIER
PRE-METAL GLASS

POLY 2

N+
POLY 1

Source: ICE, “Memory 1997” 22468

Figure 9-13. Winbond 1Mbit EEPROM Cell

Serial access EEPROMs feature low pin count. Typically they are packaged in an 8-pin package. As
illustrated in Figure 9-16, XicorÕs 128Kbit serial EEPROM uses the 8 pins in the following manner:

¥ VCC and VSS for supply voltage

¥ SCL (Serial Clock) to clock the data
¥ SDA (Serial Data) is a bi-directional pin used to transfer data into and out of the device
¥ S0, S1, S2 are select inputs used to set the first three bits of the 8-bit slave address
¥ WP (Write Protection) controls Write Protection features.

Serial EEPROMs use data transfer interface protocols for embedded control applications. These
protocols include the Microwave bus, the I2C bus, the XI2C (Extended I2C) or the SPI (Serial
Peripheral Interface) bus interfaces.

There continues to be an ongoing effort to reduce the size of serial EEPROMs. Microchip
Technology, for example, introduced a 128bit serial EEPROM in a five-lead SOT-23 package.

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POLY 1
PROGRAM LINE

POLY 2
WORD
LINE

BIT Q2

Q1

144424443
FLOATING GATE

PASSIVATION

METAL 2

INTERLEVEL GLASS

METAL 1 BIT LINE

FLOATING GATES
PROGRAM LINE
SELECT GATE N+ S/D

Source: ICE, “Memory 1997” 22470

Figure 9-14. Xicor 1Mbit EEPROM Cell

METAL POLYCIDE

POLY

Silicon Nitride
Source: ICE, “Memory 1997” 22467

Figure 9-15. Hitachi 1Mbit EEPROM Cell

Figure 9-17 shows feature sizes of three serial EEPROMs from different manufacturers that were
analyzed by ICEÕs laboratory. Note that larger cell sizes accompany low-density EEPROM
devices. When building an EEPROM chip that contains sense amplifiers, controllers, and other
peripheral circuitry, cell size is not as great a factor at low (1Kbit, 2Kbit) densities. At larger den-
sities, the size of the cell array is more critical. It becomes a larger portion of the chip. Therefore,
greater consideration must be given to the size of the cell.

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WP
Start Cycle H.V. Generation
Timing and
Control
VCC
VSS

SDA Start Write Protect

Stop Register and
Logic Logic

Control
Logic
Slave Address
Register EEPROM
SCL +Comparator Load Inc XDEC
Array

Word
S2 Address
Counter
S1
S0
R/W YDEC

8
CK DOUT
Data Register

DOUT
ACK
Source: Xicor/ICE, "Memory 1997" 22599

Figure 9-16. Xicor 128Kbit Serial EEPROM Functional Diagram

Cell Size Die Size Min Gate

Manufacturer Density Date Code
(µm2) (mm2) Length (µm)

Microchip 16K 9540 60.5 6.0 2.0

Xicor 2K 9432 100.0 4.0 2.0

ST 1K 9618 286.0 2.6 1.2

Source: ICE, "Memory 1997" 22464

Figure 9-17. EEPROM Serial Configuration Feature Sizes

This size impact is illustrated in Figure 9-18 using a 1Kbit serial EEPROM example from SGS-
Thomson. The cell array represents only 11 percent of the total surface of the chip.

Figures 9-19 and 9-20 show additional EEPROM cells. As noted, there is no design standard for
this type of cell. In laying out the EEPROM cell, the designer must take into consideration the ele-
ments of size, performance, and process complexity.

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CELL ARRAY

WL

D
2

1
PIN 1

2 BIT B

3
C

1 BIT A

TUNNEL
OXIDE DEVICE

Source: ICE, “Memory 1997” 22465

Figure 9-18. SGS-Thomson 1Kbit Serial EEPROM

PASSIVATION

BIT LINE
REFLOW GLASS
POLY 2 PGM LINE
POLY 2 WORD LINE

N+ S/D
POLY 1 FLOATING GATE

Source: ICE, “Memory 1997” 22466

Figure 9-19. Microchip 16Kbit Serial EEPROM Cell

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METAL BIT LINE

PRE-METAL GLASS

POLY 2 FLOATING GATE

POLY 3 POLY 1
WORD LINE GND/PROGRAM
CATHODE

Source: ICE, “Memory 1997” 22469

Figure 9-20. Xicor 2Kbit Serial EEPROM Cell

Multi-Level Analog Storage EEPROM

The goal of multi-level cell (MLC) is to store more than one bit of information in a single cell.
Much work has already been done regarding MLC as applied to flash memory devices. The typ-
ical development for digital flash memories is to store four different levels in the same cell, and
thus divide the number of cells by two (four data are given by two bits : 00, 01, 10, and 11).

However, for several years now, Information Storage Devices (ISD), a San Jose based company,
has proposed multi-level analog storage EEPROMs for analog storage. ISD presented a 480Kbit
EEPROM at the 1996 ISSCC conference. The multi-level storage cell is able to store 256 different
levels of charge between 0V and 2V. This means the cell needs to have a 7.5mV resolution. The
256 different levels in one cell corresponds to eight bits of information. A comparable digital
implementation requires 3.84Mbit memory elements to store the same amount of information.
The information stored will not be 100 percent accurate but is good enough for audio applications,
which allows some errors.

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Introduction to Flash Memory
ROBERTO BEZ, EMILIO CAMERLENGHI, ALBERTO MODELLI, AND ANGELO VISCONTI

Invited Paper

The most relevant phenomenon of this past decade in the field to allow cell scaling below the 65-nm node is the tunnel oxide
of semiconductor memories has been the explosive growth of the thickness reduction, as tunnel thinning is limited by intrinsic and
Flash memory market, driven by cellular phones and other types extrinsic mechanisms.
of electronic portable equipment (palm top, mobile PC, mp3 audio
player, digital camera, and so on). Moreover, in the coming years, Keywords—Flash evolution, Flash memory, Flash technology,
portable systems will demand even more nonvolatile memories, ei- floating-gate MOSFET, multilevel, nonvolatile memory, NOR cell,
ther with high density and very high writing throughput for data scaling.
storage application or with fast random access for code execution
in place. The strong consolidated know-how (more than ten years of
experience), the flexibility, and the cost make the Flash memory a I. INTRODUCTION
largely utilized, well-consolidated, and mature technology for most
of the nonvolatile memory applications. Today, Flash sales repre- The semiconductor market, for the long term, has been
sent a considerable amount of the overall semiconductor market. continuously increasing, even if with some valleys and
Although in the past different types of Flash cells and architec- peaks, and this growing trend is expected to continue in the
tures have been proposed, today two of them can be considered as coming years (see Fig. 1). A large amount of this market,
industry standard: the common ground NOR Flash, that due to its
about 20%, is given by the semiconductor memories, which
versatility is addressing both the code and data storage segments,
and the NAND Flash, optimized for the data storage market. are divided into the following two branches, both based on
This paper will mainly focus on the development of the NOR Flash the complementary metal–oxide–semiconductor (CMOS)
memory technology, with the aim of describing both the basic func- technology (see Fig. 2).
tionality of the memory cell used so far and the main cell architec-
ture consolidated today. The NOR cell is basically a floating-gate – The volatile memories, like SRAM or DRAM, that
MOS transistor, programmed by channel hot electron and erased although very fast in writing and reading (SRAM)
by Fowler–Nordheim tunneling. The main reliability issues, such as or very dense (DRAM), lose the data contents when
charge retention and endurance, will be discussed, together with the the power supply is turned off.
understanding of the basic physical mechanisms responsible. Most – The nonvolatile memories, like EPROM,
of these considerations are also valid for the NAND cell, since it is
based on the same concept of floating-gate MOS transistor. EEPROM, or Flash, that are able to balance
Furthermore, an insight into the multilevel approach, where two the less-aggressive (with respect to SRAM and
bits are stored in the same cell, will be presented. In fact, the ex- DRAM) programming and reading performances
ploitation of the multilevel approach at each technology node allows with nonvolatility, i.e., with the capability to keep
the increase of the memory efficiency, almost doubling the density the data content even without power supply.
at the same chip size, enlarging the application range, and reducing
the cost per bit. Thanks to this characteristic, the nonvolatile memories offer
Finally, the NOR Flash cell scaling issues will be covered, the system a different opportunity and cover a wide range
pointing out the main challenges. The Flash cell scaling has of applications, from consumer and automotive to computer
been demonstrated to be really possible and to be able to follow
and communication (see Fig. 3).
the Moore’s law down to the 130-nm technology generations.
The technology development and the consolidated know-how is The different nonvolatile memory families can be qualita-
expected to sustain the scaling trend down to the 90- and 65-nm tively compared in terms of flexibility and cost (see Fig. 4).
technology nodes as forecasted by the International Technology Flexibility means the possibility to be programmed and
Roadmap of Semiconductors. One of the crucial issues to be solved erased many times on the system with minimum granularity
(whole chip, page, byte, bit); cost means process complexity
Manuscript received July 1, 2002; revised January 5, 2003. and in particular silicon occupancy, i.e., density or, in sim-
The authors are with the Central Research and Development Department, pler words, cell size. Considering the flexibility-cost plane,
Non-Volatile Memory Process Development, STMicroelectronics, 20041
Agrate Brianza, Italy (e-mail: [email protected]). it turns out that Flash offers the best compromise between
Digital Object Identifier 10.1109/JPROC.2003.811702 these two parameters, since they have the smallest cell size

0018-9219/03$17.00 © 2003 IEEE

PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003 489

 Fig. 4. Nonvolatile memory (NVM) qualitative comparison in the
flexibility–cost plane. A common feature of NVMs is to retain the
Fig. 1. Semiconductor market: revenues versus year. The bottom data even without power supply.
wave refers to the semiconductor memory amount.

Based on these market needs, a well-known way to clas-

sify Flash products and the relative technologies is that of
defining two major application segments:
– code storage, where the program or the operating
system is stored and is executed by the micropro-
cessor or microcontroller;
– data (or mass) storage, where data files for image,
music, and voice are recorded and read sequentially.
Different type of Flash cells and architectures have been
proposed in the past (see Fig. 5). They can be divided in terms
of access type, parallel or serial, and in terms of the utilized
programming and erasing mechanism, Fowler–Nordheim
tunneling (FN), channel hot electron (CHE), hot-holes
Fig. 2. MOS memory tree.
(HH), and source-side hot electron (SSHE). Among all of
these architectures, today two can be considered as industry
standard: the common ground NOR Flash [1]–[3], that due
to its versatility is addressing both the code and data storage
segments, and the NAND Flash, optimized for the data
storage market [4], [5].
In the following, the basic concepts, the reliability issues,
the evolution, and scaling trends will be presented only for
the NOR Flash cell, but most of these considerations are also
valid for the NAND since both of them are based on the con-
cept of floating-gate MOS transistor.

II. NOR FLASH CELL

Fig. 3. Main nonvolatile memory applications. In 1971, Frohman-Bentchkowsky presented a floating gate
transistor in which hot electrons were injected and stored
(one transistor cell) with a very good flexibility (they can be [6], [7]. From this original work, the erasable programmable
electrically written on field more than 100 000 times, with read only memory (EPROM) cell, programmed by CHE and
byte programming and sectors erasing). erased by ultraviolet (UV) photoemission, has been devel-
The most relevant phenomenon of this past decade in the oped. The EPROM technology became the most important
field of semiconductor memories has been the explosive nonvolatile memory in the 1980s. In the same period, the
growth of the Flash memory market, driven by cellular Flash EEPROM was proposed, basically an EPROM cell,
phones and other types of electronic portable equipment with the possibility to be electrically erased [8]. The name
(palm top, mobile PC, mp3 audio player, digital camera, and Flash was given to represent the fact that the whole memory
so on). Moreover, in the coming years, portable systems will array could be erased in the same (fast) time.
demand even more nonvolatile memories, either with high The first Flash product was presented in 1988 [9]. In terms
density and very high writing throughput for data storage of applications, initially Flash products were mainly used
application or with fast random access for code execution as an “EPROM replacement,” offering the possibility to be
in place. erased on system, avoiding the cumbersome UV erase oper-

490 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

Fig. 5. The family tree of Flash memory cell architecture. The actual industry standard are: 1) The
NOR for code and data storage application and 2) NAND only for data storage.

Fig. 7. Schematic cross section of a Flash cell. The floating-gate

structure is common to all the nonvolatile memory cells based on
Fig. 6. Semiconductor memory market for the main memory, the floating-gate MOS transistor.
i.e., DRAM, Flash, and SRAM.

A. Basic Concept
ation. But the Flash market did not take off until this tech-
nology was proven to be reliable and manufacturable. In the A Flash cell is basically a floating-gate MOS transistor
late 1990s, the Flash technology exploded as the right non- (see Fig. 7), i.e., a transistor with a gate completely sur-
volatile memory for code and data storage, mainly for mobile rounded by dielectrics, the floating gate (FG), and electri-
applications. Starting from 2000, the Flash memory can be cally governed by a capacitively coupled control gate (CG).
considered a really mature technology: more than 800 mil- Being electrically isolated, the FG acts as the storing elec-
lion units of 16-Mb equivalent NOR Flash devices were sold trode for the cell device; charge injected in the FG is main-
in that year. tained there, allowing modulation of the “apparent” threshold
In Fig. 6, the Flash market is reported and compared with voltage (i.e., seen from the CG) of the cell transistor.
the DRAM and SRAM one [10]. It can be seen that the Flash Obviously the quality of the dielectrics guarantees the non-
market became and has stayed bigger than the SRAM one volatility, while the thickness allows the possibility to pro-
since 1999. Moreover, the Flash market is forecasted to be gram or erase the cell by electrical pulses. Usually the gate
above $20 billion in three or four years from now, reaching dielectric, i.e., the one between the transistor channel and the
the DRAM market amount, and only smoothly following the FG, is an oxide in the range of 9–10 nm and is called “tunnel
DRAM oscillating trend, driven by the personal computer oxide” since FN electron tunneling occurs through it. The
market. In fact, portable systems for communications and dielectric that separates the FG from the CG is formed by a
consumer markets, which are the drivers of the Flash market, triple layer of oxide–nitride–oxide (ONO). The ONO thick-
are forecasted to continuously grow in the coming years. ness is in the range of 15–20 nm of equivalent oxide thick-
In the following, we briefly describe the basics of the Flash ness. The ONO layer as interpoly dielectric has been intro-
cell functionality. duced in order to improve the tunnel oxide quality. In fact, the

BEZ et al.: INTRODUCTION TO FLASH MEMORY 491

Fig. 8. Schematic energy band diagram (lower part) as referred to a floating gate MOSFET
structure (upper part). The left side of the figure is related to a neutral cell, while the right side to a
negatively charged cell.

Fig. 9. (a) NOR Flash array equivalent circuit. (b) Flash memory cell cross section.

use of thermal oxide over polysilicon implies growth temper- contact and the sourceline. This picture can be better under-
ature higher than 1100 C, impacting the underneath tunnel stood considering the layout of a cell (see Fig. 10) and the
oxide. High-temperature postannealing is known to damage two schematic cross sections, along the direction (bitline)
the thin oxide quality. and the direction (wordline). The cell area is given by the
If the tunnel oxide and the ONO behave as ideal di- pitch times the pitch. The pitch is given by the active
electrics, then it is possible to schematically represent the area width and space, considering also that the FG must
energy band diagram of the FG MOS transistor as reported overlap the oxide field. The pitch is constituted by the cell
in Fig. 8. It can be seen that the FG acts as a potential well gate length, the contact-to-gate distance, half contact, and
for the charge. Once the charge is in the FG, the tunnel and half sourceline. It is evident, as reported in Fig. 9(b), that
ONO dielectrics form potential barriers. both contact and sourceline are shared between two adjacent
The neutral (or positively charged) state is associated with cells.
the logical state “1” and the negatively charged state, corre-
sponding to electrons stored in the FG, is associated with the B. Reading Operation
logical “0.” The data stored in a Flash cell can be determined mea-
The “NOR” Flash name is related to the way the cells are suring the threshold voltage of the FG MOS transistor. The
arranged in an array, through rows and columns in a NOR-like best and fastest way to do that is by reading the current driven
structure. Flash cells sharing the same gate constitute the by the cell at a fixed gate bias. In fact, as schematically re-
so-called wordline (WL), while those sharing the same drain ported in Fig. 11, in the current–voltage plane two cells,
electrode (one contact common to two cells) constitute the respectively, logic “1” and “0” exhibit the same transcon-
bitline (BL). In this array organization, the source electrode ductance curve but are shifted by a quantity—the threshold
is common to all of the cells [Fig. 9(a)]. voltage shift ( )—that is proportional to the stored elec-
A scanning electron microscope (SEM) cross section tron charge .
along a bitline of a Flash array is reported in Fig. 9(b), where Hence, once a proper charge amount and a corresponding
three cells can be observed, sharing two by two the drain is defined, it is possible to fix a reading voltage in such

492 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

 Fig. 12. Writing mechanism in floating-gate devices.

Fig. 10. The NOR Flash cell. (a) Basic layout. (b) Updated Flash
product (64-Mb, 1.8-V Dual bank). (c) and (d) are, respectively,
the schematic cross section along bitline (y pitch) and wordline
(x pitch).

Fig. 13. NOR Flash writing mechanism.

– The photoelectric effect, where electrons gain

enough energy to surmount the barrier thanks to
the interaction with a photon with energy larger
Fig. 11. Floating-gate MOSFET reading operation. than the barrier itself. For silicon–dioxide, this
corresponds to UV radiation. This mechanism is
the one originally used in EPROM’s products to
a way that the current of the “1” cell is very high (in the range
erase the entire device.
of tens of microamperes), while the current of the “0” cell is
– The Fowler–Nordheim electron tunneling mecha-
zero, in the microampere scale. In this way, it is possible to
nism is a quantum-mechanical tunnel induced by
define the logical state “1” from a microscopic point of view
an electric field. Applying a strong electric field
as no electron charge (or positive charge) stored in the FG and
(in the range of 8–10 MV/cm) across a thin oxide,
from a macroscopic point of view as large reading current.
it is possible to force a large electron tunneling
Vice versa, the logical state “0” is defined, respectively, by
current through it without destroying its dielectric
electron charge stored in the FG and zero reading current.
properties.
C. Writing Operation A NOR Flash memory cell is programmed by CHE injec-
tion in the FG at the drain side and it is erased by means of
Considering Fig. 8, the problem of writing an FG cell cor-
the FN electron tunneling through the tunnel oxide from the
responds to the physical problem of forcing an electron above
FG to the silicon surface (see Fig. 13).
or across an energy barrier. The problem can be solved ex-
ploiting different physical effects [11]. In Fig. 12, the three
main physical mechanisms used to write an FG memory cell III. RELIABILITY
are sketched. Many issues have to be addressed when, from the theoret-
– The CHE mechanism, where electrons gain enough ical model of a single cell, a Flash product has to be real-
energy to pass the oxide–silicon energy barrier, ized, integrating millions of cells in an array. Nonvolatility
thanks to the electric field in the transistor channel implies at least ten years of charge retention, and the data
between source and drain. In fact, the electron en- must be stored in a cell after many read/program/erase cy-
ergy distribution presents a tail in the high energy cles. The confidence in Flash memory reliability has grown
side that can be modulated by the longitudinal together with the understanding of the single memory cell
electric field. failure mechanisms.

BEZ et al.: INTRODUCTION TO FLASH MEMORY 493

 Fig. 15. Schematic of a Flash array, showing row and column
disturbs occurring when the cycled cell is programmed.
Fig. 14. Threshold voltage distribution of a 1-Mb Flash array
after UV erasure, after CHE programming, and after FN erasure.
Different models have been presented with the aim to
The high degree of testability [12] allows the detection explain the tail cells. For example, a distribution in the
at wafer level of latent defects which may cause single-cell polycrystalline structure of the FG, with a barrier height
failures related to programming disturbs, data retention, and variation at the grain boundaries, would give rise to a local
oxide defects [13], thus making Flash one of the most reliable enhancement of the tunnel barrier [15]. Another model
nonvolatile memories. explains the tail cells as due to randomly distributed positive
charges in the tunnel oxide [16]. This model is solidly based
on the well-known existence of donor-like bulk oxide traps
A. Threshold Voltage Distribution and on calculations that show the huge increase of the tunnel
When dealing with a large array of cells, e.g., from tens of current density caused by the presence of an elementary
thousands to one million, it is very important to understand positive charge closed to injecting electrode.
the type of dispersion given by the large set of cells. The best Independently from a consolidated model, it can be stated
way to do it is to compare the threshold voltage distribution that the exponential tail of the erased distribution is mostly
of the whole array, considering it after UV erasure—that can related to structural imperfections, i.e., intrinsic defects, and
be considered as the reference state—after CHE program- it can be minimized by process optimization (for example,
ming and after FN erasing. working on silicon surface preparation, tunnel oxidation, FG
Fig. 14 shows typical distributions of cell threshold volt- polysilicon optimization) but not eliminated. Flash products
ages in a large memory array. The UV-erased distribution must be designed taking into account the existence of such a
is pretty narrow and symmetrical. A more accurate analysis tail.
would reveal a Gaussian distribution due to random vari-
ations of critical dimensions, thickness, and doping which B. Program Disturb
contribute to cause a dispersion of threshold voltages, either
directly or through coupling ratios. The failure mechanisms referred to as “program disturbs”
The programmed distribution is wider than the UV-erased concern data corruption of written cells caused by the elec-
one, but it is still symmetrical. The enlargement occurs trical stress applied to these cells while programming other
because most of the parameters that cause dispersion cells in the memory array. Two types of program disturbs
of UV-erased cells also impact the threshold shift of pro- must be taken into account: row and column disturbs, also
grammed cells. referred as gate and drain stress, as schematically reported in
The distribution of threshold voltages after electrical erase Fig. 15, representing a portion of a cell array.
is much wider and heavily asymmetrical. A more detailed Row disturbs are due to gate stress applied to a cell while
analysis would show that the bulk of the distribution is again programming other cells on the same wordline. If a high
a Gaussian with a standard deviation larger than the one of voltage is applied to the selected row, all the other cells of
programmed cells. Cells in this part of the distribution are that row must withstand the gate stress without losing their
referred to as “normal” cells. But there is also an exponential data. Depending on the data stored in the cells, data can be
tail at low , composed of cells that erase faster than the lost either by a leakage in the gate oxide or by a leakage in
average, also called “tail” cells. the interpoly dielectric.
The dispersion of threshold voltages of normal cells is Column disturbs are due to drain stress applied to a cell
due to coupling ratio variations, and it has been accurately while programming other cells on the same bitline. Under
modeled [14]. Instead, the understanding of the tail cells, al- this condition, programmed cells can lose charge by FN tun-
though of key importance, is more difficult. In fact, as these neling from the FG to the drain (soft erasing). The program
cells erase faster than normal cells with the same applied disturb depends on the number of cells along bitline and
voltage, one should assume that they are somehow “defec- wordline and then depends strongly on the sector organiza-
tive.” However, they are just too numerous for being associ- tion. The most effective way to prevent disturb propagation is
ated with extrinsic defects. to use block select transistor in a divided bitline and wordline

494 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

organization to completely isolate each sector. Program dis-
turb really could be a critical issue in Flash memory, and cells
and circuits must be designed with safety margins versus the
stress sensitivity.

C. Data Retention
As in any nonvolatile memory technology, Flash memories
are specified to retain data for over ten years. This means the
loss of charge stored in the FG must be as minimal as pos-
sible. In updated Flash technology, due to the small cell size,
the capacitance is very small and at an operative programmed
threshold shift—about 2 V—corresponds a number of elec-
trons in the order of 10 to 10 . A loss of 20% in this number
(around 2–20 electrons lost per month) can lead to a wrong Fig. 16. Threshold voltage window closure as a function of
read of the cell and then to a data loss. program/erase cycles on a single cell.
Possible causes of charge loss are: 1) defects in the tunnel
oxide; 2) defects in the interpoly dielectric; 3) mobile ion
contamination; and 4) detrapping of charge from insulating
layers surrounding the FG.
The generation of defects in the tunnel oxide can be di-
vided into an extrinsic and an intrinsic one. The former is
due to defects in the device structure; the latter to the physical
mechanisms that are used to program and erase the cell. The
tunnel oxidation technology as well as the Flash cell architec-
ture is a key factor for mastering a reliable Flash technology.
The best interpoly dielectric considering both intrinsic
properties and process integration issues has been demon-
strated to be a triple layer composed of ONO. For several Fig. 17. Program and erase time as a function of the cycles
generations, all Flash technologies have used ONO as their number.
interpoly dielectric.
The problem of mobile ion contamination has been al-
ready solved on the EPROM technology, taking particular
care with the process control, but in particular using high
phosphorus content in intermediate dielectric as a gettering
element. [17], [18]. The process control and the interme-
diate dielectric technology have also been implemented in
the Flash process, obtaining the same good results.
Electrons can be trapped in the insulating layers sur-
rounding the floating gate during wafer processing, as a
result of the so-called plasma damage, or even during the UV
exposure normally used to bring the cell in a well-defined
state at the end of the process. The electrons can subse-
quently detrap with time, especially at high temperature. Fig. 18. Anomalous SILC modeling. The leakage is caused by
a cluster of positive charge generated in the oxide during erase
The charge variation results in a variation of the floating gate (left-hand side). The multitrap assisted tunneling is used to model
potential and thus in cell decrease, even if no leakage SILC: trap parameters are energy and position.
has actually occurred. This apparent charge loss disappears
if the process ends with a thermal treatment able to remove typical result of an endurance test on a single cell is shown in
the trapped charge. Fig. 16. As the experiment was performed applying constant
The retention capability of Flash memories has to be pulses, the variations of program and erase threshold voltage
checked by using accelerated tests that usually adopt levels are described as “program/erase threshold voltage
screening electric fields and hostile environments at high window closure” and give a measure of the tunnel oxide
temperature. aging. In real Flash devices, where intelligent algorithms are
used to prevent window closing, this effect corresponds
D. Programming/Erasing Endurance to a program and erase times increase (see Fig. 17).
Flash products are specified for 10 erase/program cycles. In particular, the reduction of the programmed threshold
Cycling is known to cause a fairly uniform wear-out of the with cycling is due to trap generation in the oxide and to
cell performance, mainly due to tunnel oxide degradation, interface state generation at the drain side of the channel,
which eventually limits the endurance characteristics [19]. A which are mechanisms specific to hot-electron degradation.

BEZ et al.: INTRODUCTION TO FLASH MEMORY 495

Fig. 19. Data retention tests at room temperature.

The evolution of the erase threshold voltage reflects the dy-

namics of net fixed charge in the tunnel oxide as a function
of the injected charge. The initial lowering of the erase is
due to a pile-up of positive charge which enhances tunneling
efficiency, while the long-term increase of the erase is
due to a generation of negative traps.
Cycling wear-out can be reduced by proper device en-
gineering and by optimization of the tunnel oxide process.
However, once process and product are qualified for a given
endurance specification, no major problems should come
from lot-to-lot variation.
Actually, endurance problems are mostly given by
single-cell failures, which present themselves like a reten-
tion problem after program/erase cycles. In fact, a high field
stress on thin oxide is known to increase the current density
at low electric field. The excess current component, which Fig. 20. DV as a function of the pulse number for three
causes a significant deviation from the current–voltage different channel lengths (the upper axis also shows the gate voltage
curves from the theoretical FN characteristics at low field, at each programming step).
is known as stress-induced leakage current (SILC). SILC is
clearly attributed to stress-induced oxide defects and, as far based on the ability to precisely control the amount of charge
as a conduction mechanism, it is attributed to a trap assisted stored into the floating gate in order to set the threshold
tunneling (see Fig. 18). The main parameters controlling voltage of a memory cell within any of a number of
SILC are the stress field, the amount of charge injected different voltage ranges, corresponding to different logical
during the stress, and the oxide thickness. For fixed stress levels. A cell operated with 2 different levels is capable
conditions, the leakage current increases strongly with of storing bits, the case being the conventional
decreasing oxide thickness [20]–[22]. single-bit cell.
The effect of cycling on data retention cannot be referred Three main issues must be afforded when going from con-
to in the typical cell, but must be studied considering a wide ventional to ML Flash [25]. A high programming accuracy is
array of cells, looking in particular to the tail distribution. required to obtain narrow distributions; reading operation
In Fig. 19, we report the results of retention test on a 1-Mb implies multiple, either serial or parallel, comparison with
array of cells with 8-nm tunnel oxide in order to enhance the suitable references to determine the cell status, requiring ac-
SILC defects in single cells. Retention tests have been per- curate and fast current sensing; window and read voltage
formed on arrays cycled 10 and 10 times [23]. As can be are larger while read margins are smaller than the single-bit
seen, the amount of cells that lose charge after three years are case, this for allocating all levels, requiring improved re-
much more in the case of longer endurance. Data retention liability and/or error-correction circuitry. These key points
after cycling is the issue that definitely limits the tunnel oxide will be discussed with reference to a common-ground NOR
thickness scaling. For very thin oxide, below 8–9 nm, the architecture.
number of leaky cells becomes so large that even error-cor-
rection techniques cannot fix the problem. A. Multilevel Flash Programming
CHE programming has been shown to give, under proper
IV. MULTILEVEL CONCEPT conditions, a linear relationship with unit slope between pro-
An attractive way to speed up the scaling of Flash memory gramming gate voltage and variation [26], indepen-
is offered by the multilevel (ML) concept [24]. The idea is dently of cell parameters (see Fig. 20). Very tight distri-

496 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

Fig. 21. Schematic of the control-gate voltage pulses.

Fig. 23. Threshold voltage distribution for 2 b/cell compared

with the standard 1 b/cell.

B. Reading Operation
In order to have a fast reading operation in the NOR cell, a
parallel sensing approach can be used [29]. The cell current,
obtained in reading conditions, is simultaneously compared
with three currents provided by suitable reference cells (see
Fig. 22). The comparison results are then converted to a bi-
nary code, whose content can be 11, 01, 10, or 00, due to the
Fig. 22. Parallel multilevel sensing architecture. multilevel nature. In Fig. 23, we report the threshold voltage
= =
MSB most significant bit; LSB less significant bit. distribution of a 2-b/cell memory. The 11, 10, and 01 cell dis-
tribution will give rise to a different current distribution, mea-
sured at fixed , while the 00 cell distribution does not
butions can be obtained by combining a program-and-verify
drain current as well as the programmed level of a standard
technique with a staircase ramp (see Fig. 21). In fact,
1-b/cell device. High read data rate, via page or burst mode,
this method should theoretically lead to a distribution
is normally supported by large internal read parallelism.
width for any state not larger than . Indeed, neglecting
A parallel sensing approach does not seem transferable
any error due to sense amplifier inaccuracy or voltage fluc-
to 3- or 4-b/cell generations because of the exponential in-
tuations, the last programming pulse applied to a cell will
crease, 2 1, in comparators number, respectively 7 or 15
cause its threshold voltage to be shifted above the program
per cell, that means exponential increase in sensing area and
verify decision level by an amount at most as large as .
current consumption. At this moment, a serial sensing ap-
It follows that by decreasing , it is possible to in-
proach, e.g., dichotomic, or a mixed serial-parallel is consid-
crease the programming accuracy. Obviously, this is paid in
ered the more suitable approach. Serial sensing is also useful
terms of a larger number of programming pulses together
for a 2-b/cell device when high-speed random access is not
with verify phases and, therefore, with a longer programming
necessary, e.g., in Flash Cards applications.
time. Hence, the best accuracy/time tradeoff must be chosen
for each case considering the application specification.
However, high programming throughput, equal to 1-b/cell C. Data Retention
devices, is normally achieved via a large internal program One of the main concerns about multilevel is the reduced
parallelism, which is possible because cells need a low pro- margin toward the charge loss, compared with the 1-b/cell
gramming current in ML staircase programming. To do that, approach. We can basically divide the problem of data reten-
ML devices operate with a program write buffer, whose typ- tion into two different issues.
ical length is 32–64 bytes, i.e., 128–256 cell data length. The first is related to the extrinsic charge loss, i.e., to a
Also, evolution to 3–4 b/cell will not have an impact on single bit that randomly can have different behaviors with
programming throughput. In fact, program pulses and verify respect to the average and that usually form a tail in a stan-
phases increase proportionally with the number of bits per dard distribution. It is well known that extrinsic charge loss
cell, thus keeping roughly constant the effective byte pro- strongly depends on tunnel oxide retention electric field and
gramming time. that this issue can become more critical if an enhanced cell
Despite a not-negligible programming current, another ad- threshold range has to be used to allocate the 2 levels [30].
vantage in using CHE programming for multilevel devices is This problem is usually solved with the introduction of the
to avoid the appearance of erratic bits that instead can be a error correction code (ECC), whose correction power must
potential failure mode affecting FN programming. In fact, er- be chosen as a function of the technology and of the specifi-
ratic bit behavior was observed in the FN erase of standard cation required to the memory products.
NOR memories [27] but, for its nature, it should be present in The second one is related to the intrinsic charge loss, i.e.,
every tunneling process [28]. to the behaviors of the Gaussian part of a cell distribution,

BEZ et al.: INTRODUCTION TO FLASH MEMORY 497

 Moreover, considering the multilevel approach for the
Flash cell with the capability to store two bits in the same
cell, as presented in Section IV, not only the scaling trend but
even the bit size itself is well aligned with the DRAM one.
Together with the Flash cell scaling, there has also been
an evolution of the Flash product specification and applica-
tion. Three main generations can be considered, well dif-
ferentiated as a technology node, process complexity, and
specification.
– First generation (1990–1997). The Flash applica-
tions were mainly “EPROM replacement.” The
products were characterized by a single array
Fig. 24. Shift in the threshold voltage distribution after 500 h (bulk), with memory density from 256 kb to 2 Mb.
bake at 250 C.
The program and erase algorithms were controlled
externally and all the product were dual voltage:
12 V for the write operations and 5 V for the power
supply. Cycling specification was limited to 10 .
– Second generation (1995–2000). The Flash
memory has become the right nonvolatile memory
technology for code storage application, where
software updates must be performed on the field.
In particular, portable systems, mainly cellular
phones, were strongly interested in this feature.
The cellular phone applications brought a lot of
innovations:
• The density was increased from 1 to 16 Mb
and sectors were introduced, instead of a
single (bulk) array, in order to allow different
Fig. 25. DRAM and Flash cell size reduction versus year. The use of the memory (some sectors can be used
scaling has been of about a factor 30 in ten years.
to store code while others to store data, with
different requirements in terms of cycling).
that must be characterized and defined as a function of the
Sector density was from 10 to 256 kb.
different level distributions. In order to study the data reten-
• A single voltage supply pin (5 or 3 V according
tion on multilevel memories, usually tests at high-tempera-
to the system specification) substituted the
ture bake on programmed cells are performed. A result of
two high-voltage and low-voltage pins previ-
data retention after bake (500 h, 250 C) is shown in Fig. 24,
ously used. The need to be programmed on
on one million cells [31].
field, without the possibility to have the high
The maximum shift, which occurs for the uppermost
voltage from an external pin, has developed the
level, is about 0.1 V. This means the spacing between levels
technology to internally generate the writing
is reduced by a very small amount. It is interesting to note
voltages using charge-pump techniques. A
that the three programmed levels are shifted by an amount
high-voltage supply is sometimes still used,
proportional to their respective programmed , so that the
but limited to the first programming operation
spacing between adjacent levels is reduced by only a fraction
in the system manufacturing line, to improve
of the observed maximum shift.
the throughput.
• Algorithms to perform all the operation
V. EVOLUTION AND SCALING TREND
on the array—reading programming and
The Flash memories were commercially introduced in the erasing—were embedded into the device in
early 1990s and since that time they have been able to follow order to avoid the need for an external micro-
the Moore law or, better, the scaling rules imposed by the controller.
market. Fig. 25 reports in a logarithmic scale the Flash cell • 10 writing cycles were introduced as a spec-
size as a function of time, from 1992 to 2002. It turns out ification. More than effectively needed by the
that the reduction of the cell size has been about a factor system, this high endurance is the result of a
30 in those ten years, closely following the scaling of the highly reliable technology.
DRAM, today still considered as the reference memory tech- – Third generation (from 1998 on). The portable
nology that sets the pace to the technology node evolution. system specifications push toward Flash memory
More specifically, the NOR Flash cell has scaled from 4.2 m products that look more and more like an applica-
for the 0,6- m technology node to the present cell size of tion-specific memory. Obviously, the density is one
0.16 m at the 0.13- m node. of the most important parameters, and devices well

498 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

Fig. 26. NOR Flash technology and architecture evolution.

Fig. 27. Triple well structure cross section: schematic (left side) and SEM (right side).

beyond 64 Mb will be realized entering the Flash CMOS technology have also been used for Flash. In Fig. 26,
in the gigabit era. The sectorization is becoming the different cell cross sections as a function of the different
more complex, and dual or multiple bank devices technology node are reported. For every generation, the
have already been presented. In these devices, dif- main innovative introduced steps are pointed out. It turns
ferent groups of sectors ( banks) can be differently out that the evolution of the different generations has been
managed: at the same time one sector belonging sustained by an increased process complexity, from the
to a bank can be read while another one, inside a one gate oxide and one metal process with standard local
different bank, can be programmed or erased. Also, oxidation of silicon isolation at the 0.8- m technology node,
following the general trend of reducing the power to the two gate oxides, three metals, and shallow trench iso-
supply, the device supply is scaling to 1.8 V (with lation at the 0.13- m node. In between is the introduction of
the consequent difficulties of internally generating tungsten plug, of self-aligned silicided junctions and gates,
high voltages starting from this low supply voltage and the wide use of chemical mechanical polishing steps.
value) and will go down to 1.2 V. Another issue, be- But one of the most crucial technologies for Flash evolution
coming more and more important, is the high data was the high-energy implantation development that has
throughput, in particular considering the density allowed the introduction of the triple well architecture (see
increase. Burst mode is often used in order to speed Fig. 27). With this process module, further development
up the reading operation and quickly download the of the single-voltage products has been possible, allowing
software content, reaching up to 50 MB/s. the easy management of the negative voltage required to
The introduction of the different generation as well as the erase the cell and, furthermore, the possibility to completely
reduction of the cell size has been made possible by the change the erasing scheme of the cell.
developments of Flash technology and process, and of cell In fact, as reported in Fig. 28, the cell programming and
architecture. erasing applied voltages have been changed as a function of
For what concerns the process architecture, all the main the different generation, always staying inside the CHE pro-
technology steps that have allowed the evolution of the gramming and the FN erasing. The first generation of cells

BEZ et al.: INTRODUCTION TO FLASH MEMORY 499

Fig. 28. NOR Flash cell evolution.

Fig. 29. NOR cell scaling. The basic layout has remained
unchanged through different generations. Fig. 30. NOR Flash cell scaling trends for cell area (right y axis)
and cell aspect ratio (left y axis). Both values are normalized to
the 130-nm technology node.
was erased, applying the high voltage to the source junction
and then extracting electrons from the FG-source overlap re-
gion (source erase scheme). This way was too expensive in The next technology step for the NOR Flash will be the
terms of parasitic current, as the working conditions were 90-nm technology node in 2004–2005. The cell size is ex-
very close to the junction breakdown. Moving to the second pected to stay in the range of 10–12 , translating to a cell
generation with the single-voltage devices, the voltage drop area of 0.1–0.08 m . As reported again in Fig. 29, the cell
between the source and the FG was divided, applying a neg- basic layout and structure has remained unchanged through
ative voltage to the control gate and lowering the source bias the different generations. The area scales through the scaling
to the external supply voltage (negative gate source erase of both the and pitch. Basically, this must be done con-
scheme). temporarily reducing the active device dimensions, effective
Finally, with the exploitation of the triple well also for the length ( ) and width ( ), and the passive elements,
array, the erasing potential is now divided between the neg- such as contact dimension, contact to gate distance, and so
ative CG and the positive bulk (the isolated p-well) of the on.
array, moving the tunneling region from the source to the For future generation technology nodes, i.e., the 65 nm in
whole cell channel (channel erase scheme). In this way, elec- 2007 and the 45 nm in 2010, as forecasted by ITRS, the Flash
trons are extracted from the FG all along the channel without cell reduction will face challenging issues. In fact, while the
any further parasitic current contribution from the source passive elements will follow the standard CMOS evolution,
junction, consequently reducing the erase current amount of benefiting from all the technology steps and process modules
about three orders of magnitude; the latter being a clear ben- proposed for the CMOS logic (like advanced lithography for
efit for battery saving in portable low-voltage applications. contact size, cupper for metallization in very tight pitch), the
The NOR Flash cell is forecasted to scale again following active elements will be limited in the scaling. In particular,
the International Technology Roadmap of Semiconductors the effective channel length will be limited by the possibility
(ITRS) [32]. The introduction of the 130-nm technology to further scale the active dielectric, i.e., the tunnel oxide and
node has occurred in 2002–2003 with a cell size of 0.16 m the interpoly ONO. As already presented in Section III, the
[33], following the 10- golden rule for the cell area tunnel oxide thickness scaling is limited by intrinsic issues
scaling, where is the technology node. The representation related to the Flash cell reliability, in particular the charge re-
of the memory cell size in terms of number of is a usual tention one, especially after many writing cycles. Although
way to compare different technology with the same metric; the direct tunneling, preventing the ten-year retention time,
for example, the DRAM cell size is today quoted to stay in occurs at 6–7 nm, SILC considerations push the tunnel thick-
the range of 6–8 . ness limit to no less than 8–9 nm. Moreover, the effective

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tion, strongly proportional to the , then impacting the storage application,” in IEDM Tech Dig., 2000, pp. 763–766.
[6] D. Frohman-Bentchkowsky, “Memory behavior in a floating-gate
access time. avalanche-injection MOS (FAMOS) structure,” Appl. Phys. Lett.,
Scaling the technology node, while the cell pitch will vol. 18, pp. 332–334, 1971.
more and more approach the 2 , the -pitch scaling will [7] , “FAMOS – A new semiconductor charge storage device,”
Solid State Electron., vol. 17, pp. 517–520, 1974.
be limited by the cell gate scaling. Hence, for the 65- and [8] S. Mukherjee, T. Chang, R. Pang, M. Knecht, and D. Hu, “A single
45-nm technology nodes, it is expected to have smaller cell transistor EEPROM cell and its implementation in a 512 K CMOS
EEPROM,” in IEDM Tech. Dig., 1985, pp. 616–619.
size but with an increased number of , from 10 to 14. In [9] V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J.
particular, the cell aspect ratio, i.e., the pitch over the Kreifels, and S. Wells, “An in-system reprogrammable 256 K CMOS
pitch, will continue to rise, due to the slowdown of the Flash memory2,” in ISSCC Conf. Proc., 1988, pp. 132–133.
[10] Webfeet Inc., “Semiconductor industry outlook,” presented at the
reduction. Fig. 30 reports the cell area and the cell-aspect 2002 Non-Volatile Memory Conference, Santa Clara, CA.
ratio versus the technology node, both normalized at 130 nm. [11] L. Selmi and C. Fiegna, “Physical aspects of cell operation and relia-
As can be observed, the cell area will be roughly one half at bility,” in Flash Memories, P. Cappelletti et al., Ed. Norwell, MA:
Kluwer, 1999.
90 nm (same number of 10–12 ) and will decrease, but [12] G. Casagrande, “Flash memory testing,” in Flash Memories, P. Cap-
with slower trend at 65 and 45 nm. The cell-aspect ratio will pelletti et al., Ed. Norwell, MA: Kluwer, 1999.
continue to increase, almost doubling the one at 130 nm when [13] P. Cappelletti and A. Modelli, “Flash memory reliability,” in Flash
Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, 1999.
the technology node will reach 45 nm. [14] K. Yoshikawa, S. Yamada, J. Miyamoto, T. Suzuki, M. Oshikiri, E.
Obi, Y. Hiura, K. Yamada, Y. Ohshima, and S. Atsumi, “Comparison
of current Flash EEPROM erasing methods: Stability and how to
VI. SUMMARY control,” in IEDM Tech. Dig., 1992, pp. 595–598.
[15] S. Maramatsu, T. Kubota, N. Nishio, H. Shirai, M. Matsuo, N. Ko-
With more than ten years of consolidated know-how dama, M. Horikawa, S. Saito, K. Arai, and T. Okazawa, “The solu-
and thanks to its flexibility and cost characteristics, Flash tion of over-erase problem controlling poly-Si grain size—Modified
memory is today a largely utilized, well-consolidated, and scaling principles for Flash memory,” in IEDM Tech. Dig., 1994, pp.
847–850.
mature technology for nonvolatile memory application. [16] C. Dunn, C. Kay, T. Lewis, T. Strauss, J. Screck, P. Hefley, M. Mid-
Flash sales represent a considerable amount of the overall dendorf, and T. San, “Flash EEPROM disturb mechanism,” in Proc.
semiconductor market. In particular, the NOR Flash is today Int. Rel. Phys. Symp., 1994, pp. 299–308.
[17] G. Crisenza, G. Ghidini, S. Manzini, A. Modelli, and M. Tosi,
the most diffused architecture, being able to serve both the “Charge loss in EPROM due to ion generation and transport in
code and the data storage market. interlevel dielectrics,” in IEDM Tech. Dig., 1990, pp. 107–110.
[18] G. Crisenza, C. Clementi, G. Ghidini, and M. Tosi, “Floating gate
The cell is basically a floating-gate MOS transistor, memories,” Qual. Reliab. Eng. Int., vol. 8, pp. 177–187, 1992.
programmed by CHE and erased by Fowler–Nordheim tun- [19] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mecha-
neling. The main reliability issues, like charge retention and nisms of Flash cell in program/erase cycling,” in IEDM Tech. Dig.,
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endurance, have been extensively studied and the physical [20] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model
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present specification requirements. Tech. Dig., 2001, pp. 32.2.1–32.2.4.
[21] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Vis-
The Flash cell scaling has been demonstrated to be re- conti, “New technique for fast characterization of SILC distribution
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to the 130-nm technology generations. The technology de- [22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti,
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tions,” Microelectron. Eng., vol. 48, pp. 403–408, 1999.
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[25] A. Modelli, R. Bez, and A. Visconti, “Multi-level Flash memory
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At each technology node, the multilevel approach will in- [26] C. Calligaro, A. Manstretta, A. Modelli, and G. Torelli, “Technolog-
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[28] A. Chimenton, P. Pellati, and P. Olivo, “Analysis of erratic bits in
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[1] S. Lai, “Flash memories: Where we were and where we are going,” CHE NOR flash memory,” IEEE J. Solid-State Circuits, vol. 35, pp.
in IEDM Tech. Dig., 1998, pp. 971–973. 1655–1667, Nov. 2000.
[2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An [30] H. P. Belgal et al., “A new reliability model for post-cycling charge
overview,” Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997. retention of Flash memories,” in Proc. IRPS, 2002, pp. 7–20.
[3] P. Pavan and R. Bez, “The industry standard Flash memory cell,” in [31] A. Modelli, A. Manstretta, and G. Torelli, “Basic feasibility con-
Flash Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, straints for multilevel CHE-programmed Flash memories,” IEEE
1999. Trans. Electron Devices, vol. 48, pp. 2032–2042, Sept. 2001.
[4] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra [32] International Technology Roadmap for Semiconductors, 2001 ed.
high density EPROM and Flash with NAND structure cell,” in IEDM [33] S. Keeney, “A 130 nm generation high-density ETOX Flash memory
Tech. Dig., 1987, pp. 552–555. technology,” in IEDM Tech. Dig., 2001, pp. 2.5.1–2.5.4.

BEZ et al.: INTRODUCTION TO FLASH MEMORY 501

8 SRAM TECHNOLOGY

OVERVIEW

An SRAM (Static Random Access Memory) is designed to fill two needs: to provide a direct
interface with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systems
that require very low power consumption. In the first role, the SRAM serves as cache memory,
interfacing between DRAMs and the CPU. Figure 8-1 shows a typical PC microprocessor
memory configuration.

SRAM DRAM

External Cache (L2) Main Memory

64KB to 1MB 4MB to 512MB
Microprocessor

Internal Cache (L1)

8KB to 32KB

Source: Micron/ICE, "Memory 1997" 20812

Figure 8-1. Typical PC Microprocessor Memory Configuration

The second driving force for SRAM technology is low power applications. In this case, SRAMs
are used in most portable equipment because the DRAM refresh current is several orders of mag-
nitude more than the low-power SRAM standby current. For low-power SRAMs, access time is
comparable to a standard DRAM. Figure 8-2 shows a partial list of Hitachi’s SRAM products and
gives an overview of some of the applications where these SRAMs are found.

HOW THE DEVICE WORKS

The SRAM cell consists of a bi-stable flip-flop connected to the internal circuitry by two access
transistors (Figure 8-3). When the cell is not addressed, the two access transistors are closed and
the data is kept to a stable state, latched within the flip-flop.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-1

 SRAM Technology

100 Industrial/Peripheral Buffer Memory

64Kbit Low-Power SRAM

256Kbit 1Mbit 512K x 8

Low-Power SRAM Low-Power SRAM Low-Power SRAM
50

Mass Storage Buffer Memory

32K x 8 1M x 4/512K x 8
Asynchronous SRAM 128K x 8/64K x 16 Asynchronous SRAM
Access Time (ns)

20
Asynchronous SRAM

10 32K x 32/32K x 36
PC Cache Memory Asynchronous SRAM

256K x 18/128K x 36
5 32K x 36 LVCMOS SSRAM
LVCMOS/HSTL SSRAM
Non PC Cache Memory

2
64Kbit 256Kbit 1Mbit 4Mbit
Device Density
Source: Hitachi/ICE, "Memory 1997" 22607

Figure 8-2. Hitachi’s SRAM Products

Word Line

B B

To Sense Amplifier
Source: ICE, "Memory 1997" 20019

Figure 8-3. SRAM Cell

The flip-flop needs the power supply to keep the information. The data in an SRAM cell is volatile
(i.e., the data is lost when the power is removed). However, the data does not “leak away” like in
a DRAM, so the SRAM does not require a refresh cycle.

8-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

Read/Write

Figure 8-4 shows the read/write operations of an SRAM. To select a cell, the two access transis-
tors must be “on” so the elementary cell (the flip-flop) can be connected to the internal SRAM cir-
cuitry. These two access transistors of a cell are connected to the word line (also called row or X
address). The selected row will be set at VCC. The two flip-flop sides are thus connected to a pair
of lines, B and B. The bit lines are also called columns or Y addresses.

Word Line Word Line

Column Decode Column Decode

Sense Amplifier
(Voltage Comparator)

Write Circuitry

D Out
D In

READ OPERATION WRITE OPERATION

Source: ICE, "Memory 1997" 19952

Figure 8-4. Read/Write Operations

During a read operation these two bit lines are connected to the sense amplifier that recognizes if
a logic data “1” or “0” is stored in the selected elementary cell. This sense amplifier then transfers
the logic state to the output buffer which is connected to the output pad. There are as many sense
amplifiers as there are output pads.

During a write operation, data comes from the input pad. It then moves to the write circuitry.
Since the write circuitry drivers are stronger than the cell flip-flop transistors, the data will be
forced onto the cell.

When the read/write operation is completed, the word line (row) is set to 0V, the cell (flip-flop)
either keeps its original data for a read cycle or stores the new data which was loaded during the
write cycle.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-3

SRAM Technology

Data Retention

To work properly and to ensure that the data in the elementary cell will not be altered, the SRAM
must be supplied by a VCC (power supply) that will not fluctuate beyond plus or minus five or
ten percent of the VCC.

If the elementary cell is not disturbed, a lower voltage (2 volts) is acceptable to ensure that the cell
will correctly keep the data. In that case, the SRAM is set to a retention mode where the power
supply is lowered, and the part is no longer accessible. Figure 8-5 shows an example of how the
VCC power supply must be lowered to ensure good data retention.

,,,,
Data Retention Mode
VCC
3.0V VDR ≥ 2V 3.0V
tCDR tR

,,,,
,,
,
CE

Source: Cypress/ICE, "Memory 1997" 22460

Figure 8-5. SRAM Data Retention Waveform

MEMORY CELL

Different types of SRAM cells are based on the type of load used in the elementary inverter of the
flip-flop cell. There are currently three types of SRAM memory cells :

• The 4T cell (four NMOS transistors plus two poly load resistors)
• The 6T cell (six transistors—four NMOS transistors plus two PMOS transistors)
• The TFT cell (four NMOS transistors plus two loads called TFTs)

4 Transistor (4T ) Cell

The most common SRAM cell consists of four NMOS transistors plus two poly-load resistors
(Figure 8-6). This design is called the 4T cell SRAM. Two NMOS transistors are pass-transistors.
These transistors have their gates tied to the word line and connect the cell to the columns. The
two other NMOS transistors are the pull-downs of the flip-flop inverters. The loads of the invert-
ers consist of a very high polysilicon resistor.

This design is the most popular because of its size compared to a 6T cell. The cell needs room only
for the four NMOS transistors. The poly loads are stacked above these transistors. Although the
4T SRAM cell may be smaller than the 6T cell, it is still about four times as large as the cell of a
comparable generation DRAM cell.

8-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

W
+V

B B

To Sense Amps
Source: ICE, "Memory 1997" 18470A

Figure 8-6. SRAM 4T (Four-Transistor) Cell

The complexity of the 4T cell is to make a resistor load high enough (in the range of giga-ohms) to
minimize the current. However, this resistor must not be too high to guarantee good functionality.

Despite its size advantage, the 4T cells have several limitations. These include the fact that each cell
has current flowing in one resistor (i.e., the SRAM has a high standby current), the cell is sensitive
to noise and soft error because the resistance is so high, and the cell is not as fast as the 6T cell.

6 Transistor (6T) Cell

A different cell design that eliminates the above limitations is the use of a CMOS flip-flop. In this
case, the load is replaced by a PMOS transistor. This SRAM cell is composed of six transistors, one
NMOS transistor and one PMOS transistor for each inverter, plus two NMOS transistors con-
nected to the row line. This configuration is called a 6T Cell. Figure 8-7 shows this structure. This
cell offers better electrical performances (speed, noise immunity, standby current) than a 4T struc-
ture. The main disadvantage of this cell is its large size.

Until recently, the 6T cell architecture was reserved for niche markets such as military or space that
needed high immunity components. However, with commercial applications needing faster
SRAMs, the 6T cell may be implemented into more widespread applications in the future.

Much process development has been done to reduce the size of the 6T cell. At the 1997 ISSCC con-
ference, all papers presented on fast SRAMs described the 6T cell architecture (Figure 8-8).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-5

SRAM Technology

+V

B B

To Sense Amps

Source: ICE , "Memory 1997" 18471A

Figure 8-7. SRAM 6T (Six Transistor) Cell

Cell Size Die Size

Density Company Cell Type Process
(µm2) (mm2)

4Mbit NEC 6T 12.77 0.25µm 132

4Mbit IBM 6T 18.77 0.3µm 145

0.2µm Leff

128Kbit Hitachi 6T 21.67 0.35µm 5.34

Source: ICE, "Memory 1997" 22459

Figure 8-8. 1997 ISSCC Fast SRAM Examples

TFT (Thin Film Transistor) Cell

Manufacturers have tried to reduce the current flowing in the resistor load of a 4T cell. As a result,
designers developed a structure to change, during operating, the electrical characteristics of the
resistor load by controlling the channel of a transistor.

This resistor is configured as a PMOS transistor and is called a thin film transistor (TFT). It is
formed by depositing several layers of polysilicon above the silicon surface. The source/chan-
nel/drain is formed in the polysilicon load. The gate of this TFT is polysilicon and is tied to the
gate of the opposite inverter as in the 6T cell architecture. The oxide between this control gate and
the TFT polysilicon channel must be thin enough to ensure the effectiveness of the transistor.

The performance of the TFT PMOS transistor is not as good as a standard PMOS silicon transis-
tor used in a 6T cell. It should be more realistically compared to the linear polysilicon resistor
characteristics.

8-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

Figure 8-9 shows the TFT characteristics. In actual use, the effective resistance would range from
about 11 x 1013Ω to 5 x 109Ω. Figure 8-10 shows the TFT cell schematic.

–10–6
Vd = –4V

–10–8
Drain Current, Id (A)

Vg

–10–10

Tox = 25nm
Tpoly = 38nm
–10–12
L/W = 1.6/0.6µm

2 0 –2 –4 –6 –8
Gate Voltage, Vg (V)
Source: Hitachi/ICE, Memory 1997" 19953

Figure 8-9. TFT (Thin Film Transistor) Characteristics

Word Line

Poly-Si
PMOS

BL BL

Source: ICE, "Memory 1997" 19954

Figure 8-10. SRAM TFT Cell

Figure 8-11 displays a cross-sectional drawing of the TFT cell. TFT technology requires the depo-
sition of two more films and at least three more photolithography steps.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-7

SRAM Technology

1st Metal (BIT Line)

,,,,,,
,,,,,,
,,,,,,
3rd Poly-Si 4th Poly-Si
,,,,,,,,,,, 2nd Poly-Si
,,,,,,
,,,,,,,,,,, (Gate Electrode
,,,,,,,,,,,
(Channel of TFT)
,,,,,
,,,,,,,,,,
,,,,,,,,,,
(Internal Connection) Contact
,,,,,,
,,,,,,,, ,,,,,
,,,,,,,,,,, of TFT) ,,,,,,,,,,
,,,,,,,,,,
(W-Plug)
,,,,,
,,,,,,,,
,,,,,,,, ,,,,,,,,,,
,,,,,,,,,,
2nd Direct
Contact

,,,,,,,,
,,,,,,
,,,,,,,,,,,,,
,,,,,,,,,,,,,,, ,,,,,,
,,,,,,,,,,,,, ,,,,,,,,,,
,,,,,,,,,,
,,,,,, ,,,,,
,,,,
,,,,,,,,,,
,,,,,,,,,,,,,
,,,, ,,,,,,,, ,,,,,,
,,,,,,,,,,
,,,,,,,,,
,,,,,,, ,,,,,, ,,,,,,,,,,
,,,, ,,,,,,, Isolation
N+ N+ N+ N+
Access
N+ Diffusion TiSi2
Driver Transistor
Region 1st Poly-Si
Transistor
(GND Line) (Gate Electrode
of Bulk Transistor)

Source: IEDM 91/ICE, "Memory 1997" 18749

Figure 8-11. Cross Section of a TFT SRAM Cell

Development of TFT technology continues to be performed. At the 1996 IEDM conference, two
papers were presented on the subject. There are not as many TFT SRAMs as might be expected,
due to a more complex technology compared to the 4T cell technology and, perhaps, due to poor
TFT electrical characteristics compared to a PMOS transistor.

Cell Size and Die Size

Figure 8-12 shows characteristics of SRAM parts analyzed in ICE’s laboratory in 1996 and 1997.
The majority of the listed suppliers use the conventional 4T cell architecture. Only two chips were
made with a TFT cell architecture, and the only 6T cell architecture SRAM analyzed was the
Pentium Pro L2 Cache SRAM from Intel.

As indicated by the date code of the part and its technology, this study is a presentation of what
is the state-of-the-art today. ICE expects to see more 6T cell architectures in the future.

Figure 8-13 shows the trends of SRAM cell size. Like most other memory products, there is
a tradeoff between the performance of the cell and its process complexity. Most manufactur-
ers believe that the manufacturing process for the TFT-cell SRAM is too difficult, regardless
of its performance advantages.

8-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

Cell Size Die Size Min Gate (N)

Date Code Cell Type
(µm2) (mm2) (µm)

Toshiba 9509 4T 22 144 0.65

4Mbit
Samsung 1995 4T 14.25 33 0.5
1Mbit
Galvantech 9524 4T 16.5 31 0.4
1Mbit
Hitachi 9539 4T 19 64 0.45
1Mbit
NEC 9436 4T 19 67 0.6
1Mbit
Motorola 9443 4T 40 108 0.6
1Mbit
Hualon 9523 4T 30 13.5 0.45
256Kbit
ISSI 9445 4T 27.5 50 0.5
1Mbit
Mosel-Vitelic 9409 4T 44 94.7 0.65
1Mbit
NEC 9506 4T 15.7 42.5 0.5
1Mbit
Samsung 9606 TFT 11.7 77.8 0.65
4Mbit
Sony ? TFT 20 59 0.5
1Mbit
TM Tech 9530 4T 20 35 0.35
1Mbit
UMC 9631 4T 11.25 41 0.3
2Mbit
Winbond 9612 4T 10.15 32.5 0.5
1Mbit
Intel — 6T 33 — 0.35
Pentium Pro
L2 Cache
Source: ICE, "Memory 1997" 22461

Figure 8-12. Physical Geometries of SRAMs

Figures 8-14 and 8-15 show size and layout comparisons of a 4T cell and a 6T cell using the same technol-
ogy generation (0.3µm process). These two parts were analyzed by ICE’s laboratory in 1996.

One of the major process improvements in the development of SRAM technology is the so called
self aligned contact (SAC). This process suppresses the spacing between the metal contacts and
the poly gates and is illustrated in Figure 8-16.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-9

SRAM Technology

1,000

100
Cell Size (µm2)

6T Cell

10

4T (and TFT) Cell

1
1 Micron 0.8 Micron 0.5-0.6 Micron 0.35 Micron 0.25 Micron
Technology
Source: ICE, "Memory 1997" 19989A

Figure 8-13. Trend of SRAM Cell Sizes

CONFIGURATION

As shown in Figure 8-17, SRAMs can be classified in four main categories. The segments are asyn-
chronous SRAMs, synchronous SRAMs, special SRAMs, and non-volatile SRAMs. These are
highlighted below.

Asynchronous SRAMs

Figure 8-18 shows a typical functional block diagram and a typical pin configuration of an asyn-
chronous SRAM. The memory is managed by three control signals. One signal is the chip select
(CS) or chip enable (CE) that selects or de-selects the chip. When the chip is de-selected, the part
is in stand-by mode (minimum current consumption) and the outputs are in a high impedance
state. Another signal is the output enable (OE) that controls the outputs (valid data or high
impedance). Thirdly, is the write enable (WE) that selects read or write cycles.

Synchronous SRAMs

As computer system clocks increased, the demand for very fast SRAMs necessitated variations on
the standard asynchronous fast SRAM. The result was the synchronous SRAM (SSRAM).

8-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

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POLYCIDE
@@ @@

@@
@@
@@
@@
@@ @@

N+
@@ @@
@@ @@

1
@@
@@
@@
@@

BIT
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@

WORD
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

P+
@@ @@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@

4 6
@@ @@
@@
@@
@@
@@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@ @@

5P
@@ @@

6P
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@

GND 5.2µm
@@
@@
@@
@@

@@
@@
@@
@@
@@
@@
@@
@@

@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@

@@
@@
@@
BIT 1N 2N BIT
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@

@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@

4N 3N
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@ @@

3
@@ @@

5
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@
@@
@@
@@

@@ @@

BIT N+
@@
@@
@@
@@

2
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

@@ @@
@@
@@
@@
@@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@ @@
@@g
@@g ?@@
?@@
@@g
@@g ?@@
?@@
@@g
@@g ?@@
?@@
@@@@@@@@
@@@@@@@@ ?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@ ?@@@@@@@@
?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@ ?@@@@@@@@

6.35µm

Source: ICE, “Memory 1997” 22172

Figure 8-14. 6T SRAM Cell

WORD

WORD

VCC
4
@@@@@@@@e?@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e
@@@@@@@@e?
@@h?@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@
@@@@@@@@

R2
@@h? @@
@@

R1
@@h?
@@h? @@
@@h? @@
@@
@@h? @@

@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@
@@ @@
@@ @@
@@ @@

R1
@@ @@
@@
@@
@@
@@
@@ @@

@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
1 @@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@
@@ @@
@@ @@

BIT
@@ @@

BIT
@@ @@

@@ @@

2
@@ @@
@@ @@

1
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

@@ @@
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@
@@
@@
@@

@@ @@
@@ @@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

2.5µm
@@ @@

3 4
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@

3
@@ @@
@@ @@
@@ @@
@@ @@
@@
@@
@@
@@
@@ @@

@@ @@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@
@@ @@

2
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@
@@ @@
@@ @@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@

R2
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@
@@
@@
@@

@@ @@
@@ @@
@@ @@
@@
@@
@@
@@
@@ @@
@@ @@
@@ @@

@@
@@
@@
@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@

GND
@@ @@
@@g
@@g ?@@
@@g ?@@
?@@
@@g ?@@
@@g
@@g
?@@
?@@
@@@@@@@@ ?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@
@@@@@@@@ ?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@ ?@@@@@@@@
?@@@@@@@@

4.5µm

Source: ICE, “Memory 1997” 22171

Figure 8-15. 4T SRAM Cell

Synchronous SRAMs have their read or write cycles synchronized with the microprocessor clock
and therefore can be used in very high-speed applications. An important application for syn-
chronous SRAMs is cache SRAM used in Pentium- or PowerPC-based PCs and workstations.
Figure 8-19 shows the trends of PC cache SRAM.

Figure 8-20 shows a typical SSRAM block diagram as well as a typical pin configuration. SSRAMs
typically have a 32 bit output configuration while standard SRAMs have typically a 8 bit output
configuration. The RAM array, which forms the heart of an asynchronous SRAM, is also found in
SSRAM. Since the operations take place on the rising edge of the clock signal, it is unecessary to
hold the address and write data state throughout the entire cycle.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-11

SRAM Technology

Standard Process
Transistor
Active Area

Gate
Metal Contact Metal Contact

Metal Line Metal Line

Contact to Poly Spacing

SAC Process
Transistor
Active Area

Gate
Metal Contact Metal Contact

Metal Line Metal Line

Contact to Poly Spacing Has Been Eliminated
Source: EN/ICE, "Memory 1997" 22456

Figure 8-16. Self Aligned Contact (SAC) Process

Burst Mode

The SSRAM can be addressed in burst mode for faster speed. In burst mode, the address for the
first data is placed on the address bus. The three following data blocks are addressed by an inter-
nal built-in counter. Data is available at the microprocessor clock rate. Figure 8-21 shows SSRAM
timing. Interleaved burst configurations may be used in Pentium applications or linear burst con-
figurations for PowerPC applications.

8-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

SRAMs

Asynchronous Synchronous Special Non-Volatile

• Low Speed • Interleaved Versus • Multiport • Non-Volatile RAM

• Medium Speed Linear Burst • FIFO (NVRAM)

• High Speed • Flow-Through Versus • Cache Tag • Battery-Back SRAM

Pipelined (BRAM)
• ZBT (Zero Bus Turnaround)
• Late-Write
• DDR (Double Data Rate)
• Dual Port
Source: ICE, "Memory 1997" 22454

Figure 8-17. Overview of SRAM Types

N.C. 1 32 VDD
A15 2 31 A16
A14 3 30 CS2
A12 4 29 WE
I/O0 A7 5 28 A13
Input Buffer
A6 6 27 A8
A10 I/O1
A5 7 26 A9
A9
Row Decoder

A8 I/O2 A4 8 25 A11
Sense Amps

A7 A3 9 24 OE
A6 I/O3
512 x 512 A2 10 23 A10
A5
A4 Array
I/O4 A1 11 22 CS1
A3
A0 12 21 I/O8
A2
I/O5 I/O1 13 20 I/O7

CE I/O6 I/O2 14 19 I/O6

Power
WE Column I/O3 15 18 I/O5
Down
Decoder I/O7 VSS 16 17 I/O4
OE
A14
A13
A12
A11
A1
A0

Logic Block Diagram Pin Configuration

Source: Cypress/ICE, "Memory 1997" 22458

Figure 8-18. Typical SRAM

Flow-Through SRAM

Flow-through operation is accomplished by gating the output registers with the output clock. This
dual clock operation provides control of the data out window.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-13

 SRAM Technology

64-bit CPU

32-bit CPU

16-bit CPU
With Cache

Standard
SRAM
Sync. Burst SRAM
Non Cache

1987 1990 1993 1996 1999

Year
Source: Mitsubishi/ICE, "Memory 1997" 20429A

Figure 8-19. Trend of PC Cache SRAM

/ADSC
/ADSP
Address 15 13 15

/BWE
/BW4
/BW3
/BW2
/BW1

/ADV
/CE1

/CE3
VDD

CLK
VSS

/GW
15 CE2

/OE
Registers
A6
A7

A8
A9
A0-A14
A0 A1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
ADV D0 D1 A0+
CLK Binary Q0 N.C. 1 80 N.C.
Counter
A1+ I/O 17 2 79 I/O 16
ADSC Load Q1 I/O 18 3 78 I/O 15

ADSP VDDQ 4 77 VDDQ

8 VSSQ 5 76 VSSQ
Byte 4 Byte 4 8 I/O 19 6 75 I/O 14
Write Write
I/O 20 7 74 I/O 13
Register Driver
I/O 21 8 73 I/O 12
BW4
I/O 22 9 72 I/O 11
8
VSSQ 10 71 VSSQ
Byte 3 Byte 3 8
Write Write VDDQ 11 70 VDDQ
Register Driver 32K x 32 I/O 23 12 69 I/O 10
Memory I/O 24 13 68 I/O 9
BW3
Array
8 N.C. 14 67 VSS
Byte 2 Byte 2 8 VDD 15 66 N.C.
Write Write N.C. 16 65 VDD
Register Driver VSS 17 64 ZZ
BW2 I/O 25 18 63 I/O 8
8 I/O 26 19 62 I/O 7
Byte 1 Byte 1 8 VDDQ 20 61 VDDQ
Write Write
VSSQ 21 60 VSSQ
Register Driver
32 I/O 27 22 59 I/O 6
BW1
I/O 28 23 58 I/O 5

Chip Sense I/O 29 24 57 I/O 4

Enable Amps I/O 30 25 56 I/O 3
CE Register VSSQ 26 55 VSSQ
CE2 32
32 VDDQ 27 54 VDDQ
CE2
I/O 31 28 53 I/O 2
OE Output I/O 32 29 52 I/O 1
Buffers N.C. 30 51 N.C.
Input Data
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Registers
32
/LBO
A5
A4
A3
A2
A1
A0
N.C.
N.C.
VSS
VDD
N.C.
N.C.
A10
A11
A12
A13
A14
N.C.
N.C.

32
DQ0-DQ35

Logic Block Diagram Pin Configuration

Source: Hitachi/ICE, "Memory 1997" 22457

Figure 8-20. Typical SSRAM

8-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

SYNCHRONOUS MODE

CLOCK

Address

Output

BURST MODE

Address ,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
Output

Source: ICE, "Memory 1997" 19955A

Figure 8-21. SSRAM Timing

Pipelined SRAMs

Pipelined SRAMs (sometimes called register to register mode SRAMs) add a register between the
memory array and the output. Pipelined SRAMs are less expensive than standard SRAMs for
equivalent electrical performance. The pipelined design does not require the aggressive manu-
facturing process of a standard SRAM, which contributes to its better overall yield. Figure 8-22
shows the architecture differences between a flow-through and a pipelined SRAM.

Figure 8-23 shows burst timing for both pipelined and standard SRAMs. With the pipelined
SRAM, a four-word burst read takes five clock cycles. With a standard synchronous SRAM, the
same four-word burst read takes four clock cycles.

Figure 8-24 shows the SRAM performance comparison of these same products. Above 66MHz,
pipelined SRAMs have an advantage by allowing single-cycle access for burst cycles after the first
read. However, pipelined SRAMs require a one-cycle delay when switching from reads to writes
in order to prevent bus contention.

Late-Write SRAM

Late-write SRAM requires the input data only at the end of the cycle.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-15

 SRAM Technology

Clock
Control

Register Dout

PIPELINED

Control

Dout

FLOW-THROUGH

Source: ICE, "Memory 1997" 22608

Figure 8-22. Pipelined Versus Flow-Through Architectures

Clock 1 Clock 2 Clock3 Clock 4 Clock 5

Clock

Address A A+1 A+2 A+3

Data Data A Data A+1 Data A+2 Data A+3

A 4-word burst read from pipelined SRAMs

Clock 1 Clock 2 Clock3 Clock 4 Clock 5

,,,,,,,
Clock

Address A A+1 A+2 A+3

Data Data A Data A+1 Data A+2 Data A+3

A 4-word burst read from synchronous SRAMs

Source: Electronic Design/ICE, "Memory 1997" 20863

Figure 8-23. Pipelined Versus Non-Pipelined Timings

8-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

3.3V 32K x 8 32K x 32 Pipelined 32K x 32 Non-Pipelined

Bus
Performance Performance Performance
Frequency Speed Cycle Access Cycle
Banks
(ns) Read Write Time Read Write Time Time Read Write

50 20 1 3-2-2-2 4-2-2-2 20 3-1-1-1 2-1-1-1 12 20 2-1-1-1 2-1-1-1

60 15 1 3-3-3-3 4-3-3-3 16.7 3-1-1-1 2-1-1-1 10 16.7 2-1-1-1 2-1-1-1

2 3-2-2-2 4-2-2-2

66 12 1 3-3-3-3 4-4-4-4 15 3-1-1-1 2-1-1-1 9 15 2-1-1-1 2-1-1-1

15 2 3-2-2-2 4-2-2-2

75 15 2 3-2-2-2 4-2-2-2 13.3 3-1-1-1 2-1-1-1 9 13.3 3-2-2-2 3-2-2-2

83 12 2 3-2-2-2 4-2-2-2 12 3-1-1-1 2-1-1-1 9 12 3-2-2-2 3-2-2-2

100 10 2 3-2-2-2 4-2-2-2 10 3-1-1-1 2-1-1-1 9 10 3-2-2-2 3-2-2-2

125 8 2 3-2-2-2 4-2-2-2 8 3-1-1-1 2-1-1-1 9 8 3-2-2-2 3-2-2-2

Source: Micron/ICE, "Memory 1997" 20864

Figure 8-24. SRAM Performance Comparison

ZBT (Zero Bus Turn-around)

The ZBT (zero bus turn-around) is designed to eliminate dead cycles when turning the bus around
between read and writes and reads. Figure 8-25 shows a bandwidth comparison between the
PBSRAM (pipelined burst SRAM), the late-write SRAM and the ZBT SRAM architectures.

Device Clock Speed Bus Bandwidth

SRAM
Configuration (MHz) Utilization (Mbytes/sec)

PBSRAM 128K x 36 bits 100 50% 200

Late-Write 128K x 36 bits 100 67% 268

SRAM

ZBT SRAM 128K x 36 bits 100 100% 400

Source: ICE, "Memory 1997" 22609

Figure 8-25. SSRAM Bandwidth Comparison

DDR (Double Data Rate) SRAMs

DDR SRAMs boost the performance of the device by transferring data on both edges of the clock.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-17

SRAM Technology

Cache Tag RAMs

The implementation of cache memory requires the use of special circuits that keep track of which
data is in both the SRAM cache memory and the main memory (DRAM). This function acts like a
directory that tells the CPU what is or is not in cache. The directory function can be designed with
standard logic components plus small (and very fast) SRAM chips for the data storage. An alter-
native is the use of special memory chips called cache tag RAMs, which perform the entire func-
tion. Figure 8-26 shows both the cache tag RAM and the cache buffer RAM along with the main
memory and the CPU (processor). As processor speeds increase, the demands on cache tag and
buffer chips increase as well. Figure 8-27 shows the internal block diagram of a cache-tag SRAM.

Data Bus

Processor Main
Memory
Cache Buffer
RAM

Address Bus

Cache Tag
RAM

Source: TI/ICE, "Memory 1997" 18472

Figure 8-26. Typical Memory System With Cache

FIFO SRAMs

A FIFO (first in, first out) memory is a specialized memory used for temporary storage, which aids
in the timing of non-synchronized events. A good example of this is the interface between a com-
puter system and a Local Area Network (LAN). Figure 8-28 shows the interface between a com-
puter system and a LAN using a FIFO memory to buffer the data.

Synchronous and asynchronous FIFOs are available. Figures 8-29 and 8-30 show the block dia-
grams of these two configurations. Asynchronous FIFOs encounter some problems when used in
high-speed systems. One problem is that the read and write clock signals must often be specially
shaped to achieve high performance. Another problem is the asynchronous nature of the flags. A
synchronous FIFO is made by combining an asynchronous FIFO with registers. For an equivalent
level of technology, synchronous FIFOs will be faster.

8-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

A0 VCC
65,356-Bit GND
Address
Memory
Decoder
Array
A12

RESET
I/O0-7 8
I/O Control

WE
Control Compa-
OE rator
Logic
CS

Match (Open Drain)

Source: IDT/ICE, "Memory 1997" 20865

Figure 8-27. Block Diagram of Cache-Tag SRAM

Microprocessor

LAN

System Bus Disk

Drive

FIFO

Memory

Source: IDT/ICE, "Memory 1997" 18804

Figure 8-28. FIFO Memory Solution for File Servers

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-19

SRAM Technology

Write Data

Write Clock Write

Write Data
Address
Write Enable Register
Counter
Write Latch

FF
Full
Write
Pulse Dual Port RAM Array Flag
Gen 4096 Words x 18 Bits Logic

Empty
FF

Read Enable
Read Address Read Data
Read Clock Counter Register

Read Data
Source: Paradigm/ICE, "Memory 1997" 20866

Figure 8-29. Synchronous FIFO Block Diagram

Write Data
Inhibit
Write Clock Write Counter

Full
Dual Port RAM Array Flag
4096 Words x 18 Bits Logic
Empty

Read Clock Read Counter

Inhibit

Read Data
Source: Paradigm/ICE, "Memory 1997" 20867

Figure 8-30. Asynchronous FIFO Block Diagram

Multiport SRAMs

Multiport fast SRAMs (usually two port, but sometimes four port) are specially designed chips
using fast SRAM memory cells, but with special on-chip circuitry that allows multiple ports
(paths) to access the same data at the same time.

8-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

Figure 8-31 shows such an application with four CPUs sharing a single memory. Each cell in the
memory uses an additional six transistors to allow the four CPUs to access the data, (i.e., a 10T cell
in place of a 4T cell). Figure 8-32 shows the block diagram of a 4-port SRAM.

CPU #1 CPU #2

4-Port
SRAM

CPU #3 CPU #4

Source: IDT/ICE, "Memory 1997" 18805

Figure 8-31. Shared Memory Using 4-Port SRAM

Shadow RAMs

Shadow RAMs, also called NOVROMs, NVRAMs, or NVSRAMs, integrate SRAM and EEPROM
technologies on the same chip. In normal operation, the CPU will read and write data to the
SRAM. This will take place at normal memory speeds. However, if the shadow RAM detects that
a power failure is beginning, the special circuits on the chip will quickly (in a few milliseconds)
copy the data from the SRAM section to the EEPROM section of the chip, thus preserving the data.
When power is restored, the data is copied from the EEPROM back to the SRAM, and operations
can continue as if there was no interruption. Figure 8-33 shows the schematic of one of these
devices. Shadow RAMs have low densities, since SRAM and EEPROM are on the same chip.

Battery-Backed SRAMs

SRAMs can be designed to have a sleep mode where the data is retained while the power con-
sumption is very low. One such device is the battery-backed SRAM, which features a small bat-
tery in the SRAM package. Battery-backed SRAMs (BRAMs), also called zero-power SRAMs,
combine an SRAM and a small lithium battery. BRAMs can be very cost effective, with retention
times greater than five years. Notebook and laptop computers have this “sleep” feature, but uti-
lize the regular system battery for SRAM backup.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-21

SRAM Technology

R/WP1 R/WP4
CEP1 CEP4

OEP1 OEP4

I/O0P1-I/O7P1 Column Column

I/O0P4-I/O7P4
I/O I/O

Port 1 Port 4
Address Address
A0P1-A11P1 A0P4-A11P4
Decode Decode
Logic Logic
Memory
Array
Port 2 Port 3
Address Address
A0P2-A11P2 A0P3-A11P3
Decode Decode
Logic Logic

Column Column
I/O0P2-I/O7P2 I/O0P3-I/O7P3
I/O I/O

OEP2 OEP3

CEP2 CEP3
R/WP2 R/WP3

Source: IDT/ICE, "Memory 1997" 20868

Figure 8-32. Block Diagram of a 4-Port DRAM

Figure 8-34 shows a typical BRAM block diagram. A control circuit monitors the single 5V power
supply. When VCC is out of tolerance, the circuit write protects the SRAM. When VCC falls
below approximately 3V, the control circuit connects the battery which maintains data and clock
operation until valid power returns.

RELIABILITY CONCERNS

For power consumption purposes, designers have reduced the load currents in the 4T cell struc-
tures by raising the value of the load resistance. As a result, the energy required to switch the cell
to the opposite state is decreased. This, in turn, has made the devices more sensitive to alpha par-
ticle radiation (soft error). The TFT cell reduces this susceptibility, as the active load has a low
resistance when the TFT is “on,” and a much higher resistance when the TFT is “off.” Due to
process complexity, the TFT design is not widely used today.

8-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 SRAM Technology

Nonvolatile
EEPROM
Memory Array

Store

Row SRAM
Select Rows
Memory Array

Array
A Recall

Store Control
Recall Logic
Column
I/O Circuits
I/O

Input
Data Column Select
Control

I/O

A A

CS

WE
Source: Xicor/ICE, "Memory 1997" 18479

Figure 8-33. Block Diagram of the Xicor NOVRAM Family

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SRAM Technology

A0-A10

Lithium
DQ0-DQ7
Cell Power 2K x 8
Voltage Sense SRAM Array
and
Switching VPFD E
Circuitry
W

VCC VSS
Source: SGS-Thomson/ICE, "Memory 1997" 20831A

Figure 8-34. Block Diagram of a Typical BRAM

8-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION