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Software Digital-Down-Converter Design and Optimization for DVB-T Systems

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 CTRQ 2012 : The Fifth International Conference on Communication Theory, Reliability, and Quality of Service

Software Digital-Down-Converter Design and Optimization for DVB-T Systems

Shu-Ming Tseng Jian-Cheng Yu Zheng-Hau Lin
Graduate Institute of Computer and Graduate Institute of Computer and Graduate Institute of Computer and
Communication Engineering Communication Engineering Communication Engineering
National Taipei University of National Taipei University of National Taipei University of
Technology Technology Technology
Taipei, Taiwan Taipei, Taiwan Taipei, Taiwan
[email protected] [email protected] [email protected]

Abstract –In this paper, a novel Digital-Down-Converter (DDC)

architecture for PC-based software Digital Video Broadcasting-
RF IF Baseband
Terrestrial (DVB-T) receiver is proposed. The sampling rate of
A/D is 192/7 MHz and the order of the lowpass FIR filter is seven
(8 coefficients) in DDC. Furthermore, the Combining of the Mixer RF SAW filter Tuner+
DDC Demodulation TS
IF (BPF) A/D
and Filter (CMF) is also proposed, including the pre-processing of
mixer and filter coefficients and storing the results in a look-up
IF = 36.16MHz IF = 32/7MHz IF = 0Hz
table. If the input data of length is N, the proposed CMF scheme fs = 192/7MHz fs = 48/7MHz
has 2N multiplications, while the previous architecture, which does or 20MHz
not pre-process the mixer and filter coefficient together in advance,
Hardware Software
has 3N multiplications. Finally, the algorithms also are optimized
in assembly code to satisfy DVB-T real-time reception requirement. Figure 1. The structure of DVB-T receiver

Keywords- DVB-T; DDC; Decimate; Real-time.

The rest of this paper is organized as follows: In Section II,
the system model of DDC is presented. The decision of A/D
I. INTRODUCTION
sampling rate is described in Section III. The proposed CMF
The structure of the receiver end of Digital Video scheme for DDC is described in details in Section IV. The CMF
Broadcasting –Terrestrial (DVB-T) system [1] is shown in optimization is presented in Section V. Performance discussion
Figure 1. The Digital Down Converter (DDC) is an important is described in Section VI. Finally, we conclude in Section VII.
part of DVB-T system; it converts the Intermediate Frequency
(IF) signal into baseband, reduces the signal sampling rate and II. SYSTEM MODEL
then makes it easy for the later real time demodulation. The
The previous of DDC is introduced in Figure 2. According
traditional DDC in DVB-T system was made by hardware
to [6], received signal s (n) is transformed to baseband by mixer
circuits [2] [3]. However, it is not easy to be integrated and
first:
modified. The most important benefit of Software Radio (SR)
research is that people can modify and change the signal cos( 2f IF )
processing procedure, the algorithm, and the result can be easily
Lowpass
tested. Hence, there are some researches implemented DDC by FIR
↓R I (m)
software [4] [5].
In Figure 1, the IF generated by the tuner is 32/7MHz,
defined by the DVB-T standard [1]. Besides, the sampling rate s(n) x(n) k (n)
of DDC output in DVB-T standard must be 48/7MHz [1]. The
previous DDC structure is shown in Figure 2, it composes of Lowpass
↓R Q(m)
FIR
mixer 、 lowpass Finite Impulse Response (FIR) filter and
down-sampling. sin(2f IF )
A Combining the Mixer and Filter (CMF) method is m=n/R
mixer filter
proposed. In other words, the mixer coefficients and filter
coefficients are multiplied and the results are stored in a look- Figure 2. The DDC of previous structure
up table, as shown in (5). Furthermore, The CMF algorithms
also are optimized in assembly code. The proposed CMF x(n)  s (n) * exp(  j 2 * f IF * (n / f AD )) , 1  n  N (1)
scheme combines the mixer and filter operations. Hence, it can
reduce the computational complexity by one third. Assume the where N is the length of DDC input data, fIF and fAD is IF and
input data of length N, the previous scheme has 3N sampling rate of A/D, respectively. The IF power level must be
multiplications, but the proposed CMF only has 2N. in the sampling rate range. Once it is lower than the A/D

Copyright (c) IARIA, 2012. ISBN: 978-1-61208-192-2 57

 CTRQ 2012 : The Fifth International Conference on Communication Theory, Reliability, and Quality of Service

sampling rate range, the resolution performance will be poor. cos(2πfIF)

On the contrary, if the IF power level is higher than the A/D
sampling rate range, then it will produce distortion in the LPF ↓4 I(real)
system. And then employ a low-pass FIR to avoid aliasing
effect after down-sampling: A/D
k (n)  h(0) x(n)  h(1) x(n  1)    h( M ) x(n  M ) fAD=192/7MH
z LPF ↓4 Q(imag)
M
  h(m) x(n  m)  h(n)  x(n) (2) fs=48/7MHz
m 0 sin(2πfIF)
fIF=32/7MHz
where M is the order of FIR filter, h (n) is the filter coefficients,
Figure 4. Digital-Down-Converter using fs=192/7MHz
and “  ” is linear convolution. Final step is down-sampling; R
means the down-sampling rate. After down-sampling, the data The environment of the hardware whose specification is
stream will satisfy the required sampling rate of DVB-T listed in Table I. As we know, the case A has lots of additional
standard. up-sampling computations. From Table II, the case B can save
much more time than case A.
III. CHOICE OF A/D SAMPLING RATE
In Figure 3, most of fAD is following the commercial TABLE I. HARDWARE LIST
specification: 20MHz [5] [7] to record data. According to
DVB-T standard [1], the IF of tuner is 32/7MHz. Besides, the Item Model
sampling rate of DDC output in DVB-T standard must be CPU Intel® Core™ i7-2600K (3.40GHz)
48/7MHz [1]. Memory DDR2 800 2GB x 2
cos(2πfIF) Main board ASUS P8H67-M PRO Rev 1.xx
Graphic card n.a
↑12 LPF ↓35 I(real)
TABLE II. THE ELAPSED TIMES OF DIFFERENT FAD (IN MATLAB)
A/D
Elapsed time(s)
fAD=20MHz
↑12 LPF ↓35 Q(imag) A. fAD = 20MHz 441.28
fs=240MHz fs=48/7MHz
B. fAD = 192/7MHz 175.55
sin(2πfIF)
fIF=32/7MHz IV. PROPOSED CMF SCHEME

Figure 3. Digital-Down-Converter in [5] [10] In this section, the new CMF scheme is proposed to simplify
the DDC computation. The architecture without proposed CMF
Because these three (20, 32/7, 48/7) are not in a multiple scheme is shown in Figure 4. Because fIF / fAD = 32/7 ÷ 192/7 =
relationship, it will increase computational complexity. 1/6, we have:
In [8], fAD is 4 times as much as IF; it could simplify the x(n)  s(n) * exp(  j 2 * (n *1 / 6)) , 1  n  N (3)
calculation of mixer. Moreover, integer decimation is proposed
in [9]. According to [8] [9], changing the fAD to be multiple of From (3), the exp( j 2 * (n *1/ 6)) only have possible 6
IF or the sampling rate of DDC output would simplify the DDC
values. Furthermore, the filter only has M+1 coefficient.
computation. Hence, the 192/7MHz of fAD is chosen. It will
Substitute (3) into (2) and we get:
match the multiple relation in [8] [9] simultaneously. For
architecture of fAD is 192/7MHz, as shown in Figure 4. This M
architecture avoids up-sampling calculation compared with k (n)   s(n  m) * w(( n  m) mod 6)* h(m), 0  n  N  1
Figure 3. The structure of fAD = 192/7MHz is simpler than fAD = m 0
20MHz’s. Thus, the 192/7MHz is chosen as fAD in our structure. (4)
where w (n) = exp( j 2 * (n *1/ 6)) is defined. In order to
save the elapsed time from mixer calculation, the formula (4)
will be modified as below:

Copyright (c) IARIA, 2012. ISBN: 978-1-61208-192-2 58

 CTRQ 2012 : The Fifth International Conference on Communication Theory, Reliability, and Quality of Service

M V. CMF OPTIMIZATION AND IMPLEMENT IN ASSEMBLY

k (n)   s (n  m) * w(( n  m) mod 6) * h(m), 0  n  N  1
m 0
A. Choice of filter order
M
  s (n  m) * c(m), 0  n  N  1 (5) The architecture is implemented on a personal computer by
m 0 software; the most important goal is fast enough to process the
data. As we know, the XMM register is formed 128 bits. Hence,
The major contribution of this paper is combining the w (n) it could contain 16 signed byte data. In order to utilize the
and h (m) in (5) is a look-up table in advance, then s (n) XMM registers efficiently, 7 orders FIR is chosen. In other
calculates the linear convolution with c (m) will achieve the words, there are 8 filter coefficients. The data type of designed
mixer and filter calculations. Hence, it can save the time for filter coefficients is float. The look-up table coefficients to be
computation. Because the number of mixer coefficients is not integer which data type is byte data. The two groups of look-up
equal to filter’s, we choose the least common multiple of these table coefficients could be built in a XMM register. Thus, we
two numbers: 24. Figure 5 shows the combination of look-up achieve two linear convolutions in a XMM register. For
table between mixer and filter. Here we assume M = 7. We also example, a filter instance design for DDC in [10] is 9 orders (10
set M = 7 in our architecture, the detail reason will be described coefficients); a XMM register can only hold one group of filter
in next section. coefficients. As a result, it can reduce the computational
Observing Figure 5, The 4 groups of mixer coefficients and complexity.
3 groups of filter coefficients are used to form the look-up table.
The look-up table will be divided into three parts: ①、② and ③, B. Assembly implement
so the received signal s(n) operate (5) with ①、 ② and ③ The parallel processing instructions is used in assembly and
circularly. The next step is down-sampling 4 times. This part XMM registers. The assembly computation is mainly between
could be combined with (5). For each 4 data input in DDC, it the XMM registers. Besides, the new DDC calculation is based
will generate 1 data. Thus, It could avoid 3/4 calculations form on the linear convolution in (5). Hence, the two Supplemental
FIR. Streaming SIMD Extensions 3 (SSSE3) instructions are chosen
to achieve PMADDUBSW and PHADDSW [11] which
described as below.
PMADDUBSW: Multiply and Add Packed Signed and
Mixer w(0-5) w(0-5) w(0-5) w(0-5)
Unsigned Bytes.
PHADDSW: Packed Horizontal Add and Saturate Words.
* * * These two instructions are shown in Figure 7 and Figure 8:

Filter h(0-7) h(0-7) h(0-7)

Ex: PMADDUBSW xmm1, xmm2

① ② ③ xmm1(byte) a1 a2 a3 a4 …… a13 a14 a15 a16

Figure 5. Look-up table of mixer and filter combination

xmm2(byte) b1 b2 b3 b4 …… b13 b14 b15 b16
According to (5), the block diagram of proposed algorithm:
CMF is shown in Figure 6. ↓PMADDUBSW

a1b1+ a3b3+ a13b13+ a15b16+

xmm1(word) …… a14b14 a15b16
a2b2 a4b4
c(m) ↓R I (m)
Figure 7. SIMD instruction: PMADDUBSW

s(n) k (n)
Ex: PHADDSW xmm1, xmm2

c(m) ↓R Q(m) xmm1(word) a1 a2 …… a7 a8

mixer + filter
m=n/R xmm2(word) b1 b2 …… b7 b8

↓PHADDSW
Figure 6. The block diagram of proposed CMF
xmm1(word) a1+a2 a3+a4 …… b5+b6 b7+b8

Figure 8. SIMD instruction: PHADDSW

Copyright (c) IARIA, 2012. ISBN: 978-1-61208-192-2 59

 CTRQ 2012 : The Fifth International Conference on Communication Theory, Reliability, and Quality of Service

The “PMADDUBSW” is used to multiply s (n) and c (m) in TABLE III. THE ELAPSED TIMES OF FAD =192/7MHZ USE CMF OR NOT
(5) together. The “PHADDSW” is used twice to sum the results (IN MATLAB)
in all. The data type of s (n) and c (m) in (5) is unsigned byte
and signed byte, respectively. Because of the data type, only Elapsed time(s) Multiplication
“PMADDUBSW” of SSSE3 instructions could achieve the fAD =192/7MHz (No) 175.55 3N
multiplication between s (n) and c (m). The data type of fAD =192/7MHz (Yes) 104.89 2N
“PMADDUBSW” outputs is signed word. Furthermore, the The optimization result of proposed DDC algorithm is
“PHADDSW” of SSSE3 instructions are used to add the shown in Table IV. In order to use all 16 XMM registers, the
outputs horizontally. The detail linear convolution example Windows 7 (64 bits) is chosen as system OS. Besides, the
achieved by these two instructions is shown in Figure 9. Microsoft Visual Studio 2010(Team Suite edition) is used as
Ex: a(x)  b(y), 1≦x,y≦8 development tool. It has the Performance Explorer to analyze
the elapsed time of proposed DDC in assembly code and C
a a1 a2 a7 a8 code.
TABLE IV. THE ELAPSED TIMES OF FAD =192/7MHZ (IN C CODE AND
b b1 b2 b7 b8 ASSEMBLY CODE)

↓PMADDUBSW
Function name Elapsed time(ms)
a1b1+a2b2 a3b3+a4b4 a5b5+a6b6 a7b7+a8b8 ddc (C) 88.07
ddc_asm (Assembly) 20.81
↓PHADDSW

a1b1+…+a4b4 a5b5+…+a8b8 The DDC takes 20.81ms to decode 84Mbytes data.

84Mbytes/20.81ms = 4.04Gbytes/sec. According to fAD =
↓PHADDSW
192/7MHz, the real time DVB-T signal in Taiwan has
a1b1+…+a8b8 27Mbytes/sec. Hence, the proposed DDC only takes 0.67%
CPU loading.
Figure 9. Linear convolution by “PMADDUBSW”,”PHADDSW”
For the DVB-T software radio implement, the elapsed time
of demodulation part is shown in Table V. The length of
decoding data is 3 sec. However, the total elapsed time of
VI. PERFORMANCE OF OUR DDC demodulation part is 1541.89ms. Thus, the DVB-T real-time
The new DDC algorithm will be compared with the previous computation can be implemented (1.562sec < 3sec).
architecture. First, the DDC calculation is presented by Matlab.
Then, we could know the improvement of CMF method. The TABLE V. THE ELAPSED TIME OF DEMODULATION PART
quantity of input data is 84Mbytes; Table I is our hardware
simulation environment. Block Elapsed Time (ms)
Table III presents the elapsed time about fAD = 192/7MHz Time & Frequency
use CMF or not. The mixer and filter coefficient is multiplied in 63.66
Synchronize
advance; DDC algorithm could be simpler in (5). In our case, if Remove CP & FFT 67.82
the number of DDC input data is N, there will be N Channel estimation 145.87
multiplications in (3). Moreover, our FIR filter is 7 orders, so Deinner & Depuncher 54.49
there has 8N multiplications generated by linear convolution of Deoutter interleave 17.93
(5). In fact, the down-sampling part usually combines with the Demodulator 8.93
FIR. The 8N multiplications will reduce to 2N because of Viterbi decoder 1096.79
down-sampling: 4 times. The number of multiplications in the RS Decoder 30.67
previous DDC is 3N (=N+2N). The CMF combines mixer and Descrambler 0.92
filter, so the number of multiplications could be reduced to 2N
Frame Synchronize 8.58
additionally. Thus, the CMF can save much more elapsed time
Program Initialization 27.52
than the previous DDC algorithm. As a result, the new DDC
Phase Compensation 8.44
algorithm can save about 40% elapsed time.
C++ standard library 10.27
Total elapsed time 1541.89

VII. CONCLUSION
In this paper, the new DDC architecture is designed for fAD =
192/7MHz and the algorithms are optimized by multiplying the

Copyright (c) IARIA, 2012. ISBN: 978-1-61208-192-2 60

 CTRQ 2012 : The Fifth International Conference on Communication Theory, Reliability, and Quality of Service

mixer and filter recorded in a look-up table in advance. The [12] “Intel® 64 and IA-32 Architectures Software Developer's Manual
proposed CMF can save the additional N multiplications. Volume 1,”
Moreover, it is also optimized by assembly code. As a result, http://download.intel.com/design/processor/manuals/253665.pdf
the decoding rate of the proposed system is greater than the [13] “Intel® 64 and IA-32 Architectures Software Developer's Manual
required bit rate of the real-time DVB-T. The new system is fast Volume 2A,”
enough to decode the DVB-T signal in real-time. http://download.intel.com/design/processor/manuals/253666.pdf
Finally, the new method can save more 40% time than the [14] “Intel® 64 and IA-32 Architectures Software Developer's Manual
previous architecture. It only takes 20.81ms to decode Volume 2B,”
84Mbytes data. To sum up, the new DDC coding rate is http://download.intel.com/design/processor/manuals/253667.pdf
4.04Gbytes/sec.

ACKNOWLEDGMENT
The authors would like to thank all colleagues and students
who contributed to this study.
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Copyright (c) IARIA, 2012. ISBN: 978-1-61208-192-2 61

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