2016 3rd International Conference on Information Science and Control Engineering

An FPGA based Multi-functional Signal Generator using SOPC Design Methodology

Ruan Yue, Yao Wen-ji, Wang Jinming

Zhejiang Shuren University
Hangzhou, Zhejiang Province, China
[email protected]; [email protected]; [email protected]

Abstract—This paper presents an FPGA based miniature, multi- modules necessary to the system, such as DDS, memory,
functional signal generator with digital controller inside to adapt keyboard and display controller are all embedded to an FPGA
applications such as wireless sensor network (WSN) and software chip by HDL design. Nios II’s Avalon bus main port
define radio (SDR) system. To reduce design complexity and (instruction and data control port) is then connected with
decrease development time, this work adopts a novel SOPC peripherals such as high-speed D/A converter, function choose
design methodology, which means using embedded soft-core
microprocessor Nios II and EDA tool Quartus II to accomplish
button and LCD display module. This connection is via
design process. Nios II is a configurable and optimizable soft-core Avalon bus. In this way, the system realized is flexible,
CPU which is embedded in FPGA. Using characteristics of Nios scalable, extensible, upgradable and has online programmable
II, we put together every logical units that system needs and function.
implant them into a single FPGA chip. Then uses the Avalon bus
to connect with Nios II's Avalon bus main port (instruction and II. OVERALL SYSTEM ARCHITECTURE
data control port) with function choose keys, LED display units
and other peripheral equipment. Realize a signal generator The proposed system of multi-functional signal generator
system that is flexible to reduce, extend, with low power can output various waveform, with frequency ranging from
consumption, and has System on Programmable Chip (SOPC) 1Hz to 20MHz. The system is composed by two parts: FPGA
function which means the system’s software and hardware is hardware design and software design based on hardware. The
online programmable and reconfigurable. The system design whole digital part of the design is implemented by an FPGA
process uses SOPC design methodology.
chip. The buttons, LED display and high-speed D/A
Keywords—SOPC, FPGA, signal generator, Nios II, Quartus II converters are peripherals and are ready-made on FPGA
development board.
I. INTRODUCTION Figure 1 below shows the overall architecture of the
A multi-functional signal generator is a device that can proposed system.
output various types of signals, such as sine wave, saw-tooth
Inside the FPGA, Nios II soft-core CPU performs as
wave, square wave, triangle wave, trapezoidal wave and so on.
controlling core, and DDS IP module as achievement core for
It can also digitally control the slope, gradient, width of the
waveform generation functions. At the same time, other IP
waveform, and has FM & PM functions. As modern electronic
cores are added, such as debug module, UART (Universal
devices become smaller and smaller, while their functions
more and more complex, the multiple-functional signal
generator is designed toward the directions of high integration, FPGA
high reliability and low power consumption. These trends in Debug
Nios II
signal generator design are to cope with applications in rapid Soft-core Module
developing fields such as WSN and SDR. Nowadays, there are
two different ways to implement such kind of signal generator:
one way is using Direct Digital Synthesizer (DDS) ASIC and Button Avalon
FPGA for control, plus high-speed D/A converter. This Key Bus
method is expensive, though with good performance. The
other way is using DDS designed by Hardware Description
Language (HDL) or related soft IP core, plus waveform data 7- PIO
storage memory and MCU to control. In this way, the DDS is segment DAC
LED
implemented by downloading the design to an FPGA chip. display മ 1 ㌫㔏⽪᜿മ
These methods can change traditional design flow in RS232 Figure 1
electronic systems by reducing separation of modules, DAC5651
improve speed, accuracy and reconfiguration. But there still DDS
have inflexible problems when adding peripheral devices such
as MCU or DDS chip, which make the system heterogeneous.
[1][2]
In order to design the fully digital multi-functional
generator as a true SOPC system, we choose the solution using Fig. 1 Proposed System Architecture
Nios II soft processor and Quartus II by Altera. In this design,

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2016IEEE
IEEE 1257
DOI 10.1109/ICISCE.2016.269
Asynchronous Receiver & Transmitter) module used to logic. Users can customize appropriate SOPC system using
communicate with PC, seven-segment LED display decoding SOPC Builder’s wizard-style interface, according to system
and I/O module, and button control module. These IP cores design requirements. As a result, In SOPC design, we can add
can be designed into a single FPGA, making the system highly corresponding peripheral modules outside the CPU core while
integrated. still inside FPGA chip. The connection between peripheral and
In this design, FPGA hardware system is realized by Nios II core is via Avalon bus, thus do not need to modify on
VHDL language, parameterized macro-functional module PCB level. The detailed Nios II hardware design process is
provided by Altera, LPM functions and IP cores in DSP presented in Figure 2. This development process is used to
Builder. Subsystem blocks such as DDS module can also be customize proper CPU and peripheral device, and realize them
designed and synthesized by the above methods. According to via SOPC Builder in Quartus II.
Avalon bus connection specification, OPB (On chip Peripheral Figure 2 below shows the complete design process of
Bus) is added outside the DDS module, which are packaged Nios II application system using SOPC design methodology.
together into a customized IP core. This IP core is added in the
FPGA hardware system and generates digital control signals.
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The peripheral circuit contains keyboard, LCD display and Develop drivers or
high-speed D/A converter DAC5651. The peripheral circuit is Customized peripheral, subroutines for
used to accomplish control input and I/O display, transform instructions customized hardware
waveform data to analog waveform. Thus realizes a complete (Using SOPC Builder and
module
SOPC signal generator. Quartus II)
( Using SOPC Builder )

The software design based on Nios II is similar to Customize

traditional embedded software development process. First, Define Nios II system SDK OS Transplant
write program codes according to CPU’s instruction set and module (SOPC Builder ˅
( SOPC Builder ) (SOPC
compilation environment. After compiling, programming the
code into FPGA and debug it. Builder)
Write Application
Generate Nios II programs
III. HARDWARE DESIGN system module ˄SOPC Builder˅
( SOPCBuilder ˅
The hardware design adopts the methodology of SOPC,
with the whole SOPC system divided into 3 parts: FPGA, Compile, connect,
memory and external interfaces. In the design process, we use Lock pins, hardware debug
compilation ˄SOPC Builder˅
Altera’s Cyclone® EP1C3TC144 FPGA chip. Quartus II IDE
Quartus II Downloading
(Integrated Development Environment) with SOPC Builder
toolkit is also used to accomplish the FPGA hardware system
and software based on FPGA.
FPGA Hardware Software Prototype
Prototype Design Design
A. Nios II System Hardware Development Process
( Nios Development ( Nios Development
The basic software tools used in SOPC system design are Board ) Board )
Quartus II, SOPC Builder, Modelsim, Matlab/DSP Builder
and GNU Pro. Quartus II, an IDE provided by Altera, is used
for synthesis, hardware optimization, fitting, programming
SOPC System
download and hardware tests of Nios II system. SOPC Builder, Implementation
a Nios II embedded processor development toolkit provided based on Nios II
by Altera, is used to realize and generate the configuration,
monitoring and software debugging platform of Nios II system.
Modelsim is used in system functional simulation for the HDL Fig. 2 Nios II System Development Flowchart
description of Nios II generated by SOPC Builder.
Matlab/DSP Builder can be used to design customized B. Specific Hardware System Design
hardware accelerator for Nios II. And GNU Pro is used in
The proposed system in this work is a SOPC system
software debugging.
based on Nios II soft-core. Nios II works as the embedded
In the development of traditional embedded system, the
CPU which controls peripheral modules and devices of the
hardware architecture of CPU is unchangeable. As a result, the
system. The peripheral includes 1 UART port, 8 LEDs with
alterations of peripheral devices are limited by CPU, which
seven segments, 9 buttons, customized DDS IP core and
may lead to a wholly fixed embedded system. When we need
memory used to store waveform data.
to add new peripheral modules, we would either add
Figure 3 below shows the programmable hardware
corresponding peripheral chips or switch to higher level CPUs,
system composed by various IP cores on FPGA. These IP
which is inconvenient. The development of Nios II system is
cores are connected by Avalon Bus, a simple bus architecture
different. Nios II is a flexible customized soft-core CPU, its
designed for connecting on-chip processors and peripherals
peripheral devices are optional IP core or self-customized
together into SOPC system. The Avalon bus is an interface

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that specifies the port connections between master and slave
components, and specifies the timing by which these
components communicate.

Boot Rom
Nios II Soft-
core
Avalon
Bus
Button_PIO

Memory (RAM,
7-segment LED Flash) Fig. 4 DDS Design Diagram
PIO
In Figure 4 above, there are 3 input ports. Port 1 is the
amplitude control word input; port 2 is phase control word
D/A
UART Convert input, and port 3 frequency control word input. These 3 inputs
(RS232 can control the amplitude, phase and frequency of the output
Interface) DDS waveform. The DDS module outputs the controllable
waveform by changing the control words in corresponding
input registers. In the peripheral sphere, I/O interface files are
DŽ generated through SOPC Builder. After that, the bus interface,
DŽ
DŽ
which works as a custom IP, is added outside DDS module
DŽ and successfully mounted to the system bus. The interface can
DŽ
realize communications between DDS module and Nios II,
Fig. 3 Specific Programmable Hardware System while doing Read/Write operations easily. Figure 5 presents
In this proposed system, Nios II core is 32-bit embedded the implementation process between user logic and DDS IP.
soft-core. Boot ROM is made up by embedded RAM block
M4K in FPGA and is used in system boot. GERMS Monitor DDS IP Core
program can be used to debug this module. Button_PIO is
used as PIO interfaces of buttons. 7-segment LED PIO is used DDS Function
IP Interface Files
Logic Module
as LED display interface. UART is a common serial port, and
SOPC system can use it to communicate with PC or other
devices. UART can also be used in Nios II system simulation
and debugging. The program memory is implemented using
SRAMs inside FPGA, and connects to Nios II CPU via LMB PIO
(Local Memory Bus), which realizes Read/Write access from
CPU. IP Interface Files UART
The system is also scalable. In case the RAM inside
FPGA is not enough, we can use Avalon tri-state Bus Bridge DDS Module
DDS IP Core
to connect external SRAM and Flash into the Nios II system.
Here, the SRAM in the system is similar to memory in PC,
while Flash memory similar to HDD. The DDS module is a Mounted on Avalon Bus
self-written IP core. All IP cores used in proposed system can
be customized using SOPC Builder, which means the
parameters of IP cores such as characteristics, storage capacity Fig. 5 DDS IP Implementation Process
and I/O mode can be determined in the options of SOPC
Builder’s software menu. All peripheral IP cores can be After the construction of hardware system using SOPC
connected to Nios II core through on-chip Avalon Bus. Builder, we choose generating SDK development program,
In the system, DDS module is designed by SOPC Builder VHDL system description and simulation files through
and Matlab / DSP Builder. After finishing the detailed design operations in SOPC Builder. Click “Generate” button, SOPC
of DDS module in Matlab/Simulink, DSP builder will Builder will automatically generate customized SOPC system.
automatically convert DDS block diagram to VHDL code. At the same time, HDL files used in Quartus II compilation
Figure 4 shows the detailed diagram of DDS module. are also generated. After that, the generated SOPC system is
transferred as a component in block diagram. The system is
compiled in Quartus II after its pins added and locked. Finally,
the compiled SOF file is programmed into FPGA chip via
JTAG port. At this point, the hardware development process

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of SOPC system based on Nios II is finished. The next work is module to send waveform data to high speed D/A converters.
to design software and debug it in the Nios II embedded Figure 7 below presents the flow diagram of the button
system established in FPGA. processing subroutine.

IV. SOFTWARE DESIGN Button

After the proposed hardware system is compiled in SOPC Processing
Builder and software pack SDK generated, we can then
conduct software design of the system. Read Key
The software architecture is designed as button- Value N
centralized. Operations to LEDs, buttons, D/A converters are
all treated as operations to PIO (button_pio) port registers. The Choose
connections to these peripherals all use PIO way. LED and according to N
DAC use PIO output mode, while button uses input mode. A
key interrupt is set in button PIO. The main program flow
diagram is shown in the following figure. N=1 N=2 N=6

Start Sine Sawtooth Trapezoidal

Wave wave ĂĂ wave
program program program
Initialization

Finish

Read and decide Fig. 7 Button Processing Subroutine Flow Diagram

whether button
state changes N
The main function of the source code is presented as
Y follows:
Button // main function
process #include <excalibur.h>
program
int main(void)

Output signal {int buttons, buttonsLast =0x000F;

and display // button variable, initial value is 0x000F
no_pio*pio= na_button_pio; // button pointer
Fig. 6 Main Program Flow Diagram
// set all the button port as input port
In the main program flow diagram shown above, the Pio->np_piodirection=0;
program is first initialized, which means all the instructions,
status, variables and memory units are reset to initial state. while(1)
After initialization, the program begins key scanning process. { // read the input code of button data port
This process is used to determine whether any key or button is
pressed. If no key is pressed, the program repeats detecting Buttons = pio->np_piodata ;
key pressing event, after a certain time. If any key is pressed, // determine whether a button is pressed
the program turns to button processing subroutine and do
relevant operations. The output signal waveform is sent to if (buttons ! = buttonsLast && buttonsLast= = 0x000F))
display circuits.
{ switch (buttons & 0x000F)
The button processing subroutine is an important block in
{ case 0x000E˗ // SW1, output sine wave
system software design. Almost all functions are realized
using it. This subroutine accomplishes the responses from
buttons, and generates the desired signal waveform by calling
for DDS module. The output signal waveforms can be sine
wave, saw tooth wave, square wave, triangle wave, trapezoidal Break;
wave and so on. After that, the program block orders DDS

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 case 0x000D; // SW2, output saw-tooth wave VI. CONCLUSIONS
In this paper, a highly integrated, multi-functional signal
generator system with digital controller inside is designed. The
system can output various signal waveform with frequency
Break; from 1Hz to 20MHz. The hardware of the system is
implemented on FPGA. In this system, Nios II processor
works as core, with customized DDS IP and necessary
peripheral modules. The main advantage of the proposed
system over traditional one is its hardware and software co-
case 0x000F˗ // no button pressed design using SOPC design methodology. The core
components of signal generator, such as DDS and memory
buttons =buttonsLast =0x000F˗ (waveform storage) are designed using VHDL or IP cores, and
Break; implemented on FPGA. Other functions such as the control of
external devices (such as button, display, DACs), choosing of
default: output waveform types and calculation of waveform
Break; } parameters are implemented via C programming. The program
runs on Nios II CPU inside FPGA and do not need MCUs to
} control FPGA.
// save the current button value to variable buttonsLast The proposed fully digital signal generator based on
SOPC has advantages of hardware re-configurable and
buttonsLast = buttons; }}
flexible, which makes the system design easy to modify and
consummate. The SOPC design methodology also provides a
novel approach to modern electronic system design.
The source file is first compiled in Nios SDK Shell
environment. After compilation passed, it can be downloaded
into FPGA chip. FPGA establishes hardware system based on VII. ACKNOWLEDGEMENT
configuration information, mapping source code into on-chip This work was financially supported by the natural
RAM, finally start Nios II softeare. science foundation of Zhejiang Province (ZJNSF), with
In software design of the system, the display program project number: Y105346.
module is used to display parameters of output waveform such
as frequency, duty cycle, gradient and so on. The display
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Fig. 8 FPGA implementation on oscilloscope

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