2009 第七屆微電子技術發展與應用研討會/系統設計

High-Speed CMOS Chip Design for Manchester and Miller Encoder*

Yu-Cherng Hung, Min-Ming Kuo

Department of Electronic Engineering,
National Chin-Yi University of Technology
E-mail: [email protected], [email protected]

Abstract

In this paper, we propose a modified Manchester and Miller encoder that can
operate in high frequency without a sophisticated circuit structure. Based on the
previous proposed architecture, the study has adopted the concept of parallel
operation to improve data transmission speed. In addition, in this design the technique
of hardware sharing is adopted to reduce the number of transistors. The study uses the
TSMC CMOS 0.35 μm 2P4M process technology. The simulation result of HSPICE
indicates that it functions successfully and works at 200-MHz speed. The average
power consumption of the circuit under room temperature is 549 μW. The total core
area is 70.7 μm × 72.2 μm. As expected, the circuit can be easily integrated into
Radio Frequency Identification (RFID) application.

Keywords: RFID, Manchester code, Miller code

I. Introduction

Based on the convenience and economic benefits, radio frequency identification

(RFID) applications have been greatly utilized in recent years. However, RFID is not
a new technique. The earliest inception was applied to identify military aircrafts
during the Second World War. Along with technical progress and continuous
improvement, RFID appears in new fields and derives more new applications, such as
in human tracking or biomedicine (with a sensor) [1], [2].

In RFID system, the data through modulation is transmitted between the tag and
reader. In order to reduce error rate and improve efficiency, the data is encoded before
being modulated. In general, the Manchester and Miller codes can be applied to
telecommunication and are often used in the RFID system. Figure 1 shows block
diagram of RFID system. The block labeled red marker expresses a function block of

*
This work was supported in part by the Chip Implementation Center and National Science Council,
Taiwan, R.O.C.

415
2009 Conference on Microelectronics Technology & Applications

Manchester or Miller codes. The Miller code itself carries ‘timing’ information, which
can be extracted the clock information in other site, that is, the code with a self-timing
property. Therefore, the Miller code has better performance against noise interference.
The efficiently realization of the Miller code is thus an important research.

In open literature, there are not many researches for design of CMOS circuit in
Miller encoder. Previous designs of encoder circuit were much more sophisticated
than that in this study. A circuit prototyping of Manchester and Miller encoder in this
paper was originated proposed by Shan and Zhou in 2005 [3], [4]. The circuit
provided both Manchester and Miller codes has a simple circuit structure. Based on
this proposed circuit structure, circuit realization and speed improvement are
discussed in this work. Section II describes commonly coding methods in RFID
system. Based on parallel operation and hardware sharing, an improvement CMOS
circuit is shown in Session III. Section IV presents the simulation results. Section V
makes a brief conclusion.

Fig. 1. Structure for RFID system.

II. Coding

The values ‘1’ and ‘0’ in a binary system can be coded in various forms. The
RFID system commonly uses one of the following encoding methods:
Non-Return-to-Zero code (NRZ), Manchester code, and Miller code. The three
encoding methods will be briefly described in this section.

To begin with, a simplest encoding form, that is NRZ code. NRZ uses high
voltage level to represent logic 1 and low voltage level to represent logic 0, similar to
those used by the general digital logic circuit. It is quite simple; however, the code has
no timing information. When the data with a series of ‘1’ bits or ‘0’ bits is transmitted
from sender to receiver, the receiver easily lost synchronous information especially

416
 2009 第七屆微電子技術發展與應用研討會/系統設計

for a high-speed transmission. As a result, the error rate will be increased.

Another code, the Manchester code is also called split-phase coding or
dual-phase coding because it uses the negative falling edge of the level high-to-low
transition to represent logic 0 and the positive rising edge of the level low-to-high to
represent logic 1. Figure 2 shows an example for various codes. Trace 1 is a clock
waveform; trace 2 is a sample of NRZ coding. Trace 3 shows the Manchester code
corresponds to the NRZ coding.

Miller code, however, the logic 1 in a binary system is represented by either the
positive or negative edge of the half cycle. Table 1 summarizes the encoding rules. If
bit i is logic 1, the startup voltage level of bit i does not change, but waveform must
jump after half a cycle. When two zeros are transmitted continuously, the voltage
level of the Miller code will change at the start of the cycle. For example, the trace 4
of Fig. 2 is expressed as Manchester code corresponding to trace 2 Data input. A
relational table of these coding methods lists in Table 2. It is interesting that logic 0
from Table 2 is represented by Miller code 11 or 00. The logic 1 can be represented as
Miller code 01 or 10 depend on the bits status. In our circuit, the circuit can generate
both Manchester code (VM1) and Miller code (VM2).

Table 1 Miller Coding Rules

Bit i-1 Bit i
Miller Coding Rules
(Previous) (Current)
The startup voltage level of bit i does not change, but waveform
X 1
jumps after half a cycle.
The startup voltage level of bit i changes, and does not jump
0 0
after half a cycle.
The startup voltage level of bit i does not change, nor jumps
1 0
after half a cycle.
X: Do not care.

Fig. 2. Waveform sample for various coding.

417
2009 Conference on Microelectronics Technology & Applications

Table 2 Coding Relationship

DATA 1 0 1 1 0 0 1 0
Non-Return-to-Zero 1 0 1 1 0 0 1 0
Manchester Code 01 10 01 01 10 10 01 10
Miller Code 01 00 01 10 00 11 10 00

III. Circuit design and implementation

In the section, the circuit realization for the Miller encoder was designed based
on the rule shown in Table 1. In 2005, Shan and Zhou proposed a circuit structure for
the prototype Manchester and Miller encoder, as shown in Fig. 3 [3]. This circuit
takes the Manchester code (VM1) as the input signal of the T-type flip-flop, which
will output the Miller code (VM2). The circuit is mainly composed of two types of
flip-flop (DFF1 and TFF1) and two logic gates (XOR1 and INV1). In order to
combine two timing signals of Clock and Clock2 (double frequency of Clock), a
T-type flip-flop can be utilized to achieve the frequency division by 2 [5].

Fig. 3. Prototype Manchester and Miller encoder circuit structure.

To further improve the speed of the encoder, two identical encoders operate in
interlaced to improve the overall speed, as shown in Fig. 4. Obviously, it can be
expected that the data throughput rate will double than single stage of Fig. 3. Figure 5
shows the whole circuit diagram in detail. We obtain the advantage of double higher
operation speed, however, at the cost of double hardware area. To optimize the
hardware cost and power consumption, some circuit blocks in Fig.5 can be shared and
further simplified. The grey circuit block shown in Fig. 5 can be simplified and
re-arranged.

Figure 6 shows a modified Manchester and Miller encoder. The operation of the
circuit is described as follows. The data are first switched rapidly in turn into two
individual DFFs by the de-multiplexer stage. Then, the data are processed
sequentially by top data path and bottom data path. After D-type flip-flop, data are
combined as Manchester code (VM1). A single T-flip-flop stage is functional shared

418
 2009 第七屆微電子技術發展與應用研討會/系統設計

between top data path and bottom data path. Finally, Miller codes (VM2) are obtained
at the output of the T-flip-flop stage.

Fig. 4. Conception diagram of double throughput rate.

Fig. 5. Hardware sharing of the encoder.

Fig. 6. Proposed high-speed Manchester and Miller encoder circuit structure.

Fig. 7. Layout of the Entire Core diagram.

419
2009 Conference on Microelectronics Technology & Applications

IV. Simulation result

In the study, we use TSMC CMOS 0.35-μm 2P4M process technology. Figure 7
shows the layout of the experimental chip. HSPICE simulation results show the
operation frequency of the proposed circuit reaches 200 MHz when the operating
voltage is 3.3 V. For input test pattern ‘10110010’, Figure 8 shows the simulation
results for Manchester code (VM1) and Miller code (VM2). It indicates the circuit
correctly achieves the functions shown in Table 2. The characteristics of circuit are
summarized in Table 3.

Fig.8. Simulated Waveform.

Table 3 Characteristics of the proposed circuit

Function Manchester and Miller Encoder
Process technology TSMC 0.35 μm 2P4M 3.3/5 V
32.1 μm × 65.8 μm (Core area)
Chip area
70.7 μm × 72.2 μm (Including the I/O driver)
Number of transistors 94
Supply voltage 3.3 V
Average dynamic power 549 μW
Operation frequency 200 MHz

420
 2009 第七屆微電子技術發展與應用研討會/系統設計

V. Conclusion

Based on the parallel operation and hardware sharing, this paper proposes a
modified Manchester and Miller Encoder. The prototyping structure was realized in
TSMC CMOS 0.35-μm process technology. HSPICE post-layout simulation shows
that the circuit correctly operates at 200 MHz under 3.3 V supply voltage to arrive
Manchester and Miller coding functions. Under room temperature, the average power
consumption of the circuit is 549 μW. The total layout area of the circuit is 70.7 μm ×
72.2 μm. It is expected that it can be integrated into the RFID chip design. The speed
of circuit can be further improved by using dynamic logic in the future.

Acknowledgements

We would like to express our sincere thanks to the Taiwan Semiconductor

Manufacturing Company (TSMC) and Chip Implementation Center (CIC) for
providing the chip manufacturing and related help.

References

[1] K. Finkenzeller, RFID Handbook: Fundamentals and Applicationsin Contactless

Smart Cards and Identification, 2nd ed. New York: Wiley, 2003.
[2] M. Brandl, J. Grabner, K. Kellner, F. Seifert, J. Nicolics, S. Grabner, and G.
Grabner, “A low-cost wireless sensor system and its application in dental
retainers,” IEEE Sensors Journal, vol. 9, no. 3, March 2009.
[3] Shan and Zhou, “A Simple and Practical Manchester and Miller Encoder,”
Electronic Component & Device Applications Journal, 中国电子元件行业协会
和中国电子学会元件分会会刊, China, 2005.
[4] Shan and chai, “Techniques and implementation of Miller encoder in RFID,”
Hefei University of Technology, school of computer & information, China,
2005.
[5] Y.C. Hung, M.M. Kuo, and C.K. Tung, “1.8-V 50-MHz CMOS Manchester and
Miller codes realization for RFID application,” in Proc. 3rd Intelligent Living
Technology Conference (ILT08), Taichung, Taiwan, pp. 1064-1068, June 2008.

421