Processes

A process is a sequence of statements that are executed in the specified order. The process
declaration delimits a sequential domain of the architecture in which the declaration appears.
Processes are used for behavioral descriptions.

Processes are composed of sequential statements, but process declarations are concurrent
statements. The main features of a process are the following:

• It is executed in parallel with other processes;

• It cannot contain concurrent statements;
• It defines a region of the architecture where statements are executed sequentially;
• It must contain an explicit sensitivity list or a wait statement;
• It allows functional descriptions, similar to the programming languages;
• It allows access to signals defined in the architecture in which the process appears and to those
defined in the entity to which the architecture is associated.

Structure and Execution of a Process

A process may appear anywhere in an architecture body (the part starting after the begin
keyword). The basic structure of a process declaration is the following:

The process declaration is contained between the keywords process and end process.

The optional sensitivity list is the list of signals to which the process is sensitive. Any event on any
of the signals specified in the sensitivity list causes the sequential instructions in the process to be
executed, similar to the instructions in a usual program. As opposed to a programming language,
in VHDL the end process clause does not specify the end of process execution. The process will be
executed in an infinite loop. When a sensitivity list is specified, the process will only suspend after
the last statement, until a new event is produced on the signals in the sensitivity list. Note that an
event only occurs when a signal changes value. Therefore, the assignment of the same value to a
signal does not represent an event.

When the sensitivity list is missing, the process will be run continuously. In this case, the process
must contain a wait statement to suspend the process and to activate it when an event occurs or a
condition becomes true. When the sensitivity list is present, the process cannot contain wait
statements.

The declarative part of the process is contained between the process and begin keywords. This
part may contain declarations of types, constants, variables, and subprograms (procedures and
functions) that are local to the process. Thus, the declared items can only be used inside the
process.

Note •
In a process it is not allowed to declare signals; only constants and variables may be declared.

The statement part of the process starts after the begin keyword. This part contains the
statements that will be executed on each activation of the process. It is not allowed to use
concurrent instructions inside a process.

Example 1 presents the declaration of a simple process composed of a single sequential signal
assignment

Example 1:

For a process to model combinational logic, it must contain in the sensitivity list all the signals that
are inputs of the process. In other words, the process must be reevaluated every time one of the
inputs to the circuit it models changes. In this way combinational logic is correctly modeled.

Wait Statement

Instead of a sensitivity list, a process may contain a wait statement. The use of a wait statement
has two reasons:

• To suspend the execution of a process;

• To specify a condition that will determine the activation of the suspended process.

Example 2:

Usually, the wait statement appears either at the beginning of a process, or at the end of it. In
Example 2, the wait statement appears at the end of the process. It was mentioned that this form
is equivalent to the form that contains a sensitivity list.
Combinational and Sequential Processes:

Both combinational and sequential processes are interpreted in the same way, the only difference
being that for sequential processes the output signals are stored into registers. A simple
combinational process is described in Example 3.

Example 3:

This process will be implemented by synthesis as a two-input AND gate. For a process to model
combinational logic, it must contain in the sensitivity list all the signals that are inputs of the
process.

If a process contains a wait statement or an if signal'event statement, the process will be

interpreted as a sequential process. Hence the process in Example 4 will be interpreted as a
sequential process.

Example 4:

By synthesizing this process, the circuit in figure 1 will result, where a flip-flop is added on the
output.

Figure 1. Synthesis result of a sequential process.

Sequential Signal Assignment Statement

Signals represent the interface between the concurrent domain of a VHDL model and the
sequential domain within a process.

The sequential signal assignment has the following syntax:

Typically, synthesis tools do not allow to use after clauses, or they ignore these clauses.

As a result of executing this statement in a process, the expression on the right-hand side of the
assignment symbol is evaluated and an event is scheduled to change the value of the signal. The
simulator will only change the value of a signal when the process suspends, and, if the after clause
is used, after the delay specified from the current time. Therefore, in a process the signals will be
updated only after executing all the statements of the process or when a wait statement is
encountered.

A consequence of the way in which signal assignments within processes are executed is that when
more than one value is assigned to the same signal, only the last assignment will be effective.
Thus, the two processes in Example 5 are equivalent.

Example 5

In conclusion, the following important aspects should be taken into consideration when signal
assignment statements are used inside processes:

• Any signal assignment becomes effective only when the process suspends. Until that moment,
all signals keep their old values.
• Only the last assignment to a signal will be effectively executed. Therefore, it would make no
sense to assign more than one value to a signal in the same process.

Feedback

Another consequence of the way in which signal assignments are executed is that any reading of a
signal that is also assigned to in the same process will return the value assigned to the signal in the
previous execution of the process. Reading a signal and assigning a value to it in the same process
is equivalent to a feedback. In a combinational process, the previous value is an output of the
combinational logic and so the feedback is asynchronous. In a sequential process, the previous
value is the value stored in a latch or register, so the feedback is synchronous.
Example 6 presents a process in which a synchronous feedback is used. The process describes a 4-
bit counter. The signal count is of type unsigned, type defined in the numeric_bit package.
Observe that the signal count is declared outside the process.

Example 6

The circuit that results from synthesizing the process in the previous example is shown in Figure 2

Figure 2. Example of synchronous feedback.

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Variables

Restrictions enforced on signals reduce the possibilities to use them. Because signals can only hold
the last value assigned to them, they cannot be used to store intermediary results within a
process. Another drawback is that the new values are not assigned to signals when the assignment
statement executes, but only after the process execution suspends. This causes difficulties in
analyzing descriptions

As opposed to signals, variables can be declared inside processes and can be used to store
intermediary results. However, variables can be used only in the sequential domain of the VHDL
language, that is, inside processes and subprograms, and cannot be declared or used directly in an
architecture. Thus, they are local to that process or subprogram.

Declaring and Initializing Variables

Like signals, variables must be declared before they are used. A variable declaration is similar to
that of a signal, but the variable keyword is used. This declaration specifies the type of the
variable. Optionally, for scalar variables a constrained range may be specified, and for array
variables a constrained index may be specified. For both types of variables, an initial value may be
specified. Example 7 illustrates variable declarations and initializations.

Example 7

A variable is given an initial value at the initialization phase of the simulation. This initial value is
either that specified explicitly in the variable declaration, or a default value, which is the left value
of the type. For example, for type bit the initial value is '0', and for type integer this value is –
2,147,483,647.

For synthesis, there is no hardware interpretation of initial values, so synthesis tools ignore initial
values or signal errors.

Variable Assignment Statement

A variable assignment statement replaces the current value of a variable with a new value
specified by an expression. The expression may contain variables, signals, and literals. The variable
and the result of expression evaluation must be of the same type. The syntax of the variable
assignment statement is the following:

This statement is similar to the assignments in most of the programming languages. As opposed to
a sequential signal assignment, a variable assignment is executed immediately, that is, in zero
simulation time.

The following main differences exist between signal assignment and variable assignment:

• For a signal assignment an event is scheduled to update the signal value, and this update is
executed only when the process execution suspends. For a variable assignment, an event is not
scheduled and the update is executed instantly.
• For a signal assignment a delay may be specified, while a variable assignment cannot be delayed.
• In a process only the last assignment to a signal is effective. Instead, numerous assignments to a
variable may exist in a process, and all are effective.
Example 8 illustrates the use of variables to store intermediary results.

Example 8.

The preceding example describes a full adder. The result is generated by creating two half-adders;
the first generates the outputs s1 and c1, and the second the outputs s2 and c2. Finally, the
outputs are assigned to the output ports s and cout by signal assignment statements, since ports
are signals.

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If Statement

Syntax and Execution of an if Statement

The if statement selects one or more statement sequences for execution, based on the evaluation
of a condition corresponding to that sequence. The syntax of this statement is the following:

Each condition is a Boolean expression, which is evaluated to TRUE or FALSE. More than one elsif
clauses may be present, but a single else clause may exist. First, the condition after the if keyword
is evaluated, and if it evaluates true, the corresponding statement or statements are executed. If it
evaluates false and the elsif clause is present, the condition after this clause is evaluated; if this
condition evaluates true, the corresponding statement or statements are executed. Otherwise, if
there are other elsif clauses, the evaluation of their conditions continues. If none of the conditions
evaluated is true, the sequence of statements corresponding to the else clause is executed, if this
clause is present.
Example 9

Synthesis Interpretation of an if Statement

An if statement may be implemented by a multiplexer. First consider the if statement without any
elsif branch. Example 10 presents the use of such a statement to describe a comparator.

Example 10

The resulting circuit is shown in Figure 3.

Figure 3. Synthesis of an if statement

A multi-branch if statement, in which at least one elsif clause appears, is implemented by a

multistage multiplexer. Consider the if statement in Example 11
Example 11.

The result of implementing the if statement from the previous example is presented in Figure 4.
This circuit is equivalent to that resulted by implementing a conditional signal assignment
(when…else)

Figure 4. Synthesis of a multi-branch if statement.

The structure of the if statement ensures that the earlier conditions are. tested first. In this
example, signal s0 has been tested before signal s1. This priority is reflected in the generated
circuit, where the multiplexer controlled by signal s0 is nearer to the output than the multiplexer
controlled by signal s1.

It is important to remember the existence of this priority for condition testing, so that redundant
tests can be eliminated. Consider the if statement in Example 12, which is equivalent to the if
statement in Example 11.

Example 12.
The additional condition s0 = '0' is redundant since it will be tested only if the first condition of the
if statement is false. It is recommended to avoid such redundancies, because there is no guarantee
that they will be detected and eliminated by the synthesis tool.

For multi-branch if statements, normally each condition will be dependent on different signals and
variables. If every branch is dependent on the same signal, then it is more advantageous to use a
case statement.

Incomplete if Statements

In the examples presented so far, all the if statements have been complete. In other words, the
target signal has been assigned a value under all possible conditions. However, there are two
situations when a signal does not receive a value: when the else clause of the if statement is
missing, and when the signal is not assigned to a value in some branches of the if statement. In
both cases the interpretation is the same. In the situations when a signal does not receive a value,
its previous value is preserved.

The problem is what the previous value of the signal is. If there is a previous assignment statement
in which the signal appears as target, then the previous value comes from that assignment
statement. If not, the value comes from the previous execution of the process, leading to feedback
in the circuit.

The first case is illustrated in Example 13.

Example 13.

In this case, the if statement is incomplete because the else clause is missing. In the if statement,
the signal z gets a value if the condition enable = '1' is true, but remains unassigned if the
condition is false. The previous value comes from the unconditional assignment before the if
statement.

The if statement of Example 13 is equivalent to the if statement of Example 14

Example 14.

When the if statement is incomplete and there is no previous assignment, then a feedback will
exist from the output of the circuit to the input. This is because the value of the signal from the
previous execution of the process is preserved and it becomes the value in the current execution
of the process.

This form of the if statement is used to describe a flip-flop or a register with an enable input, as in
Example 15.

Example 15.

The signal q is updated with the new value of signal d when the condition is true, but is not
updated when the condition is false. In this case, the previous value of signal q is preserved by
sequential feedback of q. The resulting circuit is presented in Figure 5.

Figure 5. Synthesis of an incomplete if statement

The if statement of Example 15 is equivalent to the complete if statement of Example 16.

Example 16.

When the condition is false, the signal q is assigned to itself, which is equivalent to preserving its
previous value.

One of the most common errors encountered in VHDL descriptions targeted for synthesis is the
unintended introduction of feedback in the circuit due to an incomplete if statement. In order to
avoid the introduction of feedback, the designer must ensure that every signal assigned to in an if
statement within a process (which is therefore an output signal of the process) receives a value
under every possible combination of conditions. In practice, there are two possibilities of doing
this: to assign a value to output signals in every branch of the if statement and including the else
clause, or to initialize signals with an unconditional assignment before the if statement

In the following example, although the if statement looks complete, different signals are being
assigned a value in each branch of the if statement. Thus both signals z and y will have
asynchronous feedback.

Example 17.

Another example is where there is a redundant test for a condition which must be true (Example
18)
Example 18.

In this case, although the if statement looks complete (assuming that signal c is of type bit), each
of the conditions in the if statement is synthesized independently. The synthesis tool will therefore
not detect that this second condition is redundant. Thus the if statement is synthesized as a three-
way multiplexer, the third input being the missing else condition which is the feedback of the
previous value. The circuit synthesized for this example is shown in Figure 6.

Figure 6. Synthesis of an if statement with a redundant condition.

If Statements with Variables

So far, in the if statements only signals were used. The same rules apply when using variables, with
a single difference. Like a signal, if a variable is assigned to only in some branches of the if
statement, then the previous value is preserved by feedback. Unlike the case when a signal is
used, the reading and writing of a variable in the same process will result in feedback only if the
read occurs before the write. In this case, the value read is the previous value of the variable. In
the case when a signal is used, a read and a write in the same process will always result in
feedback

This observation may be used to create registers or counters using variables. Remember that a
sequential process is interpreted by synthesis by placing a flip-flop or register on every signal
assigned to in the process. This means that normally variables are not written to flip-flops or
registers. However, if there is feedback of a previous variable value, then this feedback is
implemented via a flip-flop or register to make the process synchronous.

Example 19 describes a counter using the unsigned integer type. When a value of type unsigned is
incremented, if the value is the highest value of the range, then the lowest value of the range is
obtained.
Example 19.

In this example, in the else branch of the if statement the previous value of the count variable is
being read to calculate the next value. This results in a feedback.

Note that in this example actually two registers are created. According to the feedback rules,
variable count will be registered. Signal result will also be registered, because all signals assigned
to in a sequential process will be registered. This extra register will always contain the same value
as the register for variable count. The synthesis tool will normally eliminate this redundant
register.

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Concurrent Signal Assignment Statements