Jumptec® Industrial Computer AG, Brunnwiesenstraße 16, 94469 Deggendorf Germany

PISA BUS

specification

Rev 1.7

04 June 1997

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Jumptec® Industrial Computer AG, Brunnwiesenstraße 16, 94469 Deggendorf Germany

1. History of PISA BUS

January 1996 PISA Bus has been developed by Giantec Inc. Taiwan in January 1996.

April of 1996 Giantec introduced the Term „ PISA Bus“ for their definition.

May of 1996 first 486 PISA compatible product introduced by Giantec

June 1996 JUMP is joining Giantec as the first European Company

Q3/Q4 1996 other Companies join Giantec to push PISA as a BUS of the future.

January 1997 JUMP introduced its first Pentium Board using PISA Bus.

2. Additional reference

In addition to this document, the user should reference to the following industry standard specifications:

ISA Bus specification P996 rev 1.1

PCI Bus specification Rev 2.1

3. Supporting Companies

Atronics International Inc.

44700-B Industrial Drive
Freemont, CA 94538
web http://www.atil.com
phone 510 656 8400
fax 510 656 8560

Axiom Technology Inc.

3875 Schaefer Avenue, Unit E
Chino, CA 91710
phone 909 464 1881
fax 909 464 1861

Axiom Technology Co. Ltd.

3F, No. 14, Lane 235, Pao-Chiao Rd.,
Shin-Tien, Taipei, Taiwan R.O.C.
phone 886 2 917 4550/324
fax 886 2 917 3200
contact Chuck Li, president
email [email protected]

Boards / Micron AG
Am Söldnermoos 17
85399 Hallbergmoos
phone 0811/5539300
fax 0811/5539415
contact Dr. Rudi Wieczorek

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Giantec Inc.
9F, No. 121, Ming Chuan Rd.,
Hsin Tien City, Taipei, Taiwan R.O.C.
phone 886 2 219 1996
fax 886 2 219 1997
e-mail [email protected]
contact Dennis Wang, president

Jump Industrial Computer GmbH

Veilchengasse 7
94469 Deggendorf
phone 0991 370240
fax 0991 31275
email [email protected]
contact Hans Muehlbauer, VP of Marketing

Leukhard Systemelektronik GmbH

Rudolf Diesel Str. 17
78532 Tuttlingen, Germany
phone 49 7461 925 212
fax 49 7461 925 291

Portwell Inc.
6F-3, No. 160, Sec 6, Ming-Chuang E. Rd.,
Taipei, Taiwan, R.O.C.
phone 886 2 7923458
fax 886 2 7923460
email [email protected]
contact Clement Chen, vice president

Siliconrax Industrial Computer Specialists

1202 Apolin Way
Sunnyvale, CA 84086
phone 408 720 1090
fax 408 745 2570
web http://www.siliconrax.com
contact Jason Cho

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4. Available Products

Giantec PISA 486DX with cache and I/O available since May 96
Backplane with 4 ISA and 4 PCI Slots available since May 96
Pentium Pro CPU with I/O planned for May 97

Axiom PISA 486DX all in one CPU in development for Feb 97

PISA Pentium CPU in development for Apr 97

JUMP PISA Pentium CPU with I/O, LCD available in Feb 97

and Ethernet

many other companies planning to introduce products using PISA Bus in Q2 and Q3 of 1997.

5. Advantages of PISA Bus

- half size Boards available for space critical applications including PCI and ISA

- world wide support by many companies

- allows compact backplanes using ISA and PCI, backplanes are about ½ size of PICMG

- allows for 66 MHz PCI Bus because of shorter routing for PCI Bus

- future expansion for 64 Bit PCI Bus possible

- supports 4 external PCI slots

- Std ISA Bus CPU can be used in PISA Slot for upgradeability

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6. Pinout of PISA Bus

ISA-Bus PCI-Bus 5V card universal card 3.3V card

pin top layer bot layer top layer bot layer PCI Conn PCI Conn PCI Conn
num. up row up row low row low row side B side A side B side A side B side A
1 /IOCHCHK GND
I2CLK I2DAT
2 SD7 RSTDRV
GND GND
3 SD6 Vcc
INTB# INTA#
4 SD5 IRQ9
INTD# INTC#
5 SD4 -5V
Vcc Vcc
6 SD3 DRQ2

7 SD2 -12V -12V TRST# -12V TRST# -12V TRST# 1

Vcc V I/O TCK +12V TCK +12V TCK +12V 2
8 SD1 /0WS GND TMS GND TMS GND TMS 3
PCIRST# PCICLK2 TDO TDI TDO TDI TDO TDI 4
9 SD0 +12V VCC VCC VCC VCC VCC VCC 5
GNT#0 GND VCC INTA# VCC INTA# VCC INTA# 6
10 IOCHRDY GND INTB# INTC# INTB# INTC# INTB# INTC# 7
REQ#0 GNT#1 INTD# VCC INTD# VCC INTD# VCC 8
11 AEN /SMEMW PRSNT1# PRSNT1# PRSNT1# 9
GND GND VCC V I/O 3.3V 10
12 SA19 /SMEMR PRSNT2# PRSNT2# PRSNT2# 11
PCICLK1 REQ#1 GND GND 12
13 SA18 /IOW GND GND 13
GND AD31 14
14 SA17 /IOR GND RST# GND RST# GND RST# 15
AD30 AD29 CLK VCC CLK V I/O CLK 3.3V 16
15 SA16 /DACK3 GND GNT# GND GNT# GND GNT# 17
REQ#2 PCICLK3 REQ# GND REQ# GND REQ# GND 18
16 SA15 DRQ3 VCC V I/O 3.3V 19
AD31 AD30 AD31 AD30 AD31 AD30 20
17 SA14 /DACK1 AD29 3.3V AD29 3.3V AD29 3.3V 21
GNT#2 PCICLK4 GND AD28 GND AD28 GND AD28 22
18 SA13 DRQ1 AD27 AD26 AD27 AD26 AD27 AD26 23
AD28 AD27 AD25 GND AD25 GND AD25 GND 24
19 SA12 /RFRSH 3.3V AD24 3.3V AD24 3.3V AD24 25
AD26 AD25 C/BE3# IDSEL C/BE3# IDSEL C/BE3# IDSEL 26
20 SA11 SYSCLK AD23 3.3V AD23 3.3V AD23 3.3V 27
AD24 CBE#3 GND AD22 GND AD22 GND AD22 28
21 SA10 IRQ7 AD21 AD20 AD21 AD20 AD21 AD20 29
AD22 AD23 AD19 GND AD19 GND AD19 GND 30
22 SA9 IRQ6 3.3V AD18 3.3V AD18 3.3V AD18 31
AD20 AD21 AD17 AD16 AD17 AD16 AD17 AD16 32
23 SA8 IRQ5 C/BE2# 3.3V C/BE2# 3.3V C/BE2# 3.3V 33
AD18 AD19 GND FRAME# GND FRAME# GND FRAME# 34
24 SA7 IRQ4 IRDY# GND IRDY# GND IRDY# GND 35
PWRGDIN REQ#3 3.3V TRDY# 3.3V TRDY# 3.3V TRDY# 36
25 SA6 IRQ3 DEVSEL# GND DEVSEL# GND DEVSEL# GND 37
GND STOP# GND STOP# GND STOP# 38
26 SA5 /DACK2 LOCK# 3.3V LOCK# 3.3V LOCK# 3.3V 39
GND GNT#3 PERR# SDONE PERR# SDONE PERR# SDONE 40
27 SA4 T/C 3.3V SBO# 3.3V SBO# 3.3V SBO# 41
AD16 AD17 SERR# GND SERR# GND SERR# GND 42

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28 SA3 BALE 3.3V PAR 3.3V PAR 3.3V PAR 43

FRAME# IRDY# C/BE1# AD15 C/BE1# AD15 C/BE1# AD15 44
29 SA2 Vcc AD14 3.3V AD14 3.3V AD14 3.3V 45
CBE#2 DEVSEL# GND AD13 GND AD13 GND AD13 46
30 SA1 OSC AD12 AD11 AD12 AD11 AD12 AD11 47
TRDY# LOCK# AD10 GND AD10 GND AD10 GND 48
31 SA0 GND GND AD09 GND AD09 M66EN AD09 49
STOP# PERR# GND GND 50
32 GND GND 51
AD08 C/BE0# AD08 C/BE0# AD08 C/BE0# 52
33 AD07 3.3V AD07 3.3V AD07 3.3V 53
GND SERR# 3.3V AD06 3.3V AD06 3.3V AD06 54
34 AD05 AD04 AD05 AD04 AD05 AD04 55
AD15 AD03 GND AD03 GND AD03 GND 56
35 /SBHE /MCS16 GND AD02 GND AD02 GND AD02 57
CBE#1 AD14 AD01 AD00 AD01 AD00 AD01 AD00 58
36 LA23 /IOCS16 VCC VCC V I/O V I/O VCC VCC 59
PAR AD12 ACK64# REQ64# ACK64# REQ64# ACK64# REQ64# 60
37 LA22 IRQ10 VCC VCC VCC VCC VCC VCC 61
GND GND VCC VCC VCC VCC VCC VCC 62
38 LA21 IRQ11

39 LA20 IRQ12
GND M66EN
40 LA19 IRQ15
AD13 AD10
41 LA18 IRQ14
AD11 AD8
42 LA17 /DACK0
AD9 AD7
43 /MEMR DRQ0
CBE#0 AD5
44 /MEMW /DACK5
AD6 AD3
45 S D8 DRQ5
AD4 AD1
46 SD9 /DACK6
AD2 AD0
47 SD10 DRQ6

48 SD11 /DACK7
Vcc V I/O
49 SD12 DRQ7
Vcc Vcc
50 SD13 Vcc
GND GND
51 SD14 /MASTER
GND GND
52 SD15 GND

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7. Electrical characteristics of PISA Bus

7.1. power supply definition

power supply pins:

PISA current max PCI 5V PCI uni PCI 3.3V

GND 19 22 18 21
VCC 9 9A 13 8 10
+12V 1 1A 1 1 1
-12V 1 1A 1 1 1
-5V 1 1A
V I/O 2 2A 5

The PISA Bus power pins are not used to supply power to the I/O Boards. The I/O slots are supplied over
the backplane.

The PISA CPU Board does generate its own 3.3V and CPU voltages as needed, and therefore needs no
3.3V supply pins.

additional pins on the PISA Bus.

The PISA Bus supports all ISA Bus signals and 32Bit PCI signals except the following signals:

JTAG signals which are only for test purpose

SBO# and SDONE which are needed for cache on PCI BUS.
64 Bit extension signals

All other PCI signals are supported.

The PISA definition includes 3 unconnected Pins for future extension.

in addition to ISA and PCI Bus signals, the PISA Bus supports a Powergood input signal.

The PISA connector supports a total of 188 pins, 98 are used for ISA Bus signals and 90 for PCI bus
signals.

7.2. IDSEL mapping

target device AD line Description

0 AD11 PISA CPU chipset internal device
1 AD12 PISA CPU chipset internal device
2 AD13 PISA CPU onboard device # 1
3 AD14 PISA CPU onboard device # 2
4 AD15 PISA CPU onboard device # 3
5 AD16 PISA CPU onboard device # 4
6 AD17
7 AD18
8 AD19 PISA Backplane slot # 1
9 AD20 PISA Backplane slot # 2
10 AD21 PISA Backplane slot # 3
11 AD22 PISA Backplane slot # 4
12 AD23
13 AD24
14 AD25
15 AD26

7.3. Clock distribution

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The PISA CPU supplies all PCI clocks for 4 Bus slots over the PISA connector and all internal Clocks for
onboard devices.

The PISA CPU onboard PCI CLK delay is specified to be 750 ps later than the PCI clocks routed to the
PISA connector. The difference is measured from the PISA connector pad to the onboard device input
pin.
The backplane manufacturer has to route the clocks on the backplane with a delay of 600 ps including the
delay of both (the PISA and the PCI) connectors.

7.4. Additional signals

The PISA CPU supplies all PCI and ISA Bus signals, together with some additional signals for better
signal integration.

The additional signals are:

I2CLK

I2CLK is the I2C-BUS clock for a backplane EEPROM

I2DAT

I2DAT is the 12C-BUS data for a backplane EEPROM

PWRGDIN

Pgoodin is is a low active reset input to the CPU

7.5. Interrupt-Routing

Following interrupt routing on the backplane is recommended for proper bios support:

Backplane Slot PISA INT A PISA INT B PISA INT C PISA INT D
Slot 1 (AD19) INT A INT B INT C INT D
Slot 2 (AD20) INT D INT A INT B INT C
Slot 3 (AD21) INT C INT D INT A INT B
Slot 4 (AD22) INT B INT C INT D INT A

e.g. INT B signal of PCI-Slot 3 (IDSEL AD21) has to be routed to signal INT D of the PISA board

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Jumptec® Industrial Computer AG, Brunnwiesenstraße 16, 94469 Deggendorf Germany

8. Mechanical specification

The PISA Bus Board is designed to allow for small systems and therefore, the Board is made as small as
possible.

The Board should either end with the Bus connector, or if it is longer, it should not cover the area down to
the connector, because this area is reserved for future 64 bit expansion.

120 125
mm mm

155,5 mm

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