Experiment no-: 1

Aim-:To study and verify the operation of AND gate using CMOS technology.
Software used-:Tanner EDA
Theory-:
The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH output (1)
results only if all the inputs to the AND gate are HIGH (1). If none or not all inputs to the AND gate
are HIGH, a LOW output results. The function can be extended to any number of inputs.
C = A.B = A AND B
INPUT OUTPUT
A B C
0 0 0
0 1 0
1 0 0
1 1 1

Circuit diagram-:

Program/Code-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Output waveform-:

Result-: AND Gate using CMOS Technology is successfully implemented using Tanner EDA.
Discussion-:
CMOS logic gates are made of IGFET (MOSFET) transistors rather than bipolar junction
transistors.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
CMOS gate inputs are sensitive to static electricity. They may be damaged by high voltages, and
they may assume any logic level if left floating.
Pullup and pulldown resistors are used to prevent a CMOS gate input from floating if being
driven by a signal source capable only of sourcing or sinking current.
CMOS gates dissipate far less power than equivalent TTL gates, but their power dissipation
increases with signal frequency, whereas the power dissipation of a TTL gate is approximately
constant over a wide range of operating conditions.
CMOS gate inputs draw far less current than TTL inputs, because MOSFETs are voltage-
controlled, not current-controlled, devices.
CMOS gates are able to operate on a much wider range of power supply voltages than TTL:
typically 3 to 15 volts versus 4.75 to 5.25 volts for TTL.
CMOS gates tend to have a much lower maximum operating frequency than TTL gates due to
input capacitances caused by the MOSFET gates.
B-series CMOS gates have “buffered” outputs to increase voltage gain from input to output,
resulting in faster output response to input signal changes. This helps overcome the inherent
slowness of CMOS gates due to MOSFET input capacitance and the RC time constant thereby
engendered.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
 Experiment no-:2
Aim-: To study and verify the operation of OR gate using CMOS technology.
Software used-: Tanner EDA
Theory-:
The OR gate is a digital logic gate that implements logical disjunction. A HIGH output (1) results
if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results.
In another sense, the function of OR effectively finds the maximum between two binary digits,
just as the complementary AND function finds the minimum.
C = A+B = A OR B
INPUT OUTPUT
A B C
0 0 0
0 1 1
1 0 1
1 1 1

Circuit diagram-:

Program/Code-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Output waveform-:

Result-:
OR Gate using CMOS Technology is successfully implemented using Tanner EDA.

Discussion-:
Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
CMOS logic gates are made of IGFET (MOSFET) transistors rather than bipolar junction
transistors.
CMOS gate inputs are sensitive to static electricity. They may be damaged by high voltages, and
they may assume any logic level if left floating.
Pullup and pulldown resistors are used to prevent a CMOS gate input from floating if being
driven by a signal source capable only of sourcing or sinking current.
CMOS gates dissipate far less power than equivalent TTL gates, but their power dissipation
increases with signal frequency, whereas the power dissipation of a TTL gate is approximately
constant over a wide range of operating conditions.
CMOS gate inputs draw far less current than TTL inputs, because MOSFETs are voltage-
controlled, not current-controlled, devices.
CMOS gates are able to operate on a much wider range of power supply voltages than TTL:
typically 3 to 15 volts versus 4.75 to 5.25 volts for TTL.
CMOS gates tend to have a much lower maximum operating frequency than TTL gates due to
input capacitances caused by the MOSFET gates.
B-series CMOS gates have “buffered” outputs to increase voltage gain from input to output,
resulting in faster output response to input signal changes. This helps overcome the inherent
slowness of CMOS gates due to MOSFET input capacitance and the RC time constant thereby
engendered.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
 Experiment no-:3
Aim-: To study and verify the steady state and transient state response of inverter using MOS
technology.

Software used-:Tanner EDA

Theory-:
An inverter circuit outputs a voltage representing the opposite logic-level to its input. Its main
function is to invert the input signal applied. ... Alternatively, inverters can be constructed using
two complementary transistors in a CMOS configuration.

Circuit diagram-:

Program/Code-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Output waveform-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Result-: the steady state and transient state response of inverter using MOS technology is
successfully implemented using tanner EDA.

Discussion-:
A steady-state response is the behavior after a long time when steady conditions have been reached.A
transient response is the response of a system to a change from an equilibrium or a steady state.The
inverter is truly the nucleus of all digital designs. Once its operation and properties areclearly
understood, designing more intricate structures such as NAND gates, adders, mul-tipliers, and
microprocessors is greatly simplified. The electrical behavior of these com-plex circuits can be almost
completely derived by extrapolating the results obtained forinverters. The analysis of inverters can be
extended to explain the behavior of more com-plex gates which in turn form the building blocks for
mod-ules such as multipliers and processors.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
 Experiment no-: 4
Aim-:To study and verify the operation of Xnor gate using CMOS technology.
Software used-:Tanner EDA
Theory-:
The Exclusive-NOR Gate, also written as: “Ex-NOR” or “XNOR”, function is achieved by
combining standard gates together to form more complex gate functions and an example of a
2-input Exclusive-NOR gate

Circuit diagram-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Program/Code-:

Output waveform-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Result-: EX-NOR Gate using CMOS Technology is successfully implemented using Tanner EDA.

Discussion-:
CMOS logic gates are made of IGFET (MOSFET) transistors rather than bipolar junction
transistors.
CMOS gate inputs are sensitive to static electricity. They may be damaged by high voltages, and
they may assume any logic level if left floating.
Pullup and pulldown resistors are used to prevent a CMOS gate input from floating if being
driven by a signal source capable only of sourcing or sinking current.
CMOS gates dissipate far less power than equivalent TTL gates, but their power dissipation
increases with signal frequency, whereas the power dissipation of a TTL gate is approximately
constant over a wide range of operating conditions.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
CMOS gate inputs draw far less current than TTL inputs, because MOSFETs are voltage-
controlled, not current-controlled, devices.
CMOS gates are able to operate on a much wider range of power supply voltages than TTL:
typically 3 to 15 volts versus 4.75 to 5.25 volts for TTL.
CMOS gates tend to have a much lower maximum operating frequency than TTL gates due to
input capacitances caused by the MOSFET gates.
B-series CMOS gates have “buffered” outputs to increase voltage gain from input to output,
resulting in faster output response to input signal changes. This helps overcome the inherent
slowness of CMOS gates due to MOSFET input capacitance and the RC time constant thereby
engendered.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
 Experiment no-:5
Aim-: To study and verify the operation of OAI ((A+B)(C+D))’ logic using CMOS
technology.
Software used-: Tanner EDA
Theory-:
OR-AND-Invert (OAI) logic and OAI gates are two-level compound (or complex) logic functions
constructed from the combination of one or more OR gates followed by a NAND gate.
The complement of OAI Logic is AND-OR-Invert (AOI) logic where the AND gates precede a NOR
gate.

Circuit diagram-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Program/Code-:
.include “C:\Program Files\Tanner EDA\T-Spice 11.2\Models\m12_125.md”
.print tran a1 a2 a3 a4 out
.tran 10ns 300ns
.param 1=1u
.options persist=2

Output waveform-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Result-:
The operation of OAI has been studied and verified.
Discussion-:
OR-AND-Invert (OAI) logic and OAI gates are two-level compound (or complex) logic functions.
The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND
gate.

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
 Experiment no-:6

Software used-:Tanner EDA

Theory-:
AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions
constructed from the combination of one or more AND gates followed by a NOR gate.
Construction of AOI cells is particularly efficient using CMOS technology where the total
number of transistor gates can be compared to the same construction using NAND logic or NOR
logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a
NAND gate.

Circuit diagram-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Program/Code

Output waveform-:

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Result-: The operation of AOI has been studied and verified.
Discussion-:
AND-OR-Invert (AOI) logic are two-level logic functions constructed from the combination of
one or more AND gates followed by a NOR gate. If we construct AND, OR and NOT gate
separately, Number of transistor in AOI gates are less. We need individual logic gate as from
CMOS point of view this is beneficial.
Less number of Transistors for implementing a particular logic function helps in multiple ways :
Increased speed
Reduced Power
Smaller area
Potentially lower fabrication cost

Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE
Name-:Aakash Aggarwal
Roll no-:41796202816
Branch-:ECE