Experiment 1: Introduction to Development Platform

Christopher L. Padua

I. Introduction

DE1 starter kit is a education and 1) module exercise1 (CLOCK_50, PB,

development board that the host LEDR);
computer can access various 2)
components on the board. It is used 3) input CLOCK_50;
to verify the functionality of the 4) input [3:0] PB;
components or used as a debug
5) reg [9:0] state;
tool for development of Verilog 6) output [7:0] LEDR;
programs. 7)
8) assign LEDR = state;
II. Methodology 9)
10) Always @ (posedge CLOCK_50)
The first part of the experiment is 11) if (PB[0] == 0)
by familiarizing the use Quartus 12) state <=
application. In this exercise, the 10’b0000000000;
Quartus II 9.0 Web Edition was used 13) Else
and ran. A new project will be 14) state[0] <= 1;
created by selecting File>New 15)
Project Wizard then a dialog box
16) endmodule
will pop up that will ask for the
working directory where all the After completing the Verilog HDL
projects will be saved. The working file, a new Tcl script file was created
directory will be named and typed the following code:
FPGAprojects and the project name
is exercise 1. After the directory and 1 set_location_assignment
project is created, select Cyclone II PIN_R22 –to PB[0]
under the device family drop box 2 set_location_assignment
and select EP2C20F484C7 in the list PIN_L1 –to CLOCK_27A
of available devices then click next 3 set_location_assignment
and finish completing the creation PIN_U22 –to LEDR[0]
of the new project. 4 set_location_assignment
PIN_U21 –to LEDR[1]
A new was created as exercise1.v 5 set_location_assignment
and mark the check box with “Add PIN_V22 –to LEDR[2]
File To Project”. Typed the following 6 set_location_assignment
code on exercise1.v panel and save: PIN_V21 –to LEDR[3]
 7 set_location_assignment 12) state <=
PIN_W22 –to LEDR[4] 10’b1111111111;
8 set_location_assignment 13) Else
PIN_W21 –to LEDR[5] 14) state <=
9 set_location_assignment 10’0000000000;
PIN_Y22 –to LEDR[6] 15)
10 set_location_assignment 16) endmodule
PIN_Y21 –to LEDR[7]

Then source pin_assign.tcl was III. Results and Discussion

typed in the TCL console box. The
next step performed is compiling Output:
the file by selecting the Processing
> Start Compilation in the main
menu and waited for the
compilation to finish. The DE1
Starter Kit was checked if it is
turned on and connected to the PC
then continued by opening the
Programmer from Tools and
selected the exercise1.pof.

In the next exercise, the same

procedure in exercise 1 was
performed but named the new Figure 1-1: Exercise 1 Output
project as exercise2 and the Verilog
HDL file to exercise2.v. The code in The LEDR0 lit up when KEY0 is
exercise1.v was modified by typing pressed as the expected result.
the following code:

1) module exercise2 (CLOCK_50, PB,

LEDR);
2)
3) input CLOCK_50;
4) input [3:0] PB;
5) reg [9:0] state;
6) output [9:0] LEDR;
7)
8) assign LEDR = state;
9)
10) Always @ (posedge CLOCK_50)
11) if (PB[0] == 0) Figure 1-2: Exercise 2 Output
 V. Reference

 Intel.com. (2018). Cyclone II

FPGA Starter Development
Kit. [online] Available at:
https://www.intel.com/con
tent/www/us/en/program
mable/products/boards_an
d_kits/dev-kits/altera/cyc2-
2c20n-kit.html [Accessed 13
June. 2019].
 Intel.com. (2018). [online]
Available at:
https://www.intel.com/con
Figure 1-3: Exercise 2 Output
tent/dam/altera-
www/global/en_US/portal/
In exercise 2, all lights turned off
dsn/42/doc-us-dsnbk-42-
when KEY1 was pressed.
4904342209-de1-
usermanual.pdf [Accessed
IV. Conclusion
13 June. 2019].

In conclusion, we are able to

familiarize the use of the
development platform in how to
create new projects and files that
are needed to be programmed. We
are able to create the Verilog HDL
and Tcl files using the Quartus II 9.0
Web Edition IDE and learned to
access, control, and assign LED pins
on the DE1 Starter Kit by using
different codes and configuration in
the Verilog HDL and Tcl files.