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Scan Insertion Lab Observations: Vlsiguru DFT Training

1) The document describes observations from a scan insertion lab experiment on a design with 1 clock domain and a 10-bit shift register. 2) The goal was to insert scan for the design and include the shift register in the scan chain without converting it to scan FFs, using 2 scan chains. 3) Key observations included the use of a top-down approach with no lockup latches or DRC violations, and the resulting design containing 73 scan FFs across two scan chains of length 37 and 36 with no non-scan FFs converted to scan.

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423 views2 pages

Scan Insertion Lab Observations: Vlsiguru DFT Training

1) The document describes observations from a scan insertion lab experiment on a design with 1 clock domain and a 10-bit shift register. 2) The goal was to insert scan for the design and include the shift register in the scan chain without converting it to scan FFs, using 2 scan chains. 3) Key observations included the use of a top-down approach with no lockup latches or DRC violations, and the resulting design containing 73 scan FFs across two scan chains of length 37 and 36 with no non-scan FFs converted to scan.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 8: -

Problem Definition: - Design has 1 clock domain and a 10bit shift register. Insert scan for
the design and make the 10bit shift register has part of the scan chain without
converting it to Scan FFs. Use 2 scan chains with new ports for scan in and scan out.
Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands

Outputs: -

  Scan inserted Netlist


  ATPG Dofile
  ATPG Testproc
 Scan Def
What is issue?
Design has 1 clock domain and a 10bit shift register. Insert scan for the design and
make the 10bit shift register has part of the scan chain without converting it to Scan FFs.
How resolved?
Ans. In dofile insert command =>
add non scan instance of shift register

delete non-scan instance


add scan instances.

Observations: -
1) Write block diagram with all DFT inputs?

SYS_Clk

Reset

Top Design: loop_stack


Input Scan Channel Output Scan channel

Scan_En

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

2) How many clock


domains? SysClk

3) How many resets?


Reset

4) Number of scan
chains. 2 scan chains

5) Clock mixing or not clock


mixing?. Not clock mixing

6) How many Lockup-latches are added during scan insertion?


No lockup latches are added during scan insertion.

7) Is it top-down or bottom up approach?


Top-down approach

8) How many terminal lockup latches are


added? Ans. Zero

9) Number of scan flops and non-scan flops in the design


73 flop scan and 9 non scan flop
10) Chain length?
chain 1 length 37.
chain 2 length 36

11) Number of DRC violations?


NO DRC violations occur

12) Log file: - please note your observations from the log file
Top module is loop_stack
Number of shift registers =9
Number of new Pins inserted= 5 (scan_in1, scan_in2, scan_en, scan_out1, scan_out2)

Vlsiguru Confidential 2

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