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Scan Insertion Lab Observations: Vlsiguru DFT Training

The document describes observations from a scan insertion lab experiment. The goal was to insert scan chains into a design with an existing block using 4 scan chains, balancing the chains across the entire design. Key details include the number of scan and non-scan flops, clock domains, lockup latches added, and DRC violations observed after scan insertion.

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220 views2 pages

Scan Insertion Lab Observations: Vlsiguru DFT Training

The document describes observations from a scan insertion lab experiment. The goal was to insert scan chains into a design with an existing block using 4 scan chains, balancing the chains across the entire design. Key details include the number of scan and non-scan flops, clock domains, lockup latches added, and DRC violations observed after scan insertion.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 10: -

Problem Definition: - Design has modules where in block1 is alreay scan inserted with 4
scan chains. Insert scan for other blocks with 4 chains. Balance the scan chains for the
entire design from the top module using 4 chains. Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands
Outputs: -

  Scan inserted Netlist


  ATPG Dofile
  ATPG Testproc
 Scan Def
What is issue?
. Design has modules where in block1 is alreay scan inserted with 4 scan chains. Insert
scan for other blocks with 4 chains.
How resolved?
Declare block 1’s scan chain as subchain using add_subchain command and inserted 4
scan chains for top module and stitching with block1.
Observations: -
1) Write block diagram with all DFT inputs?

Top Design: rmon


Output Scan channel
Input Scan Channel

Scan_En

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

2) How many clock domains?


. Clk_sys, tx_clk, rx_clk.

3) How many resets?


There is no reset pin.

4) Number of scan
chains Ans. 4 scan chains

5) Clock mixing or not clock mixing?


. clock mixing

6) How many Lockup-latches are added during scan insertion? .


6 lockup latches are added during scan insertion.

7) Is it top-down or bottom up approach?


. Bottom-up approach

8) How many terminal lockup latches are


added? 4 Terminal lockup latches

9) Number of scan flops and non-scan flops in the design?


. 195 scannable flops 17 non-scannable flip flops

10) Chain length?


Ans. Longest chain length 53.

11) Number of DRC violations? Ans.


FN1, FP13 DRC violations occur

12) Log file: - please note your observations from the log file
Top module is rmon
Number of shift registers =6
Number of lockup latches inserted =
6 Number of inverters inserted = 6.
Number of new Pins inserted= 9 (scan_in1, scan_in2, scan_in3, scan_in4, scan_en,
scan_out1, scan_out2, scan_out3, scan_out4)

Vlsiguru Confidential 2

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