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Scan Insertion Lab Observations: Vlsiguru DFT Training

1. The document describes observations from a scan insertion lab experiment mixing clock domains and edges to insert scan. 2. The design has 3 clocks across 2 clock domains and 1 reset, with the scan insertion tool performing clock mixing to merge the domains and edges into a single scan chain. 3. Scan insertion added 2 lockup latches and converted 128 non-scan flops to scanable, resulting in a design with 130 total scannable flops across 1 scan chain.

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1K views3 pages

Scan Insertion Lab Observations: Vlsiguru DFT Training

1. The document describes observations from a scan insertion lab experiment mixing clock domains and edges to insert scan. 2. The design has 3 clocks across 2 clock domains and 1 reset, with the scan insertion tool performing clock mixing to merge the domains and edges into a single scan chain. 3. Scan insertion added 2 lockup latches and converted 128 non-scan flops to scanable, resulting in a design with 130 total scannable flops across 1 scan chain.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 12c : -
Problem Definition: -
Design has 3 clocks (one +ve , one -ve, one using both edges)
c) c) mix edges and clock domains and insert scan
Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands

Outputs: -

  Scan inserted Netlist


  ATPG Dofile
  ATPG Testproc
 Scan Def

Q. What is issue?
Ans: We have to mix clock domains,clock merge and insert scan
Q. How issue resolved

Ans : by using this command we perform clock mixing and edge merge
Insert test logic -ram on -clock merge -edge merge
After this command we get one which consist of first + edge then – ve edge in single chain

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Observations: -

1) Write block diagram with all DFT inputs?

Reset
ProcClk

FastClk

St81

Input Scan channel Output Scan channel


Top Design: Idma
Scan_en
Scan_chain Input1
Scan_out1

2) How many clock domains? FastClk, ProcClk, St81


3) How many resets? Reset
4) Number of scan chains 1 scan chains
5) Clock mixing or not clock mixing? clock mixing
6) How many Lockup-latches are added during scan insertion? 2
7) Is it top-down or bottom up approach? Top Down approach
8) How many terminal lockup latches are added? 0
9) Number of scan flops and non-scan flops in the design? 128 scanable flops and 2
non-scan elements
10) Chain length? 2 (total 128 memory elements)
#chains: 1 , 128

11)Number of DRC violations? No Violation only warning C3(note),C8,C9,D5,D7

12) Log file: - please note your observations from the log
file Top module is Idma

Vlsiguru Confidential 2
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Number of shift registers =0


Number of INV inserted =1
Number of lockup latch =2
Number of MUX inserted =0
Number of terminal Lockup latch added =0
No of scan memory element =130
No of non scan memory element converted to scanable =128
Number of new Pins inserted= 3 ( 1 scan inputs, 1 Scan_out ,scan_en )

Vlsiguru Confidential 3

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