Republic of the Philippines

BATANGAS STATE UNIVERSITY

Pablo Borbon Main II

Alangilan, Batangas City

ECE-302: ELECTRONICS CIRCUITS ANALYSIS AND DESIGN

Laboratory Activity No. 1

TRANSISTOR CHARACTERISRIC AND BIAS

Submitted by:

Group No. 4

Aguila, Archangel D.

Delos Reyes, King Jhonzon A.

Masacayan, Neildon Joseph A.

ICE-3202
 Submitted to:

Engr. Antonette V. Chua

Instructor

I. Introductory Information

Transistor biasing is the process of setting a transistor DC operating voltage or current

conditions to the correct level so that any AC input signal can be amplified correctly by the
transistor. A transistor steady state of operation depends a great deal on its base current, collector
voltage, and collector current and therefore, if a transistor is to operate as a linear amplifier, it
must be properly biased to have a suitable operating point.

Establishing the correct operating point requires the proper selection of bias resistor and load
resistor to provide the appropriate input current and collector voltage or a conditions. The correct
biasing point for a bipolar transistor, either NPN or PNP , generally relies somewhere between
the two extremes of operation with respect to it being either “fully-ON” or “fully-OFF” along its
load line. This central operating point is called the “ Quiescent Operating point” or known as the
“Q-point” for short.

When a bipolar transistor is biased so that the Q-point is near to the middle of its operating
range, that is approximately halfway between cut off and saturation, it is said to be operating as a
Class-A amplifier. The mode of operation allows the output current to increase and decrease
around the amplifier Q-point without distortion as the input signal swings through a complete
cycles. In other words, the output current flows for the full 360º of the input cycle.

One of the most frequently used biasing circuits for a transistor circuit is with the self-bias of
the emitter-bias circuit when one or more biasing resistor are used to setup the initial DC values
of transistor currents, (Ib),(Ic), and (Ie).

The two most common form of transistor biasing are:Beta dependent and Beta Independent.
Transistor bias voltages are largely dependent on transistor beta, (β) so the biasing setup for one
transistor may not necessarily be the same for another transistor. Transistor biasing can be
achieved either by using a single feedback resistor or by using a simple voltage divider network
to provide the required biasing circuit.The common emitter transistor is biased using a voltage
divider network to increase stability. The name of this biasing configuration comes from the fact
that the two resistorsRB1 and RB2 form a voltage or potential divider network across the supply
with their center point junction connected the transistors base terminal as shown.This voltage
divider biasing configuration is the most widely used transistor biasing method, as the emitter
diode of the transistor is forward biased by the voltage dropped across resistor RB2. Also,
voltage divider network biasing makes the transistor circuit independent of changes in beta as the
voltages at the transistors base, emitter, and collector are dependant on external circuit values.To
calculate the voltage developed across resistor RB2 and therefore the voltage applied to the base
terminal we simply use the voltage divider formula for resistors in series.Generally the voltage
drop across resistor RB2 is much less than for resistor RB1. Then clearly the transistors base
voltage VB with respect to ground, will be equal to the voltage across RB2.The current flowing
through resistor RB2 is generally set at 10 times the value of the required base current IB so that
it has no effect on the voltage divider current or changes in Beta.The goal of Transistor
Biasing is to establish a known Q-point in order for the transistor to work efficiently and produce
an undistorted output signal. Correct biasing of the transistor also establishes its initial AC
operating region with practical biasing circuits using either a two or four-resistor bias network.In
bipolar transistor circuits, the Q-point is represented by ( VCE, IC ) for the NPN transistors or
( VEC, IC ) for PNP transistors. The stability of the base bias network and therefore the Q-point
is generally assessed by considering the collector current as a function of both Beta (β) and
temperature.Here we have looked briefly at five different configurations for “biasing a
transistor” using resistive networks. But we can also bias a transistor using either silicon diodes,
zener diodes or active networks all connected to the base terminal of the transistor or by biasing
the transistor from a dual power supply.

OBJECTIVES:

To plot the output characteristic of an NPN Bipolar Junction Transistor

To plot the DC load line of BJT bias circuit

To determine the operating points of BJT bias circuit

To determine the effects of beta in several transistor bias circuit

To plot the output characteristics of an n-channel Field Effect Transistor

To plot the transfer characteristics of an n-channel Field Effect Transistor

To plot the DC load line of a FET bias circuit

 II. Materials/Components

 Laptop w/ Multisim

 DMM

 Power Supply

 Bread board

 Connecting wires

 Potentiometer

 Resistor

 Transistor

III. Procedures

BJT Output Characteristic

1. Construct the circuit shown in the Figure 1. The resistor R1 and R2 are used to vary the
values of Ib and Ic, respectively.

2. Vary R1 to fix the base current to 5µA, then vary R2 to change the value of Vᴄᴇ.

3. Record the values of Ic for the values of Vᴄᴇ= 0V up to Vᴄᴇ= 18V at an increment of
0.5V.

4. Plot the collector current versus the collector-to-emitter voltage.

5. Repeat the steps with Ib=5µA up to Ib=50µA at a 5µA increment.

CIRCUIT 1

Data&Result:
When Ib=5µA

Vᴄᴇ Iᴄ
 0V 4.519µA

0.5V 636.158µA

1V 640.377µA

1.5V 644.818µA

2V 649.703µA

2.5V 654.143µA

3V 658.140µA

3.5V 661.693µA

4V 667.022µA

4.5V 670.575µA

5V 675.904µA

5.5V 680.345µA

6V 684.786µA

6.5V 687.450µA

7V 693.667µA

7.5V 696.332µA

8V 699.885µA

8.5V 705.214µA

9V 710.543µA

9.5V 714.095µA

10V 717.648µA

10.5V 722.977µA

11V 728.306µA

11.5V 731.859µA

12V 735.412µA

12.5V 738.964µA
 13V 744.294µA

13.5V 749.623µA

14V 753.175µA

When Ib=10µA

Vᴄᴇ Ic

0V -7.550µA

0.5V 1.376mA

1V 1.386mA

1.5V 1.395mA

2V 1.405mA

2.5V 1.413mA

3V 1.425mA

3.5V 1.434mA

4V 1.441mA

4.5V 1.450mA

5V 1.460mA

5.5V 1.472mA

6V 1.479mA

6.5V 1.488mA

7V 1.496mA

7.5V 1.508mA

8V 1.517mA

8.5V 1.526mA
 9V 1.537mA

9.5V 1.545mA

10V 1.556mA

10.5V 1.561mA

11V 1.572mA

11.5V 1.581mA

12V 1.592mA

12.5V 1.600mA

13V 1.608mA

When Ib=15µA

Vᴄᴇ Ic

0V 1.037mA

0.5V 2.184mA

1V 2.199mA

1.5V 2.213mA

2V 2.228mA

2.5V 2.243mA

3V 2.258mA

3.5V 2.273mA

4V 2.288mA

4.5V 2.302mA

5V 2.317mA

5.5V 2.331mA

6V 2.347mA
 6.5V 2.363mA

7V 2.377mA

7.5V 2.391mA

8V 2.407mA

8.5V 2.421mA

9V 2.435mA

9.5V 2.451mA

10V 2.466mA

10.5V 2.480mA

11V 2.496mA

11.5V 2.510mA

12V 2.524mA

12.5V 2.538mA

When Ib=20µA

Vᴄᴇ Ic

0V -11.670µA

0.5V 3.011mA

1V 3.030mA

1.5V 3.050mA

2V 3.070mA

2.5V 3.091mA

3V 3.111mA

3.5V 3.131mA

4V 3.152mA

4.5V 3.173mA
 5V 3.192mA

5.5V 3.213mA

6V 3.233mA

6.5V 3.254mA

7V 3.276mA

7.5V 3.299mA

8V 3.316mA

8.5V 3.336mA

9V 3.357mA

9.5V 3.377mA

10V 3.396mA

10.5V 3.419mA

11V 3.437mA

11.5V 3.460mA

When Ib=25µA

Vᴄᴇ Ic

0V -13.021µA

0.5V 3.837mA

1V 3.864mA

1.5V 3.889mA

2V 3.916mA

2.5V 3.942mA

3V 3.968mA

3.5V 3.994mA

4V 4.020mA
 4.5V 4.047mA

5V 4.073mA

5.5V 4.098mA

6V 4.125mA

6.5V 4.151mA

7V 4.174mA

7.5V 4.201mA

8V 4.230mA

8.5V 4.253mA

9V 4.297mA

9.5V 4.308mA

10V 4.334mA

10.5V 4.357mA

When Ib=30µA

Vᴄᴇ Ic

0V -14.089µA

0.5V 4.673mA

1V 4.706mA

1.5V 4.737mA

2V 4.769mA

2.5V 4.801mA

3V 4.832mA

3.5V 4.865mA

4V 4.896mA

4.5V 4.928mA
 5V 4.958mA

5.5V 4.990mA

6V 5.022mA

6.5V 5.054mA

7V 5.084mA

7.5V 5.116mA

8V 5.150mA

8.5V 5.182mA

9V 5.212mA

9.5V 5.244mA

When Ib=35

Vᴄᴇ Ic

0V -14.944µA

0.5V 5.508mA

1V 5.546mA

1.5V 5.581mA

2V 5.622mA

2.5V 5.656mA

3V 5.693mA

3.5V 5.736mA

4V 5.770mA

4.5V 5.809mA

5V 5.846mA

5.5V 5.882mA

6V 5.921mA
 6.5V 5.956mA

7V 5.993mA

7.5V 6.031mA

8V 6.070mA

8.5V 6.107mA

When Ib=40µA

Vᴄᴇ Ic

0V -15.609µA

0.5V 6.286mA

1V 6.332mA

1.5V 6.373mA

2V 6.416mA

2.5V 6.461mA

3V 6.498mA

3.5V 6.546mA

4V 6.583mA

4.5V 6.631mA

5V 6.674mA

5.5V 6.713mA

6V 6.759mA

6.5V 6.759mA

7V 6.844mA

7.5V 6.887mA

8V 6.928mA
 Operating Points of a BJT Amplifier

1. Construct the circuit shown in Figure 2.

2. Measure the base current.

3. Plot the output characteristic of a transistor using the measured base current.

4. Plot the DC load line, i.e. using Rc then model Vᴄᴇ as a voltage supply, in the
same plot as the output characteristic of the transistor. Vary Vᴄᴇ(0.5V
increment)and record the current across Rc.

5. Identify the intersection of two plots, this is the operating point of the circuit.

6. Using a DMM, measure the operating points of Figure 2.

7. Record the measurements

CIRCUIT 2
Data&Result:

Ib 14.433µA

Ic 2.276mA

Ie 2.288mA

Vbe 685.077mV

Vce 7.953mV

Vb 685.077mV

Ve 0V

Vc 7.953mV
 Icsat= Vcc/Rc

Icsat= 4.839mA

Transistor Bias Circuit

1) Construct a fixed bias circuit using a general purpose transistor. Vcc= 15V, Rb = 1MΩ,
Rc= 2.7 kΩ.

2) Measure the operating points, Ib, Ic, Vbe, and Vce.

 3) Calculate the β from the measurements.

β = Ic / Ib

4) Record the measurements.

5) Repeat the step 1-4 for an emitter bias circuit using a general purpose transistor. Vcc =
15V, Rb= 1MΩ, Rc= 2.2 kΩ and Re= 2.2 kΩ.

6) Repeat steps 1-4 again for a voltage divider bias using a general purpose transistor. Vcc
=15 V, R1= 33kΩ, R2 = 6.8 kΩ, Rc= 1.8 kΩ, and Re= 0.68 kΩ.

7) Repeat steps 1-4 again for a common base configuration. Vcc 15 V, Vee= -15 V, Rc=
2.2 kΩ and Re= 2.2kΩ.

8) Repeat steps 1-7using a higher beta transistor.

9) Calculate the differences in measurements for Ib, Vbe, Ic, Vce and β.

| Ib1 Ib 2|
％ΔIb= Ib1 x100%
|Vbe2 Vbe1|
％ΔVbe= Vbe1 x100 0 0

| Ic 2  Ic1|
％ΔIc= Ic1 x100 0 0
|Vce 2 Vce1|
％ΔVce= Vce1 x100 0 0

| 2  1|
％Δβ= 1 x100 0 0

Fixed biased Emitter stabilized

 Voltage Divider common based

Data&Result:
 Fixed Bias

1 2

Iᴄ 2.162 mA 3.98mA

Iⲃ 11.102µA 11.213µA

Vⲃᴇ 638.15mV 518.052mV

Vᴄᴇ 9.157V 4.254V

β 194.74 354.95

|11.213A11.10A|
％ΔIb= 11.102A x100%  1 0 0

|518.052mV  638.15V |
％ΔVbe= 638.15V x100 0 0  18.82 0 0

|3.98mA 2.162mA|
％ΔIc= 2.162mA x100 0 0  84.09 0 0

|4.254V 9.157V |
％ΔVce= 9.157V x100 0 0  53.54 0 0

|354.95194.74|
％Δβ= 194.74 100 0 0  82.27 0 0

Emitter Stabilize

1 2(higher beta)

Iᴄ 1.763mA 2.472mA

Iⲃ 8.048µA 6.955µA

Vⲃᴇ 641.073mV 505.119mV

Vᴄᴇ 7.225V 4.108V

β 219.06 344.43
 |6.955A08.048A|
％ΔIb= 8.048A x100%  13.58 0 0

|505.119mV  641.073mV |
％ΔVbe= 641.073mV x100 0 0  21.21 0 0

|2.472mA1.763mA|
％ΔIc= 1.763mA x100 0 0  40.22 0 0

|4.108V  7.225V |
％ΔVce= 7.225V x100 0 0  43.14 0 0

|355.43 219.06|
％Δβ= 219.06 100 0 0  62.25 0 0

Common Base

1 2(higher beta)

Iᴄ 5.704mA 5.768mA

Iⲃ 26.983µA 19.222µA

Vⲃᴇ 673.586mV 532.929mV

Vᴄᴇ 3.126V 2.844V

β 211.39 300.07

|19.222A26.983A|
％ΔIb= 26.983A x100%  28.76 0 0

|532.929mV  673.586mV |
％ΔVbe= 673.586mV x100 0 0  20.88 0 0

|5.768mA5.704mA|
％ΔIc= 5.704mA x100 0 0  1.12 0 0

|2.844V 3.126V |
％ΔVce= 3.126V x100 0 0  9.02 0 0

|300.07 211.39|
％Δβ= 211.39 100 0 0  41.95 0 0
 Voltage Divider

1 2(higher beta)

Iᴄ 1.902mA 2.091mA

Iⲃ 8.486µA 3.823µA

Vⲃᴇ 642.49mV 488.754mV

Vᴄᴇ 9.794V 9.184V

β 224.13 546.95

|3.8233A8.486A|
％ΔIb= 8.486A x100%  54.95 0 0

|488.754mV  642.49mV |
％ΔVbe= 642.49mV x100 0 0  23.93 0 0

|2.091mA1.902mA|
％ΔIc= 1.902mA x100 0 0  9.94 0 0

|9.184V 9.704V |
％ΔVce= 9.704V x100 0 0  5.36 0 0

|546.95 224.13|
％Δβ= 224.13 100 0 0  144.03 0 0
 FET Output and Transfer Characteristic

1. Construct the circuit shown in the Figure3.

2. Vary R1 so that the Vgs = 0V.

3. Measure and record Id at every 0.25 V of Vds, stops measuring once Id becomes almost
constant. This Id is the maximum drain-to-source saturation current, Idss.

4. Record the values at which Id becomes constant, these are saturation currents for an
input voltage Vgs.

5. Repeat steps 2-4 with a 0.5 V decrement in Vgs. Stop when Id is almost zero(µA range).
Record Vgs, this now is the estimated pinch-off voltage.

6. Plot the saturation currents with respect to Vgs.

7. Using Shockley’s equation, plot the transfer relations and compare the plot with the plot
from step 6.

8. Repeat the process for a D-MOSFET. Vary Vgs from 0 to 2 V at an increment of 0.5 V.
9. Repeat the process for an E-MOSFET, start with Vgs= 0V incremented at 0.5 V. record the
voltage at which the current starts flowing. This is the threshold voltage. Stop at Vgs = 8V.
Note:k can be determined by using any point in the transfer curve.

CIRCUIT 4 E-MOSFET

CIRCUIT 4 JFET
Data and result

VDS ID@0V [email protected] ID@-1V

252.981 mV 1.148 mA 842.11 µA 500.601 µA

500.453 mV 2.148 mA 1.571 mA 842.69 µA

750.85mV 3.642 mA 2.033 mA 1.023 mA

1.002 V 3.675 mA 2.43 mA 1.055 mA

1.253 V 4.201 mA 2.603 mA 1.056 mA

1.505 V 4.577 mA 2.653 mA 1.057 mA

 1.752 V 4.786 mA 2.655 mA 1.058 mA

2.007 V 4.843 mA 2.658 mA 1.059 mA

 JFET

 E-MOSFET

VDS VGS=8V VGS=7V VGS=6V VGS=5V VGS=4V VGS=3V

30 12.7 mA 11.23 mA 10.1 mA 8.76 mA 6.34 mA 3.79 mA

25 10.6 mA 9.16 mA 8.37 mA 7.11 mA 5.39 mA 3.14 mA

20 8.47 mA 7.49 mA 6,8 mA 5.70 mA 4.25 mA 2.51 mA

15 6.35 mA 5.36 mA 5.10 mA 4.31 mA 3.21 mA 1.88 mA

10 4.23 mA 3.76 mA 3.43 mA 2.86 mA 2.12 mA 1.27 mA

0 0 mA 0 mA 0 mA 0 mA 0 mA 0 mA
 FET Bias Circuit

1) Test a FET for its parameters. (use a general purpose JFET).

2) Construct a JFET fixed bias circuit. Vdd= 15V, Rd= 1 kΩ. Use a voltage divider
(potentiometer) to have Vgs = -1 V.

3) Measure the operating points

4) Plot the circuit’s input characteristics in the transfer curve of the transistor.

5) Repeat the steps 3-4 for self biasing circuits. Vdd= 15 V, Rd= 1kΩ, Rs= 1.2 kΩ, Rg= 1MΩ.

6) Repeat the steps 3-4 for a voltage divider bias. Vdd= 15 V, R1 = 10 kΩ, R2 = 3 kΩ, Rd=
1kΩ, Rs =1.2 kΩ.

CIRCUIT 5 VOLTAGE DIVIDER

CIRCUIT 5 SELF BIAS FIXED BIAS
DATA AND RESULT:

 JFET FIXED BIAS

VDS 13. 443 V

VGS -1 V

ID 1.20 mA

IDss 4.95 mA

 VOLTAGE DIVIDER

VDS 7V

VGS -379.026 mV

ID 3.20 mA

IDss 4.95 mA

 JFET SELF-BIAS

VDS 12.681 V

ID 928 µA =0.928 mA

VGS -1.113 mA

IDss 4.95 mA

IV.Analysis

Based on the graph after eight different trials conducted the beta tends to increase varying
that the Ic is also higher therefore the member of the group conclude that the higher the Ic
current, the higher the Beta may produced.

The figure 2 emitter stabilize circuit constructed in the multisim to identify the operating
points as well as getting its Ic sat by using the DMM. Measuring its base current and plotting the
output characteristics of the transistor using the recorded base current. Knowing the intersection
of two plots for the operating point of the circuit.

After comparing the circuits plotted and recording their measurements, the most stable bias
circuit based on different circuit trials, the voltage divider circuit comes on top for being stable
because it does not depend on the beta transistor unlike other circuits.

Based on the table shown on figure 4 the relationship of voltage and current are directly
proportional to each other when voltage supply is zero then current produce is also zero but when
voltage supply is greater than zero then the current produced is increasing. In the JFET biasing
circuit it became stable and nearly reaches zero with an Id of negative one while E-MOSFET
biasing circuit reaches a Vgs of 3v to became stable and reach near to zero.

By plotting each circuit’s input characteristics in the transfer curve of the transistor type of
circuit and measuring the parameters for JFET bias circuit such as VDS, VGS, ID and IDss in
different types of circuit, self bias circuit, fixed bias and voltage divider bias their results vary
but their IDss remains the same.

V. Conclusion

A transistor is a semiconductor device used to amplify or switch electronic signals

and power. The Bipolar Transistor basic construction consists of two PN-junctions producing
three connecting terminals with each terminal being given a name to identify it from the other
two. These three terminals are known and labeled as the Emitter ( E ), the Base ( B ) and
the Collector ( C ) respectively. The most commonly used transistor configuration is the NPN
Transistor. We also learnt that the junctions of the bipolar transistor can be biased in one of three
different ways –Common Base, Common Emitter and Common Collector. It is one of the
Bipolar Junction Transistor (BJT) types. This transistor is mostly used for amplifying and
switching the signals. As the Bipolar Transistor is a three terminal device, there are basically
three possible ways to connect it within an electronic circuit with one terminal being common to
both the input and output. Each method of connection responding differently to its input signal
within a circuit as the static characteristics of the transistor varies with each circuit arrangement.

1. To plot output characteristics of an NPN bipolar junction transistor the curves show the
relationship between the collector current (IC) and the collector-emitter voltage (VCE) with the
varying of base current (IB). We know that the transistor is ‘ON’ only when at least a small amount
of current and small amount of voltage is applied at its base terminal relative to emitter otherwise
the transistor is in ‘OFF’ state.
 The collector current (IC) is mostly affected by the collector voltage (VCE) at but this IC is
not highly affected. Already we know that the emitter current is the sum of base and collector
currents. In other words IE =IC+ IB. The current flowing through the resistive load (RL) is equal
to the collector current of the transistor. The equation for the collector current is given by,

IC= (VCC-VCE)/ RL

The straight line indicates the ‘Dynamic load line’ which is connecting the points A (where
VCE= 0) and B (where IC = 0). The region along this load line represents the ‘active region’ of the
transistor.

The common emitter configuration characteristics curves are used to calculate the collector
current when the collector voltage and base current is given. The load line (red line) is used to
determine the Q-point in the graph. The slope of the load line is equal to the reciprocal of the
load resistance, in other words -1/RL.

2.-3. The dc load line represents all the possible combinations of IC and VCE for a given amplifier.
For a transistor circuit to amplify it must be properly biased with dc voltages. To construct DC
load line of a transistor we need to find the saturation current and cutoff voltage. The dc
operating point between saturation and cutoff is called the Q-point. The purpose of biasing is to
establish a stable operating point (Q-point). The Q-point is the best point for operation of a
transistor for a given collector current.  The dc load line helps to establish the Q-point

4. β (beta) of a transistor is the gain or amplification factor of a transistor. It is the factor by

which current is amplified in the circuit. You will get different results to the effects of beta in
several transistor bias circuits. If you are wondering about how you would know that which type
of bias circuit is Beta dependent or not then just find out the equations for Ic, check for the Beta
dependency on it. Try using Voltage Divider Bias Circuit which is Beta independent, there
would be hardly any change in result if you change the transistor.

5.-6. The curve between drain current, ID and drain-source voltage, VDS of a JFET at constant
gate-source voltage, VGS is known as output characteristics of JFET. The characteristic is
analogous to collector characteristic of a BJT. The voltage VGS applied to the Gate controls the
current flowing between the Drain and the Source terminals. VGS refers to the voltage applied
between the Gate and the Source while VDS refers to the voltage applied between the Drain and
the Source. The transfer characteristic for a JFET can be determined experimentally, keeping
drain-source voltage, VDS constant and determining drain current, ID for various values of
gate-source voltage, VGS. Drain current decreases with the increase in negative gate-source bias
as observed. The ID corresponding to various values of gate-source voltage for a constant
drain-source voltage and plotting them can also be derived from the drain characteristic by
noting values of drain current.

7. The operating point of the circuit in this configuration (labeled Q) is generally designed to be
in the active region, approximately in the middle of the load line for amplifier applications.
Adjusting the base current so that the circuit is at this operating point with no signal applied is
called biasing the transistor. The point is arbitrary, and a circuit can be developed to bias the
JFET to operate a point, the amplifier needs to work in a linear region of the output characteristic
curves. The DC load line for the common source JFET amplifier produces a straight line. The
actual position of the Q-point on the DC load line is generally positioned at the mid center point
of the load line (for class-A operation) and is determined by the mean value of Vg which is
biased negatively as the JFET is a depletion-mode device