PIC18F2455/2550/4455/4550 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) ‘The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the ‘wo serial 10 modules. (Generically, ine USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a fullduplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. Itcan also be configured as a half- duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated Circuits, serial EEPROMs, et ‘The Enhanced USART module implements aditional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break recep- tion and 12-bit Break character transmit, These make it ideally suited for use in Local Interconnect Network bus. (LIN bus) systems, The EUSART can be configured in the following modes: + Asynchronous (full-duplex) with + Auto-wake-up on Break signal = Auto-baud calibration = 12-bit Break character transmission + Synchronous ~ Master (half-duplex) with selectable clock polarity + Synchronous — Slave (half-duplex) with selectable clock polarity The pins of the Enhanced USART are multiplexed with PORTE, In order to configure ROB/TXICK and RG7IRX/DTISDO as an EUSART: + SPEN bit (RCSTAcT>) must be set (= + TRISC<7> bit must be set (= 1) + TRISC<6> bit must be set = 1) Note: The EUSART control will automatically reconfigure the pin from input to output as needed, ‘The operation of the Enhanced USART module is controlled through three registers: + Transmit Status and Control (TXSTA) + Receive Status and Control (RCSTA) + Baud Rate Control (BAUDCON) ‘These are detailed on the following pages in Register 20-1, Register 20-2 and Register 20:3, respectively. { 2008 Microchip Tecnology Ine DS98632E-page 243,PIC18F2455/2550/4455/4550 TXSTA: TRANSMIT STATUS AND CONTROL REGISTER RW RO RM RIO RW Ra RW 1X8 TXEN® | SYNC | SENDS | BRGH TRMT Tx8D bit) We Wrtable bit U=Unimplemented bit, read as 0 -n= Value at POR 1 = Bitis set (0'= Bitis cleared x= Bitis unknown bit7, SRC: Clock Source Select bit Asynchronous mode: Dont care, ‘Synchronous mode: faster mode (clock generated internally rom BRG) lave mode (clock from external source) bie TX: 9-Bit Transmit Enable bit elects 8-bit transmission Selects 8-bit transmission bits TXEN: Transmit Enable bit") 1 = Transmit enabled ransmit disabled bit SYNC: EUSART Mode Select bit synchranaus mode synchronous mode bits SENDB: Send Break Character bit Asynchronous mode: fend Sync Break on next transmission (cleared by hardware upon completion) yc Break transmission completed ‘Synchronous mode. Dont care, bit BRGH: High Baud Rate Select bit Asynchronous mode: 1= High speed 0 = Low speed Unused in this mode. bit TRMT: Transmit Shift Register Status bit 1 =TSRemply 0= TSR full bio TX9D: Sth bit of Transmit Data Can be address/data bit or a party bit Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode. s39632E-page 244 18 2008 Microchip Technology Ine.PIC18F2455/2550/4455/4550 REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER RAO RAO RW RWO RW RO RO Rox ‘SPEN Xo SREN REN | ADDEN FERR ‘OERR RXeD bi, Bito| Legend: R= Readable bit U= Unimplemented bit, read as ‘0 Value at POR Bitis cleared X= Bitis unknown bit7 ‘SPEN: Serial Port Enable bit = Serial port enabled (configures RXIDT and TX/CK pins as serial port pins) eri port disabled (held in Reset) bits RX8: 9-Bit Receive Enable bit Selects 9-bit reception elects 8-bit reception bits 'SREN: Single Receive Enable bit ‘Asynchronaus made: Don't care. ‘Synchronous mode — Master: Enables single receive Disables single receive ‘This bits cleared atter reception is complete Don't care. ita REN: Continuous Receive Enable Asynchronous mode: ables receiver jisables receiver ‘Synchronous mode ables cortinuous receive until enable bit CREN is cleared (GREN overrides SREN) 0 = Disables continuous receive bits ADDEN: Address Detect Enable bit Asynchronous mode @-bit (RX9 = Enables address detection, enables interupt and loads the receive buffer when RSR«8> is set Disables address detection, all bytes are received and ninth bit can be used as pariy bit Asynchronous mode 8-bit (RX@ = 0) Dont care. bit2 FERR: Framing Error bit raming error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 ERR: Overrun Error bit \verrun error (can be cleared by clearing bit CREN) bito RXSD: sth bit of Received Data This can be address/data bit or @ parity bit and must be calculated by user firmware, { 2008 Microchip Tecnology Ine DS98632E-page 245,