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This document provides an overview of digital communication systems and error correction techniques. It discusses key topics like information theory, source and channel coding, modulation, error detection and correction schemes. Specific error correction techniques covered include BCH codes, convolutional codes, and Reed-Solomon codes. The document then focuses on BCH codes, providing details on encoding and decoding using linear feedback shift registers. It describes implementing a BCH encoder and decoder in VHDL and programming an FPGA with the designed encoder and decoder. Experimental results from the FPGA implementation are presented.

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35 views3 pages

Page No. List of Figures List of Abbreviations 1

This document provides an overview of digital communication systems and error correction techniques. It discusses key topics like information theory, source and channel coding, modulation, error detection and correction schemes. Specific error correction techniques covered include BCH codes, convolutional codes, and Reed-Solomon codes. The document then focuses on BCH codes, providing details on encoding and decoding using linear feedback shift registers. It describes implementing a BCH encoder and decoder in VHDL and programming an FPGA with the designed encoder and decoder. Experimental results from the FPGA implementation are presented.

Uploaded by

krishna hegde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CONTENTS

Chapter No. Name of the Content Page No.


List of Figures i
List of Abbreviations ii
1 Introduction 1
Overview 3
Objective 3
2 LITERATURE SURVEY 4
2.1 Basic Structure of communication system 4
2.2 Digital Communication System 5
2.3 Information System 6
2.4 Types of Errors 7
2.5 Types of Codes 8
2.6 Shannon’s Theorem 9
2.7 Line Coding Techniques 12
2.8 Channel Coding Techniques 13
2.8.1 BCH Codes 14
2.8.2 Reed Solomon Codes 14
2.8.3 Convolution Codes 15
2.9 Source Encoding and Decoding 16
2.10 Channel Encoding and Decoding 17
2.10.1 Channel Decoding 19
2.11 Error Detection Schemes 20
2.12 Methods of Controlling Errors 22
2.12.1 Automatic Repeat Request 22
2.12.2 Error Detection Methods 23
2.12.3 Forward Error Detection Mechanism 23
2.13 Modulation and Demodulation 25
2.14 Fields 25
2.14.1 Galois Fields 26
2.14.2 Properties of Galois Fields 28
2.14.3 Primitive Polynomial 29
2.14.4 Construction of Galois Fields 31
2.14.5 Galois Field Arithmetic 32
2.14.6 Addition and Subtraction 32
3 Introduction to bch codes 33
3.1 Use of BCH Codes 34
4 Linear Feed Back Shift Register 36
4.1 Primitive Polynomial 36
4.2 Taps 36
4.3 External LFSR 36
4.4 Internal LFSR 36
4.5 BCH Encoder using LFSR 37
4.6 BCH Decoder using LFSR 38
5 Encoder 41

5.1 BCH Encoder 42


5.2 Generator Polynomial 43
5.3 Operation Of Encoder 44
5.4 Example 45
5.5 Simulation Results of Encoder 47
6 Decoder 52

6.1 BCH Decoder 53


6.2 Operation of Decoder 54
6.2.1 Syndrome Calculation 55
6.2.2 Calculating Error Locater Polynomial 56
6.2.3 Recalculation of Parity 58
6.2.4 Example 58
6.2.5 Simulation Results of Decoder 60
7 ALGORITHMS 65

7.1Berleklamp Massey Algorithm 65


7.1.2 Description 67
7.2 Algorithm 67
8 SOFTWARE 73

8.1 Modelsim Altera 73


8.2 Quartus II 73
8.3 VHSIC Hardware Description Language 73
8.3.1 Data Types 74
8.3.2 Design Units 74
8.3.3 Architecture 75
8.3.4 Objects 75
8.3.5 Signals 75
8.3.6 Advantages of VHDL 76
8.3.7 Simulation with modelsim and Quartus II 76
8.3.8 TestBench 78
8.3.9 Example 79
9 Field Programmable Gate Array 80

9.1 FPGA Design and programming 82


9.1.1 FPGA Encoder Design 83
9. 1.2 FPGA Decoder design 85
9.2 PLL 85
9.3 Crystal Oscillator 87
9.4 JTAG 88
9.5 Altera Cyclone III EP3C4F78017 89
9.6 Cyclone III Device Family Architecture 90
9.7 Logic Element and Array Blocks 91
9.8 Memory Blocks 91
9.9 Embedded Multilpliers and DSP Support 91
9.10 Clock Networks and PLLS 92
9.11 Quartus II software Support 92
9.12 Common FPGA Applications 94
9.13 Hardware Results 95
10 Experimental Results 96
Experimental Results 98
Simulation Results 101
CONCLUSION 105
REFERENCES 106

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